Producing method of semiconductor device, semiconductor wafer and semiconductor device

Abstract

To provide a method for producing a semiconductor device capable of measuring a positional deviation of upper and lower layers on a wafer with accuracy.SOLUTION: A method for producing a semiconductor device, which includes a first step of forming a first layer 39 in which a reference mark 56 for measuring the positional deviation of resist 55 with respect to a first element pattern for a semiconductor element is formed on a main surface 2 of a wafer, a second step of forming the resist 55 on the first layer 39 so as to cover the reference mark 56 and the first element pattern, a third step of forming a positional deviation determination pattern 59 overlapping on the reference mark 56 in plan view, a peripheral pattern 60 surrounding the positional deviation determination pattern 59 in plan view, and a second element pattern for the semiconductor element using the resist 55 by exposing and developing the resist 55, and a fourth step of determining the positional deviation of the second element pattern with respect to the first element pattern by measuring a relative position of the positional deviation determination pattern 59 with respect to the reference mark 56.SELECTED DRAWING: Figure 5B

Description

[Technical field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device, a semiconductor wafer, and a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including: a chip having a first main surface on one side and a second main surface on the other side; a first region of a first conductivity type formed on the second main surface side of the chip; a second region of a second conductivity type formed on the first main surface side of the chip and forming a p-n junction with the first region; a device region provided on the first main surface; a first trench structure that includes a first trench penetrating the p-n junction from the first main surface, a first insulating film exposing the first region from a wall surface of the first trench, and first polysilicon embedded in the first trench with the first insulating film in between, and defines the device region; and a second trench structure that includes a second trench penetrating the p-n junction from the first main surface, a second insulating film exposing the first region from a wall surface of the second trench, and second polysilicon embedded in the second trench with the second insulating film in between, and defines the device region on the device region side of the first trench structure. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2023-32332 A

[0004] [overview] An embodiment of the present disclosure provides a method for manufacturing a semiconductor device that can accurately measure misalignment between upper and lower layers on a wafer.

[0005] A manufacturing method of a semiconductor device according to one embodiment of the present disclosure includes: a first step of forming, on a main surface of a wafer, a first layer having a reference mark for measuring a misalignment of a resist relative to a first element pattern for a semiconductor element; a second step of forming a resist on the first layer so as to cover the reference mark and the first element pattern; a third step of exposing and developing the resist to form, using the resist, a misalignment determination pattern that overlaps the reference mark in a planar view, a surrounding pattern that surrounds the reference mark in a planar view, and a second element pattern for the semiconductor element; and a fourth step of determining a misalignment of the second element pattern relative to the first element pattern by measuring a relative position of the misalignment determination pattern with respect to the reference mark. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic diagram showing a wafer used in the manufacture of semiconductor devices. [Diagram 2] FIG. 2 is an enlarged view of a main portion of the wafer of FIG. [Diagram 3] FIG. 3 is a diagram showing an element structure formed on the wafer. [Figure 4A] FIG. 4A is a diagram showing an example of a method for manufacturing the semiconductor device. [Figure 4B] FIG. 4B is a diagram showing a step subsequent to that of FIG. 4A. [Figure 4C] FIG. 4C is a diagram showing a step subsequent to that of FIG. 4B. [Figure 4D] FIG. 4D is a diagram showing a step subsequent to that of FIG. 4C. [Figure 4E] FIG. 4E is a diagram showing a step subsequent to that of FIG. 4D. [Figure 4F] FIG. 4F is a diagram showing a step subsequent to that of FIG. 4E. [Figure 4G] FIG. 4G shows a step subsequent to that of FIG. 4F. [Figure 4H] FIG. 4H is a diagram showing a step subsequent to that of FIG. 4G. [Figure 4I] FIG. 4I is a diagram showing a step subsequent to that of FIG. 4H. [Figure 4J] FIG. 4J is a diagram showing a step subsequent to that of FIG. 4I. [Figure 4K] FIG. 4K is a diagram showing a step subsequent to that of FIG. 4J. [Figure 4L] FIG. 4L shows a process subsequent to that of FIG. 4K. [Figure 4M] FIG. 4M is a diagram showing a step subsequent to that of FIG. 4L. [Figure 4N] FIG. 4N shows a process subsequent to that of FIG. 4M. [Figure 4O] FIG. 4O is a diagram showing a step subsequent to that of FIG. 4N. [Figure 4P] FIG. 4P is a diagram showing a process subsequent to that of FIG. 4O. [Figure 5A] FIG. 5A is a diagram showing a planar pattern (first configuration) of the first resist film. [Figure 5B] FIG. 5B is a diagram showing a cross-sectional pattern (first configuration) of the first resist film. [Figure 6A] FIG. 6A is a diagram showing a plane pattern (second configuration) of the first resist film. [Figure 6B] FIG. 6B is a diagram showing a cross-sectional pattern (second form) of the first resist film. [Figure 7A] FIG. 7A is a diagram showing a plane pattern of the second resist film. [Figure 7B] FIG. 7B is a diagram showing a cross-sectional pattern of the second resist film. [Figure 8] FIG. 8 is an enlarged view of a main part of the wafer after the element structure is formed. [Figure 9] FIG. 9 is an enlarged view of a portion surrounded by a two-dot chain line IX in FIG. [Figure 10] FIG. 10 is a schematic plan view of the semiconductor device. [Figure 11] FIG. 11 is an enlarged view of a portion surrounded by a two-dot chain line XI in FIG. [Figure 12A] FIG. 12A is a diagram showing the measurement results of the positional deviation of the resist film in Sample 1. FIG. [Figure 12B]FIG. 12B is a diagram showing the measurement results of the positional deviation of the resist film in Sample 2. In FIG. [Figure 13A] FIG. 13A is a diagram showing an example of a method for manufacturing the semiconductor device. [Figure 13B] FIG. 13B is a diagram showing a step subsequent to that of FIG. 13A. [Figure 13C] FIG. 13C is a diagram showing a step subsequent to that of FIG. 13B. [Figure 13D] FIG. 13D is a diagram showing a step subsequent to that of FIG. 13C. [Figure 13E] FIG. 13E is a diagram showing a step subsequent to that of FIG. 13D. [Figure 13F] FIG. 13F is a diagram showing a step subsequent to that of FIG. 13E. [Figure 14A] FIG. 14A is a diagram showing an example of a method for manufacturing the semiconductor device. [Figure 14B] FIG. 14B is a diagram showing a step subsequent to that of FIG. 14A. [Figure 14C] FIG. 14C is a diagram showing a step subsequent to that of FIG. 14B. [Figure 14D] FIG. 14D is a diagram showing a step subsequent to that of FIG. 14C. [Figure 14E] FIG. 14E is a diagram showing a step subsequent to that of FIG. 14D. [Figure 14F] FIG. 14F is a diagram showing a step subsequent to that of FIG. 14E. [Figure 15] FIG. 15 is a diagram showing a cross-sectional pattern (third form) of the first resist film. [Figure 16] FIG. 16 is a diagram showing a plane pattern (fourth embodiment) of the first resist film.

[0007] [Detailed Description] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0008] FIG. 1 is a schematic diagram showing a wafer 1 used for manufacturing a semiconductor device 100. As shown in FIG.

[0009] The wafer 1 may be a semiconductor wafer of, for example, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), diamond (C), gallium oxide (Ga2O3), or the like. The wafer 1 is formed in a flat disk shape. Of course, the wafer 1 may be formed in a flat rectangular parallelepiped shape. The wafer 1 has a first wafer main surface 2 on one side, a second wafer main surface 3 on the other side, and a wafer side surface 4 connecting the first wafer main surface 2 and the second wafer main surface 3.

[0010] The wafer 1 has a mark 5 on the wafer side surface 4 that indicates the crystal orientation of the wafer. The mark 5 may include either or both of an orientation flat and an orientation notch. The orientation flat is a cutout that is cut out linearly in a plan view. The orientation notch is a cutout that is cut out in a concave shape (e.g., a tapered shape) toward the center of the first wafer main surface 2 in a plan view.

[0011] For example, a plurality of element regions 6 and a plurality of cutting lines 7 are set on the wafer 1. Each element region 6 corresponds to a semiconductor device 100 (described later) that will be finally obtained. Each of the element regions 6 is set to have a quadrangular shape in a plan view.

[0012] In this embodiment, the multiple element regions 6 are arranged in a matrix along the first direction X and the second direction Y in a plan view. The multiple element regions 6 are arranged at intervals inward from the periphery of the first wafer main surface 2 in a plan view. The multiple lines to cut 7 are arranged in a lattice shape extending along the first direction X and the second direction Y to partition the multiple element regions 6.

[0013] Fig. 2 is an enlarged view of a main part of the wafer 1 in Fig. 1. Referring to Fig. 2, the lines to cut 7 are formed as band-like regions of a certain width. The lines to cut 7 may also be referred to as "regions to cut". A determination mark region 8 is formed in the lines to cut 7. In the determination mark region 8, a determination mark is formed for determining the presence or absence of patterning deviation during the formation of an element structure.

[0014] For example, in the process of creating an element structure in the element region 6, multiple layers are stacked on the first wafer main surface 2. Impurity regions, wiring layers, contact holes, etc. are formed in each layer in a pattern as designed. Each layer is patterned (for example, by photolithography) independently of the others. Since any misalignment between upper and lower layers can cause problems such as poor connections, it is necessary to determine whether or not there is any misalignment between the layers. The determination marks are used to determine whether or not there is any misalignment.

[0015] In this embodiment, a plurality of determination mark regions 8 are formed on the line to cut 7. The plurality of determination mark regions 8 are aligned along the length direction of the line to cut 7 in a portion sandwiched between adjacent element regions 6. One determination mark region 8 is assigned to a determination mark for misalignment of a set of upper and lower consecutive layers. For example, one determination mark region 8 is assigned to a determination mark for misalignment between the first layer and the second layer, and another determination mark region 8 is assigned to a determination mark for misalignment between the second layer and the third layer.

[0016] FIG. 3 is a diagram showing an element structure 54 formed on the wafer 1. A plurality of types of functional elements are formed in the element region 6. The plurality of types of circuit elements may form, for example, an LSI (Large Scale Integration). Examples of such functional elements include a CMIS (Complementary MIS), a BJT (Bipolar Junction Transistor), an IGBT (Insulated Gate Bipolar Transistor), a JFET (Junction Field Effect Transistor), a non-volatile memory, a capacitor, a resistor, and the like. As an example of these element structures 54, the structure of a CMIS transistor 9 will be described in FIG. 3.

[0017] The wafer 1 includes a substrate 10 and an epitaxial layer 11. The substrate 10 may be a p-type silicon substrate. The impurity concentration of the substrate 10 is, for example, 1.0×10 13 cm -3 Above 1.0×10 20 cm -3 In this embodiment, the epitaxial layer 11 may be an n-type silicon semiconductor layer. The epitaxial layer 11 is stacked on the substrate 10. The impurity concentration of the epitaxial layer 11 may be, for example, 1.0×10 13 cm -3 Above 1.0×10 17 cm -3 It may be the following.

[0018] In the element region 6, an element isolation portion 12 is formed in the epitaxial layer 11, which divides the region on the first wafer main surface 2 into a plurality of active regions. The element isolation portion 12 may have, for example, an STI (Shallow Trench Isolation) structure. In FIG. 3, the element isolation portion 12 divides an n-side active region 15 for an n-type first MISFET 13 and a p-side active region 16 for a p-type second MISFET 14. The first MISFET 13 and the second MISFET 14 are complementarily connected to form a CMIS transistor 9.

[0019] A p-type well 17 is formed on the first wafer main surface 2 of the n-side active region 15. The impurity concentration of the p-type well 17 is higher than the impurity concentration of the epitaxial layer 11, and is, for example, 1.0×10 17 cm -3 Above 1.0×10 19 cm -3 It may be the following.

[0020] In the n-side active region 15, an n-side planar gate structure is formed on the first wafer main surface 2 of the epitaxial layer 11. The n-side planar gate structure includes an n-side gate insulating film 18 and an n-side gate electrode 19 laminated in this order from the first wafer main surface 2 side. The n-side gate insulating film 18 may include a silicon oxide film. The n-side gate insulating film 18 preferably includes a silicon oxide film made of an oxide of the epitaxial layer 11. The n-side gate electrode 19 preferably includes conductive polysilicon.

[0021] An n-type source region 20 and an n-type drain region 21 are formed at a distance from each other in the surface layer of the p-type well 17. The impurity concentrations of the n-type source region 20 and the n-type drain region 21 are higher than the impurity concentration of the p-type well 17, and are, for example, 1.0×10 19 cm -3 Above 1.0×10 21 cm -3 The n-type source region 20 and the n-type drain region 21 are formed in a self-aligned manner with respect to the n-side sidewall 22.

[0022] The n-side active region 15 further includes an n-type source extension region 23 and an n-type drain extension region 24 extending integrally from the n-type source region 20 and the n-type drain region 21, respectively. The impurity concentrations of the n-type source extension region 23 and the n-type drain extension region 24 are lower than the impurity concentrations of the n-type source region 20 and the n-type drain region 21, and are, for example, 1.0×10 18 cm -3 Above 1.0×10 21 cm-3 The n-type source extension region 23 and the n-type drain extension region 24 are formed in a self-aligned manner with respect to the n-side gate electrode 19.

[0023] The n-side active region 15 further includes a p-type source pocket implant region 25 and a p-type drain pocket implant region 26 that extend integrally from the n-type source region 20 and the n-type drain region 21, respectively. The impurity concentrations of the p-type source pocket implant region 25 and the p-type drain pocket implant region 26 are higher than that of the p-type well 17, and are, for example, 1.0×10 18 cm -3 Above 1.0×10 20 cm -3 The p-type source pocket implantation region 25 and the p-type drain pocket implantation region 26 cross the boundary between the n-side sidewall 22 and the n-side gate electrode 19, and face the n-side gate electrode 19 with the n-side gate insulating film 18 interposed therebetween.

[0024] The p-type source pocket implantation region 25 and the p-type drain pocket implantation region 26 cover the bottom and sides of the n-type source extension region 23 and the n-type drain extension region 24, respectively. In the center of the n-side active region 15, the region sandwiched between the p-type source pocket implantation region 25 and the p-type drain pocket implantation region 26 is an n-side channel region 27 formed of a part of the p-type well 17. The n-side channel region 27 is opposed to the n-side gate electrode 19 with the n-side gate insulating film 18 sandwiched therebetween.

[0025] In the p-side active region 16, a p-side planar gate structure is formed on the first wafer main surface 2 of the epitaxial layer 11. The p-side planar gate structure includes a p-side gate insulating film 28 and a p-side gate electrode 29 laminated in this order from the first wafer main surface 2 side. The p-side gate insulating film 28 may include a silicon oxide film. The p-side gate insulating film 28 preferably includes a silicon oxide film made of an oxide of the epitaxial layer 11. The p-side gate electrode 29 preferably includes conductive polysilicon.

[0026] A p-type source region 30 and a p-type drain region 31 are formed in the epitaxial layer 11 with a gap therebetween. The impurity concentrations of the p-type source region 30 and the p-type drain region 31 are higher than the impurity concentration of the n-type well, and are, for example, 1.0×10 19 cm -3 Above 1.0×10 21 cm -3 The p-type source region 30 and the p-type drain region 31 are formed in a self-aligned manner with respect to the p-side sidewall 32.

[0027] The p-side active region 16 further includes a p-type source extension region 33 and a p-type drain extension region 34 extending integrally from the p-type source region 30 and the p-type drain region 31, respectively. The impurity concentrations of the p-type source extension region 33 and the p-type drain extension region 34 are lower than the impurity concentrations of the p-type source region 30 and the p-type drain region 31, and are, for example, 1.0×10 18 cm -3 Above 1.0×10 21 cm -3 The p-type source extension region 33 and the p-type drain extension region 34 are formed in a self-aligned manner with respect to the p-side gate electrode 29.

[0028] The p-side active region 16 further includes an n-type source pocket implant region 35 and an n-type drain pocket implant region 36 that extend integrally from the p-type source region 30 and the p-type drain region 31, respectively. The impurity concentrations of the n-type source pocket implant region 35 and the n-type drain pocket implant region 36 are higher than that of the epitaxial layer 11, and may be, for example, 1.0×10 18 cm -3 Above 1.0×10 20 cm -3 The n-type source pocket implantation region 35 and the n-type drain pocket implantation region 36 cross the boundary between the p-side sidewall 32 and the p-side gate electrode 29, and face the n-side gate electrode 19 with the p-side gate insulating film 28 interposed therebetween.

[0029] The n-type source pocket implantation region 35 and the n-type drain pocket implantation region 36 cover the bottom and sides of the p-type source extension region 33 and the p-type drain extension region 34, respectively. In the center of the p-side active region 16, the region sandwiched between the n-type source pocket implantation region 35 and the n-type drain pocket implantation region 36 is a p-side channel region 37 formed of a part of the epitaxial layer 11. A p-side gate electrode 29 faces the p-side channel region 37 with a p-side gate insulating film 28 sandwiched therebetween.

[0030] An interlayer insulating layer 38 is formed on the first wafer main surface 2 of the epitaxial layer 11. The interlayer insulating layer 38 covers the entire element region 6 and the cutting line 7. The interlayer insulating layer 38 includes a plurality of insulating layers 39-41. In this embodiment, the interlayer insulating layer 38 includes a first insulating layer 39, a second insulating layer 40, and a third insulating layer 41, which are stacked in this order from the first wafer main surface 2 side. Each of the insulating layers 39-41 may include a silicon oxide film.

[0031] A first conductive layer 42 is formed on the first insulating layer 39. The first conductive layer 42 is covered with the second insulating layer 40. The first conductive layer 42 includes a first wiring layer 43 on the element region 6 side and a first outer layer 44 on the cutting line 7 side. Some of the multiple first wiring layers 43 are electrically connected to the n-type source region 20, the n-type drain region 21, the p-type source region 30, and the p-type drain region 31 through first via electrodes 45 embedded in the first insulating layer 39.

[0032] A second conductive layer 46 is formed on the second insulating layer 40. The second conductive layer 46 is covered with a third insulating layer 41. The second conductive layer 46 includes a second wiring layer 47 on the element region 6 side and a second outer layer 48 on the cutting line 7 side. Some of the multiple second wiring layers 47 are electrically connected to the first wiring layer 43 through second via electrodes 49 embedded in the second insulating layer 40.

[0033] A third conductive layer 50 is formed on the third insulating layer 41. The third conductive layer 50 includes a third wiring layer 51 on the element region 6 side and a third outer layer 52 on the cutting line 7 side. Some of the multiple third wiring layers 51 are electrically connected to the second wiring layer 47 through third via electrodes 53 embedded in the third insulating layer 41.

[0034] Next, a process for fabricating the semiconductor device 100 in the element region 6 of the wafer 1 will be described with reference to Figures 4A to 4P. Figures 4A to 4P are diagrams showing an example of a manufacturing method for the semiconductor device 100 in the order of steps. Figures 4A to 4P show a cross section of the wafer 1 corresponding to Figure 3.

[0035] 4A, after an isolation portion 12 is formed in an element region 6 of a wafer 1, an element structure 54 including a CMIS transistor 9 is formed. Various impurity regions, gate insulating films 18 and 28, and gate electrodes 19 and 29 of the CMIS transistor 9 are formed by known semiconductor manufacturing techniques.

[0036] 4B, a first insulating layer 39, as an example of a first layer, is formed on the first wafer main surface 2 so as to cover the element structure 54 including the CMIS transistor 9. The first insulating layer 39 may be formed by, for example, a CVD method.

[0037] 4C, a first via electrode 45 is embedded in the first insulating layer 39. For example, a plurality of via holes are selectively formed in the first insulating layer 39, and each via hole is backfilled with a conductive material to form the first via electrode 45. The first via electrode 45 may be formed of, for example, tungsten (W).

[0038] 4D, a first conductive layer 42 is formed on the first insulating layer 39. For example, a conductive material is deposited on the first insulating layer 39 by a sputtering method, and then the conductive material is patterned to obtain the first conductive layer 42 selectively formed on the first insulating layer 39. The first conductive layer 42 includes a first wiring layer 43 as an example of a first element pattern on the element region 6 side, and a first outer layer 44 on the cutting line 7 side.

[0039] Here, the process of forming the first conductive layer 42 will be described in more detail with reference to Figures 5A and 5B. Figures 5A and 5B are diagrams respectively showing a planar pattern and a cross-sectional pattern of the first resist film 55. Figure 5B is an enlarged view showing the structure of the line to cut 7.

[0040] 5A and 5B, the first outer layer 44 is formed in a ring shape in a plan view. The first outer layer 44 is a mark that serves as a reference for determining the positional deviation of the first resist film 55 in a later process, and may be referred to as a first reference mark 56. In this embodiment, the first reference mark 56 is a mark in a ring shape in a plan view formed on the main surface of the first insulating layer 39. The first reference mark 56 may be an endless ring shape as shown in FIG. 5A, or may be a ring shape with ends. The first reference mark 56 may be, for example, a ring shape with ends that is divided at a part (for example, four corners, etc.) of the ring in FIG. 5A. The first reference mark 56 may also be a square ring shape in a plan view as shown in FIG. 5A, or may be a circular ring shape, an elliptical ring shape, or a triangular ring shape.

[0041] 4E, a second insulating layer 40 is formed on the first insulating layer 39 so as to cover the first conductive layer 42. The second insulating layer 40 may be formed by, for example, a CVD method.

[0042] 4F, a second via electrode 49 is embedded in the second insulating layer 40. For example, a plurality of via holes are selectively formed in the second insulating layer 40, and each via hole is backfilled with a conductive material to form the second via electrode 49. The second via electrode 49 may be formed of, for example, tungsten (W).

[0043] Next, referring to FIG. 4G, a first resist film 55 is formed on the second insulating layer 40. The first resist film 55 indirectly covers the first wiring layer 43 and the first outer layer 44 via the second insulating layer 40. The first resist film 55 may be a known photoresist (either negative or positive type is possible). The thickness of the first resist film 55 may be, for example, 35000 Å or more and 40000 Å or less. For example, the material of the first resist film 55 is applied to the entire surface of the second insulating layer 40, prebaked, and then the resist material is exposed to light. The exposed resist material is developed to obtain the first resist film 55. After development, a cleaning (rinsing) step and a post-baking step may be performed as necessary.

[0044] The first resist film 55 after development has a first element side opening 57 and a first outer opening 58. The first element side opening 57 matches the pattern of the second wiring layer 47. The first outer opening 58 matches the pattern of the second outer layer 48.

[0045] Here, the first outer opening 58 will be described in detail with reference to Figures 5A and 5B. In Figure 5A, the opening portion of the first resist film 55 is shown in white, and the film portion of the first resist film 55 is filled in gray. The first outer opening 58 includes a first determination pattern 59, a first surrounding pattern 60, and a second surrounding pattern 61. The first determination pattern 59, the first surrounding pattern 60, and the second surrounding pattern 61 may be referred to as a first determination opening, a first surrounding opening, and a second surrounding opening, respectively.

[0046] The first determination pattern 59 is formed in a region overlapping the first reference mark 56 in a planar view. The region overlapping the first reference mark 56 may be a region including both a ring-shaped region coinciding with the first reference mark 56 in a planar view and an inner region of the first reference mark 56 surrounded by the ring-shaped region. In other words, the entire inner region surrounded by the outer periphery of the first reference mark 56 may be referred to as the region overlapping the first reference mark 56. In this embodiment, the first determination pattern 59 is formed in a region spaced inward from the first reference mark 56. The first determination pattern 59 may be island-shaped in a planar view.

[0047] The first determination pattern 59 is used to check whether or not the first resist film 55 is misaligned with respect to the previously formed first wiring layer 43. For example, as shown in Fig. 5A, if a distance L1 from a center C1 of the first determination pattern 59 to a widthwise center of the ring-shaped first reference mark 56 is substantially constant along the circumferential direction of the first reference mark 56, it can be determined that there is no misalignment.

[0048] The first surrounding pattern 60 is formed in a ring shape larger than the first reference mark 56 in a plan view, and surrounds the first reference mark 56. The second surrounding pattern 61 is formed in a ring shape larger than the first surrounding pattern 60 in a plan view, and further surrounds the first surrounding pattern 60.

[0049] The first surrounding pattern 60 and the second surrounding pattern 61 are auxiliary opening patterns that suppress light interference caused by the influence of multiple element regions 6 around the line to cut 7. In each element region 6 around the line to cut 7, many functional elements are formed in addition to the CMIS transistor 9 shown in Fig. 3. Therefore, when the first determination pattern 59 is formed in the determination mark region 8, the patterning accuracy of the first determination pattern 59 may be reduced due to light interference caused by the influence of the element structure 54 in the element region 6.

[0050] 6A and 6B, in an embodiment in which only first determination pattern 59 is formed as first outer opening 58, the accuracy of the exposure process may decrease due to interference from the surrounding light, and the taper angle θ of the sidewall of first determination pattern 59 may vary. Therefore, a position of center C1 of first determination pattern 59 that is shifted from the actual center C1 may be erroneously image-recognized as center C1', and may be determined to be misaligned. In particular, when first resist film 55 is relatively thick, such as between 35,000 Å and 40,000 Å, the variation in taper angle θ becomes significant.

[0051] In contrast, as shown in Figures 5A and 5B, if a first surrounding pattern 60 and a second surrounding pattern 61 are formed to surround the first determination pattern 59, it is possible to suppress the interference of light due to the influence of the element structure 54 in the element region 6. This makes it possible to make the taper angle θ in the first determination pattern 59 constant. As a result, it is possible to improve the accuracy of misalignment determination. Note that while only one of the first surrounding pattern 60 and the second surrounding pattern 61 may be used, by doubly surrounding the first determination pattern 59, it is possible to further improve the accuracy of misalignment determination.

[0052] Next, referring to FIG. 4H, a second conductive layer 46 is formed on the second insulating layer 40. For example, a conductive material is deposited on the second insulating layer 40 via the first resist film 55 by a sputtering method. This forms the second conductive layer 46 made of the conductive material deposited inside the first element side opening 57 and the first outer opening 58. The second conductive layer 46 includes a second wiring layer 47 as an example of the second element pattern on the element region 6 side, and a second outer layer 48 on the cutting line 7 side. Next, referring to FIG. 4I, the first resist film 55 is removed.

[0053] Here, the process of forming the second conductive layer 46 will be described in more detail with reference to Figures 7A and 7B. Figures 7A and 7B are diagrams respectively showing a planar pattern and a cross-sectional pattern of the second resist film 62. Figure 7B is an enlarged view showing the structure of the line to cut 7.

[0054] 7A and 7B, the second outer layer 48 includes a second reference mark 63, a first peripheral mark 64, and a second peripheral mark 65. The second reference mark 63 matches the planar shape of the first determination pattern 59 and may be an island shape in a planar view. The first peripheral mark 64 matches the planar shape of the first peripheral pattern 60 and is formed in a ring shape larger than the second reference mark 63 in a planar view, surrounding the second reference mark 63. The second peripheral mark 65 matches the planar shape of the second peripheral pattern 61 and is formed in a ring shape larger than the first peripheral mark 64 in a planar view, further surrounding the first peripheral mark 64.

[0055] 4J, a third insulating layer 41 is formed on the second insulating layer 40 so as to cover the second conductive layer 46. The third insulating layer 41 may be formed by, for example, a CVD method.

[0056] 4K, a third via electrode 53 is embedded in the third insulating layer 41. For example, a plurality of via holes are selectively formed in the third insulating layer 41, and each via hole is backfilled with a conductive material to form the third via electrode 53. The third via electrode 53 may be formed of, for example, tungsten (W).

[0057] Next, referring to FIG. 4L, a second resist film 62 is formed on the third insulating layer 41. The second resist film 62 indirectly covers the second wiring layer 47 and the second outer layer 48 through the third insulating layer 41. The second resist film 62 may be a known photoresist (either negative or positive). The thickness of the second resist film 62 may be, for example, 35000 Å or more and 40000 Å or less. For example, the material of the second resist film 62 is applied to the entire surface of the third insulating layer 41, prebaked, and then the resist material is exposed to light. The exposed resist material is developed to obtain the second resist film 62. After development, a cleaning (rinsing) step and a post-baking step may be performed as necessary.

[0058] The second resist film 62 after development has a second element side opening 66 and a second outer opening 67. The second element side opening 66 matches the pattern of the third wiring layer 51. The second outer opening 67 matches the pattern of the third outer layer 52.

[0059] 7A and 7B, the second outer opening 67 will be described in detail. In Fig. 7A, the opening portion of the second resist film 62 is shown in white, and the film portion of the second resist film 62 is painted gray. The second outer opening 67 includes a second determination pattern 68, a first surrounding pattern 69, and a second surrounding pattern 70.

[0060] Second determination pattern 68 is formed in a region that overlaps with second reference mark 63 in plan view. In this embodiment, second determination pattern 68 is formed so as to cover the entire second reference mark 63. Second determination pattern 68 may be in the shape of an island that is larger than second reference mark 63 in plan view.

[0061] The second determination pattern 68 is used to check whether or not the second resist film 62 is misaligned with respect to the previously formed second wiring layer 47. For example, as shown in Fig. 7A, if a distance L2 from a center C2 of the second reference mark 63 to a sidewall of the second determination pattern 68 is substantially constant along the circumferential direction of the second determination pattern 68, it can be determined that there is no misalignment.

[0062] The first surrounding pattern 69 is formed in a ring shape larger than the second reference mark 63 in a plan view, and surrounds the second reference mark 63. The second surrounding pattern 70 is formed in a ring shape larger than the first surrounding pattern 60 in a plan view, and further surrounds the first surrounding pattern 69.

[0063] The first surrounding pattern 69 and the second surrounding pattern 70, like the first surrounding pattern 60 and the second surrounding pattern 61 of the first resist film 55, are auxiliary opening patterns that suppress light interference caused by the influence of multiple element regions 6 around the planned cutting line 7.

[0064] Therefore, if the first surrounding pattern 69 and the second surrounding pattern 70 are formed to surround the second judgment pattern 68, it is possible to suppress the interference of light due to the influence of the element structure 54 in the element region 6. This makes it possible to make the taper angle θ in the second judgment pattern 68 constant. As a result, it is possible to improve the accuracy of the positional deviation judgment. Note that although only one of the first surrounding pattern 69 and the second surrounding pattern 70 may be used, by doubly surrounding the second judgment pattern 68, it is possible to further improve the accuracy of the positional deviation judgment.

[0065] Next, referring to FIG. 4M, a third conductive layer 50 is formed on the third insulating layer 41. For example, a conductive material is deposited on the third insulating layer 41 via the second resist film 62 by a sputtering method. This forms a third conductive layer 50 made of the conductive material deposited inside the second element side opening 66 and the second outer opening 67. The third conductive layer 50 includes a third wiring layer 51 on the element region 6 side and a third outer layer 52 on the cutting line 7 side. Next, referring to FIG. 4N, the second resist film 62 is removed.

[0066] Next, referring to Fig. 4O, a surface insulating film 71 is formed on the third insulating layer 41 so as to cover the third conductive layer 50. The surface insulating film 71 may be formed by, for example, a CVD method. The surface insulating film 71 may be, for example, a silicon oxide film, a silicon nitride film, or the like. Thereafter, openings are selectively formed in the surface insulating film 71, thereby forming pads 72 for external connection in each element region 6. The state of the first wafer main surface 2 of the wafer 1 after the pads 72 are formed is shown in Fig. 8.

[0067] Fig. 8 is an enlarged view of a main part of the wafer 1 (wafer device 200) after the element structure 54 is formed. Fig. 9 is an enlarged view of a part surrounded by a two-dot chain line IX in Fig. 8.

[0068] 8 and 9, the wafer device 200 is the wafer 1 on which an element structure 54 is formed in each element region 6. The wafer device 200 may be the wafer 1 after the element structures 54 are formed and before cutting along the cutting lines 7. In the wafer device 200, semiconductor devices 100 having the same element structures 54 are fabricated in each element region 6. In the determination mark region 8 between adjacent semiconductor devices 100 (element regions 6), a reference mark used for determining misalignment of each layer of the resist film remains.

[0069] 9, the first reference mark 56 used to determine the misalignment of the first resist film 55 and the second outer layer 48 deposited and formed in the first outer opening 58 of the first resist film 55 remain in the determination mark region 8A at the top of the page. Also, the second reference mark 63 used to determine the misalignment of the second resist film 62 and the third outer layer 52 deposited and formed in the second outer opening 67 of the second resist film 62 remain in the determination mark region 8B adjacent to the lower side of the determination mark region 8A.

[0070] 4P, the wafer 1 (wafer devices 200) is cut along the lines to cut 7. Through the steps including those described above, a plurality of semiconductor devices 100 are manufactured from one wafer 1.

[0071] Fig. 10 is a schematic plan view of the semiconductor device 100. Fig. 11 is an enlarged view of a portion surrounded by a two-dot chain line XI in Fig. 10.

[0072] 10 and 11, a semiconductor device 100 includes a chip 74 having an element region 6 and an outer periphery region 73, a plurality of element structures 54 formed in the element region 6, and pads 72 electrically connected to each element structure 54. The chip 74 is formed by the above-mentioned substrate 10 and epitaxial layer 11. The outer periphery region 73 surrounding the element region 6 is a remaining portion of the above-mentioned line 7 to cut.

[0073] In the peripheral region 73, a portion of the second outer layer 48 that was not removed when the wafer 1 was cut is formed as a peripheral pattern 75. For example, as shown in Fig. 11, the peripheral pattern 75 is formed in the shape of a ring having ends. In this embodiment, the peripheral pattern 75 includes a first peripheral pattern 76 and a second peripheral pattern 77 that surrounds the first peripheral pattern 76.

[0074] One end 78 and the other end 79 of the first outer peripheral pattern 76 are exposed to the outside from the same end face 84 of the chip 74, and an intermediate portion 80 between the one end 78 and the other end 79 is disposed more inward than the end face 84 of the chip 74. Similarly, one end 81 and the other end 82 of the second outer peripheral pattern 77 are exposed to the outside from the same end face 84 of the chip 74, and an intermediate portion 83 between the one end 81 and the other end 82 is disposed more inward than the end face 84 of the chip 74.

[0075] Although FIG. 11 shows only the second outer layer 48, a portion of the third outer layer 52 may also remain in the outer peripheral region 73.

[0076] 12A and 12B are diagrams showing measurement results of misalignment of a resist film for Sample 1. In Fig. 12A and 12B, each rectangular block indicates an area exposed by one light irradiation (one shot) by an exposure device (stepper).

[0077] Sample 1 in Fig. 12A uses a resist on which a first determination pattern 59 and a first surrounding pattern 60 surrounding it are formed for misalignment determination, following Fig. 5A and Fig. 5B. Sample 2 in Fig. 12B uses a resist on which only a first determination pattern 59 is formed for misalignment determination, following Fig. 6A and Fig. 6B.

[0078] The misalignment in the cross-hatched areas in FIG. 12A and FIG. 12B was compared. The amount and direction of misalignment are indicated by arrows extending from each area. The longer the arrow, the greater the amount of misalignment in that area. More specifically, the residual error in each area was measured, and the measurement results were represented by the arrows in each area. Then, by comparing the lengths of the arrows in FIG. 12A and FIG. 12B, it was determined which area had the greater amount of misalignment. Here, the "residual error" may indicate the amount of misalignment of a component that cannot be corrected any more, other than the shift misalignment, rotation misalignment, magnification misalignment, etc. of the stepper.

[0079] 12A and 12B, it can be seen that Sample 1, in which the first surrounding pattern 60 is formed, has a smaller residual error than Sample 2. As an example, the residual error of Sample 2 in a certain area was reduced to about ⅓ by adopting the configuration of Sample 1.

[0080] Next, another embodiment of an example of a manufacturing method for the semiconductor device 100 will be described with reference to Figures 13A to 13F. In Figures 13A to 13F, structures similar to those shown in Figures 4A to 4P are given the same reference symbols and descriptions thereof will be omitted. A major difference between the steps of Figures 13A to 13F and those of Figures 4A to 4P is that in the steps of Figures 13A to 13F, a first fiducial mark opening 85 and a first fiducial mark embedding layer 86 formed in the second insulating layer 40 are used as a fiducial mark for determining misalignment of the first resist film 55.

[0081] More specifically, first, referring to FIG. 13A, the same steps as those in FIG. 4A to FIG. 4E are performed. Next, referring to FIG. 13B, a first opening 87 is formed in a second insulating layer 40 as an example of a first layer. The first opening 87 includes a first contact opening 88 on the element region 6 side and a first reference mark opening 85 on the line to cut 7 side. The first opening 87 is formed by selectively etching the second insulating layer 40. The first wiring layer 43 is exposed from the first contact opening 88, and the first outer layer 44 is exposed from the first reference mark opening 85. The first reference mark opening 85 may be ring-shaped in plan view, similar to the above-mentioned first reference mark 56 (see FIG. 5A).

[0082] 13C, a conductive material is deposited on second insulating layer 40, thereby filling first contact opening 88 and first reference mark opening 85 with the conductive material. This results in second via electrode 49 filled in first contact opening 88 and first reference mark filling layer 86 filled in first reference mark opening 85. Since first reference mark filling layer 86 is filled in first reference mark opening 85, it is formed in a ring shape in a plan view.

[0083] 13D, a third insulating layer 41 is formed on the second insulating layer 40 so as to cover the second via electrode 49 and the first reference mark embedding layer 86. The third insulating layer 41 may be formed by, for example, a CVD method.

[0084] Next, referring to FIG. 13E, a first resist film 55 is formed on the third insulating layer 41. The first resist film 55 indirectly covers the second via electrode 49 and the first reference mark embedding layer 86 through the third insulating layer 41. The first resist film 55 is formed in the same manner as in the step of FIG. 4G, and is exposed and developed. After development, the first resist film 55 has a first element side opening 57 and a first outer opening 58.

[0085] 13E, similarly to the first resist film 55 shown in FIGS. 5A and 5B, the first outer opening 58 includes a first determination pattern 59, a first surrounding pattern 60, and a second surrounding pattern 61. The misalignment of the first resist film 55 can be determined based on the positional relationship between the first determination pattern 59 and the first reference mark embedding layer 86. Moreover, since the first surrounding pattern 60 and the second surrounding pattern 61 are formed to surround the first determination pattern 59, the accuracy of misalignment determination can be improved.

[0086] Next, referring to FIG. 13F, the third insulating layer 41 is selectively etched through the first resist film 55 to form a second opening 89. The second opening 89 includes a second contact opening 90 on the element region 6 side and a second reference mark opening 91 on the cutting line 7 side. The second contact opening 90 is an opening for the third via electrode 53. The second reference mark opening 91 is an opening for an embedded electrode corresponding to the second reference mark 63, the first perimeter mark 64, and the second perimeter mark 65 in FIGS. 7A and 7B. Thereafter, the same steps as those in FIGS. 4H to 4P are performed to obtain individual semiconductor devices 100.

[0087] Next, with reference to Figures 14A to 14F, still another embodiment of an example of a manufacturing method for the semiconductor device 100 will be described. In Figures 14A to 14F, structures similar to those shown in Figures 4A to 4P are given the same reference numerals and descriptions thereof will be omitted. A major difference between the process of Figures 14A to 14F and the process of Figures 4A to 4P is that in the process of Figures 14A to 14F, the positional deviation of the first resist film 55 is determined not when the wiring layer is formed but when the impurity region and the gate structure are formed.

[0088] 14A, after the element isolation portion 12 and the p-type well 17 are formed in the element region 6 of the wafer 1, impurities are selectively implanted into the first wafer main surface 2 through a resist film 92. The resist film 92 has an opening 93 that selectively exposes the first wafer main surface 2. The opening 93 includes an element side opening 94 on the element region 6 side and an outer opening 95 on the cutting line 7 side.

[0089] By impurity implantation through the element side opening 94, a predetermined pattern of p-type source pocket implantation regions 25, p-type drain pocket implantation regions 26, n-type source pocket implantation regions 35 and n-type drain pocket implantation regions 36 are formed on the first wafer main surface 2. On the other hand, by impurity implantation through the outer opening 95, a predetermined pattern of fiducial mark impurity regions 96 are formed on the first wafer main surface 2. The fiducial mark impurity regions 96 may be ring-shaped in plan view, similar to the above-mentioned first fiducial mark 56 (see FIG. 5A).

[0090] 14B, a reference conductive layer 97 as an example of a first layer is formed on the first wafer main surface 2. For example, a conductive material is deposited on the first wafer main surface 2 via the resist film 92 by a sputtering method. This forms a reference conductive layer 97 made of the conductive material deposited inside the element-side opening 94 and the outer opening 95. The reference conductive layer 97 in the element-side opening 94 is formed in a ring shape in a plan view.

[0091] 14C, the resist film 92 is removed, and then the reference conductive layer 97 on the element region 6 side is removed. As a result, the reference conductive layer 97 is selectively left as a reference mark 99 on the line 7 to cut.

[0092] 14D, a base insulating film 98 is formed on the first wafer main surface 2 so as to cover the reference conductive layer 97. The base insulating film 98 is a film that serves as a base for the p-side gate insulating film 28 and the n-side gate insulating film 18.

[0093] Next, referring to FIG. 14E, a first resist film 55 is formed on the base insulating film 98. The first resist film 55 indirectly covers the reference mark 99 via the base insulating film 98. The first resist film 55 is formed in the same manner as in the step of FIG. 4G, and is exposed and developed. After development, the first resist film 55 has a first element side opening 57 and a first outer opening 58.

[0094] 14E, like the first resist film 55 shown in FIGS. 5A and 5B, the first outer opening 58 includes a first determination pattern 59, a first surrounding pattern 60, and a second surrounding pattern 61. The misalignment of the first resist film 55 can be determined based on the positional relationship between the first determination pattern 59 and the reference mark 99. Moreover, since the first surrounding pattern 60 and the second surrounding pattern 61 are formed to surround the first determination pattern 59, the accuracy of misalignment determination can be improved.

[0095] 14F, the base insulating film 98 is selectively etched via the first resist film 55 to form the p-side gate insulating film 28 and the n-side gate insulating film 18 in the element region 6. Thereafter, an element structure 54 including a CMIS transistor 9 is formed, and then the same steps as those in FIGS. 4A to 4P are performed to obtain individual semiconductor devices 100.

[0096] Although embodiments of the present disclosure have been described, the present disclosure may be embodied in other forms.

[0097] For example, in the embodiment described above, the first resist film 55 has the first determination pattern 59 as a pattern for determining misalignment, and has the first surrounding pattern 60 and the second surrounding pattern 61 as auxiliary patterns for suppressing optical interference. The first determination pattern 59, the first surrounding pattern 60, and the second surrounding pattern 61 are all opening patterns formed in the first resist film 55.

[0098] 15, the first resist film 55 may have a mesa pattern as a pattern for determining misalignment and an auxiliary pattern. That is, the first resist film 55 may have a pattern opposite to that of FIG. 5A and FIG. 5B. For example, the first resist film 55 may have a first determination mesa pattern 101 corresponding to the first determination pattern 59, a first surrounding mesa pattern 102 corresponding to the first surrounding pattern 60, and a second surrounding mesa pattern 103 corresponding to the second surrounding pattern 61. In this case, if the distance L1 from the center C1 of the first determination mesa pattern 101 to the width direction center of the ring-shaped first reference mark 56 is substantially constant in the circumferential direction of the first reference mark 56, it can be determined that there is no misalignment.

[0099] Furthermore, in the above embodiment, the first reference mark 56 is ring-shaped in plan view, but as shown in FIG. 16, it may be formed in an island shape in plan view.

[0100] In the above embodiment, the positional deviation of first resist film 55 is determined based on whether distance L1 from center C1 of first determination pattern 59 to the widthwise center of ring-shaped first reference mark 56 is constant, but the deviation may be determined by other methods. For example, the positional deviation may be determined based on whether the center of first determination pattern 59 and the center of first reference mark 56 (the intersection of a pair of diagonal lines in FIG. 5A) coincide with each other.

[0101] In addition, in the above-described embodiment, a double-surrounding structure of the first surrounding pattern 60 and the second surrounding pattern 61 was used as an auxiliary pattern for suppressing light interference, but a third surrounding pattern, a fourth surrounding pattern, ... an nth surrounding pattern (n is a natural number) may also be formed.

[0102] In the above embodiment, only the CMIS transistor 9 is shown as an example of the element structure 54 formed on the wafer 1, but various structures including various functional elements can be adopted as the element structure 54.

[0103] The embodiments of the present disclosure are illustrative in all respects and should not be construed as limiting, and are intended to include modifications in all respects.

[0104] The following characteristics can be extracted from the description of this specification and the drawings.

[0105] [Appendix 1-1] a first step of forming a first layer (39, 40, 99) on a main surface of a wafer (1) on which a reference mark (56) for measuring a positional deviation of a resist (55) relative to a first element pattern (25, 26, 35, 36, 43) for a semiconductor element (9, 54) is formed; a second step of forming a resist (55) on the first layer (39, 40, 99) so as to cover the reference mark (56) and the first element pattern (25, 26, 35, 36, 43); a third step of forming, by exposing and developing the resist (55), a position shift determination pattern (59, 101) overlapping the reference mark (56) in a plan view, surrounding patterns (60, 61, 102, 103) surrounding the position shift determination pattern (59, 101) in a plan view, and a second element pattern (47) for the semiconductor element (9, 54), using the resist (55); and a fourth step of determining a misalignment of the second element pattern (47) with respect to the first element pattern (25, 26, 35, 36, 43) by measuring the relative position of the misalignment determination pattern (59, 101) with respect to the reference mark (56).

[0106] According to this method, since the surrounding patterns (60, 61, 102, 103) surrounding the position shift determination pattern (59, 101) are formed outside the reference mark (56), it is possible to suppress optical interference caused by the influence of the surrounding element structures, thereby improving the accuracy of determining the position shift of the resist (55) relative to the first element patterns (25, 26, 35, 36, 43).

[0107] [Appendix 1-2] In the third step, a plurality of the surrounding patterns (61, 103) including a first surrounding pattern (60, 102) surrounding the position shift determination pattern (59, 101) and a second surrounding pattern (61, 103) further surrounding the first surrounding pattern (60, 102) are formed using the resist (55).

[0108] According to this method, the position shift determination pattern (59, 101) is surrounded by at least the first surrounding pattern (60, 102) and the second surrounding pattern (61, 103) in a double manner, thereby making it possible to further improve the accuracy of position shift determination.

[0109] [Appendix 1-3] The wafer (1) includes a plurality of element regions (6) in which the semiconductor elements (9, 54) are formed, and a region to be cut (7) that partitions the plurality of element regions (6), The method for manufacturing a semiconductor device (100) according to claim 1-2, wherein the reference mark (56) is formed in the region to be cut (7).

[0110] [Appendix 1-4] The method for manufacturing the semiconductor device (100) according to claim 1-2 or 1-3, wherein the position shift determination pattern (59), the first surrounding pattern (60), and the second surrounding pattern (61) are all opening patterns formed in the resist (55).

[0111] [Appendix 1-5] The method for manufacturing the semiconductor device (100) according to claim 1-2 or 1-3, wherein the position shift determination pattern (101), the first surrounding pattern (102), and the second surrounding pattern (103) are all mesa patterns defined by an opening pattern formed in the resist (55).

[0112] [Appendix 1-6] The method for producing a semiconductor device (100) according to any one of Appendix 1-1 to Appendix 1-5, wherein the resist (55) has a thickness of 35000 Å or more and 40000 Å or less.

[0113] [Appendix 1-7] The first step comprises: a first step of forming an insulating layer (39) as the first layer (39) on a main surface of the wafer (1); A method for manufacturing a semiconductor device (100) according to any one of Appendices 1-1 to 1-6, comprising a second step of selectively depositing a conductive material on the insulating layer (39) to form element wiring (43) corresponding to the first element pattern (43) and a reference mark conductive layer (56) corresponding to the reference mark (56).

[0114] [Appendix 1-8] In the first step, the reference mark conductive layer (56) is formed in a ring shape in a plan view, The method for manufacturing a semiconductor device (100) according to appendix 1-7, wherein in the third step, the position shift determination pattern (59, 101) having an island shape in a planar view is formed on an area surrounded by the reference mark conductive layer (56), and the surrounding patterns (60, 61, 102, 103) are formed in a ring shape in a planar view surrounding the reference mark conductive layer (56).

[0115] [Appendix 1-9] The first step comprises: a first step of forming an insulating layer (40) as the first layer (40) on a main surface of the wafer (1); a second step of selectively removing the insulating layer (40) to form an element wiring opening (88) corresponding to the first element pattern (43) and a reference mark opening (85) corresponding to the reference mark (56); A method for manufacturing a semiconductor device (100) according to any one of Appendices 1-1 to 1-6, comprising a third step of embedding an element buried wiring (49) in the element wiring opening (88) and embedding a reference mark embedding layer (86) in the reference mark opening (85).

[0116] [Appendix 1-10] In the first step, the reference mark embedding layer (86) is formed in a ring shape in a plan view, The method for manufacturing a semiconductor device (100) according to appendix 1-9, wherein in the third step, the position shift determination pattern (59, 101) having an island shape in a planar view is formed on an area surrounded by the reference mark embedding layer (86), and the surrounding patterns (60, 61, 102, 103) are formed in a ring shape in a planar view surrounding the reference mark embedding layer (86).

[0117] [Appendix 1-11] The first step comprises: a first step of selectively injecting impurities into a main surface of the wafer (1) to form element impurity regions (25, 26, 35, 36) corresponding to the first element patterns (25, 26, 35, 36) and a reference mark impurity region (96); A method for manufacturing a semiconductor device (100) according to any one of Appendices 1-1 to 1-6, comprising a second step of forming the reference mark (99) by selectively leaving the first layer (99) on the reference mark impurity region (96) on the main surface of the wafer (1).

[0118] [Appendix 1-12] In the first step, the reference mark (99) is formed in a ring shape in a plan view, The method for manufacturing a semiconductor device (100) according to appendix 1-11, wherein in the third step, the position shift determination pattern (59, 101) having an island shape in a planar view is formed on an area surrounded by the reference mark (99), and the surrounding pattern (60, 61, 102, 103) is formed in a ring shape in a planar view surrounding the reference mark (99).

[0119] [Appendix 1-13] A wafer body (1) having a plurality of element regions (6) and a region to be cut (7) that divides the plurality of element regions (6); a first element pattern (43) formed in each of the element regions (6); an outer mark (56) formed in the intended cutting region (7) in the same layer as the first element pattern (43); a second element pattern (47) formed in an upper region of the first element pattern (43); A semiconductor wafer (200) including an outer pattern (63) formed in the intended cutting area (7) in the same layer as the second element pattern (47) and overlapping the outer mark (56) in a planar view, and surrounding patterns (64, 65) surrounding the first outer mark in a planar view.

[0120] [Appendix 1-14] a chip (74) having an element region (6) and an outer peripheral region (73); An element pattern (47) formed in the element region (6); a peripheral pattern (75, 76, 77) formed in the peripheral region (73) in the same layer as the element pattern (47) and formed in a ring shape having ends in a plan view; The outer peripheral pattern (75, 76, 77) has one end (78, 81) and the other end (79, 82) of the terminated ring exposed to the outside from the same end face (84) of the chip, and a portion (80, 83) between the one end (78, 81) and the other end (79, 82) is positioned inside the end face (84) of the chip (74), in this semiconductor device (100).

[0121] [Appendix 1-15] The semiconductor device (100) according to appendix 1-14, wherein the peripheral patterns (75, 76, 77) include a first peripheral pattern (76) and a second peripheral pattern (77) surrounding the first peripheral pattern (76). [Explanation of symbols]

[0122] 1: Wafer 2: First wafer main surface 3: Second wafer main surface 4: Wafer side 5: Landmark 6: Element area 7: Cutting line 8: Judgment mark area 8A: Judgment mark area 8B: Judgment mark area 9: CMIS transistor 10: Substrate 11: Epitaxial layer 12: Element isolation section 15: n-side active area 16: p-side active area 17: p-type well 18: n-side gate insulating film 19: n-side gate electrode 20: n-type source region 21: n-type drain region 22: n-side sidewall 23: n-type source extension region 24: n-type drain extension region 25: p-type source pocket implantation region 26: p-type drain pocket implant region 27: n-side channel region 28: p-side gate insulating film 29: p-side gate electrode 30: p-type source region 31: p-type drain region 32: p-side sidewall 33: p-type source extension region 34: p-type drain extension region 35: n-type source pocket implantation region 36: n-type drain pocket implantation region 37: p-channel region 38: Interlayer insulation layer 39: First insulating layer 40: Second insulating layer 41: Third insulating layer 42: First conductive layer 43: 1st wiring layer 44: 1st outer layer 45: First via electrode 46: Second conductive layer 47: 2nd wiring layer 48: 2nd outer layer 49: Second via electrode 50: Third conductive layer 51: 3rd wiring layer 52 :Third outer layer 53: Third via electrode 54: Element structure 55: First resist film 56: First reference mark 57: First element side opening 58: 1st outer opening 59: First judgment pattern 60: First surrounding pattern 61: Second surrounding pattern 62: Second resist film 63: Second reference mark 64: First surrounding mark 65: Second surrounding mark 66: Second element side opening 67:Second outer opening 68: Second judgment pattern 69: First surrounding pattern 70: Second surrounding pattern 71: Surface insulating film 72: Pad 73: Outer area 74: Tip 75: Outer pattern 76: First outer pattern 77: Second outer pattern 78:One end 79:Other end 80: Middle section 81:One end 82:Other end 83: Middle section 84: End face 85: First reference mark aperture 86: First reference mark embedding layer 87: First opening 88: First contact opening 89: Second opening 90: Second contact opening 91: Second reference mark aperture 92: Resist film 93 :Aperture 94: Element side opening 95:Outside opening 96: Impurity region for reference mark 97: Reference conductive layer 98: Base insulating film 99: Reference mark 100: Semiconductor device 101: First judgment mesa pattern 102: First surrounding mesa pattern 103: Second surrounding mesa pattern 200: Wafer device

Claims

1. a first step of forming a first layer on a main surface of a wafer, the first layer having a reference mark for measuring a positional deviation of a resist relative to a first element pattern for a semiconductor element; a second step of forming a resist on the first layer so as to cover the reference mark and the first element pattern; a third step of exposing and developing the resist to form, by using the resist, a position shift determination pattern that overlaps the reference mark in a plan view, a surrounding pattern that surrounds the position shift determination pattern in a plan view, and a second element pattern for the semiconductor element; a fourth step of determining misalignment of the second element pattern with respect to the first element pattern by measuring a relative position of the misalignment determination pattern with respect to the reference mark.

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the third step, a plurality of the surrounding patterns including a first surrounding pattern surrounding the position shift determination pattern and a second surrounding pattern further surrounding the first surrounding pattern are formed using the resist.

3. the wafer includes a plurality of element regions in which the semiconductor elements are to be formed, and regions to be cut that partition the plurality of element regions; The method for manufacturing a semiconductor device according to claim 2 , wherein the reference mark is formed in the region to be cut.

4. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the position shift determination pattern, the first peripheral pattern, and the second peripheral pattern are all opening patterns formed in the resist.

5. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the position shift determination pattern, the first peripheral pattern, and the second peripheral pattern are all mesa patterns defined by an opening pattern formed in the resist.

6. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the resist has a thickness of 35,000 Å or more and 40,000 Å or less.

7. The first step comprises: a first step of forming an insulating layer as the first layer on a main surface of the wafer; The method for manufacturing a semiconductor device according to any one of claims 1 to 6, further comprising a second step of selectively depositing a conductive material on the insulating layer to form element wiring corresponding to the first element pattern and a reference mark conductive layer corresponding to the reference mark.

8. In the first step, the reference mark conductive layer is formed in a ring shape in a plan view, 8. The method for manufacturing a semiconductor device according to claim 7, wherein in the third step, the position shift determination pattern having an island shape in a planar view is formed on an area surrounded by the reference mark conductive layer, and the surrounding pattern is formed in a ring shape in a planar view surrounding the reference mark conductive layer.

9. The first step comprises: a first step of forming an insulating layer as the first layer on a main surface of the wafer; a second step of selectively removing the insulating layer to form an element wiring opening corresponding to the first element pattern and a reference mark opening corresponding to the reference mark; 7. The method for manufacturing a semiconductor device according to claim 1, further comprising a third step of embedding an element buried wiring in said element wiring opening and embedding a fiducial mark embedding layer in said fiducial mark opening.

10. In the first step, the reference mark embedding layer is formed in a ring shape in a plan view, 10. The method for manufacturing a semiconductor device according to claim 9, wherein in the third step, the position shift determination pattern having an island shape in a planar view is formed on an area surrounded by the reference mark embedded layer, and the surrounding pattern is formed in a ring shape in a planar view surrounding the reference mark embedded layer.

11. The first step comprises: a first step of selectively injecting impurities into a main surface of the wafer to form an element impurity region corresponding to the first element pattern and a reference mark impurity region; 7. The method for manufacturing a semiconductor device according to claim 1, further comprising a second step of forming the reference mark by selectively leaving the first layer on the reference mark impurity region of the main surface of the wafer.

12. In the first step, the reference mark is formed in a ring shape in a plan view, 12. The method for manufacturing a semiconductor device according to claim 11, wherein in the third step, the position shift determination pattern having an island shape in a planar view is formed on an area surrounded by the reference mark, and the surrounding pattern is formed in a ring shape in a planar view surrounding the reference mark.

13. a wafer body having a plurality of element regions and a region to be cut that divides the plurality of element regions; a first element pattern formed in each of the element regions; an outer mark formed in the intended cutting region in the same layer as the first element pattern; a second element pattern formed in an upper region of the first element pattern; a semiconductor wafer including: an outer pattern formed in the region to be cut in the same layer as the second element pattern, the outer pattern overlapping the outer mark in a planar view; and a surrounding pattern surrounding the first outer mark in a planar view.

14. a chip having an element region and a peripheral region; An element pattern formed in the element region; a peripheral pattern formed in the same layer as the element pattern in the peripheral region and shaped like a ring having ends in a plan view; A semiconductor device in which the outer peripheral pattern has one end and the other end of the end ring exposed to the outside from the same end face of the chip, and the portion between the one end and the other end is positioned inside the end face of the chip.

15. The semiconductor device according to claim 14 , wherein the perimeter pattern includes a first perimeter pattern and a second perimeter pattern surrounding the first perimeter pattern.

Images