Manufacturing process for silicon carbide power device having variable dopant concentration
Patent Information
- Application Number
- JP2024126663
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-07-22
- Filing Date
- 2024-08-02
- Publication Date
- 2025-03-05
Smart Images
Figure 2025028820000001_ABST
Abstract
Description
[Technical field]
[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to Italian Patent Application No. 102023000016734, filed on August 4, 2023, and entitled "PROCESSO DI FABBRICAZIONE PER DISPOSITIVI DI POTENZA IN CARBURO DI SILICIO CON CONCENTRAZIONE DI DROGANTE VARIABILE", which is incorporated by reference herein to the fullest extent permitted by law.
[0002] FIELD OF THEINVENTION Exemplary embodiments of the present disclosure relate to a manufacturing process for silicon carbide power devices having variable dopant concentrations. [Background technology]
[0003] As is known, semiconductor materials with a wide band gap, for example greater than 1.1 eV, a low on-state resistance, a high thermal conductivity, a high operating frequency and a high charge carrier saturation velocity make it possible to obtain electronic devices, such as diodes and transistors, with higher performance than silicon electronic devices, in particular for power applications (i.e. for operating voltages comprised for example between 600 V and 1300 V, or for certain operating conditions such as high temperatures).
[0004] In particular, it is known to obtain such electronic devices starting from wafers of silicon carbide (SiC) of one of the polytypes, for example 3C-SiC, 4H-SiC and 6H-SiC, which are distinguished by the characteristics listed above. Electronic power devices that can be obtained using a SiC type semiconductor can be, for example, vertical conduction MOSFETs or JFETs.
[0005] Ion implantation is today an integrated technique for introducing dopants into silicon carbide. In fact, due to the low diffusivity of SiC compared to other semiconductor materials (such as silicon), diffusion of dopants may not be a convenient technique to use. Furthermore, epitaxial growth may not be an effective alternative, particularly for locally confined doping.
[0006] As is known, the crystal structure of SiC, in addition to the energy and type of ions used, influences the depth distribution obtained during implantation. Indeed, so-called channeling can significantly increase the depth of penetration of dopant ions in crystalline materials compared to amorphous targets. This phenomenon can occur when the direction of the incident ion beam is substantially parallel to the main crystal axes or faces and within a well-defined and contained range (i.e. within the so-called "critical channeling angle"). In these directions, the reduction in energy loss per ion path length is smaller, with the benefit that the ions can travel deeper in the target. Indeed, when implantation is performed along the crystal axes using SiC technology, the deepest channeled ions can penetrate over distances many times greater than the range expected for the corresponding random implantation, assuming the same implantation energy is used.
[0007] It is known to use a hard implantation mask, for example of silicon oxide (SiO2), configured to locally shield the SiC die or chip during implantation, in order to form an implantation region that is locally confined both in terms of shape and doping profile. However, the applicant has found that the use of a hard mask can cause flatness problems of the layer to which it is applied after removal of the mask itself. In fact, the hard mask can cause lattice stress on the SiC substrate.
[0008] Moreover, the use of hard masks may not be compatible with the progressive increase in density of elementary cells that can be obtained on the same die as a result of the reduction in their dimensions (technical term, "miniaturization"), i.e. as a result of the reduction in the "pitch" of the device aimed at increasing the current that can be extracted from the power device during use, i.e. it may be difficult to scale. Indeed, taking into account the miniaturization of the elementary cells and their resulting mutual proximity, processes based on the use of masks may present matching problems between regions belonging to layers of the die arranged on top of each other, which may result in undesirable electrical phenomena due to a layout that does not correspond to the design specifications. In particular, the definition of areas of a SiC die with a variable doping profile for the purpose of parameterizing the electrical characteristics of the device (on-state resistance, shielding of the gate area from high electric fields, etc.) may prove to be complex using implantation masks. Summary of the Invention
[0009] As a result, it is an object of the various embodiments of the present disclosure to overcome or at least alleviate the disadvantages and limitations of the prior art.
[0010] According to various embodiments of the present disclosure, a manufacturing process is provided for silicon carbide power devices having variable dopant concentrations, as defined in the appended claims. [Brief description of the drawings]
[0011] For a better understanding of the various embodiments of the present disclosure, reference is made to the accompanying drawings, in which preferred embodiments thereof are given, by way of non-limiting examples, in which: [Figure 1] FIG. 2 is a cross-sectional view through a power device according to one embodiment of the present disclosure. [Figure 2A] 1A-1D are cross-sectional views through a semiconductor wafer at successive machining steps of a manufacturing process according to one embodiment of the present disclosure. [Figure 2B]1A-1D are cross-sectional views through a semiconductor wafer at successive machining steps of a manufacturing process according to one embodiment of the present disclosure. [Figure 2C] 1A-1D are cross-sectional views through a semiconductor wafer at successive machining steps of a manufacturing process according to one embodiment of the present disclosure. [Figure 2D] 1A-1D are cross-sectional views through a semiconductor wafer at successive machining steps of a manufacturing process according to one embodiment of the present disclosure. [Figure 2E] 1A-1D are cross-sectional views through a semiconductor wafer at successive machining steps of a manufacturing process according to one embodiment of the present disclosure. [Figure 2F] 1A-1D are cross-sectional views through a semiconductor wafer at successive machining steps of a manufacturing process according to one embodiment of the present disclosure. [Figure 2G] 1A-1D are cross-sectional views through a semiconductor wafer at successive machining steps of a manufacturing process according to one embodiment of the present disclosure. [Figure 2H] 1A-1D are cross-sectional views through a semiconductor wafer at successive machining steps of a manufacturing process according to one embodiment of the present disclosure. [Figure 2I] 1A-1D are cross-sectional views through a semiconductor wafer at successive machining steps of a manufacturing process according to one embodiment of the present disclosure. [Diagram 3] FIG. 2C is a simplified block diagram of the process of FIGS. 2A-2I. [Figure 4] 1A-1D are cross-sectional views through power devices according to different embodiments of the present disclosure. [Diagram 5] FIG. 5 is an enlarged detail view of FIG. [Figure 6] 1A-1D are simplified block diagrams of manufacturing processes according to different embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0012] A power device manufactured according to one embodiment of the present disclosure is partially illustrated in Figure 1 and is designated by the number 1. The power device 1 is for example a MOSFET, in particular a power MOSFET, and even more particularly a vertical conduction MOSFET obtained using Silicon Carbide (SiC) technology, housed in a die or chip not shown in the attached figures. Hereinafter, the power device 1 will consequently also be referred to interchangeably as a "MOSFET", without this implying any loss of generality.
[0013] FIG. 1 shows a cross-sectional view of a MOSFET 1 in a reference system of mutually perpendicular axes X, Y and Z.
[0014] MOSFET 1 comprises a number of elementary cells (only one of which is shown in the accompanying drawings) which are identical to each other and arranged on the same die so as to share a drain terminal D, a gate terminal G and a source terminal S, i.e. the elementary cells are electrically connected in parallel with each other.
[0015] The MOSFET 1 is formed in a body 2 of semiconductor material. The body 2 is bounded at the top by a front face 2a and at the bottom by a rear face 2b, which are opposite each other in the direction of the axis Z. The body 2 may comprise a substrate, or else a substrate on which one or more epitaxial layers are grown, made of silicon carbide of one of its polytypes, here the 4H-SiC polytype.
[0016] In one embodiment, specifically, the body 2 comprises a substrate 10 bounded at the bottom by a rear surface 2b, a first epitaxial layer 12 on the substrate 10, and a second epitaxial layer 22 extending over the first epitaxial layer 12 and bounded at the top by a front surface 2a.
[0017] The substrate 10 is made of a single crystal semiconductor material, for example one of the polytypes of silicon carbide, here the polytype 4H-SiC, and has a lattice structure with spatial symmetry, and the first and second epitaxial layers 12, 22 are made of the same material and retain the same crystal structure.
[0018] A drift region 101, a first current spreading layer (hereinafter simply “first CSL”) 30, and a plurality of deep body regions 15 (two of which are shown in FIG. 1) are formed in the first epitaxial layer 12. A second current spreading layer (hereinafter simply “second CSL”) 40, a plurality of shallow body regions 20 (two of which are shown in FIG. 1), and a plurality of source regions 25 (two of which are shown in FIG. 1) are formed in the second epitaxial layer 22.
[0019] The body 2 of semiconductor material in FIG. 1, i.e. the substrate 10 and the drift region 101, has a first conductivity, for example N-type. The deep body region 15 has a second conductivity, opposite to the first conductivity, P-type, and has a first doping level (or dopant concentration) P1. The first CSL 30 is N-type and has a second doping level N1. The shallow body region 20 is P-type and has a third doping level P2. The second CSL 40 is N-type and has a fourth doping level N2. The first and third doping levels P1, P2 may be different from each other, and similarly the second and fourth doping levels N1, N2 may be different from each other. In any event, the first doping level P1 and the second doping level N1 are selected such that, taking into account the total volumes of the deep body regions 15 and the first CSL 30, the first total charge QP1 in the deep body regions 15 is significantly greater than the second total charge QN1 in the first CSL 30. Typically, the first total charge QP1 in the deep body regions 15 is at least five times greater than the second total charge QN1 in the first CSL 30. Finally, the multiple source regions 25 have a first conductivity.
[0020] In first epitaxial layer 12, adjacent deep body regions 15 are separated along axis X by portions of first CSL 30, and in second epitaxial layer 22, adjacent shallow body regions 20 are separated along axis X by portions of second CSL 40. Further, each shallow body region 20 at least partially overlaps and is in contact with a respective deep body region 15, and second CSL 40 at least partially overlaps and is in contact with first CSL 30.
[0021] Each source region 25 extends from the front surface 2a and is at least partially contained in a respective shallow body region 20. At least one of the source regions 25 of each base cell includes a body contact region 28 that extends from the front surface 2a to the respective shallow body region 20. Furthermore, each source region 25 and second CSL 40 laterally bound a channel region 27 in the respective shallow body region 20.
[0022] The deep body region 15, the shallow body region 20, the source region 25, and the body contact region 28 extend in stripes parallel to the Y-axis.
[0023] The superposition of the first and second epitaxial layers 12, 22 is such that, in use, the voltage between the gate terminal G and the source terminal S (V GS ) is the conduction threshold voltage of the basic cell (V TH ), a current can flow between the source terminal S and the drain terminal D through each of the channel regions 27, the second and first CSLs 40 and 30, and the drift region 101. The first and second CSLs 30, 40 in effect form a concentration layer whose function is to locally tailor the resistance encountered by the charge carriers (or more generally to improve the value of the on-state resistance of the MOSFET 1), and the drift region 101 forms a drift layer for the charge carriers in use.
[0024] The body 2 of FIG. 1, and more generally the MOSFET 1, is obtained by a manufacturing process forming various embodiments of the subject matter of the present disclosure, the successive steps of which are illustrated in FIGS. 2A-2I and shown diagrammatically in the flow chart of FIG. 3.
[0025] 2A shows a cross-sectional view of a wafer 100 of silicon carbide (4H-SiC polytype), here having a first conductivity (N-type) and a first surface 100a and a second surface 100b opposite each other in the direction of the axis Z. The wafer 100 initially comprises a substrate 10 on which is formed, by a first epitaxial growth (first step S1), a first epitaxial layer 12, for example with a thickness along the axis Z comprised between 1 μm and 60 μm. The crystal or lattice structure of the first epitaxial layer 12 allows ion implantation by exploiting the channeling phenomenon.
[0026] The deep body region 15 and subsequently the first CSL 30 are formed by channeling ion implantation. Channeling implantation is obtained when the ion beam during implantation is aligned with a channeling direction: for example, for SiC, 000-1 or 11-23. Typically, the substrate is cut from an ingot grown in 000-1 direction, the surface being tilted 4° for a substrate with a diameter of 150 mm or 200 mm (due to the cutting of the wafer). To perform a channeling implantation on a 000-1 wafer, the ion beam during implantation is oriented with a tilt of 4°, and for wafers grown in 11-23 direction, with a tilt of 13° or 21°.
[0027] With reference to FIG. 2B, which identifies a second step S2 of the manufacturing process, a deep body mask 105 is applied on the first surface 100a of the wafer 100. The deep body mask 105 exposes the portion of the wafer 100 in which the deep body region 15 is to be formed. Using the deep body mask 105, a first channeling ion implantation of dopant ions of P type, i.e. corresponding to a second conductivity opposite to the first conductivity of the wafer 100, is performed (here indicated by an arrow 110 inclined with respect to the axis Z to indicate the channeling implantation). The first channeling ion implantation is performed, for example, using ions of aluminum (Al) or boron (B) and an implantation energy comprised between 20 keV and 2000 keV. The deep body region 15 is thus defined by a first thickness T1 comprised between 0.5 and 5 μm along the axis Z starting from the first surface 100a and a first dimension L1 comprised between 1 and 10 μm along the axis X, and has a thickness of 1×10 17 ~1×10 19 atoms / cm 3 It has a first doping level P1 of the order of magnitude.
[0028] According to one embodiment, the wafer 100 is then subjected to an annealing step for activation of the dopant ions and for reduction of defects in the crystal lattice that may be caused by the implantation.
[0029] During a third step S3 (FIG. 2C), the deep body mask 105 is used to create a plurality of first intentionally damaged regions (also simply referred to as “IDR”) 50 for the purpose of self-aligned formation of the first CSL 30, as described below. The first damaged regions 50 are surface regions of the wafer 100, and assuming that the deep body mask 105 is again used, the first damaged regions 50 are obtained in regions corresponding to the respective deep body regions 15.
[0030] The applicant has found in practice that the effect of channeling can be altered by deliberate damage of the surface region of the wafer 100. Such damage can be obtained, for example, by a first random ion implantation (i.e. non-channel ion implantation) of a non-reactive or non-dopant species (indicated by arrows 120 in FIG. 2C), which induces damage to the crystal lattice of the wafer 100 without locally altering the conductive properties of the wafer 100. Suitable species for this purpose include, for example, ions of silicon (Si), argon (Ar), germanium (Ge) and helium (He).
[0031] Thus, according to an aspect of the present disclosure, first damage regions 50 are formed in the first surface 100a and aligned (along axes X and Y) with and defined in the respective deep body regions 15 so as to locally alter or inhibit channeling in a subsequent implantation step for forming the first CSL 30. Each first damage region 50 starts at the first surface 100a and extends in the wafer 100 to a maximum depth comprised, for example, between 0.05 and 0.2 μm (both values included). The thickness (depth along axis Z) of each first damage region 50 may be uniform or otherwise vary between a minimum value of 0.05 μm and a maximum value of 0.2 μm. As illustrated in FIG. 2C, thanks to the use of a deep body mask 105 also in the third step S3, each first damage region 50 has an extent along axis X that is substantially equal to the first dimension L1 of the respective deep body region 15.
[0032] To form the first damaged region 50, 13 atoms / cm 2 Implant doses in excess of 100 nm and energies sufficient to displace atoms from the crystalline system for the desired depth (e.g., energies in the range of 30-300 keV) may be used. The damage-inducing implants are performed in the absence of channeling conditions, and annealing of the wafer 100 during the process is avoided so as not to remove the damage created.
[0033] According to a further embodiment, the first damaged area 50 is obtained by one or more steps of local etching of the first surface 100a in the deep body region 15 through a deep body mask 105. For example, a RIE (Reactive Ion Etching) process may be used with the properties of physical etching, i.e. plasma ion bombardment with Ar ions. The depth that can be obtained is for example equal to 0.1 μm.
[0034] The lattice structure of the wafer 100 in the first damaged region 50 is different from the lattice structure of the undamaged regions of the wafer 100. Specifically, the wafer 100, when damaged, has an amorphous structure that does not have the spatial symmetry of portions of the wafer 100 where no intentional damage is present, or a disordered crystal structure or lattice structure.
[0035] When the deep body mask 105 is removed, the first damaged region 50 extends over a portion of the first epitaxial layer 12 where the first CSL 30 of the MOSFET 1 of Fig. 1 is not present. In other words, the first damaged region 50 is formed in a portion complementary to the portion of the wafer 100 where the first CSL 30 is implanted (third step S3). Fig. 2D refers to a fourth step S4 of the manufacturing process and shows how the first damaged region 50 actually acts as an implantation mask for a second channeling ion implantation (here indicated by an arrow 130 inclined with respect to the axis Z to indicate the channeling implantation) of dopant ions corresponding to N-type, i.e. the first conductivity.
[0036] In particular, the entire wafer 100 is subjected to the second channeling ion implant, but the first CSL 30 is obtained substantially exclusively in those portions of the wafer 100 that are free of surface damage, i.e., outside the deep body regions 15. In this manner, the deep body regions 15 are shielded from the second channeling ion implant, and at the same time, the first CSL 30 is defined in a self-aligned manner with respect to the deep body regions 15 in the first epitaxial layer 12 to a desired depth determined by the implant conditions.
[0037] A second channeling ion implantation (arrows 130) is performed using, for example, phosphorus (P) or nitrogen (N) ions and an implantation energy comprised between 20 keV and 2000 keV. These parameters result in a second doping level N1 between the deep body regions 15, for example 10 17 atoms / cm 3 10, the first doping level P1 of deep body region 15 and the second doping level N1 of first CSL 30 are selected in relation to the total volumes of deep body region 15 and first CSL 30 such that a first total charge QP1 in deep body region 15 is at least five times greater than a second total charge QN1 in deep body region 15.
[0038] In this step, a thin implanted layer of maximum thickness 0.3 μm may be formed in the first damaged region 50. In other words, the CSL may be superficially confined to the damaged region. The applicant has found that the presence of such a thin CSL, in conjunction with the overlying layers formed in subsequent steps, does not affect the operation of the MOSFET 1. However, as will also be explained below and as applied to the manufacturing processes forming the subject matter of various embodiments of the present disclosure, in order to prevent possible crystallographic defects in the layers overlying the damaged region, the first damaged region 50 is selectively removed, for example by etching the wafer 100 in a hydrogen (H2) environment, prior to the subsequent machining steps.
[0039] In this manner, processing of first epitaxial layer 12 of MOSFET 1 of Figure 1 is completed. In particular, drift region 101 itself is thus defined in the portion of first epitaxial layer 12 not occupied by first CSL 30 and deep body region 15.
[0040] Next (FIG. 2E, step S5), a second epitaxial layer 22 is formed on the wafer 100 by a second epitaxial growth. In particular, the second epitaxial layer 22, like the wafer 100, is made of silicon carbide (4H-SiC polytype), i.e. a material that can be ion-implanted by utilizing the channeling phenomenon, for example with 1×10 15 ~1×10 17 atoms / cm 3 The second epitaxial layer 22 is grown over a second thickness T2 (measured starting from the first surface 100a) comprised between 0.1 μm and 3 μm and for example equal to 1.5 μm.
[0041] Wafer 100 and second epitaxial layer 22 form a work wafer 118, which essentially corresponds to body 2 and extends between front surface 2a and rear surface 2b of body 2. Work wafer 118 is processed as described for the steps following the fifth step S5 to define the structure of MOSFET 1 present in second epitaxial layer 22.
[0042] With reference to FIG. 2F (sixth step S6), a shallow body mask 125 is applied on the second epitaxial layer 22, which exposes the portions of the second epitaxial layer 22 in which the shallow body regions 20 are to be formed. In particular, the shallow body mask 125 has openings in the direction of the axis Z at positions corresponding to the respective deep body regions 15, which are not necessarily of the same dimension. Using the shallow body mask 125, a third channeling ion implantation of dopant ions corresponding to P-type, i.e. a second conductivity opposite to the first conductivity of the second epitaxial layer 22, is performed (here indicated by an arrow 140 inclined with respect to the axis Z to indicate the channeling implantation). The third channeling ion implantation is performed, for example, using aluminum (Al) or boron (B) ions and an implantation energy comprised between 20 keV and 2000 keV. The shallow body region 20 thus defined has a depth equal to a second thickness T of the second epitaxial layer 22, a second dimension L along the axis X comprised between 1 and 10 μm, and a length L of 1×10 17 ~1×10 19 atoms / cm 3 and a third doping level P2 of the order of 0.5.
[0043] In the work wafer 118 of FIG. 2F, and thus in the MOSFET 1 of FIG. 1, the depth of the shallow body regions 20 starting from the front side 2a corresponds to the thickness of the second epitaxial layer 22. Furthermore, the shallow body mask 125 is such that the shallow body regions 20 of the MOSFET 1 are aligned to the deep body regions 15 in a direction parallel to the axis Z. As described above, each shallow body region 20 overlaps and contacts a respective deep body region 15. The first and second dimensions L1, L2 are different from each other, specifically, each shallow body region 20 has a dimension along the axis X that is smaller than the corresponding dimension of the respective deep body region 15.
[0044] The first and second dimensions L1 and L2 are design parameters of the MOSFET 1 corresponding to the electrical performance of the MOSFET 1, as will be described in more detail below. Accordingly, the first and second dimensions L1 and L2 can be selected by adjusting the respective deep body mask 105 and shallow body mask 125, such that each deep body region 15 has dimensions along the same axis X that are larger (Figure 1), smaller, or the same as the extent of the respective shallow body region 20 according to the desired performance (L1 > L2, L1 < L2, or L1 = L2, respectively).
[0045] During the seventh step S7 (Figure 2G), the shallow body mask 125 is used to create a plurality of second regions 70 that are intentionally damaged for the purpose of self-aligned formation of the second CSL 40. The second damaged regions 70 are surface regions of the second epitaxial layer 22 and are aligned (along axes X and Y) with the respective shallow body regions 20 and defined within the respective shallow body regions 20 to locally vary or suppress channeling.
[0046] The above damage can be obtained, for example, by implantation of second random (i.e., non-channel) ions of non-reactive or non-doping species (indicated by arrow 150 in Figure 2G), i.e., into the crystal lattice of the second epitaxial layer 22 to cause damage without locally changing its conductive properties. Chemical species designed for this purpose include, for example, ions of silicon (Si), argon (Ar), germanium (Ge), and helium (He).
[0047] To form the second damaged regions 70, an implantation dose exceeding 10 13 atoms / cm 2 and an energy sufficient to displace atoms from the crystal system for the desired depth (e.g., an energy in the range of 30 - 300 keV) can be used. Each second damaged region 70 begins at the front surface 2a in the second epitaxial layer 22 and extends to a maximum depth included, for example, in the range of 0.05 - 0.2 μm (including both end values).
[0048] When the shallow body mask 125 is removed, the damaged regions 70 extend over those portions of the second epitaxial layer 22 where the second CSL 40 of the MOSFET 1 of Figure 1 is not present. In other words, the second damaged regions 70 are formed in those portions of the second epitaxial layer 22 that are complementary to those portions of the second CSL 40 that are implanted (seventh step S7). Figure 2H relates to an eighth step S8 of the manufacturing process and in fact shows how the second damaged regions 70 act as an implantation mask for a fourth channeling ion implantation (here indicated by an arrow 160 inclined with respect to the axis Z to indicate the channeling implantation) of dopant ions corresponding to N-type, i.e. the first conductivity.
[0049] In particular, the entire second epitaxial layer 22 is exposed to the fourth channeling ion implant, but the formation of the second CSL 40 by channeling is obtained substantially only in those portions of the epitaxial layer 22 that are free of surface damage, i.e., outside the shallow body regions 20. In this manner, the shallow body regions 20 are shielded from the fourth channeling ion implant, and at the same time, the second CSL 40 is defined in the second epitaxial layer 22 in a manner that is self-aligned with respect to the plurality of shallow body regions 20.
[0050] A fourth channeling ion implantation (arrow 160) is performed using, for example, nitrogen or phosphorus ions and an implantation energy comprised between 20 keV and 2000 keV. The parameters are a fourth doping level N2 between the shallow body regions 20, for example 10 17 atoms / cm 3 , or otherwise, a fourth doping level N2 of the order of 2 to 20 times the doping level of the portion of the semiconductor layer containing it, and a depth along the axis Z, starting from the front side 2a, in the MOSFET 1, which is, for example, equal to the second thickness T2 of the shallow body region 20.
[0051] At the end of the fourth channeling ion implant, the second CSL 40 of the MOSFET 1 contacts and overlaps the first CSL 30 and at least partially contacts and overlaps the deep body region 15 .
[0052] The second damaged region 70 is then selectively removed, for example, by etching the work wafer 118 in a hydrogen environment (H2).
[0053] In one embodiment, illustrated in the enlarged detail views of Figures 4 and 5, the deep body region and the first CSL, here indicated by 115 and 130 respectively, can be obtained by repeating steps S1' to S4', similar to steps S1 to S4 already described, for a programmed number of iterations Q. In practice, in each iteration, a portion of the first epitaxial layer 12 is grown (S1', FIG. 6), a channeling ion implantation of dopant ions is performed (S2', FIG. 6) using the deep body mask 105, thus obtaining portions of the deep body regions 115 with respective concentrations P11, ..., P1K, ..., P1Q, intentionally damaged regions (not shown) are formed on the surface of the respective portions of the deep body regions 115 (S3', FIG. 6) by one or more local etching steps through the deep body mask 105, and portions of the first CSL 130 with respective concentrations N11, ..., N1K, ..., N1Q are formed by channeling ion implantation using the damaged regions as implantation masks (S4', FIG. 6). The dopant species concentrations P11, ..., P1K, ..., P1Q, and N11, ..., N1K, ..., N1Q may be selected in each case according to design preference such that the first total charge QP1′ in the deep body region 115 is significantly greater, typically at least five times greater, than the second total charge QN1′ in the first CSL 130 (added in FIG. 4). Furthermore, the dopant species concentrations P1K, ..., P1Q, and N11, ..., N1K, ..., N1Q may be selected such that in each Kth portion of the epitaxial layer (FIG. 5), the first layer total charge QP1K in the portion of the deep body region 115 is significantly greater, typically at least five times greater, than the second layer total charge QN1K in the portion of the first CSL 130.
[0054] The process then proceeds to steps S5 to S8, which have already been described.
[0055] The elementary cells of the MOSFET 1 are formed following an eighth step S8 of the manufacturing process of the body 2. In detail, referring to Fig. 2I, in which only one elementary cell is illustrated, the source regions 25 (having a first conductivity) and the body contact regions 28 (having a second conductivity), if present, are defined by formation techniques known in the sector such as implantation, diffusion, etc.
[0056] Each source region 25 and each body contact region 28 begins at the front surface 2a of the epitaxial layer 22, extends in the respective shallow body region 20, and for a respective depth of, for example, 0.2 μm and 2 μm. The source regions 25 are typically greater than the N doping level of the drift region 101, and are typically 1×10 18 ~1×10 20 atoms / cm 3 , each having an extent along axis X of, for example, 2 μm. 18 ~1×10 20 atoms / cm 3 It has a doping denoted P+ of the order of .
[0057] In this manner, the second layer 22 of the MOSFET 1 of FIG. 1 is completed, and indeed the entire body 2 as well.
[0058] A number of gate regions 35 are then formed on the front surface 2a of the body 2 by deposition and lithographic definition steps using typical sector techniques. Each of the gate regions 35 is formed by a gate insulating layer 36 (e.g. silicon oxide) in contact with the front surface 2a of the body 2, a gate conductive layer 37 (e.g. polysilicon layer) directly overlapping the gate insulating layer 36, and a passivation layer 38 covering the gate conductive layer 37 and encapsulating the gate conductive layer 37 together with the gate insulating layer 36. In detail, the gate insulating layer 36 of each gate region 35 extends partially over a respective portion of the second CSL 40, over two channel regions 27 adjacent to and delimiting said respective portion of the second CSL 40, and over two source regions 25 adjacent to the respective channel regions 27. The gate conductive layers 37 of the gate regions 35 are electrically connected in parallel in a manner not shown here and form a gate terminal G of the MOSFET 1.
[0059] The MOSFET 1 further comprises a source metallization region 26, for example of a metal material and / or a metal silicide, which forms the source terminal S of the MOSFET 1 and extends over the front surface 2a of the body 2 and is in direct electrical contact with the source region 25 and with a body contact region 28. The body contact region 28 is in fact used to bias the shallow body region 20, and thus the deep body region 15, with the potential of the source terminal S.
[0060] Finally, the MOSFET 1 comprises a drain metallization region 11 of a conductive material, e.g., a metal or a silicide, which extends onto the rear face 2b of the body 2 (in the opposite direction to the source metallization region 26) in direct electrical contact with the substrate 10 and forms the drain terminal D of the MOSFET 1.
[0061] The MOSFET 1 manufactured according to various embodiments of the process of the present disclosure exhibits improved electrical performance. The use of contained implantation energies makes it possible to obtain a reduced lateral distribution of the dopant ions, possibly due to the channeling phenomenon, and therefore a concentration profile of the dopant ions in the body 2 that can be controlled and that matches that established at the design stage. Furthermore, given that the first and second layers 12, 22 are defined using contained implantation energies, it is possible to use thin masks, so it is easier to obtain a larger lateral definition.
[0062] Techniques that rely on intentionally damaged regions (IDR) carried out under random implantation conditions (i.e. no channeling) on already implanted regions (here, for example, obtained by channel implantation) allow a further improvement in lateral definition, in particular because the regions formed in the step after the damage can be self-aligned with already existing regions that exhibit, for example, different or opposite doping levels. By locally modifying or suppressing channeling by damage, it is in fact possible to arbitrarily select the extent of the regions formed in the subsequent step (by channeling) and to protect the already existing regions from the subsequent channeling implantation and thus retain their desired doping level. The superficially damaged regions in fact act as an implantation mask for the subsequent channel implantation.
[0063] In this way, it is possible to define doping levels precisely and with lower production costs (contained implantation energies, self-alignment) within an epitaxially grown layer (here of silicon carbide) using a profile that can be variable along the dimension of the layer itself (here, for example, in the plane XY) and in the direction of layer superposition (here along the axis Z).
[0064] In MOSFET 1, this provides greater flexibility in defining the junction between the body and drain regions and in controlling the concentration of the conductive channel, with overall benefits in terms of the scalability of MOSFET 1 in the miniaturization direction and therefore in terms of an increase in the number of basic cells.
[0065] The first and second dimensions L1, L2, as well as the first and second thicknesses T1, T2 and the first and third doping levels P1, P2, are in fact design parameters of the MOSFET 1 that correspond to the electrical performance of the MOSFET 1. In particular, the deep body region 15 and the shallow body region 20 form an overall body structure that functions to shield layers overlying the body 2, in particular the gate insulating layer 36, with respect to the strong electric field of the body 2. Improved shielding may result in a reduced switching-on voltage of the power device.
[0066] The presence of the deep body region 15 indicates that the MOSFET 1 is in the off state and the voltage (V DS ) is high, e.g., higher than 400 V, this means that higher values of the electric field are obtained in the depth of the body 2 away from the front surface 2a. This results in the electric field having lower values in the shallower parts of the body 2 (here the second CSL 40), specifically near the gate insulating layer 36. As a result, the MOSFET 1 exhibits reliable performance.
[0067] The first and second dimensions L1, L2, and simultaneously the first and second thicknesses T1, T2, and the first and third doping levels P1, P2, are selected to provide a shape for the body structure (for example, an inverted T shape in MOSFET 1) and a doping profile which serve to obtain the desired electrical parameters (precisely shielding against electric fields, etc.) also with respect to the dimensions of the individual elementary cells.
[0068] At the same time, the first and second CSLs 30, 40 also form current spreading structures, whose dimensions (relative to the shape and dimensions of the body structure) and whose doping profile can be flexibly selected by the processes according to various embodiments of the present disclosure. In particular, different dopant concentrations between the different CSLs allow for effective modulation of the channel concentration and thus the electrical parameters of the device, and further combat undesirable phenomena such as pinching of the body region and uncontrolled variation of the on-state resistance during use.
[0069] Finally, it is apparent that modifications and variations can be made to what has been described and illustrated herein without departing from the scope of the present disclosure, as defined in the appended claims.
[0070] For example, the body structures may have shapes different from those shown. The deep body region may be less extensive (along axis X) than the shallow body region, where the shallow body region at least partially overlaps and contacts the first CSL. Alternatively, the deep body region and the shallow body region may be coextensive (along axis X).
[0071] In a manufacturing process variant (not shown), the channeling ion implantation of the first and second CSLs 30, 40 is such as to define respective depths that are smaller or larger than the aforementioned first and second thicknesses T1, T2.
Claims
1. 1. A manufacturing process for a vertical conduction power device, comprising: forming a layer containing a semiconductor material having a lattice structure with spatial symmetry and growing a first epitaxial layer having the lattice structure with spatial symmetry and a first conductivity; forming a first body region in the first epitaxial layer, the first body region having a second conductivity type opposite to the first conductivity type; forming a first current spreading layer having the first conductivity in the first epitaxial layer between the first body regions; Including, Forming the first body region includes: performing a first body channeling ion implant using a first body mask; forming the first current spreading layer; forming a first shallow damage region in the first body region through the first body mask such that the lattice structure changes in the first shallow damage region; performing a first current spreading channeling ion implant using the first shallow damaged region as an implant mask.
2. forming the first shallow damage region; non-channel random ion implantation of non-reactive or non-dopant ion species selected from the group consisting of silicon, argon, germanium, and helium ions; and A first chemical etch.
3. 2. The manufacturing process of claim 1 , wherein a first doping level of the first body region and a second doping level of the first current spreading layer are selected such that a first total charge in the first body region is at least five times greater than a second total charge in the first current spreading layer.
4. forming the first epitaxial layer and growing a second epitaxial layer having the lattice structure and the first conductivity with spatial symmetry; forming a second body region in the second epitaxial layer, the second body region having the second conductivity type; forming a second current spreading layer having the first conductivity between the second body regions of the second epitaxial layer; Further comprising: Forming the second body region includes: performing a second body channeling ion implant using a second body mask; forming the second current spreading layer; forming a second shallow damage region in the second body region through the second body mask such that the lattice structure changes in the second shallow damage region of the second body region; 2. The manufacturing process of claim 1, further comprising: performing a second current spreading channeling ion implant using the second shallow damaged region in the second body region as an implant mask.
5. The manufacturing process of claim 4 , wherein the second body mask has openings at locations corresponding to respective first body regions.
6. 5. The manufacturing process of claim 4, further comprising removing the first shallow damaged region prior to growing the second epitaxial layer.
7. The manufacturing process of claim 4 further comprising removing the second shallow damaged region.
8. 5. The manufacturing process of claim 4, wherein the second body regions extend depthwise throughout the second epitaxial layer to and in contact with each of the first body regions.
9. 5. The manufacturing process of claim 4, wherein the second current spreading layer extends throughout the second epitaxial layer, down to the first epitaxial layer, and in contact with the first epitaxial layer.
10. 4. The manufacturing process of claim 3, wherein the first doping level of the first body region is different from the third doping level of the second body region and / or the second doping level of the first current spreading layer is different from the fourth doping level of the second current spreading layer.
11. forming the second shallow damage region; a second non-channel random ion implantation of a non-reactive or non-dopant ion species selected from the group consisting of silicon, argon, germanium, and helium ions; and a second chemical etch.
12. growing a portion of the first epitaxial layer having the lattice structure and the first conductivity with spatial symmetry; forming a portion of the first body region having the second conductivity type in a last grown portion of the first epitaxial layer; forming a portion of the first current spreading layer between portions of the first body region of the last-grown portion of the first epitaxial layer; and repeating iteratively. forming the portion of the first body region in the last-grown portion of the first epitaxial layer; performing a respective body channeling ion implant using the first body mask; forming the portion of the first current spreading layer; forming a shallow damage region in the portion of the first body region of the last-grown portion of the first epitaxial layer through the first body mask such that the lattice structure changes in the first shallow damage region in the portion of the first body region of the last-grown portion of the first epitaxial layer; and performing a respective current spreading channeling ion implantation using the first shallow damaged region in the portion of the first body region in the last-grown portion of the first epitaxial layer as an implantation mask.
13. The manufacturing process of claim 1 , wherein the semiconductor material comprises silicon carbide.
14. A vertical conduction power device, comprising: a substrate containing a semiconductor material whose lattice structure has spatial symmetry; a first epitaxial layer disposed on the substrate, the first epitaxial layer having the lattice structure with spatial symmetry and a first electrical conductivity; a first body region in the first epitaxial layer, the first body region having a second conductivity type opposite to the first conductivity type; a first current spreading layer having the first conductivity in the first epitaxial layer between the first body regions; A vertical conduction power device comprising:
15. 15. The power device of claim 14, wherein a first doping level of the first body region and a second doping level of the first current spreading layer are selected such that a first total charge in the first body region is at least five times greater than a second total charge in the first current spreading layer.
16. a second epitaxial layer disposed on the first epitaxial layer, the second epitaxial layer having the lattice structure with spatial symmetry and the first conductivity; a second body region in the second epitaxial layer, the second body region having the second conductivity type; a second current spreading layer having the first conductivity type between the second body regions of the second epitaxial layer; 15. The power device of claim 14, wherein the second body regions extend throughout the second current spreading layer in a direction perpendicular to a plane of the second current spreading layer, are at locations corresponding to, and are in contact with, respective first body regions.
17. The power device of claim 14 , wherein the semiconductor material comprises silicon carbide.