Switching control circuit

Abstract

To provide a switching control circuit capable of preventing malfunction of a driving circuit due to negative voltage noise.SOLUTION: A switching control circuit controls switching of a first switching element on a power source side to drive a load and a second switching element on a ground side. The switching control circuit includes a first level shift circuit including a first resistor and a first transistor, a driving circuit that drives the first switching element on the basis of the output from the first level shift circuit, a first switch connected in parallel to the first resistor, and an ON / OFF control circuit that turns on the first switch when a low-potential side electrode of the first switching element has a negative voltage.SELECTED DRAWING: Figure 15

Description

[Technical field]

[0001] The present invention relates to a switching control circuit. [Background technology]

[0002] In a bridge circuit for power conversion, switching elements in each of the upper and lower arms are operated under the control of a switching control circuit to perform power conversion (for example, Patent Document 1).

[0003] The switching control circuit includes a drive circuit that drives the switching elements of the upper arm and the lower arm, a control circuit that controls the drive circuit, and a level shift circuit that transmits signals between the control circuit and the drive circuit. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 4620437 Summary of the Invention [Problem to be solved by the invention]

[0005] In the switching control circuit, the lower arm switching element operates with reference to a ground voltage, and the upper arm switching element operates with reference to a VS potential that varies in response to the on / off state of the lower arm switching element.

[0006] Therefore, the level shift circuit level-shifts an input signal to the switching element of the upper arm, which is based on the ground potential, to a signal based on the VS potential and outputs the signal to the drive circuit.

[0007] The level shift circuit includes, for example, a resistor connected to a floating power supply potential VB, and an n-channel MOSFET provided between the resistor and ground. When the n-channel MOSFET is turned on, the potential of the connection node between the n-channel MOSFET and the resistor becomes lower than the floating power supply potential VB by a certain voltage determined by the product of the resistance and the on-current of the n-channel MOSFET, and when the n-channel MOSFET is turned off, the potential of the connection node becomes the floating power supply potential VB. As a result, the input signal based on the ground potential is level-shifted to a signal based on the VS potential.

[0008] However, when the switching element of the upper arm is switched from on to off, the VS potential of the node to which the switching element of the upper arm and the switching element of the lower arm are connected may become lower than the ground potential, resulting in so-called negative voltage noise.

[0009] When negative voltage noise occurs, an unintended current may flow through the resistor of the level shift circuit, causing the voltage of the connection node to fluctuate. Such an unintended current may cause a problem in signal transmission between the control circuit and the drive circuit, leading to a malfunction of the drive circuit.

[0010] The present invention has been made in view of the above problems, and an object of the present invention is to provide a switching control circuit capable of preventing malfunction of a drive circuit due to negative voltage noise. [Means for solving the problem]

[0011] One invention for achieving the above-mentioned object is a switching control circuit that controls switching of a first switching element on a power supply side and a second switching element on a ground side that drive a load, the switching control circuit comprising: a first level shift circuit including a first resistor and a first transistor; a drive circuit that drives the first switching element based on an output from the first level shift circuit; a first switch connected in parallel to the first resistor; and an on / off control circuit that turns on the first switch when a low potential side electrode of the first switching element becomes a negative voltage. Effect of the Invention

[0012] According to the present invention, it is possible to provide a switching control circuit capable of preventing malfunction of a drive circuit due to negative voltage noise. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is a circuit diagram for explaining an overview of a general switching control circuit 10. [Diagram 2] FIG. 2 is a circuit diagram for explaining details of a switching control circuit 10. [Diagram 3] 1 is a diagram illustrating a semiconductor device 1 equipped with a switching control circuit 10. FIG. [Figure 4] 1 is a diagram illustrating a part of a cross section of a semiconductor device 1. FIG. [Diagram 5] 1 is a diagram illustrating a part of a cross section of a semiconductor device 1. FIG. [Figure 6] 2 is a diagram for explaining a current flowing inside the semiconductor device 1. FIG. [Figure 7] 2 is a diagram for explaining a current flowing inside the semiconductor device 1. FIG. [Figure 8] 2 is a diagram for explaining a current flowing inside the semiconductor device 1. FIG. [Figure 9] 2 is a diagram for explaining a current flowing inside the semiconductor device 1. FIG. [Figure 10] 3 is a diagram illustrating an unintended current flowing in the switching control circuit 10. FIG. [Figure 11]4 is a timing chart of the HO potential from the drive circuit 14. [Figure 12] 13 is a timing chart of the drain voltage of the reset-side transistor 13t. [Figure 13] 1 is a timing chart of a VB potential and a VS potential. [Figure 14] 11 is a timing chart of the current flowing through a parasitic element (described later) and resistor 13r. [Figure 15] FIG. 2 is a circuit diagram illustrating details of a switching control circuit 50 according to an embodiment. [Figure 16] 2 is a circuit diagram for explaining details of an on / off control circuit 51. FIG. [Figure 17] 1 is a diagram illustrating a semiconductor device 5 on which a switching control circuit 50 is mounted. [Figure 18] 2 is a diagram illustrating a partial cross section of the semiconductor device 5. FIG. [Figure 19] 2 is a diagram illustrating a partial cross section of the semiconductor device 5. FIG. [Figure 20] 1 is a timing chart of a VB potential and a VS potential; [Figure 21] 13 is a timing chart of the current flowing through resistor 13r. [Figure 22] 11 is a timing chart of the drain voltages of set-side and reset-side transistors 12t and 13t. [Figure 23] 4 is a timing chart of the HO-VS voltage from the drive circuit 14. [Figure 24] 11 is a timing chart of the GC-VS voltage from the on / off control circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, a preferred embodiment of the present invention will be described with reference to the drawings. The same or equivalent components, members, etc. shown in each drawing are given the same reference numerals, and duplicated descriptions will be omitted as appropriate. At least the following points will become clear from the description of this specification and the attached drawings.

[0015] ==General Switching Control Circuit 10== First, a description will be given of a general switching control circuit 10. Fig. 1 is a circuit diagram for explaining an overview of the switching control circuit 10. The switching control circuit 10 is a circuit that controls switching of a power supply side switching element (corresponding to a "first switching element") that drives a load and a ground side switching element (corresponding to a "second switching element").

[0016] FIG. 1 shows an example of a connection between a switching control circuit 10 and IGBTs 21 and 22 which are switching elements that form a bridge circuit for power conversion.

[0017] As shown in FIG. 1, in this example, an IGBT 21 is used as a switching element on the power supply side, and an IGBT 21 is used as a switching element on the ground side.

[0018] The IGBT 21, which is the switching element on the power supply side, may be referred to hereinafter as the "upper arm IGBT 21." Also, the IGBT 22, which is the switching element on the ground side, may be referred to hereinafter as the "lower arm IGBT 22."

[0019] The IGBTs 21 and 22 are connected in series to each other to form a half bridge. Freewheeling diodes 23 and 24 are connected in anti-parallel to the IGBTs 21 and 22, respectively.

[0020] A ground potential (GND potential) is applied to the emitter of the IGBT 22 of the lower arm, and a power supply potential (HV potential) is applied to the collector of the IGBT 21 of the upper arm.

[0021] 1 is an intermediate potential that varies from HV potential to GND potential. "VB" is the potential on the high potential side of power supply 25 with the VS potential as a reference. "COM" is the reference potential and the GND potential. "VCC" is the potential on the high potential side of power supply 26 with the GND potential as a reference.

[0022] "HIN" and "LIN" are input signals input from a microcomputer or the like to a control circuit 11, which will be described later. "HO" is a high-side output signal output to the gate of the IGBT 21 of the upper arm. "LO" is a low-side output signal output to the gate of the IGBT 22 of the lower arm.

[0023] The switching control circuit 10 alternately turns on the IGBT 21 of the upper arm and the IGBT 22 of the lower arm to alternately output a high potential or a low potential from the VS terminal which is the output terminal of the switching control circuit 10, thereby supplying AC power to the load.

[0024] That is, when a high potential is output to the load, the switching control circuit 10 operates the IGBTs 21 and 22 so that the IGBT 21 of the upper arm is turned on and the IGBT 22 of the lower arm is turned off. When a low potential is output to the load, the switching control circuit 10 operates the IGBTs 21 and 22 so that the IGBT 21 of the upper arm is turned off and the IGBT 22 of the lower arm is turned on.

[0025] At this time, the switching control circuit 10 outputs a gate signal based on the GND potential to the gate of the IGBT 22 in the lower arm, and outputs a gate signal based on the VS potential to the gate of the IGBT 21 in the upper arm.

[0026] The VS potential varies depending on the on / off state of the upper arm IGBT 21 and the lower arm IGBT 22. For this reason, the switching control circuit 10 needs to include a level shift circuit (described later in detail).

[0027] <Details of the switching control circuit 10> 2 is a circuit diagram for explaining the details of the switching control circuit 10. The switching control circuit 10 includes a control circuit 11, a level shift circuit 12 (corresponding to a "first level shift circuit"), a level shift circuit 13 (corresponding to a "second level shift circuit"), and a drive circuit 14.

[0028] The control circuit 11 controls the level shift circuits 12 and 13. The control circuit 11 outputs a set signal SET2 to the level shift circuit 12 when the input signal HIN changes from a low (L) level to a high (H) level.

[0029] Furthermore, the control circuit 11 outputs a reset signal RESET1 to the level shift circuit 13 when the input signal HIN changes from H level to L level.

[0030] The level shift circuit 12 includes a resistor 12r (corresponding to a "first resistor") and a transistor 12t (corresponding to a "first transistor"). The level shift circuit 12 outputs a set signal SET2 for switching the IGBT 21 of the upper arm from off to on.

[0031] In the following, the level shift circuit 12 may be referred to as the "set-side level shift circuit 12", the resistor 12r as the "set-side resistor 12r", and the transistor 12t as the "set-side transistor 12t".

[0032] In this example, the transistor 12t is an n-channel MOS transistor. The gate of the transistor 12t is connected to the control circuit 11. The drain of the transistor 12t is connected to one end of the resistor 12r and a drive circuit 104 (described later). A ground potential GND is applied to the source of the transistor 12t. The other end of the resistor 12r is connected to the high potential side of the power supply 25.

[0033] The level shift circuit 13 includes a resistor 13r (corresponding to a "second resistor") and a transistor 13t (corresponding to a "second transistor"). The level shift circuit 13 outputs a reset signal RESET2 for switching the upper arm switching element 21 from on to off.

[0034] In the following, the level shift circuit 13 may be referred to as the "reset-side level shift circuit 13", the resistor 13r as the "reset-side resistor 13r", and the transistor 13t as the "reset-side transistor 13t".

[0035] In this example, the transistor 13t is an n-channel MOS transistor. The gate of the transistor 13t is connected to the control circuit 11. The drain of the transistor 13t is connected to one end of the resistor 13r and the drive circuit 14. The GND potential is applied to the source of the transistor 13t. The other end of the resistor 13r is connected to the high potential side of the power supply 25.

[0036] The drive circuit 14 drives the switching element 21 based on the outputs from the level shift circuits 12 and 13. That is, the drive circuit 14 drives the IGBT 21 based on the set signal SET2 from the level shift circuit 12 and the reset signal RESET2 from the level shift circuit 13.

[0037] In this example, only the drive circuit 14 that drives the switching element 21 of the upper arm is shown, and the description of the drive circuit that drives the switching element 22 of the lower arm is omitted for convenience.

[0038] <Operation of the switching control circuit 10> The following describes the switching operation of the switching control circuit 10. The following describes the operation when the input signal HIN input to the control circuit 11 changes from a low (L) level to a high (H) level, and the operation when the input signal HIN changes from an H level to an L level.

[0039] First, the operation when the input signal HIN input to the control circuit 11 changes from L level to H level will be described.

[0040] At this time, the control circuit 11 outputs a set signal SET1 to the set-side transistor 12t so as to turn on the set-side transistor 12t for a certain period of time.

[0041] The set-side transistor 12t converts the set signal SET1 from the control circuit 11 into a set signal SET2 based on the VS potential and outputs it to the drive circuit .

[0042] Specifically, the set-side transistor 12t outputs a drain potential that is lower than the floating power supply potential VB by a certain voltage due to a current flowing through the resistor 12r to the drive circuit as a set signal SET2.

[0043] The driving circuit 14 switches the output HO of the driving circuit from the L level to the H level in response to the set signal SET2 from the set-side transistor 12t.

[0044] Next, the operation when the input signal HIN input to the control circuit 11 changes from H level to L level will be described.

[0045] At this time, the control circuit 11 outputs a reset signal RESET1 to the reset-side transistor 13t so as to turn on the reset-side transistor 13t for a certain period of time.

[0046] The reset-side transistor 13t converts the reset signal RESET1 from the control circuit 11 into a reset signal RESET2 based on the VS potential and outputs it to the drive circuit .

[0047] Specifically, the reset transistor 13t outputs a drain potential that is lower than the floating power supply potential VB by a certain voltage due to a current flowing through the resistor 13r to the drive circuit 14 as a reset signal RESET2.

[0048] The drive circuit 14 switches the output HO of the drive circuit 14 from H level to L level in response to the reset signal RESET2 from the reset-side transistor 12t.

[0049] <Planar structure> 3 is a diagram illustrating a semiconductor device 1 equipped with a switching control circuit 10. The semiconductor device 1 includes a high side region 101 (corresponding to a "high side region"), a high voltage junction termination region (HVJT) 102, and a reference potential region 103 (corresponding to a "reference potential region") on a p-type semiconductor substrate 100. As the semiconductor substrate 100, for example, a silicon (Si) substrate is used.

[0050] A drive circuit 14 is formed in the high side region 101. Also arranged in the high side region 101 are a VB terminal 105, a VS terminal 106, and an HO terminal 107. The VB terminal 105 is a terminal to which a VB potential is applied. The VS terminal 106 is a terminal to which a VS potential is output. The HO terminal 107 is a terminal to which an HO potential is applied.

[0051] The high-voltage junction termination region 102 is provided around the high-side region 101. In the high-voltage junction termination region 102, a part of the set-side transistor 12t and the reset-side transistor 13t are provided (described in detail later).

[0052] The reference potential region 103 is a region on the front surface of the semiconductor substrate 100 excluding the high side region 101 and the high voltage junction termination region 102. The reference potential region 103 is electrically isolated from the high side region 101 by the high voltage junction termination region 102.

[0053] The control circuit 11 is formed in the reference potential region 103. A GND terminal 108, an HIN terminal 109, and a VCC terminal 110 are arranged in the reference potential region 103. The GND terminal 108 is a terminal to which a GND potential that is a reference potential of the control circuit 11 is applied. The HIN terminal 109 is a terminal to which an input signal HIN to the control circuit 11 is input. The VCC terminal is electrically connected to a power supply (not shown) of the control circuit 11, and is a terminal to which a VCC potential that is a power supply potential of the control circuit 11 is applied.

[0054] In the present embodiment, the switching control circuit 10 is mounted on one semiconductor substrate 100. However, the present invention is not limited to this, and the semiconductor device 1 may be configured with two semiconductor chips, each including, for example, a configuration corresponding to the high side region 101 and a configuration corresponding to the reference potential region 103, on a substrate such as DCB (Direct Bonded Copper).

[0055] <Cross-sectional structure> Fig. 4 is a diagram illustrating a cross section of semiconductor device 1 on AA' including transistor 12t on the set side of Fig. 3. Fig. 5 is a diagram illustrating a cross section of semiconductor device 1 on DD' including high-voltage junction termination region 102 of Fig. 3.

[0056] As shown in FIGS. 4 and 5, the semiconductor device 1 has an n-type region 111, an n-type region 112, and an n-type region 113 on the front surface of a p-type semiconductor substrate 100. - type region 112, p - A type region 113 and a type region 114 are provided.

[0057] 3, the n-type region 111 corresponds to the high side region 101, and a VB potential is applied to the n-type region 111. The drive circuit 14 is also formed in the n-type region 111. In FIG. 4, an n-channel MOSFET 141 and a p-channel MOSFET 142 which constitute the drive circuit 14 are shown in the n-type region 111. A source 141s of the n-channel MOSFET 141 is connected to the VS terminal 106 (FIG. 3).

[0058] The n-type region 111 further includes n + A mold contact region 115 is provided on the substrate 110. An electrode that connects to the VB terminal 105 (FIG. 3) is provided on the contact region 115.

[0059] n - 3, the n-type region 112 is provided in the high-voltage junction termination region 102. The high-voltage junction termination region 102 is a region provided outside the n-type region 111, and in this embodiment, is provided in a ring shape around the n-type region 111. -The n-type region 112 has a lower impurity concentration than the n-type region 111.

[0060] As shown in Figure 4, n - The drift region 116 of the set-side transistor 12t and the n + An n-type drain region 117 is provided on the periphery of the drain region 117. An n-type region 124 is provided on the drain region 117. A drain electrode 12d of the transistor 12t is provided on the drain region 117.

[0061] The set-side transistor 12t has a p-type region 114 (described later) on top thereof. + The n-type contact region 118 is provided adjacent to the n-type contact region 118. + The source region 119 has a .alpha.-type.

[0062] An n-type region 123 is provided around the source region 119. + type contact region 118 and n + A source electrode 12s is provided on the source regions 119 of the mold so as to contact these regions.

[0063] Source electrodes 12s and n - A gate electrode 12g of the transistor 12t is provided on the p-type region 120 between the first and second regions 112 and 114, with a gate insulating film 122 interposed therebetween. A reference potential is applied to the source electrode 12s. A set signal SET1 is input to the gate electrode 12g.

[0064] A set-side resistor 12r is provided via an insulating film (not shown) on the n-type region 111. The resistor 12r is made of polycrystalline silicon or the like.

[0065] p - The type region 113 is n - In this embodiment, the p - The type region 113 is n - The n-type region 112 is disposed between the transistor 12t in the n-type region 111 and separates them.

[0066] p - The type region 113 is n - having a depth penetrating the mold region 112, - The transistor 12t in the n-type region 112 is electrically isolated from the n-type region 111.

[0067] The p-type region 120 and the p-type region 114 are n - In this embodiment, the p-type region 120 and the p-type region 114 are in contact with each other. - It is provided in an annular shape around the mold area 112 .

[0068] The upper portion of the p-type region 114 is provided with a p + A contact area 118 is provided. + The contact region 118 is electrically connected to the GND terminal, and + Since the p-type contact region 115 is electrically connected to the VB terminal, the potential of the VB terminal is higher during normal operation, so that the p-type region 120 and the p-type region 114 and the n-type contact region 115 are electrically connected to the VB terminal. - The depletion layer is mainly formed from the pn junction with the n-type region 112. - Type region 112 spreads to n - By remaining in the mold region 112, the high side region 101 and the reference potential region 103 are electrically separated in the lateral direction.

[0069] In the above description, only the set-side transistor 12t has been mentioned, but the same is true for the reset-side transistor 13t.

[0070] <Malfunctions occurring in a typical switching control circuit 10> A malfunction occurring in the switching control circuit 10 will be described. Figures 6 to 14 are diagrams for explaining a malfunction occurring in the switching control circuit 10. Among these, Figures 6 to 9 are diagrams for explaining a current flowing inside the semiconductor device 1 equipped with the switching control circuit 10. Also, Figure 10 is a diagram for explaining an unintended current flowing in the switching control circuit 10.

[0071] 10 to 13 are various timing charts of the switching control circuit 10. Fig. 10 shows the HO potential (Fig. 1) from the drive circuit 14 to the upper arm IGBT 21, Fig. 12 shows the drain voltages of the set-side and reset-side transistors 12t, 13t, Fig. 13 shows the VB potential and VS potential, and Fig. 14 shows the current flowing through a parasitic element (described later) and resistor 13r.

[0072] First, there will be described the parasitic elements formed inside the semiconductor device 1. As shown in Figures 6 to 9, inside the semiconductor device 1, parasitic diodes 150 and 151, a parasitic resistor 152, and a parasitic transistor 153 are formed.

[0073] The parasitic diode 150 is formed by a p-type semiconductor substrate 100 and an n - The parasitic diode 151 is formed by a p-type semiconductor substrate 100 and an n-type region 111.

[0074] The parasitic resistor 152 is formed by the resistance of the p-type semiconductor substrate 100. The parasitic transistor 153 is formed by the n-type region 111, the p-type region of the semiconductor substrate 100, and the n-type region of the semiconductor substrate 100. - It is an NPN transistor formed between the type regions 112. An equivalent circuit of the semiconductor device 1 together with these parasitic elements is shown in FIG.

[0075] If the above-mentioned parasitic elements exist, when negative voltage noise occurs, this may cause a malfunction in the switching control circuit 10. The malfunction will be described in detail below.

[0076] The negative voltage noise is a type of switching noise that occurs due to the switching of the IGBTs 21 and 22.

[0077] Negative voltage noise is a negative voltage noise that occurs when the IGBT 21 in the upper arm of the bridge circuit is turned off and the VS potential drops, causing the VS potential to undershoot due to the influence of the load and wiring inductance.

[0078] In the following example, the initial state is a state in which the IGBT 21 of the upper arm is on and the IGBT 22 of the lower arm is off. Then, consider a case in which the IGBT 21 of the upper arm is switched off and the IGBT 22 of the lower arm is switched on by a reset signal RESET1 from the control circuit 11 from that state.

[0079] ·Time t0 12, from the initial state, at time t0, the reset-side transistor 13t is turned on by the reset signal RESET1 from the control circuit 11. At this time, as shown in FIG. 12, the drain potential of the transistor 13t drops due to a voltage drop across the reset-side resistor 13r, and falls below the input threshold of the drive circuit 104.

[0080] ·Time t1 At time t0, when the drain potential of the reset-side transistor 13t drops below the input threshold of the drive circuit 14, the drive circuit 14 turns off the upper arm IGBT 21 at time t1, which is a signal delay time inside the drive circuit 14 after time t0. At this time, the drive circuit 14 switches the HO-VS voltage to the gate of the IGBT 21 to the L level (FIG. 10).

[0081] At this time, if negative voltage noise occurs that has an absolute value greater than the power supply voltage VBS (VB-VS) of the drive circuit 14, the VB potential becomes negative until the negative voltage noise disappears (period (A) in FIG. 13).

[0082] As a result, at time t1, the parasitic diodes 150 and 151 are forward biased and are turned on.

[0083] From time t1 to time t2 (period (A) in Figure 12) When the parasitic diodes 150 and 151 are turned on, holes and electrons are injected into the n-type region 111 and the p-type semiconductor substrate 100, respectively, and carriers (electrons and holes) are accumulated. The accumulation of carriers continues until the negative voltage noise period (period (A)) ends.

[0084] 6 shows the current flowing in the semiconductor device 1 during period (A). As shown in this figure, a forward current flows through the parasitic diodes 150 and 151.

[0085] ·Time t2 At time t2, the period of the negative voltage noise (period (A) in FIG. 13) ends, and when the VB potential recovers from the negative voltage to, for example, 0.6 V or higher, the parasitic diodes 150 and 151 are in a reverse bias state.

[0086] When a reverse bias is applied to the parasitic diodes 150 and 151, a so-called reverse recovery current flows.

[0087] 7 shows a current flowing through the semiconductor device 1 at time t2. As shown in this figure, at time t2, a reverse recovery current flows through the parasitic resistance 152. When the reverse recovery current flows through the parasitic resistance 152, the substrate potential rises due to a voltage drop across the parasitic resistance 152, and the parasitic transistor 153 turns on.

[0088] From time t2 to time t3 (period (B)) 8 shows the current flowing in the semiconductor device 1 during period (B). As shown in this figure, the reverse recovery current flows between the collector and emitter of the parasitic transistor 153 and through the resistors 12r and 13r on the set and reset sides.

[0089] FIG. 14 shows the currents (only the reverse recovery currents) flowing through the parasitic diode 150, the parasitic transistor 153, and the set-side resistor 12r.

[0090] When the reverse recovery current starts to flow at time t2, the reverse recovery current flowing through the parasitic diode 150 and the parasitic transistor 153 thereafter attenuates (period (B) in FIG. 14).

[0091] On the other hand, a reverse recovery current also starts to flow through the set-side and reset-side resistors 12r, 13r, but this current is smaller than the reverse recovery current flowing through the parasitic diode 150 and the parasitic transistor 153 during period (B).

[0092] From time t3 to time t4 (period (C)) From around time t3, the reverse recovery current flowing through the parasitic diode 150 and the parasitic transistor 153 further attenuates, and the reverse recovery current flowing through the set-side and reset-side resistors 12r, 13r increases (period (C) in FIG. 14).

[0093] As a result, the drain voltages of the set-side and reset-side transistors 12t, 13t start to decrease (period (C) in FIG. 12).

[0094] The increase in the reverse recovery current flowing through the resistors 12r and 13r occurs because the on-resistance of the parasitic transistor 153 starts to increase compared to the resistors 12r and 13r as the parasitic transistor 153 turns from on to off.

[0095] The path of the reverse recovery current in period (C) is shown in the circuit diagram of Figure 10. In this diagram, parasitic diodes 150 and 151, a parasitic resistor 152, and a parasitic transistor are also shown.

[0096] ·Time t4 As shown in FIG. 12, when the drain voltages of the set-side and reset-side transistors 12t, 13t decrease, the drain voltages of both the set-side and reset-side transistors 12t, 13t may unintentionally fall below the input threshold voltage of the drive circuit 14.

[0097] As a result, both the set signal SET2 and the reset signal RESET2 are erroneously output to the drive circuit 14.

[0098] In addition, a typical drive circuit 14 is designed to maintain the output logic when the set signal SET2 and the reset signal RESET2 are input simultaneously, so no malfunction occurs when the set signal SET2 and the reset signal RESET2 decrease by exactly the same amount due to negative voltage noise.

[0099] However, due to variations in the characteristics of each element, the amount of drop in the drain voltage on the set side and the reset side will not actually be the same, and a difference will occur.

[0100] In this example, as shown in FIG. 12, at time t4, only the drain voltage of the set-side transistor 12t falls below the input threshold voltage of the drive circuit 104, and the set signal SET2 is erroneously output to the drive circuit 104.

[0101] In this case, as shown in FIG. 11, at time t4, a malfunction occurs in which the drive circuit 14 erroneously turns on the IGBT 21.

[0102] From time t4 At about time t4, the parasitic transistor 153 turns off.

[0103] 9 shows the current flowing through the semiconductor device 1 immediately after the parasitic transistor 153 is turned off. As shown in this figure, the reverse recovery current flowing through the parasitic transistor 153 disappears, while the reverse recovery current flowing through the set-side and reset-side resistors 12r, 13r remains.

[0104] Immediately after the parasitic transistor 153 is turned off, the reverse recovery current flowing through the set-side and reset-side resistors 12r and 13r reaches a peak (around time t4 in FIG. 14). After time t4, the reverse recovery current flowing through the resistors 12r and 13r attenuates and disappears (period (D) in FIG. 14).

[0105] When the reverse recovery current further decreases, the drain voltages of the transistors 12t and 13t start to recover (period (D) in FIG. 12).

[0106] The above describes malfunctions that may occur in the general switching control circuit 10. As described above, when an unnecessary current flows through the resistor 12r on the set side, the driver circuit 14 may erroneously turn on the IGBT 21.

[0107] Furthermore, during the period from when the negative voltage noise occurs at time t1 until the parasitic transistor 153 turns off, the level shift circuits 12 and 13 do not transmit signals normally.

[0108] Therefore, if the input signal to the switching control circuit 10 switches from L level to H level during this period, the set signal SET2 is not output to the drive circuit 14, causing a malfunction in which the IGBT 21 does not turn on. The period during which normal signal transmission is not possible is a maximum of about 10 μs.

[0109] The switching control circuit 50 of the embodiment described next is capable of preventing the malfunction of the drive circuit caused by the above-mentioned negative voltage noise.

[0110] == Implementation form == Fig. 15 is a circuit diagram for explaining details of the switching control circuit 50 of this embodiment. The switching control circuit 50 is different from the general switching control circuit 10 of Fig. 2 in that it further includes an on / off control circuit 51, a switch 52 (corresponding to a "first switch"), and a switch 53 (corresponding to a "second switch").

[0111] The following description will focus on the differences from a general switching control circuit 10, and a description of the commonalities will be omitted.

[0112] [Switch 52] As described above, when a reverse recovery current flows through the set-side resistor 12r due to negative voltage noise, a malfunction may occur in which the drive circuit 14 erroneously turns on the IGBT 21.

[0113] The switch 52 is provided to prevent the reverse recovery current from flowing through the resistor 12r on the set side by diverting the reverse recovery current through the switch 52 (details will be described later).

[0114] The switch 52 is connected in parallel to the set-side resistor 12r. In this embodiment, the switch 52 is a p-channel MOS transistor.

[0115] [Switch 53] The switch 53 has the same configuration as the switch 52. The switch 53 is connected in parallel to the resistor 13r on the reset side. In this embodiment, the switch 53 is a p-channel MOS transistor.

[0116] As described above, if a reverse recovery current flows through the set-side resistor 12r due to negative voltage noise, the drive circuit 14 may malfunction by erroneously turning on the IGBT 21.

[0117] In other words, even if a reverse recovery current flows through resistor 13r on the reset side, the above-mentioned malfunction does not occur. However, by providing switch 53, the circuit structure of the switching control circuit 50 can be made symmetrical with respect to the set side and the reset side. This makes it possible to stabilize the operation of the circuit.

[0118] [On-off control circuit 51] The on / off control circuit 51 is provided to control the on / off of the above-mentioned switches 52 and 53.

[0119] When the low potential electrode of the switching element 21 becomes a negative voltage (when negative voltage noise occurs), the on / off control circuit 51 turns on the switch 52. In this embodiment, when negative voltage noise occurs, the on / off control circuit 51 also turns on the switch 53.

[0120] 16 is a circuit diagram for explaining details of ON / OFF control circuit 51. ON / OFF control circuit 51 includes a diode element 511 and a circuit 512.

[0121] Diode element 511 passes a current when the low potential side electrode of switching element 21 is at a negative voltage (when negative voltage noise is occurring).

[0122] In this embodiment, the diode element 511 is a diode-connected n-channel MOS transistor (corresponding to a "third transistor"). The gate electrode and drain electrode of the n-channel MOS transistor are grounded, and the source electrode is connected to the low potential side electrode of the switching element 21 via resistors R1 and R2 (described later).

[0123] The circuit 512 outputs a signal that turns on the switches 52 and 53 for a predetermined period based on the current flowing through the diode element 511. The circuit 512 is formed in the high side region 101 (FIG. 17, which will be described later).

[0124] The circuit 512 of this embodiment includes resistors R1, R2, and R3, a Schmitt trigger circuit 513, NOT circuits 514 and 516, a diode element 515, and a capacitance C1. These will be described in detail together with the operation of the switching control circuit 50, which will be described later.

[0125] <Planar structure> 17 is a diagram illustrating a semiconductor device 5 equipped with a switching control circuit 50. The planar structure of the semiconductor device 5 is different from that of the above-described semiconductor device 1 in the arrangement within the high-voltage junction termination region 102. An enlarged view of a portion of the high-voltage junction termination region 102 is shown at the bottom of FIG.

[0126] Compared to the general semiconductor device 1 of FIG. 3, high voltage junction termination region 102 further includes a diode element 511 disposed therein.

[0127] As shown in the lower part of FIG. 15, in the semiconductor device 5, the transistor 12t of the set-side level shift circuit 12 is composed of two transistors having a common channel direction.

[0128] Between the two transistors 12t, a diode element 511 of the ON / OFF control circuit 51 is disposed. As described above, the diode element 511 is a diode-connected transistor.

[0129] That is, the two transistors constituting transistor 12t and the transistor constituting diode element 511 (that is, three transistors) are disposed in high voltage junction termination region 102.

[0130] By using such an arrangement, the characteristics of the transistors constituting the transistor 12t and the diode element 511 can be made similar, and the circuit operation can be stabilized.

[0131] In this example, the transistor 12t is configured by two transistors, but is not limited to this. That is, the transistor 12t may be configured by three or more transistors having a common channel direction.

[0132] On the other hand, the transistors constituting the diode element 511 may also be configured with a plurality of transistors having a common channel direction.

[0133] For example, the transistor 12t may be composed of three transistors, and the transistor constituting the diode element 511 may be composed of two transistors.

[0134] The three transistors constituting the transistor 12t and the two transistors constituting the diode element 511 may be arranged alternately in a direction perpendicular to the channel direction.

[0135] <Cross-sectional structure> 18 is a diagram for explaining a cross section of the semiconductor device 5 on BB' including a transistor constituting the diode element 511 of FIG. 17. Also, FIG. 19 is a diagram for explaining a cross section of the semiconductor device 5 on BB' including a transistor constituting the diode element 511 of FIG. - 1 is a diagram illustrating a cross section of a semiconductor device 5 on a CC' including a mold region 113 (also referred to as a "slit region").

[0136] The cross section of the semiconductor device 5 on the line AA' in FIG. 17 including the transistor 12t on the set side is the same as that shown in FIG.

[0137] The cross-sectional structure on BB' shown in Fig. 18 is different from that shown in Fig. 4 in that the transistor 12t in Fig. 4 is a diode element 511. Specifically, the source electrode 12s and the gate electrode 12g in Fig. 4 are connected to each other and serve as an anode 511a in Fig. 18. Also, the drain electrode 12d in Fig. 4 serves as a cathode 511c in Fig. 18.

[0138] The cross-sectional structure on CC' shown in Fig. 19 is different from that shown in Fig. 4 in that - It is different in that the mold region 113 extends across the separation region.

[0139] That is, p - The mold region 113 is provided in a slit shape along CC' in FIG. - n around the mold region 113 - The pn junction with the type region 112 electrically isolates the diode element 511 from the transistor 12t.

[0140] <Operation of the switching control circuit 50> The operation of the switching control circuit 50 of this embodiment will be described using the above-mentioned general switching control circuit 10 as a comparative example.

[0141] Figures 20 to 24 are diagrams for explaining the operation of the switching control circuit 50. Figures 20 to 23 are various timing charts of the switching control circuit 50, in which Figure 20 shows the VB potential and the VS potential, Figure 21 shows the current flowing through the resistor 13r, Figure 22 shows the drain voltage of the set-side transistor 12t, and Figure 23 shows the HO-VS voltage from the drive circuit 14. Figure 24 shows the GC-VS voltage from the on-off control circuit.

[0142] The operation of the switching control circuit 50 will be described below in chronological order. Note that the waveforms of the comparative example shown in Figures 20 to 24 are the same as those in the example of Figures 11 to 14. In Figures 20 to 24, times t1, t2, and t3 are the same as times t1, t2, and t3 in the example of Figures 11 to 14. In Figures 21 to 24, times t5 and t6 are times after time t3.

[0143] ·Before time t1 In the state where no negative voltage noise is occurring (before time t1), in this embodiment, the potential of the output terminal GC of the ON / OFF control circuit 51 is GC-VS=15 V (VB-VS), that is, the switches 52 and 53 (FIG. 15) are in the OFF state.

[0144] From time t1 to time t2 (period (A)) In this embodiment and the comparative example, when the low-side switching element 22 is turned on at time t1 and negative voltage noise occurs, the drain potentials of the set-side and reset-side transistors 12t, 13t rise (FIG. 22).

[0145] In this embodiment, when the drain potentials of the transistors 12t and 13t become higher than the VS potential by, for example, 30 V or more, the output voltage of the voltage dividing resistor formed by the resistors R1 and R2 of the on / off control circuit 51 (FIG. 16) exceeds the threshold voltage (2 V in this embodiment) of the Schmitt trigger circuit 513, and the potential of the output terminal GC switches to GC-VS=0 V.

[0146] At this time, the Schmitt trigger circuit 513 outputs an L-level signal to the NOT circuit 514. Then, the NOT circuit 514 outputs an H-level signal.

[0147] As a result, the capacitance C1 is charged via the diode element 515. When the voltage of the capacitance C1 exceeds the threshold of the NOT circuit 516, an H-level signal is output to the NOT circuit 516, and the NOT circuit 516 outputs an L-level signal.

[0148] This turns on the switches 52 and 53 (FIG. 15). Even after the negative voltage noise period ends (after time t2), the switches 52 and 53 are kept on for a certain period of time (T1) by the circuit 512 (FIG. 16).

[0149] When the NOT circuit 516 of the circuit 542 starts to output an L-level signal, the capacitor C1 starts to discharge through the resistor R3. When the voltage of the capacitor C1 falls below the threshold of the NOT circuit 516, the NOT circuit 516 outputs an H-level signal. This turns off the switches 52 and 53 (FIG. 15).

[0150] The time (T1) from the end of the negative voltage noise period until the switches 52 and 53 (FIG. 15) are turned off can be set to a predetermined time mainly by adjusting the capacitance value of the capacitor C1 and the resistance value of the resistor R3.

[0151] Time t2 to t5 In this embodiment, when the period of the negative voltage noise ends at time t2 and the VS potential rises, a reverse recovery current starts to flow through the parasitic diode 150.

[0152] In the comparative example, as the reverse recovery current flowing through the parasitic transistor 153 attenuates, the reverse recovery currents through the resistors 12r and 13r start to increase (the same as the period (B) in FIG. 14).

[0153] On the other hand, in this embodiment, a reverse recovery current flows through the switches 52 and 53 (FIG. 15) in the on state, which suppresses the reverse recovery current flowing through the resistors 12r and 13r.

[0154] Therefore, in this embodiment, the current flowing through the resistors 12r and 13r is smaller than that in the comparative example, and the drop in the drain voltage of the transistors 12t and 13t is suppressed (from time t2 to time t5 in FIG. 22).

[0155] From time t5 to time t6 In this embodiment, when a certain time (T1) has elapsed since the end of the negative voltage noise period (time t2), the switches 52 and 53 are turned off (time t5).

[0156] The time T1 is set in advance as the time required to drain the accumulated carriers, as described above. Therefore, when the switches 52 and 53 are turned off, the reverse recovery current has almost disappeared.

[0157] Therefore, the switching control circuit 50 can prevent malfunctions caused by a drop in the drain voltage of the transistors 12t and 13t after the switches 52 and 53 are turned off (FIG. 23).

[0158] In this embodiment, signal transmission is not possible during the period from when the negative voltage noise occurs (time t1) until the switches 52 and 53 are turned off (time t5), and signal transmission becomes possible after time t5.

[0159] ·Time t6 In the comparative example, as the reverse recovery current flowing through the resistors 12r and 13r (FIG. 2) decays, the drain voltage of the set-side transistor 12t increases and exceeds the input threshold of the drive circuit 104 (time t6 in FIG. 22).

[0160] That is, in the comparative example, signal transmission is not possible during the period from when negative voltage noise occurs at time t1 to time t6, but signal transmission becomes possible after time t6.

[0161] Here, the periods during which signal transmission is not possible in this embodiment and the comparative example will be summarized. As described above, the period during which signal transmission is not possible in this embodiment is the period from time t1 to time t5. Moreover, the period during which signal transmission is not possible in the comparative example is the period from time t1 to time t6 (>t5).

[0162] That is, according to this embodiment, the period during which signal transmission is not possible can be made shorter than in the comparative example.

[0163] The time it takes for the reverse recovery current to disappear after the negative voltage noise occurs depends on the magnitude of the reverse recovery current and the impedance of the supply path of the reverse recovery current.

[0164] In this embodiment, by lowering the impedance of the supply path of the reverse recovery current during the period when the switches 52 and 53 are on, a larger reverse recovery current flows than in the comparative example (from time t2 to time t3 in FIG. 21).

[0165] Therefore, in this embodiment, the reverse recovery current disappears in a shorter time than in the comparative example, and the period during which a signal cannot be transmitted in this embodiment is shorter than in the comparative example (FIG. 22).

[0166] According to the switching control circuit 50 of the present embodiment described above, it is possible to prevent malfunction of the drive circuit due to negative voltage noise.

[0167] ==Summary== The switching control circuit 50 of the embodiment described above is a switching control circuit that controls switching of a first switching element on the power supply side and a second switching element on the ground side that drive a load, and includes a first level shift circuit including a first resistor and a first transistor, a drive circuit 14 that drives the first switching element based on the output from the first level shift circuit, a first switch connected in parallel to the first resistor, and an on / off control circuit 51 that turns on the first switch when the low potential side electrode of the first switching element becomes a negative voltage.

[0168] With this configuration, the reverse recovery current caused by the generation of negative voltage noise can be prevented from flowing through the first switch and thus through the first resistor, thereby making it possible to prevent malfunction of the drive circuit due to negative voltage noise.

[0169] The switching control circuit 50 further includes a second level shift circuit including a second resistor and a second transistor, the first level shift circuit outputs a set signal for switching the first switching element from off to on, the second level shift circuit outputs a reset signal for switching the first switching element from on to off, and the drive circuit 14 drives the first switching element based on the set signal and the reset signal. With this configuration, the switching control circuit 50 has high symmetry with respect to the set side and the reset side. This stabilizes the operation of the circuit.

[0170] The switching control circuit further includes a second switch connected in parallel to the second resistor, and the on / off control circuit turns on the second switch when the low potential electrode becomes negative. With this configuration, the symmetry of the switching control circuit 50 is further increased with respect to the set side and the reset side. This further stabilizes the operation of the circuit.

[0171] In the switching control circuit 50, the first and second transistors are n-channel MOS transistors, and the first and second switches are p-channel MOS transistors. With this configuration, the switching control circuit 50 can be easily manufactured.

[0172] The switching control circuit 50 further includes a control circuit 11 that controls the first level shift circuit, the drive circuit 14 is formed in a high side region of the substrate, and the control circuit 11 is formed in a reference potential region electrically isolated from the high side region by a high voltage junction termination region provided around the high side region. With this configuration, interference between the drive circuit 14 and the control circuit 11 can be suppressed.

[0173] In the switching control circuit 50, the on / off control circuit 51 includes a diode element 515 that passes a current when the low potential side electrode is at a negative voltage, and a circuit 512 that turns on the first switch for a predetermined period based on the current that flows through the diode element 515. With this configuration, the period during which the first switch is turned on can be determined in advance, thereby making it possible to shorten the period during which signals cannot be transmitted as much as possible.

[0174] In the above switching control circuit, the diode element 515 is a diode-connected third transistor, the first and third transistors are composed of a plurality of transistors having a common channel direction, and the plurality of transistors are arranged such that the transistors constituting the first and third transistors are alternately arranged in a direction perpendicular to the channel direction. With this configuration, the characteristics of the first and third transistors can be made similar, and the circuit operation can be stabilized.

[0175] The switching control circuit further includes a control circuit for controlling the first level shift circuit, the drive circuit is formed in a high side region of the substrate, the control circuit is formed in a reference potential region electrically isolated from the high side region by a high voltage junction termination region provided around the high side region, and the multiple transistors are formed in the high voltage junction termination region. With this configuration, interference between the drive circuit 14 and the control circuit 11 can be suppressed. [Explanation of symbols]

[0176] Semiconductor Devices 1,5 Switching control circuit 10 Control circuit 11 Level shift circuit 12,13 Resistor 12r, 13r Transistor 12t,13t Drain electrode 13d Source electrode 13s Drive circuit 14 n-channel MOSFET 141 p-channel MOSFET 142 IGBTs 21, 22 Freewheeling diode 23,24 Power supply 25,26 Semiconductor substrate 100 High Side Area 101 High voltage junction termination region 102 Reference potential area 103 VB terminal 105 VS terminal 106 HO terminal 107 GND terminal 108 HIN terminal 109 VCC terminal 110 n-type region 111 n - type area 112 p - type area 113 p-type region 114 Contact Area 115 Drift Region 116 Drain Region 117 Contact Area 118 Source Area 119 p-type region 120 Gate insulating film 122 Parasitic diode 150,151 Parasitic resistance 152 Parasitic transistor 153 Switching control circuit 50 On-off control circuit 51 Diode element 511 Circuit 512 Schmitt trigger circuit 513 NOT circuit 514,516 Diode element 515 Switch 52,53

Claims

1. A switching control circuit that controls switching of a first switching element on a power supply side and a second switching element on a ground side that drive a load, a first level shift circuit including a first resistor and a first transistor; a drive circuit that drives the first switching element based on an output from the first level shift circuit; a first switch connected in parallel with the first resistor; an on-off control circuit that turns on the first switch when a low potential side electrode of the first switching element becomes a negative voltage. Switching control circuit.

2. 2. The switching control circuit of claim 1, a second level shift circuit including a second resistor and a second transistor; the first level shift circuit outputs a set signal for switching the first switching element from off to on; the second level shift circuit outputs a reset signal for switching the first switching element from on to off; The drive circuit drives the first switching element based on the set signal and the reset signal. Switching control circuit.

3. 3. A switching control circuit according to claim 2, a second switch connected in parallel to the second resistor; The on / off control circuit is When the low potential side electrode becomes a negative voltage, the second switch is turned on. Switching control circuit.

4. 4. A switching control circuit according to claim 3, the first and second transistors are n-channel MOS transistors, the first and second switches are p-channel MOS transistors; Switching control circuit.

5. 2. The switching control circuit of claim 1, A control circuit for controlling the first level shift circuit is further provided. The drive circuit includes: formed in a high side region of the substrate, The control circuit includes: A reference potential region is formed in the high side region and electrically isolated from the high side region by a high voltage junction termination region provided around the high side region. Switching control circuit.

6. 2. The switching control circuit of claim 1, The on / off control circuit is a diode element that passes a current when the low potential side electrode is at a negative voltage; a signal output circuit that outputs a signal for turning on the first switch for a predetermined period based on a current flowing through the diode element. Switching control circuit.

7. 7. A switching control circuit according to claim 6, the diode element is a diode-connected third transistor, The first and third transistors are composed of a plurality of transistors having a common channel direction, The plurality of transistors are arranged such that the transistors constituting the first and third transistors are alternately arranged in a direction perpendicular to the channel direction. Switching control circuit.

8. 8. A switching control circuit according to claim 7, A control circuit for controlling the first level shift circuit is further provided. The drive circuit includes: formed in a high side region of the substrate, The control circuit includes: a reference potential region electrically isolated from the high side region by a high voltage junction termination region provided around the high side region; the plurality of transistors are formed in the high voltage junction termination region; Switching control circuit.

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