Drive circuit and liquid discharge device

Abstract

To provide a drive circuit capable of improving the waveform accuracy of a driving signal.SOLUTION: This drive circuit comprises: a first storage unit that stores first and second delay amounts; a modulation circuit that modulates a first basic driving delay signal obtained by delaying a basic driving signal in accordance with the first delay amount and outputs a modulation signal; an amplification circuit that outputs a first amplification modulation signal obtained by amplifying the modulation signal; a level switching signal generation circuit that generates a level switching signal in accordance with a second basic driving delay signal obtained by delaying the basic driving signal in accordance with the second delay amount; a level shifting circuit that outputs the first amplification modulation signal when the level switching signal is at first potential, and outputs a signal obtained by shifting the potential of the first amplification modulation signal when the level switching signal is at second potential higher than the first potential; and a demodulation circuit that demodulates a second amplification modulation signal, and outputs the driving signal.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a drive circuit and a liquid ejection device. [Background technology]

[0002] A liquid ejection device that ejects liquid to form an image or document on a medium is known that uses a piezoelectric element. In such a liquid ejection device, a piezoelectric element is provided corresponding to each of a plurality of nozzles that eject liquid, and each is driven according to a drive signal. When the piezoelectric element is driven, liquid is ejected from the nozzle provided corresponding to the piezoelectric element. In order to operate such a piezoelectric element, it is necessary to supply a sufficient current. Therefore, a drive circuit that outputs a drive signal that drives the piezoelectric element is configured to include an amplifier circuit that amplifies a source signal that is the basis of the drive signal by an amplifier circuit.

[0003] Patent Document 1 discloses a drive circuit that can efficiently amplify a signal by including a pulse modulation circuit that modulates a base drive signal that is the basis of the drive signal and outputs a modulated signal, an amplifier circuit that amplifies the modulated signal and outputs an amplified modulated signal from a first output point, a level shift circuit that shifts the potential of the amplified modulated signal and outputs a level-shift amplified modulated signal from a second output point, and a demodulation circuit that demodulates the level-shift amplified modulated signal and outputs a drive signal. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2022-057167 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in terms of waveform accuracy of the drive signal, the technique described in Patent Document 1 is not sufficient and there is room for improvement. [Means for solving the problem]

[0006] One aspect of the drive circuit according to the present invention is A drive circuit that outputs a drive signal to drive a drive unit, a first storage unit in which the first delay amount and the second delay amount are stored; a first delay circuit that outputs a first master drive delay signal obtained by delaying a master drive signal on which the drive signal is based according to the first delay amount; a second delay circuit that outputs a second master drive delay signal obtained by delaying the master drive signal according to the second delay amount; a modulation circuit that modulates the first group drive delay signal and outputs a modulated signal; an amplifier circuit that amplifies the modulated signal and outputs a first amplified modulated signal; a level switching signal generating circuit that generates a level switching signal, which is a digital signal including a first potential and a second potential higher than the first potential, in response to the second unit drive delay signal; a level shift circuit that outputs the first amplified modulated signal as a second amplified modulated signal when the level switching signal is at the first potential, and outputs a signal obtained by shifting a potential of the first amplified modulated signal as the second amplified modulated signal when the level switching signal is at the second potential; a demodulation circuit that demodulates the second amplified modulated signal and outputs the drive signal; Equipped with.

[0007] One aspect of the liquid ejection device according to the present invention is to A discharge unit that discharges liquid; A drive circuit that outputs a drive signal for driving the ejection unit; Equipped with The drive circuit includes: a first storage unit in which the first delay amount and the second delay amount are stored; a first delay circuit that outputs a first master drive delay signal obtained by delaying a master drive signal on which the drive signal is based according to the first delay amount; a second delay circuit that outputs a second master drive delay signal obtained by delaying the master drive signal according to the second delay amount; a modulation circuit that modulates the first group drive delay signal and outputs a modulated signal; an amplifier circuit that amplifies the modulated signal and outputs a first amplified modulated signal; a level switching signal generating circuit that generates a level switching signal, which is a digital signal including a first potential and a second potential higher than the first potential, in response to the second unit drive delay signal; a level shift circuit that outputs the first amplified modulated signal as a second amplified modulated signal when the level switching signal is at the first potential, and outputs a signal obtained by shifting a potential of the first amplified modulated signal as the second amplified modulated signal when the level switching signal is at the second potential; a demodulation circuit that demodulates the second amplified modulated signal and outputs the drive signal; Equipped with. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram illustrating an example of a structure of a liquid ejection device. [Diagram 2] FIG. 2 is a diagram illustrating a functional configuration of the liquid ejection device. [Diagram 3] FIG. 4 is a diagram showing an example of an arrangement of a plurality of ejection parts in a head unit. [Figure 4] FIG. 4 is a diagram illustrating an example of a configuration of a discharge unit. [Diagram 5] FIG. 4 is a diagram showing an example of a signal waveform of a drive signal. [Figure 6] FIG. 2 is a diagram illustrating an example of a functional configuration of a drive circuit in the first embodiment. [Figure 7] FIG. 4 is a diagram for explaining the operation of the drive circuit in the first embodiment. [Figure 8] 4A to 4C are diagrams illustrating an example of waveforms of a master drive signal, a first master drive delay signal, a second master drive delay signal, a level switching signal, and a drive signal in the first embodiment. [Figure 9] FIG. 11 is a diagram illustrating an example of a functional configuration of a drive circuit in a second embodiment. [Figure 10] FIG. 11 is a diagram for explaining the operation of the drive circuit in the second embodiment. [Figure 11]13A to 13C are diagrams illustrating an example of waveforms of a base drive signal, a first base drive delay signal, a second base drive delay signal, a level switching signal, and a drive signal in the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Preferred embodiments of the present invention will be described below with reference to the drawings. The drawings are used for the convenience of explanation. Note that the embodiments described below do not unduly limit the contents of the present invention described in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0010] In the following description, a consumer inkjet printer is used as an example of the liquid ejection device according to the present invention. However, the liquid ejection device is not limited to an inkjet printer, and may be, for example, a color material ejection device used in manufacturing color filters for liquid crystal displays and the like, an electrode material ejection device used in forming electrodes for organic electroluminescence displays, surface-emitting displays and the like, a bioorganic material ejection device used in manufacturing biochips, and the like.

[0011] 1. First embodiment 1-1. Overview of liquid ejection device FIG. 1 is a diagram showing an example of the structure of a liquid ejection device 1. As shown in FIG. The apparatus 1 includes a moving body 2 and a moving unit 3 that moves the moving body 2 back and forth along the main scanning direction.

[0012] The moving unit 3 has a carriage motor 31 which serves as a drive source for the reciprocating movement of the moving body 2 along the main scanning direction, a carriage guide shaft 32 which has both ends fixed, and a timing belt 33 which extends approximately parallel to the carriage guide shaft 32 and is driven by the carriage motor 31.

[0013] The moving body 2 has a carriage 24. The carriage 24 is supported by a carriage guide shaft 32 so as to be freely reciprocating, and is fixed to a part of a timing belt 33. Then, the carriage motor 31 drives the timing belt 33 forward and backward, so that the moving body 2 having the carriage 24 reciprocates while being guided by the carriage guide shaft 32. In addition, a head unit 20 is located in a portion of the moving body 2 facing the medium P. That is, the head unit 20 is mounted on the carriage 24. A large number of nozzles that eject ink as a liquid are located on the surface of the head unit 20 facing the medium P. In addition, various control signals for controlling the operation of the head unit 20 are supplied to the head unit 20 via a cable 190. As such a cable 190, a flexible flat cable that can slide following the reciprocating movement of the moving body 2 can be used.

[0014] The liquid ejection device 1 also includes a transport unit 4 that transports the medium P along the transport direction on a platen 40. The transport unit 4 has a transport motor 41 that is a drive source for transporting the medium P, and a transport roller 42 that rotates in response to the driving force of the transport motor 41 to transport the medium P along the transport direction.

[0015] In the liquid ejection device 1 configured as described above, the head unit 20 ejects ink onto the medium P in synchronization with the timing at which the medium P is transported by the transport unit 4. As a result, the ink ejected by the head unit 20 lands at the desired position on the medium P, forming the desired image or characters on the surface of the medium P.

[0016] Next, a description will be given of the functional configuration of the liquid ejection device 1. Fig. 2 is a diagram showing the functional configuration of the liquid ejection device 1. As shown in Fig. 2, the liquid ejection device 1 includes a control unit 10, a head unit 20, a moving unit 3, a transport unit 4, and a cable 190. The cable 190 electrically connects the control unit 10 and the head unit 20.

[0017] The control unit 10 includes a power supply circuit 11, a control unit 100, and a drive circuit 50.

[0018] The power supply circuit 11 generates voltage signals VHV1, VHV2, and VDD of a predetermined voltage value from a commercial AC power supply supplied from outside the liquid ejection device 1, and outputs the voltage signals to each part of the liquid ejection device 1. Here, the voltage signals VHV1 and VHV2 output by the power supply circuit 11 are, for example, a DC voltage of 21 V, and the voltage signal VDD is, for example, a DC voltage of 3.3 V. Such a power supply circuit 11 may be configured to include, for example, an AC / DC converter that generates a DC voltage of a predetermined voltage value from the commercial AC power supply, and a DC / DC converter that generates the voltage signals VHV1, VHV2, and VDD by converting the voltage value of the generated DC voltage. Note that the power supply circuit 11 may output a DC voltage of a different voltage value in addition to the voltage signals VHV1, VHV2, and VDD. In the following description, the voltage of the voltage signal VHV1 may be referred to as a voltage vhv1, the voltage of the voltage signal VHV2 may be referred to as a voltage vhv2, and the voltage of the voltage signal VDD may be referred to as a voltage vdd.

[0019] The control unit 100 receives image data from an external device (not shown) provided outside the liquid ejection device 1, such as a host computer. By performing various image processing and the like on the image data, various control signals for controlling each part of the liquid ejection device 1 are generated and output to each part.

[0020] Specifically, the control unit 100 generates a control signal Ctrl1 for controlling the reciprocating movement of the moving body 2 based on the image data, and outputs it to a carriage motor 31 included in the moving unit 3. The control unit 100 also generates a control signal Ctrl2 for controlling the transport of the medium P based on the image data, and outputs it to a transport motor 41 included in the transport unit 4. In this way, the control unit 100 controls the reciprocating movement of the moving body 2 along the main scanning direction and the transport of the medium P along the transport direction. In other words, the head unit 20 can eject ink onto the medium P at a predetermined timing synchronized with the transport of the medium P. This makes it possible to land ink at a desired position on the medium P, and form a desired image or character on the medium P.

[0021] In addition, the control unit 100 may convert the control signal Ctrl1 for controlling the reciprocating movement of the moving body 2 into a signal by a carriage motor driver not shown, and then supply it to the moving unit 3.Similarly, the control signal Ctrl2 for controlling the transportation of the medium P may be converted into a signal by a transport motor driver not shown, and then supply it to the transport unit 4.

[0022] The control unit 100 also outputs a basic drive signal dA to the drive circuit 50. This basic drive signal dA is a digital signal including information that defines the signal waveform of the drive signal COM supplied to the head unit 20. The drive circuit 50 converts the basic drive signal dA into an analog signal, and then generates the drive signal COM by amplifying the converted analog signal. The drive circuit 50 then supplies the generated drive signal COM to the head unit 20. The configuration and operation of the drive circuit 50 will be described in detail later.

[0023] The control unit 100 also generates a drive data signal DATA for controlling the operation of the head unit 20 and outputs it to the head unit 20. The head unit 20 has a selection control unit 210, a plurality of selection units 230, and a liquid ejection head 21. The liquid ejection head 21 also has a plurality of ejection units 600 including a piezoelectric element 60. Each of the plurality of selection units 230 is provided corresponding to the piezoelectric element 60 included in each of the plurality of ejection units 600 of the liquid ejection head 21.

[0024] A drive data signal DATA is input to the selection control unit 210. The selection control unit 210 generates a selection signal S that instructs each of the selection units 230 whether to select or not select the drive signal COM based on the drive data signal DATA, and outputs the selection signal S to each of the selection units 230. The drive signal COM and the corresponding selection signal S are input to each of the selection units 230. Each of the selection units 230 generates and outputs a drive signal VOUT by selecting or not selecting the drive signal COM based on the selection signal S. That is, each of the selection units 230 generates a drive signal VOUT based on the drive signal COM, and supplies it to one end of the piezoelectric element 60 included in the corresponding ejection unit 600 included in the liquid ejection head 21.

[0025] A reference voltage signal VBS is commonly supplied to the other ends of the piezoelectric elements 60 included in the multiple ejection parts 600. The reference voltage signal VBS is a signal that functions as a reference potential for driving the piezoelectric elements 60 driven by the drive signal VOUT, and is a signal of a constant potential such as 5.5 V, 6 V, or ground potential (0 V).

[0026] The piezoelectric elements 60 are provided corresponding to each of the multiple nozzles in the head unit 20. The piezoelectric elements 60 are driven in response to the potential difference between a drive signal VOUT supplied to one end and a reference voltage signal VBS supplied to the other end. An amount of ink is ejected from the ejection section 600 according to the amount of driving of the piezoelectric element 60 .

[0027] In addition, while Figure 2 illustrates a case where the head unit 20 has one liquid ejection head 21, the number of liquid ejection heads 21 that the head unit 20 has is not limited to one, and the head unit 20 may have multiple liquid ejection heads 21 depending on the type and number of inks to be ejected, etc.

[0028] As described above, the liquid ejection device 1 in this embodiment has a plurality of piezoelectric elements 60 that are driven by the supply of drive signals COM and VOUT, and is equipped with a liquid ejection head 21 that ejects ink as an example of a liquid by driving the plurality of piezoelectric elements 60, and a drive circuit 50 that outputs the drive signal COM.

[0029] 1-2. Configuration of the discharge section Next, an example of the configuration of the multiple ejection parts 600 of the liquid ejection head 21 and an arrangement of the multiple ejection parts 600 in the head unit 20 will be described. Fig. 3 is a diagram showing an example of the arrangement of the multiple ejection parts 600 in the head unit 20. Fig. 3 illustrates an example in which the head unit 20 has four liquid ejection heads 21.

[0030] As shown in FIG. 3, each of the four liquid ejection heads 21 has a plurality of ejection sections 600 arranged in a row in one direction. That is, the liquid ejection head 21 includes a nozzle row L in which nozzles 651, which will be described later and are included in the ejection section 600, are arranged in one direction. The liquid ejection heads 21 are also arranged in the head unit 20 in a row in a direction intersecting the nozzle row L. That is, the head unit 20 is formed with the same number of nozzle rows L as the liquid ejection heads 21. Note that the arrangement of the nozzles 651 in the nozzle row L is not limited to one row, and may be arranged in a staggered manner such that, for example, the even-numbered nozzles 651 counting from one end of the plurality of nozzles 651 and the odd-numbered nozzles 651 counting from one end of the plurality of nozzles 651 are positioned at different positions, or the plurality of nozzles 651 may be arranged in two or more rows to form one nozzle row L.

[0031] Next, an example of the configuration of the ejection unit 600 will be described. FIG. 4 is a diagram showing an example of the configuration of the ejection unit 600. As shown in FIG. 4, the ejection unit 600 includes a piezoelectric element 60, a vibration plate 621, a cavity 631, and a nozzle 651. The vibration plate 621 is displaced in response to the driving of the piezoelectric element 60 provided on the upper surface in FIG. 4. The vibration plate 621 functions as a diaphragm that expands / contracts the internal volume of the cavity 631. The inside of the cavity 631 is filled with ink. The cavity 631 functions as a pressure chamber whose internal volume changes due to the displacement of the vibration plate 621 caused by the driving of the piezoelectric element 60. The nozzle 651 is an opening formed in the nozzle plate 632 and communicates with the cavity 631. Then, as the internal volume of the cavity 631 changes, the ink stored inside the cavity 631 is ejected from the nozzle 651.

[0032] Piezoelectric element 60 has a structure in which piezoelectric body 601 is sandwiched between a pair of electrodes 611, 612. In piezoelectric body 601 of this structure, the electrodes 611, 612 and the central portion of diaphragm 621 bend in the vertical direction in FIG.

[0033] Specifically, a drive signal VOUT is supplied to an electrode 611, which is one end of the piezoelectric element 60, and a reference voltage signal VBS is supplied to an electrode 612, which is the other end. When the piezoelectric element 60 is driven upward in response to a change in the voltage of the drive signal VOUT, the vibration plate 621 is displaced upward. As a result, the internal volume of the cavity 631 expands. Therefore, the ink stored in the reservoir 641 is drawn into the cavity 631. On the other hand, when the piezoelectric element 60 is driven downward in response to a change in the voltage value of the drive signal VOUT, the vibration plate 621 is displaced downward. As a result, the internal volume of the cavity 631 is reduced. Therefore, an amount of ink is ejected from the nozzle 651 according to the degree of reduction in the internal volume of the cavity 631.

[0034] As described above, the liquid ejection head 21 includes the piezoelectric element 60, and ejects ink onto the medium P by driving the piezoelectric element 60. Note that the ejection section 600 and the piezoelectric element 60 included in the ejection section 600 are not limited to the configuration shown in the figure, and may have any structure as long as the piezoelectric element 60 is driven based on the drive signal VOUT and ink is ejected from the corresponding nozzle 651 by driving the piezoelectric element 60.

[0035] 1-3. Configuration and operation of the drive circuit Next, the configuration and operation of the drive circuit 50 will be described.

[0036] 1-3-1. Signal waveform of drive signal COM In describing the configuration and operation of the drive circuit 50, an example of the signal waveform of the drive signal COM output by the drive circuit 50 will first be described. FIG. 5 is a diagram showing an example of the signal waveform of the drive signal COM. As shown in FIG. 5, the drive signal COM includes a trapezoidal waveform Adp for each period T. The trapezoidal waveform Adp includes a certain period at voltage vc, a certain period at voltage vb lower than voltage vc following the certain period at voltage vc, a certain period at voltage vt higher than voltage vc following the certain period at voltage vb, and a certain period at voltage vc following the certain period at voltage vt. That is, the drive signal COM changes voltage between voltage vt and voltage vb, and includes a trapezoidal waveform Adp that starts at voltage vc and ends at voltage vc in period T.

[0037] The voltage vc corresponds to a potential that is a reference for the displacement of the piezoelectric element 60. When the voltage of the drive signal COM supplied to the piezoelectric element 60 changes from the voltage vc to the voltage vb, the piezoelectric element 60 is driven in the upward direction shown in FIG. 4. As a result, the vibration plate 621 is displaced in the upward direction shown in FIG. 4. When the vibration plate 621 is displaced in the upward direction shown in FIG. 4, the internal volume of the cavity 631 expands, and ink is drawn from the reservoir 641 into the cavity 631. After that, the voltage of the drive signal COM supplied to the piezoelectric element 60 changes from the voltage vb to the voltage vt, and the piezoelectric element 60 is driven in the downward direction shown in FIG. 4. As a result, the vibration plate 621 is displaced in the downward direction shown in FIG. 4. When the vibration plate 621 is displaced in the downward direction shown in FIG. 4, the internal volume of the cavity 631 decreases, and the ink stored in the cavity 631 is ejected from the nozzle 651.

[0038] Furthermore, the ink near the nozzle 651 and the diaphragm 621 may continue to vibrate for a certain period after the ink is ejected from the nozzle 651 by driving the piezoelectric element 60. The certain period of the voltage vc included in the drive signal COM also functions as a period for stopping such vibrations that occur in the ink and the diaphragm 621 and do not contribute to the ejection of ink.

[0039] Here, the signal waveform of the drive signal COM shown in Figure 5 is an example and is not limited to this, and may include signal waveforms of various shapes depending on the physical properties of the ink ejected by the liquid ejection head 21, the length of the period T of the drive signal COM, the transport speed of the medium P, etc.

[0040] 1-3-2.Drive circuit configuration Next, the configuration of the drive circuit 50 will be described. Fig. 6 is a diagram showing an example of the functional configuration of the drive circuit 50 in the first embodiment. As shown in Fig. 6, the drive circuit 50 has a D / A conversion circuit 510, an adder 511, a pulse modulation circuit 520, an inverter 521, a demodulation circuit 560, a feedback circuit 570, a first storage unit 700, a second storage unit 702, a first delay circuit 704, a second delay circuit 706, a level switching signal generation circuit 710, and an amplification level shift circuit 800. .

[0041] The first delay circuit 704 and the second delay circuit 706 receive a base drive signal dA, which is a digital signal, from the control unit 100. The first delay circuit 704 outputs a first base drive delay signal dA1 obtained by delaying the base drive signal dA according to the first delay amount dly1. The second delay circuit 706 outputs a second base drive delay signal dA2 obtained by delaying the base drive signal dA according to the second delay amount dly2. For example, the first delay circuit 704 outputs a first base drive delay signal dA1 obtained by delaying the base drive signal dA by the first delay amount dly1, and the second delay circuit 706 outputs a second base drive delay signal dA2 obtained by delaying the base drive signal dA by the second delay amount dly2. The drive circuit 50 outputs a signal obtained by amplifying the base drive signal aA as the drive signal COM, so the base drive signal aA is a signal that is the basis of the drive signal COM.

[0042] The first storage unit 700 stores the first delay amount dly1 and the second delay amount dly2. The first storage unit 700 may be, for example, a non-volatile memory. Alternatively, the first storage unit 700 may be a volatile memory, and the first delay amount dly1 and the second delay amount dly2 may be set in the first storage unit 700 by external communication from the control unit 100 or the like. In other words, the first delay amount dly1 and the second delay amount dly2 may be predetermined values, or may be rewritable from outside the drive circuit 50.

[0043] The first master drive delay signal dA1, which is a digital signal, is input to the D / A conversion circuit 510 from the first delay circuit 704. The D / A conversion circuit 510 performs digital-to-analog conversion on the first master drive delay signal dA1, and then outputs the converted analog signal as the master drive signal aA. The voltage amplitude of this master drive signal aA is, for example, 1 to 2 V, and the drive circuit 50 outputs a signal obtained by amplifying the master drive signal aA as the drive signal COM. In other words, the master drive signal aA corresponds to a signal that is a target before amplification of the drive signal COM.

[0044] The base drive signal aA is input to the positive input terminal of the adder 511. A feedback signal VFB, which is the drive signal COM fed back via a feedback circuit 570 (described later), is input to the negative input terminal of the adder 511. The adder 511 then outputs a signal obtained by subtracting the feedback signal VFB from the base drive signal aA to the pulse modulation circuit 520.

[0045] The pulse modulation circuit 520 generates a modulated signal MS by pulse-modulating the signal output by the adder 511. The modulated signal MS is a digital signal including an L-level potential and an H-level potential higher than the L-level. The pulse modulation circuit 520 outputs the generated modulated signal MS to the amplifier circuit 550. The pulse modulation circuit 520 generates a pulse density modulated signal (PDM signal) by modulating the signal output by the adder 511 by a pulse density modulation (PDM) method, and outputs the PDM signal as the modulated signal MS to the amplifier circuit 550. Specifically, the pulse modulation circuit 520 compares the voltage of the output signal of the adder 511 with a predetermined reference voltage vref. The pulse modulation circuit 520 generates and outputs a modulated signal MS that is H level when the voltage of the output signal of the adder 511 is larger than the reference voltage vref, and is L level when the voltage of the output signal of the adder 511 is smaller than the reference voltage vref.

[0046] In this manner, the circuit configured by the D / A conversion circuit 510, the adder 511, and the pulse modulation circuit 520 functions as a modulation circuit 500 that modulates the first unit drive delay signal dA1 and outputs the modulated signal MS.

[0047] The level switching signal generating circuit 710 receives the second unit drive delay signal dA2 and generates a level switching signal LS in response to the second unit drive delay signal dA2. The level switching signal LS is a digital signal that includes an L level potential and an H level potential that is higher than the L level. The level switching signal generating circuit 710 switches the level switching signal LS from L level to H level when the value of the second unit drive delay signal dA2 increases and becomes larger than the threshold value dvth while the level switching signal LS is at L level. Also, the level switching signal generating circuit 710 switches the level switching signal LS from H level to L level when the value of the second unit drive delay signal dA2 decreases and becomes smaller than the threshold value dvth while the level switching signal LS is at H level.

[0048] The second storage unit 702 stores the threshold value dvth. The second storage unit 702 may be, for example, a non-volatile memory. Alternatively, the second storage unit 702 may be a volatile memory, and the threshold value dvth may be set in the second storage unit 702 by external communication from the control unit 100 or the like. In other words, the threshold value dvth may be a predetermined value, or may be rewritable from outside the drive circuit 50.

[0049] The second storage unit 702 may be a storage unit different from the first storage unit 700, or may be the same storage unit as the first storage unit 700. That is, the first delay amount dly1, the second delay amount dly2, and the threshold value dvth may be stored separately in two storage units, or may be stored in one storage unit.

[0050] The amplification level shift circuit 800 includes transistors M1 and M2 that switch in response to the modulation signal MS, and transistors M3 and M4 that switch in response to the level switching signal LS, and outputs an amplified modulation signal obtained by amplifying the modulation signal MS when the level switching signal LS is at an L level, and outputs a signal obtained by shifting the potential of the amplified modulation signal when the level switching signal LS is at an H level.

[0051] In this embodiment, the amplification level shift circuit 800 includes an amplification circuit 550 and a level shift circuit 750. The amplification circuit 550 outputs a first amplified modulation signal AMS1, which is an amplified modulation signal obtained by amplifying the modulation signal MS, by the switching operation of the transistors M1 and M2. The level shift circuit 750 outputs the first amplified modulation signal AMS1 as the second amplified modulation signal AMS2 when the level switching signal LS is at the L level, and outputs a signal obtained by shifting the potential of the first amplified modulation signal AMS1 as the second amplified modulation signal AMS2 when the level switching signal LS is at the H level, by the switching operation of the transistors M3 and M4. The configurations of the amplification circuit 550 and the level shift circuit 750 will be described in detail below.

[0052] The amplifier circuit 550 includes a gate drive circuit 530, a diode D1, a capacitor C1, and transistors M1 and M2. The amplifier circuit 550 generates a first amplified modulated signal AMS1 by amplifying the modulated signal MS, and outputs the first amplified modulated signal AMS1 from a first output point OP1.

[0053] The gate drive circuit 530 outputs gate signals HGD1 and LGD1 based on the modulation signal MS. Specifically, the modulation signal MS is input to a gate driver 531 included in the gate drive circuit 530, and the gate driver 531 generates a gate signal HGD1 by level-shifting the modulation signal MS and outputs it to the transistor M1. The modulation signal MS is also input to a gate driver 532 included in the gate drive circuit 530 after its logical level is inverted by an inverter 521, and the gate driver 532 generates a gate signal LGD1 by level-shifting a signal obtained by inverting the logical level of the modulation signal MS and outputs it to the transistor M2.

[0054] The transistors M1 and M2 are both configured as N-channel MOSFETs. The transistor M1 has a source terminal, which is one end, electrically connected to a first output point OP1 from which a first amplified modulation signal AMS1 is output, and a drain terminal, which is the other end, is supplied with a voltage vhv1 of the voltage signal VHV1 as a power supply voltage. The transistor M1 is driven based on a gate signal HGD1 input to a gate terminal. The transistor M2 has a drain terminal which is one end electrically connected to the first output point OP1, a source terminal which is the other end is supplied with a ground potential, and operates based on a gate signal LGD1 input to a gate terminal.

[0055] Then, the transistor M1 operates based on the gate signal HGD1, and the transistor M2 operates based on the gate signal LGD1, whereby a first amplified modulated signal AMS1 obtained by amplifying the modulated signal MS with the voltage vhv1 is generated at the first output point OP1.

[0056] Here, the operation of the gate drive circuit 530 will be described. The gate drive circuit 530 includes gate drivers 531 and 532. As described above, the gate driver 531 receives the modulation signal MS, and the gate driver 532 receives a signal in which the logic level of the modulation signal MS is inverted by the inverter 521. That is, the signal input to the gate driver 531 and the signal input to the gate driver 532 are exclusively at H level. Here, exclusively at H level includes the case where an H level signal is not input to the gate driver 531 and the gate driver 532 at the same time. That is, it does not exclude the case where an L level signal is input to the gate driver 531 and the gate driver 532 at the same time.

[0057] The low-potential power supply terminal of the gate driver 531 is electrically connected to the first output point OP1. Therefore, the signal generated at the first output point OP1 is supplied as a voltage signal HVS1 to the low-potential power supply terminal of the gate driver 531. The high-potential power supply terminal of the gate driver 531 is electrically connected to the cathode terminal of the diode D1 and one end of the capacitor C1. The anode terminal of the diode D1 is supplied with a voltage vm, and the other end of the capacitor C1 is electrically connected to the first output point OP1. That is, the diode D1 and the capacitor C1 form a bootstrap circuit, and the output voltage of the bootstrap circuit is supplied to the high-potential power supply terminal of the gate driver 531. Therefore, the high-potential power supply terminal of the gate driver 531 is supplied with a voltage signal HVD1 that is higher by a voltage vm than the voltage signal HVS1 input to the low-potential power supply terminal of the gate driver 531.

[0058] Therefore, when an H-level modulation signal MS is input, the gate driver 531 outputs a gate signal HGD1 whose voltage is based on a voltage signal HVD1 whose voltage is higher by a voltage vm than the voltage of the first output point OP1, and when an L-level modulation signal MS is input, the gate driver 531 outputs a gate signal HGD1 whose voltage is based on a voltage signal HVS1, which is the voltage of the first output point OP1.

[0059] Here, the voltage vm is a voltage capable of driving each of the transistors M1, M2 and the transistors M3, M4 described later, and is, for example, a DC voltage of 7.5 V. Such a voltage vm is generated, for example, by stepping down or stepping up the voltage signals VHV1, VHV2, VDD output by the power supply circuit 11.

[0060] A ground potential signal is supplied as a voltage signal LVS1 to a low potential power supply terminal of the gate driver 532. A voltage vm is supplied as a voltage signal LVD1 to a high potential power supply terminal of the gate driver 532. Thus, when an H level signal obtained by inverting the logical level of an L level modulation signal MS by the inverter 521 is input to the gate driver 532, the gate driver 532 outputs a gate signal LGD1 of a voltage based on the voltage signal LVD1 of the voltage vm, and when an L level signal obtained by inverting the logical level of an H level modulation signal MS by the inverter 521 is input to the gate driver 532, the gate driver 532 outputs a gate signal LGD1 of a voltage based on the voltage signal LVS1 of the ground potential.

[0061] The level shift circuit 750 includes a gate drive circuit 730, diodes D11 and D12, The level shift circuit 750 includes capacitors C11 and C12, transistors M3 and M4, and a bootstrap circuit BS. The level shift circuit 750 outputs the first amplified modulated signal AMS1 or a signal obtained by shifting the potential of the first amplified modulated signal AMS1 as a second amplified modulated signal AMS2 to a second output point OP2.

[0062] The gate drive circuit 730 outputs a gate signal HGD2 for driving the transistor M3 and a gate signal LGD2 for driving the transistor M4 based on the level switching signal LS. Specifically, the level switching signal LS is input to a gate driver 731 included in the gate drive circuit 730, and the gate driver 731 generates a gate signal HGD2 by level-shifting the level switching signal LS and outputs it to the transistor M3. The level switching signal LS is also input to a gate driver 732 included in the gate drive circuit 730 after its logical level is inverted by an inverter 721, and the gate driver 732 generates a gate signal LGD2 by level-shifting a signal obtained by inverting the logical level of the level switching signal LS and outputs it to the transistor M4.

[0063] The transistors M3 and M4 are both configured with N-channel MOSFETs. The transistor M3 has a source terminal which is one end electrically connected to a second output point OP2 from which the second amplified modulation signal AMS2 is output, a power supply voltage is supplied to the drain terminal which is the other end, and the transistor M3 operates based on a gate signal HGD2 input to the gate terminal. The transistor M4 has a drain terminal which is one end electrically connected to the second output point OP2, a source terminal which is the other end is supplied with the first amplified modulation signal AMS1, and the transistor M4 operates based on a gate signal LGD2 input to the gate terminal.

[0064] Then, with transistor M3 operating based on gate signal HGD2 and transistor M4 operating based on gate signal LGD2, the first amplified modulated signal AMS1 or a signal with the potential of the first amplified modulated signal AMS1 shifted is generated as the second amplified modulated signal AMS2 at the second output point OP2.

[0065] The bootstrap circuit BS includes a diode D13 and a capacitor C13. One end of the capacitor C13 is electrically connected to the first output point OP1, the first amplified modulation signal AMS1 is supplied to the one end, and the other end is electrically connected to the drain terminal of the transistor M3. The voltage signal VHV2 is supplied to the anode terminal of the diode D13, and the cathode terminal of the diode D13 is electrically connected to the other end of the capacitor C13 and the drain terminal of the transistor M3. Although only one diode D13 is illustrated in FIG. 6, the bootstrap circuit BS may include a plurality of diodes D13 connected in series. That is, the bootstrap circuit BS includes N diodes D13, where N is a predetermined integer equal to or greater than 1. Therefore, a voltage vhv2-vf×N, which is the difference between the voltage vhv2 of the voltage signal VHV2 and the sum vf×N of the forward drop voltages of the N diodes D13, is supplied to the drain terminal of the transistor M3 as a power supply voltage. When the transistor M2 of the amplifier circuit 550 is conductive, charge is stored in the capacitor 13, so that the voltage across the capacitor 13 becomes the voltage vhv2-vf×N.

[0066] Then, the bootstrap circuit BS generates a voltage signal VHV3 by adding the voltage of the first amplified modulation signal AMS1 to the voltage vhv2-vf×N across the capacitor 13, and outputs it to the drain terminal of the transistor M3. In other words, the bootstrap circuit BS outputs a voltage signal VHV3 obtained by level-shifting the potential of the first amplified modulation signal AMS1 by the voltage vhv2-vf×N.

[0067] Here, the operation of the gate drive circuit 730 will be described. The gate drive circuit 730 includes gate drivers 731 and 732. As described above, the gate driver 731 A level switching signal LS is input to gate driver 731, and a signal in which the logical level of level switching signal LS is inverted by inverter 721 is input to gate driver 732. That is, the signal input to gate driver 731 and the signal input to gate driver 732 are exclusively at H level. Here, exclusively at H level includes the case where an H level signal is not input to gate driver 731 and gate driver 732 at the same time. That is, it does not exclude the case where an L level signal is input to gate driver 731 and gate driver 732 at the same time.

[0068] The low-potential power supply terminal of the gate driver 731 is connected to the second output point OP2. Therefore, the signal generated at the second output point OP2 is supplied as a voltage signal HVS2 to the low-potential power supply terminal of the gate driver 731. The high-potential power supply terminal of the gate driver 731 is electrically connected to the cathode terminal of the diode D11 and one end of the capacitor C11. The anode terminal of the diode D11 is supplied with a voltage vm, and the other end of the capacitor C11 is electrically connected to the second output point OP2. That is, the diode D11 and the capacitor C11 form a bootstrap circuit, and the output voltage of the bootstrap circuit is supplied to the high-potential power supply terminal of the gate driver 731. Therefore, the high-potential power supply terminal of the gate driver 731 is supplied with a voltage signal HVD2 that is higher by a voltage vm than the voltage signal HVS2 input to the low-potential power supply terminal of the gate driver 731. Therefore, when an H-level level switching signal LS is input, the gate driver 731 outputs a gate signal HGD2 whose voltage is based on a voltage signal HVD2 whose voltage is higher by a voltage vm than the voltage of the second output point OP2, and when an L-level level switching signal LS is input, the gate driver 731 outputs a gate signal HGD2 whose voltage is based on a voltage signal HVS2, which is the voltage of the second output point OP2.

[0069] The low-potential power supply terminal of the gate driver 732 is connected to the first output point OP1. Therefore, the first amplified modulation signal AMS1 generated at the first output point OP1 is supplied as a voltage signal LVS2 to the low-potential power supply terminal of the gate driver 732. In addition, the high-potential power supply terminal of the gate driver 732 is electrically connected to the cathode terminal of the diode D12 and one end of the capacitor C12. In addition, the anode terminal of the diode D12 is supplied with a voltage vm, and the other end of the capacitor C12 is electrically connected to the first output point OP1. That is, the diode D12 and the capacitor C12 form a bootstrap circuit, and the output voltage of the bootstrap circuit is supplied to the high-potential power supply terminal of the gate driver 732. Therefore, the high-potential power supply terminal of the gate driver 732 is supplied with a voltage signal LVD2 having a voltage higher than the voltage signal LVS2 input to the low-potential power supply terminal of the gate driver 732 by a voltage vm.

[0070] Therefore, when an H-level signal obtained by inverting the logical level of the L-level level switching signal LS by the inverter 721 is input to the gate driver 732, the gate driver 732 outputs a gate signal LGD2 of a voltage value based on a voltage signal LVD2 which is a voltage vm higher than the voltage of the first output point OP1 when an H-level signal obtained by inverting the logical level of the L-level level switching signal LS by the inverter 721 is input, and outputs a gate signal HGD2 of a voltage value based on a voltage signal LVS2 which is the voltage of the first output point OP1 when an L-level signal obtained by inverting the logical level of the H-level level switching signal LS by the inverter 721 is input.

[0071] In the level shift circuit 750 configured as above, when the level switching signal generation circuit 710 outputs a level switching signal LS of L level, the first output point OP1 of the amplifier circuit 550 and the second output point OP2 of the level shift circuit 750 are electrically connected via the transistor M4. Therefore, when the level switching signal LS is at L level, the level shift circuit 750 outputs the first amplified and converted signal OP2 supplied to the second output point OP2 via the transistor M4. The modulated signal AMS1 is output as a second amplified modulated signal AMS2.

[0072] On the other hand, when the level switching signal generation circuit 710 outputs an H-level level switching signal LS, the first output point OP1 of the amplifier circuit 550 and the second output point OP2 of the level shift circuit 750 are electrically connected via the bootstrap circuit BS and the transistor M3. Therefore, when the level switching signal LS is at an H level, the level shift circuit 750 outputs, as the second amplified modulation signal AMS2, a voltage signal VHV3, which is a signal obtained by shifting the potential of the first amplified modulation signal AMS1 by the voltage vhv2-vf×N of the voltage signal VHV2.

[0073] In the following description, an operation mode in which the level shift circuit 750 outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2 is referred to as a first mode MD1, and an operation mode in which the level shift circuit 750 outputs a signal obtained by level-shifting the potential of the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2 is referred to as a second mode MD2. That is, the level shift circuit 750 is in the first mode MD1 when the level switching signal LS is at an L level, and in the second mode MD2 when the level switching signal LS is at an H level.

[0074] For example, when the value of the second unit drive delay signal dA2 is smaller than the threshold value dvth, the level switching signal generating circuit 710 outputs the level switching signal LS of L level, and the operation mode of the level shift circuit 750 becomes the first mode MD1. After that, when the value of the second unit drive delay signal dA2 becomes larger than the threshold value dvth, the level switching signal generating circuit 710 switches the level switching signal LS from L level to H level. As a result, the operation mode of the level shift circuit 750 is switched from the first mode MD1 to the second mode MD2. Then, immediately after switching the level switching signal LS from L level to H level, the level switching signal generating circuit 710 outputs a pulse signal that becomes L level for a short period of time as the level switching signal LS one or more times in order to reduce waveform distortion of the drive signal COM that may occur due to switching of the operation mode of the level shift circuit 750.

[0075] Also, for example, when the value of the second unit drive delay signal dA2 is greater than the threshold value dvth, the level switching signal generating circuit 710 outputs the level switching signal LS of H level, and the operation mode of the level shift circuit 750 becomes the second mode MD2. After that, when the value of the second unit drive delay signal dA2 becomes smaller than the threshold value dvth, the level switching signal generating circuit 710 switches the level switching signal LS from H level to L level. As a result, the operation mode of the level shift circuit 750 is switched from the second mode MD2 to the first mode MD1. Then, immediately after switching the level switching signal LS from H level to L level, the level switching signal generating circuit 710 outputs a pulse signal that becomes H level for a short period of time as the level switching signal LS one or more times in order to reduce waveform distortion of the drive signal COM that may occur due to switching of the operation mode of the level shift circuit 750.

[0076] In the following description, the pulse signal that becomes L level for a short period of time when the operation mode of the level shift circuit 750 is switched from the first mode MD1 to the second mode MD2, and the pulse signal that becomes H level for a short period of time when the operation mode of the level shift circuit 750 is switched from the second mode MD2 to the first mode MD1 may be collectively referred to as a counter pulse CP.

[0077] The second amplified modulated signal AMS2 output by the level shift circuit 750 is input to the demodulation circuit 560. The demodulation circuit 560 smoothes and demodulates the second amplified modulated signal AMS2 output by the level shift circuit 750, and outputs the drive signal COM.

[0078] The demodulation circuit 560 includes an inductor 561 and a capacitor 562. One end of the inductor 561 is electrically connected to the second output point OP2. is electrically connected to one end of the capacitor 562. The other end of the capacitor 562 is supplied with a ground potential. That is, the inductor 561 and the capacitor 562 configure a low-pass filter circuit. The second amplified modulation signal AMS2 output from the level shift circuit 750 is smoothed by this low-pass filter circuit, and is output from the drive circuit 50 as the drive signal COM.

[0079] The feedback circuit 570 receives the drive signal COM generated by the demodulation circuit 560 and outputs a feedback signal VFB to the modulation circuit 500. Specifically, the feedback circuit 570 supplies the feedback signal VFB obtained by dividing the drive signal COM to the adder 511. This causes the drive signal COM to be fed back to the pulse modulation circuit 520. As a result, the waveform accuracy of the drive signal COM output by the drive circuit 50 is improved. Here, the feedback circuit 570 may feed back, as the feedback signal VFB, a plurality of signals including a signal obtained by dividing the drive signal COM and a signal obtained by extracting high-frequency components of the drive signal COM. That is, the feedback circuit 570 may include a plurality of feedback circuits including a circuit that feeds back a signal obtained by dividing the drive signal COM and a circuit that feeds back a signal obtained by extracting high-frequency components of the drive signal COM. This makes it possible to individually feed back the high-frequency components included in the drive signal COM. As a result, the drive circuit 50 is capable of self-oscillation based on the high-frequency components, and the frequency of the modulation signal MS can be increased to a level that sufficiently ensures the accuracy of the drive signal COM. Therefore, the waveform accuracy of the drive signal COM output by the drive circuit 50 is further improved.

[0080] 1-3-3. Operation of the drive circuit Next, the operation of the drive circuit 50 will be described. FIG. 7 is a diagram for explaining the operation of the drive circuit 50. In FIG. 7, only the drive signal COM in an arbitrary period T among the drive signals COM output by the drive circuit 50 is illustrated. In FIG. 7, for convenience of illustration and explanation, an ideal signal waveform without circuit delay or wiring delay is illustrated. In addition, in FIG. 7, the voltage of the drive signal COM corresponding to the threshold value dvth is illustrated as vth. Furthermore, the digital values ​​of the base drive signal dA, the first base drive delay signal dA1, and the second base drive delay signal dA2 corresponding to the voltages vt, vb, and vc of the drive signal COM are illustrated as dvt, dvb, and dvc, respectively. In addition, in FIG. 7, a case where the voltage vth is lower than the voltage vc and the threshold value dvth is larger than the digital value dvc is illustrated, but this is not limited thereto.

[0081] 7, in the period from time t0 to time t10, the first drive delay signal dA1 of the digital value dvc is input to the D / A conversion circuit 510, and the drive circuit 50 outputs the drive signal COM of the voltage vc. Since the digital value dvc is smaller than the threshold value dvth, the level switching signal generation circuit 710 generates a level switching signal LS of the L level. As a result, the operation mode of the level shift circuit 750 becomes the first mode MD1, and the level shift circuit 750 outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2.

[0082] During the period from time t10 to time t20, the first group drive delay signal dA1 decreasing from the digital value dvc to the digital value dvb is input to the D / A conversion circuit 510, and the drive circuit 50 outputs the drive signal COM decreasing from the voltage vc to the voltage vb. During the period from time t10 to time t20, the digital value of the second group drive delay signal dA2 is smaller than the threshold value dvth, so that the level switching signal generation circuit 710 generates an L-level level switching signal LS. As a result, the operation mode of the level shift circuit 750 maintains the first mode MD1, and the level shift circuit 750 outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2.

[0083] In the period from time t20 to time t30, the first drive delay signal dA1 having a digital value dvb is input to the D / A conversion circuit 510, and the drive circuit 50 outputs a drive signal COM having a voltage vb. Since the digital value dvb is smaller than the threshold value dvth, the level switching signal generation circuit 710 generates a level switching signal LS of an L level. As a result, The operation mode remains in the first mode MD1, and the level shift circuit 750 outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2.

[0084] During the period from time t30 to time t40, the first group drive delay signal dA1 increasing from the digital value dvb to the digital value dvt is input to the D / A conversion circuit 510, and the drive circuit 50 outputs the drive signal COM increasing from the voltage vb to the voltage vt. During the period from time t30 to time tc1 within the period from time t30 to time t40, the digital value of the second group drive delay signal dA2 is smaller than the threshold value dvth, so that the level switching signal generation circuit 710 generates an L-level level switching signal LS. As a result, the operation mode of the level shift circuit 750 maintains the first mode MD1, and the level shift circuit 750 outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2. On the other hand, during the period from time tc1 to time t40 within the period from time t30 to time t40, the digital value of the second unit drive delay signal dA2 is greater than the threshold value dvth, so the level switching signal generation circuit 710 generates an H-level level switching signal LS. As a result, the operation mode of the level shift circuit 750 transitions from the first mode MD1 to the second mode MD2, and the level shift circuit 750 outputs a signal obtained by shifting the potential of the first amplified modulation signal AMS1 as the second amplified modulation signal AMS2.

[0085] When the operation mode of the level shift circuit 750 transitions from the first mode MD1 to the second mode MD2, the reference potential of the first amplified modulated signal AMS1 output as the second amplified modulated signal AMS2 changes abruptly from the ground potential to a voltage vhv2-vf×N. If the response speed of the drive circuit 50 cannot keep up with this abrupt change in the reference potential, distortion may occur in the signal waveform of the drive signal COM. In order to reduce distortion of the signal waveform of the drive signal COM, after the operation mode of the level shift circuit 750 transitions from the first mode MD1 to the second mode MD2 at time tc1, the level switching signal generation circuit 710 outputs a counter pulse CP that inverts the logical level of the level switching signal LS for a short period of time. During the period in which the level switching signal generating circuit 710 outputs the counter pulse CP, the operation mode of the level shift circuit 750 becomes the first mode MD1 or the second mode MD2 according to the logical level of the level switching signal LS, and the level shift circuit 750 outputs the first amplified modulated signal AMS1 or a signal obtained by shifting the potential of the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2. This counter pulse CP makes the change in the reference potential of the first amplified modulated signal AMS1 output as the second amplified modulated signal AMS2 gentler, and as a result, distortion of the signal waveform of the drive signal COM is reduced.

[0086] As described above, in the period from time t30 to time t40, the drive circuit 50 outputs the drive signal COM that increases from the voltage vb to the voltage vt. At this time, the piezoelectric element 60 and the demodulation circuit 560 are supplied with a current by the second amplified modulation signal AMS2 output by the drive circuit 50, and electric charges are stored. The current for storing electric charges in the piezoelectric element 60 and the demodulation circuit 560 is supplied via the capacitor C13. Therefore, the electric charges stored in the capacitor C13 are discharged, and the voltage of the capacitor C13 is likely to decrease. In such a period from time t30 to time t40, the level shift circuit 750 outputs a counter pulse CP, so that the current is supplied to the piezoelectric element 60 and the demodulation circuit 560 without passing through the capacitor C13 during the period when the level switching signal LS is at the L level. That is, in the period from time t30 to time t40, the counter pulse CP is output, and the electric charges stored in the capacitor C13 of the bootstrap circuit BS are likely to be discharged. As a result, the risk of distortion occurring in the signal waveform of the drive signal COM due to a drop in the voltage of the capacitor C13 is reduced.

[0087] In the period from time t40 to time t50, the first drive delay signal dA1 having a digital value dvt is input to the D / A conversion circuit 510, and the drive circuit 50 outputs the drive signal COM having a voltage vt. Since the digital value dvt is greater than the threshold value dvth, the level switching signal generation circuit 7 10 generates a level switching signal LS of H level. As a result, the operation mode of the level shift circuit 750 maintains the second mode MD2, and the level shift circuit 750 outputs a signal obtained by shifting the potential of the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2.

[0088] During the period from time t50 to time t60, the first unit drive delay signal dA1 decreasing from the digital value dvt to the digital value dvc is input to the D / A conversion circuit 510, and the drive circuit 50 outputs the drive signal COM decreasing from the voltage vt to the voltage vc. During the period from time t50 to time tc2 within the period from time t50 to time t60, the digital value of the second unit drive delay signal dA2 is greater than the threshold value dvth, so the level switching signal generation circuit 710 generates an H-level level switching signal LS. As a result, the operation mode of the level shift circuit 750 maintains the second mode MD2, and the level shift circuit 750 outputs a signal obtained by shifting the potential of the first amplified modulation signal AMS1 as the second amplified modulation signal AMS2. On the other hand, during the period from time tc2 to time t60 within the period from time t50 to time t60, the digital value of the second unit drive delay signal dA2 is smaller than the threshold value dvth, so the level switching signal generation circuit 710 generates an L-level level switching signal LS. As a result, the operation mode of the level shift circuit 750 transitions from the second mode MD2 to the first mode MD1, and the level shift circuit 750 outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2.

[0089] When the operation mode of the level shift circuit 750 transitions from the second mode MD2 to the first mode MD1, the reference potential of the first amplified modulated signal AMS1 output as the second amplified modulated signal AMS2 changes abruptly from the voltage vhv2-vf×N to the ground potential. If the response speed of the drive circuit 50 cannot keep up with this abrupt change in the reference potential, distortion may occur in the signal waveform of the drive signal COM. In order to reduce distortion of the signal waveform of the drive signal COM, after the operation mode of the level shift circuit 750 transitions from the second mode MD2 to the first mode MD1 at time tc2, the level switching signal generation circuit 710 outputs a counter pulse CP that inverts the logical level of the level switching signal LS for a short period of time. During the period in which the level switching signal generating circuit 710 outputs the counter pulse CP, the operation mode of the level shift circuit 750 becomes the first mode MD1 or the second mode MD2 according to the logical level of the level switching signal LS, and the level shift circuit 750 outputs the first amplified modulated signal AMS1 or a signal obtained by shifting the potential of the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2. This counter pulse CP makes the change in the reference potential of the first amplified modulated signal AMS1 output as the second amplified modulated signal AMS2 gentler, and as a result, distortion of the signal waveform of the drive signal COM is reduced.

[0090] As described above, in the period from time t50 to time t60, the drive circuit 50 outputs the drive signal COM that decreases from the voltage vt to the voltage vc. At this time, the electric charge stored in the piezoelectric element 60 and the demodulation circuit 560 is discharged, and the current generated by the discharge of the electric charge is supplied to the drive circuit 50. In such a period from time t50 to time t60, the level shift circuit 750 outputs a counter pulse CP, so that the current supplied to the drive circuit 50 during the period when the level switching signal LS is at the H level is supplied to the capacitor C13 via the transistor M3. That is, in the period from time t50 to time t60, by outputting the counter pulse CP, a regenerative current flows in the capacitor C13 of the bootstrap circuit BS, and an electric charge is stored in the capacitor C13. As a result, the risk of distortion of the signal waveform of the drive signal COM due to the voltage drop of the capacitor C13 is reduced.

[0091] In the period from time t60 to time t70, the first drive delay signal dA1 having a digital value dvc is input to the D / A conversion circuit 510, and the drive circuit 50 outputs the drive signal COM having a voltage vc. Since the digital value dvc is smaller than the threshold value dvth, the level switching signal generation circuit 710 generates a level switching signal LS of an L level. As a result, The operation mode remains in the first mode MD1, and the level shift circuit 750 outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2.

[0092] 1-3-4. Operation of the level switching signal generation circuit As described above, when the level switching signal LS is at L level and the value of the second unit drive delay signal dA2 increases and becomes larger than the threshold value dvth, the level switching signal generating circuit 710 switches the level switching signal LS from L level to H level. Furthermore, the level switching signal generating circuit 710 switches the level switching signal LS from L level to H level, then from H level to L level, and further from L level to H level. In other words, the level switching signal generating circuit 710 outputs a counter pulse CP that inverts the logical level of the level switching signal LS for a predetermined period of time.

[0093] As described above, when the level switching signal LS is at H level and the value of the second unit drive delay signal dA2 decreases and becomes smaller than the threshold value dvth, the level switching signal generating circuit 710 switches the level switching signal LS from H level to L level. Furthermore, the level switching signal generating circuit 710 switches the level switching signal LS from H level to L level, and then from L level to H level, and then from H level to L level. That is, the level switching signal generating circuit 710 outputs a counter pulse CP that inverts the logical level of the level switching signal LS for a predetermined period of time.

[0094] The counter pulse CP is intended to reduce distortion of the signal waveform of the drive signal COM caused by a change in the logical level of the level switching signal LS causing the switching operation of the transistors M3 and M4. Therefore, the counter pulse CP needs to be output during a period when the voltage of the drive signal COM rises or falls, and if the counter pulse CP is output during a period when the voltage of the drive signal COM is constant, the counter pulse CP may cause distortion in the signal waveform of the drive signal COM.

[0095] On the other hand, the voltage of the drive signal COM changes in response to changes in the value of the first unit drive delay signal dA1, but due to the circuit delay amount dly3 of the modulation circuit 500, the amplifier circuit 550, and the level shift circuit 750, the voltage of the drive signal COM changes with a delay of the circuit delay amount dly3 relative to the change in the first unit drive delay signal dA1.

[0096] As described above, the first master drive delay signal dA1 is a signal obtained by delaying the master drive signal dA by the first delay amount dly1, and the second master drive delay signal dA2 is a signal obtained by delaying the master drive signal dA by the second delay amount dly2. Therefore, with respect to the master drive signal dA, the drive signal COM is delayed by the first delay amount dly1+circuit delay amount dly3, and the counter pulse CP is delayed by the second delay amount dly2. Therefore, the level switching signal generating circuit 710 needs to output the counter pulse CP during the period in which the voltage of the drive signal COM changes, taking into account the difference in delay time (dly1+dly3)-dly2.

[0097] FIG. 8 shows an example of waveforms of the master drive signal dA, the first master drive delay signal dA1, the second master drive delay signal dA2, the level switching signal LS, and the drive signal COM in this embodiment.

[0098] In the example of Fig. 8, the voltage of the drive signal COM rises in the period from time t1 to time t4, and falls in the period from time t5 to time t8. Meanwhile, counter pulses CP are output in the period from time t2 to time t3 and in the period from time t6 to time t7. The period from time t2 to time t3 when the counter pulse CP is output is included in the period from time t1 to time t4 when the voltage of the drive signal COM rises. In addition, the period from time t6 to time t7 when the counter pulse CP is output is included in the period from time t5 to time t8 when the voltage of the drive signal COM falls. Therefore, distortion is less likely to occur in the signal waveform of the drive signal COM.

[0099] In this embodiment, the first delay amount dly1 and the second delay amount dly2 can be set independently of each other, so that it is easy to set the first delay amount dly1 and the second delay amount dly2, taking into account the circuit delay amount dly3, which is a fixed value, so that the counter pulse CP is output only during periods when the voltage of the drive signal COM rises and falls.

[0100] 8, the difference between the period from time t5 to time t8 when the voltage of the drive signal COM drops and the period from time t6 to time t7 when the counter pulse CP is output is small. Therefore, taking into account the circuit delay amount dly3, it is preferable that the second delay amount dly2 is greater than the first delay amount dly1 in order to prevent the counter pulse CP from being output during the period before and after the voltage of the drive signal COM drops.

[0101] In the first embodiment, the ejection unit 600 including the piezoelectric element 60 is an example of a “drive unit.” Also, the L-level potential of the level switching signal LS is an example of a “first potential,” and the H-level potential of the level switching signal LS is an example of a “second potential.”

[0102] 1-4.Effects As described above, in the liquid ejection device 1 of the first embodiment, in the drive circuit 50, the modulation circuit 500 modulates the first master drive delay signal dA1 obtained by delaying the master drive signal dA according to the first delay amount dly1 to output the modulated signal MS, and the level switching signal generation circuit 710 generates the level switching signal LS according to the second master drive delay signal dA2 obtained by delaying the master drive signal dA according to the second delay amount dly2, and the first delay amount dly1 and the second delay amount dly2 can be set independently of each other in the first storage unit 700. Therefore, in consideration of the delay time of the drive signal COM, it is easy to set the first delay amount dly1 and the second delay amount dly2 so that the level switching signal LS switches from the L level to the H level during the period when the voltage of the drive signal COM increases and the level switching signal LS switches from the H level to the L level during the period when the voltage of the drive signal COM decreases. Therefore, according to the liquid ejection device 1 of the first embodiment, the risk of the waveform of the drive signal COM being distorted due to a shift in the timing at which the potential of the level switching signal LS is switched in the drive circuit 50 is reduced, thereby improving the waveform accuracy of the drive signal COM.

[0103] In the liquid ejection device 1 of the first embodiment, in the drive circuit 50, the level switching signal generation circuit 710 switches the level switching signal LS from L level to H level in response to an increase in the value of the second unit drive delay signal dA2 when the level switching signal LS is at L level, and then outputs a counter pulse CP to reduce waveform distortion of the drive signal COM caused by this switching. In addition, the level switching signal generation circuit 710 switches the level switching signal LS from H level to L level in response to a decrease in the value of the second unit drive delay signal dA2 when the level switching signal LS is at H level, and then outputs a counter pulse CP to reduce waveform distortion of the drive signal COM caused by this switching. If the counter pulse CP is output during a period in which the voltage of the drive signal COM is constant, the counter pulse CP may conversely cause distortion in the waveform of the drive signal COM. In contrast, according to the first embodiment of the liquid ejection device 1, it is easy to set the first delay amount dly1 and the second delay amount dly2 in the drive circuit 50 so that a counter pulse CP is output during periods when the voltage of the drive signal COM rises and falls, thereby reducing waveform distortion of the drive signal COM and improving the waveform accuracy of the drive signal COM.

[0104] In the liquid ejection device 1 of the first embodiment, the first delay amount dly1 and the second delay amount dly2 stored in the first storage unit 700 in the drive circuit 50 are rewritable. Therefore, the first delay amount dly1 and the second delay amount dly2 can be rewritten depending on the circuit delays of the modulation circuit 500, the amplifier circuit 550, and the level shift circuit 750. The first delay amount dly1 and the second delay amount dly2 can be adjusted to appropriate values ​​from the output of the amplifier.

[0105] 2. Second embodiment In the following, the second embodiment will be described mainly with respect to the differences from the first embodiment, with the same reference numerals used for the same components as in the first embodiment, and explanations that overlap with the first embodiment will be omitted or simplified.

[0106] Fig. 9 is a diagram showing an example of the functional configuration of the drive circuit 50 of the liquid ejection device 1 of the second embodiment. As shown in Fig. 9, the drive circuit 50 in the second embodiment has a D / A conversion circuit 510, an adder 511, a pulse modulation circuit 520, an inverter 521, a demodulation circuit 560, a feedback circuit 570, a first storage unit 700, a second storage unit 702, a first delay circuit 704, a second delay circuit 706, a level switching signal generation circuit 710, and an amplification level shift circuit 800, similar to the first embodiment. The configurations and functions of the D / A conversion circuit 510, the adder 511, the pulse modulation circuit 520, the inverter 521, the demodulation circuit 560, the feedback circuit 570, the first storage unit 700, the first delay circuit 704, the second delay circuit 706, and the amplification level shift circuit 800 are similar to those of the first embodiment, and therefore will not be described.

[0107] In the second embodiment, the level switching signal generating circuit 710 switches the level switching signal LS from L level to H level when the value of the second unit drive delay signal dA2 increases and becomes larger than the first threshold value dvth1 while the level switching signal LS is at L level. Also, the level switching signal generating circuit 710 switches the level switching signal LS from H level to L level when the value of the second unit drive delay signal dA2 decreases and becomes smaller than the second threshold value dvth2 while the level switching signal LS is at H level. The second threshold value dvth2 is a value different from the first threshold value dvth1.

[0108] The second storage unit 702 stores a first threshold dvth1 and a second threshold dvth2. The second storage unit 702 may be, for example, a non-volatile memory. Alternatively, the second storage unit 702 may be a volatile memory, and the first threshold dvth1 and the second threshold dvth2 may be set in the second storage unit 702 by external communication from the control unit 100 or the like. In other words, the first threshold dvth1 and the second threshold dvth2 may be predetermined values, or may be rewritable from outside the drive circuit 50.

[0109] The second storage unit 702 may be a storage unit different from the first storage unit 700, or may be the same storage unit as the first storage unit 700. That is, the first delay amount dly1 and the second delay amount dly2 and the first threshold value dvth1 and the second threshold value dvth2 may be stored separately in two storage units, or may be stored in one storage unit.

[0110] When the value of the second unit drive delay signal dA2 is smaller than the first threshold value dvth1, the level switching signal generating circuit 710 outputs the level switching signal LS of the L level, and the operation mode of the level shift circuit 750 becomes the first mode MD1. After that, when the value of the second unit drive delay signal dA2 becomes larger than the first threshold value dvth1, the level switching signal generating circuit 710 switches the level switching signal LS from the L level to the H level. As a result, the operation mode of the level shift circuit 750 is switched from the first mode MD1 to the second mode MD2. Then, immediately after switching the level switching signal LS from the L level to the H level, the level switching signal generating circuit 710 outputs a counter pulse CP as the level switching signal LS in order to reduce waveform distortion of the drive signal COM that may occur due to switching of the operation mode of the level shift circuit 750.

[0111] In addition, when the value of the second unit drive delay signal dA2 is greater than the second threshold value dvth2, the level switching signal generating circuit 710 outputs the level switching signal LS of H level, and the level shift circuit 7 The operation mode of the level shift circuit 750 becomes the second mode MD2. Thereafter, the value of the second unit drive delay signal dA2 becomes smaller than the second threshold value dvth2, so that the level switching signal generation circuit 710 switches the level switching signal LS from H level to L level. This switches the operation mode of the level shift circuit 750 from the second mode MD2 to the first mode MD1. Then, immediately after switching the level switching signal LS from H level to L level, the level switching signal generation circuit 710 outputs a counter pulse CP as the level switching signal LS in order to reduce waveform distortion of the drive signal COM that may occur due to switching of the operation mode of the level shift circuit 750.

[0112] FIG. 10 is a diagram for explaining the operation of the drive circuit 50 in the second embodiment. Note that FIG. 10 illustrates only the drive signal COM in an arbitrary period T among the drive signals COM output by the drive circuit 50. For convenience of illustration and explanation, FIG. 10 illustrates a signal waveform in an ideal case without circuit delay or wiring delay. Also, in FIG. 10, the voltages of the drive signal COM corresponding to the first threshold dvth1 and the second threshold dvth2, respectively, are illustrated as vth1 and vth2. Furthermore, the digital values ​​of the base drive signal dA, the first base drive delay signal dA1, and the second base drive delay signal dA2 corresponding to the voltages vt, vb, and vc of the drive signal COM are illustrated as dvt, dvb, and dvc, respectively. Note that FIG. 10 illustrates a case where the voltage vth is lower than the voltage vc, the first threshold dvth1 is smaller or larger than the digital value dvc, and a case where the voltage vth2 is higher than the voltage vc, and the second threshold dvth2 is larger than the digital value dvc, but is not limited thereto.

[0113] 10, in the period from time t0 to time t10, the first group drive delay signal dA1 having a digital value dvc is input to the D / A conversion circuit 510, and the drive circuit 50 outputs a drive signal COM having a voltage vc. Since the digital value dvc is smaller than the second threshold value dvth2, the level switching signal generation circuit 710 generates a level switching signal LS of an L level. As a result, the operation mode of the level shift circuit 750 becomes the first mode MD1, and the level shift circuit 750 outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2.

[0114] During the period from time t10 to time t20, the first group drive delay signal dA1 decreasing from the digital value dvc to the digital value dvb is input to the D / A conversion circuit 510, and the drive circuit 50 outputs the drive signal COM decreasing from the voltage vc to the voltage vb. During the period from time t10 to time t20, the digital value of the second group drive delay signal dA2 is smaller than the second threshold value dvth2, so that the level switching signal generation circuit 710 generates an L-level level switching signal LS. As a result, the operation mode of the level shift circuit 750 maintains the first mode MD1, and the level shift circuit 750 outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2.

[0115] In the period from time t20 to time t30, the first drive delay signal dA1 of the digital value dvb is input to the D / A conversion circuit 510, and the drive circuit 50 outputs the drive signal COM of the voltage vb. Since the digital value dvb is smaller than the first threshold value dvth1, the level switching signal generation circuit 710 generates a level switching signal LS of the L level. As a result, the operation mode of the level shift circuit 750 maintains the first mode MD1, and the level shift circuit 750 outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2.

[0116] In the period from time t30 to time t40, the first group drive delay signal dA1 increasing from digital value dvb to digital value dvt is input to the D / A conversion circuit 510, and the drive circuit 50 outputs a drive signal COM increasing from voltage vb to voltage vt. In the period from time t30 to time t40, in the period from time t30 to time tc1, the digital value of the second group drive delay signal dA2 is smaller than the first threshold value dvth1, so that the level switching signal generation circuit 710 generates an L-level level switching signal LS. As a result, the operation mode of the level shift circuit 750 is the second The first mode MD1 is maintained, and the level shift circuit 750 outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2. On the other hand, in the period from time tc1 to time t40 within the period from time t30 to time t40, the digital value of the second unit drive delay signal dA2 is greater than the first threshold value dvth1, so the level switching signal generation circuit 710 generates an H-level level switching signal LS. As a result, the operation mode of the level shift circuit 750 transitions from the first mode MD1 to the second mode MD2, and the level shift circuit 750 outputs a signal obtained by shifting the potential of the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2.

[0117] At time tc1, after the operation mode of the level shift circuit 750 transitions from the first mode MD1 to the second mode MD2, the level switching signal generation circuit 710 outputs a counter pulse CP that inverts the logical level of the level switching signal LS for a short period of time. During the period in which the level switching signal generation circuit 710 outputs the counter pulse CP, the operation mode of the level shift circuit 750 becomes the first mode MD1 or the second mode MD2 according to the logical level of the level switching signal LS, and the level shift circuit 750 outputs the first amplified modulated signal AMS1 or a signal obtained by shifting the potential of the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2. This counter pulse CP makes the change in the reference potential of the first amplified modulated signal AMS1 output as the second amplified modulated signal AMS2 gentler, and as a result, distortion of the signal waveform of the drive signal COM is reduced.

[0118] In the period from time t40 to time t50, the first drive delay signal dA1 with a digital value dvt is input to the D / A conversion circuit 510, and the drive circuit 50 outputs a drive signal COM with a voltage vt. Since the digital value dvt is greater than the second threshold value dvth2, the level switching signal generation circuit 710 generates an H-level level switching signal LS. As a result, the operation mode of the level shift circuit 750 maintains the second mode MD2, and the level shift circuit 750 outputs a signal obtained by shifting the potential of the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2.

[0119] During the period from time t50 to time t60, the first unit drive delay signal dA1 decreasing from the digital value dvt to the digital value dvc is input to the D / A conversion circuit 510, and the drive circuit 50 outputs the drive signal COM decreasing from the voltage vt to the voltage vc. During the period from time t50 to time tc2 within the period from time t50 to time t60, the digital value of the second unit drive delay signal dA2 is greater than the second threshold value dvth2, so the level switching signal generation circuit 710 generates an H-level level switching signal LS. As a result, the operation mode of the level shift circuit 750 maintains the second mode MD2, and the level shift circuit 750 outputs a signal obtained by shifting the potential of the first amplified modulation signal AMS1 as the second amplified modulation signal AMS2. On the other hand, during the period from time tc2 to time t60 within the period from time t50 to time t60, the digital value of the second unit drive delay signal dA2 is smaller than the second threshold value dvth2, so the level switching signal generation circuit 710 generates an L-level level switching signal LS. As a result, the operation mode of the level shift circuit 750 transitions from the second mode MD2 to the first mode MD1, and the level shift circuit 750 outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2.

[0120] At time tc2, after the operation mode of the level shift circuit 750 transitions from the second mode MD2 to the first mode MD1, the level switching signal generation circuit 710 outputs a counter pulse CP that inverts the logical level of the level switching signal LS for a short period of time. During the period in which the level switching signal generation circuit 710 outputs the counter pulse CP, the operation mode of the level shift circuit 750 becomes the first mode MD1 or the second mode MD2 according to the logical level of the level switching signal LS, and the level shift circuit 750 outputs the first amplified modulated signal AMS1 or a signal obtained by shifting the potential of the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2. This counter pulse CP makes the change in the reference potential of the first amplified modulated signal AMS1 output as the second amplified modulated signal AMS2 gentler, and as a result, distortion of the signal waveform of the drive signal COM is reduced.

[0121] In the period from time t60 to time t70, the first group drive delay signal dA1 having a digital value dvc is input to the D / A conversion circuit 510, and the drive circuit 50 outputs the drive signal COM having a voltage vc. Since the digital value dvc is smaller than the second threshold value dvth2, the level switching signal generation circuit 710 generates a level switching signal LS of an L level. As a result, the operation mode of the level shift circuit 750 maintains the first mode MD1, and the level shift circuit 750 outputs the first amplified modulated signal AMS1 as the second amplified modulated signal AMS2.

[0122] In the second embodiment, as in the first embodiment, the first master drive delay signal dA1 is a signal obtained by delaying the master drive signal dA by the first delay amount dly1, and the second master drive delay signal dA2 is a signal obtained by delaying the master drive signal dA by the second delay amount dly2. Therefore, with respect to the master drive signal dA, the drive signal COM is delayed by the first delay amount dly1+circuit delay amount dly3, and the counter pulse CP is delayed by the second delay amount dly2. Therefore, the level switching signal generating circuit 710 needs to output the counter pulse CP during the period in which the voltage of the drive signal COM changes, taking into account the difference in delay time (dly1+dly3)-dly2.

[0123] FIG. 11 shows an example of waveforms of the base drive signal dA, the first base drive delay signal dA1, the second base drive delay signal dA2, the level switching signal LS, and the drive signal COM in the second embodiment.

[0124] In the example of Fig. 11, the voltage of the drive signal COM rises in the period from time t1 to time t4, and falls in the period from time t5 to time t8. Meanwhile, the counter pulse CP is output in the period from time t2 to time t3 and in the period from time t6 to time t7. The period from time t2 to time t3 when the counter pulse CP is output is included in the period from time t1 to time t4 when the voltage of the drive signal COM rises. In addition, the period from time t6 to time t7 when the counter pulse CP is output is included in the period from time t5 to time t8 when the voltage of the drive signal COM falls. Therefore, distortion is unlikely to occur in the signal waveform of the drive signal COM.

[0125] In the second embodiment, since the first threshold dvth1 and the second threshold dvth2 can be set independently of each other, it is easy to set the first threshold dvth1 so that the level switching signal LS switches from L level to H level in a period in which the voltage of the drive signal COM rises, and to set the second threshold dvth2 so that the level switching signal LS switches from H level to L level in a period in which the voltage of the drive signal COM falls, taking into account the circuit delay amount dly3. Also, in the second embodiment, since the first delay amount dly1 and the second delay amount dly2 can be set independently of each other, it is easy to set the first delay amount dly1 and the second delay amount dly2 so that the counter pulse CP is output only in a period in which the voltage of the drive signal COM rises and a period in which the voltage of the drive signal COM falls, taking into account the circuit delay amount dly3, which is a fixed value.

[0126] 11, the difference between the period from time t5 to time t8 when the voltage of the drive signal COM drops and the period from time t6 to time t7 when the counter pulse CP is output is small. Therefore, taking into account the circuit delay amount dly3, it is preferable that the second delay amount dly2 is greater than the first delay amount dly1 so that the counter pulse CP is not output during the period before and after the voltage of the drive signal COM drops. Also, it is preferable that the second threshold value dvth2 is greater than the first threshold value dvth1.

[0127] Other configurations of the liquid ejection device 1 of the second embodiment are similar to those of the first embodiment, and therefore description thereof will be omitted.

[0128] In the second embodiment, the discharge unit 600 including the piezoelectric element 60 is an example of the "drive unit." Moreover, the L level potential of the level switching signal LS is an example of a "first potential," and the H level potential of the level switching signal LS is an example of a "second potential."

[0129] According to the liquid ejection device 1 of the second embodiment described above, the same effects as those of the liquid ejection device 1 of the first embodiment can be obtained.

[0130] In addition, in the liquid ejection device 1 of the second embodiment, the first threshold dvth1 for switching the level switching signal LS from L level to H level and the second threshold dvth2 for switching from H level to L level can be set independently in the second storage unit 702 in the drive circuit 50. Therefore, in consideration of the delay time of the drive signal COM, it is easy to set the first threshold dvth1 so that the level switching signal LS switches from L level to H level during the period when the voltage of the drive signal COM increases, and to set the second threshold dvth2 so that the level switching signal LS switches from H level to L level during the period when the voltage of the drive signal COM decreases. In addition, in the liquid ejection device 1 of the second embodiment, it is easy to set the first delay amount dly1, the second delay amount dly2, the first threshold dvth1, and the second threshold dvth2 in the drive circuit 50 so that the counter pulse CP is output during the period when the voltage of the drive signal COM increases and decreases. Therefore, according to the liquid ejection device 1 of the second embodiment, the risk of the waveform of the drive signal COM being distorted due to a shift in the timing at which the potential of the level switching signal LS is switched in the drive circuit 50 is reduced, thereby improving the waveform accuracy of the drive signal COM.

[0131] 3. Variations The present invention is not limited to the present embodiment, and various modifications are possible within the scope of the present invention.

[0132] For example, in each of the above embodiments, the base drive signal dA is input to the drive circuit 50 from the control unit 100, but the control unit 100 may also input data of the difference between two consecutive digital values ​​of the base drive signal dA and add up each value of the data to restore the base drive signal dA.

[0133] In addition, in each of the above embodiments, the first delay circuit 704 and the second delay circuit 706 each output a signal obtained by delaying the master drive signal dA, which is a digital signal, but each may output a signal obtained by delaying the master drive signal aA, which is an analog signal output from the D / A conversion circuit 510. In this case, the first delay circuit 704 outputs a first master drive delay signal aA1 obtained by delaying the master drive signal aA by the first delay amount dly1, and the second delay circuit 706 outputs a second master drive delay signal aA2 obtained by delaying the master drive signal aA by the second delay amount dly2. Then, the first master drive delay signal aA1 is input to the positive input terminal of the adder 511, and the second master drive delay signal aA2 is input to the level switching signal generation circuit 710.

[0134] Although the embodiments have been described above, the present invention is not limited to these embodiments, and can be embodied in various forms without departing from the spirit and scope of the present invention. For example, the above-described embodiments can be appropriately combined.

[0135] The present invention includes configurations that are substantially the same as the configurations described in the embodiments, for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effects. The present invention also includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. The present invention also includes configurations that achieve the same effects as the configurations described in the embodiments, or configurations that can achieve the same purpose. The present invention also includes configurations in which publicly known technology is added to the configurations described in the embodiments.

[0136] The following can be derived from the above-described embodiment.

[0137] One aspect of the drive circuit is A drive circuit that outputs a drive signal to drive a drive unit, a first storage unit in which the first delay amount and the second delay amount are stored; a first delay circuit that outputs a first master drive delay signal obtained by delaying a master drive signal on which the drive signal is based according to the first delay amount; a second delay circuit that outputs a second master drive delay signal obtained by delaying the master drive signal according to the second delay amount; a modulation circuit that modulates the first group drive delay signal and outputs a modulated signal; an amplifier circuit that amplifies the modulated signal and outputs a first amplified modulated signal; a level switching signal generating circuit that generates a level switching signal, which is a digital signal including a first potential and a second potential higher than the first potential, in response to the second unit drive delay signal; a level shift circuit that outputs the first amplified modulated signal as a second amplified modulated signal when the level switching signal is at the first potential, and outputs a signal obtained by shifting a potential of the first amplified modulated signal as the second amplified modulated signal when the level switching signal is at the second potential; a demodulation circuit that demodulates the second amplified modulated signal and outputs the drive signal; Equipped with.

[0138] In this drive circuit, the drive signal changes according to the change in the value of the base drive signal, but due to the circuit delays of the modulation circuit, the amplification circuit, and the level shift circuit, the drive signal changes with a delay relative to the change in the base drive signal. If the modulation circuit modulates the base drive signal to output a modulated signal, and the level switching signal generation circuit generates a level switching signal according to the base drive signal, it may be difficult to consider the delay time of the drive signal and make the level switching signal switch from the first potential to the second potential during the period when the voltage of the drive signal rises, and the level switching signal switch from the second potential to the first potential during the period when the voltage of the drive signal drops. In contrast, in this drive circuit, the modulation circuit modulates the first base drive delay signal obtained by delaying the base drive signal according to the first delay amount, and outputs the modulated signal, and the level switching signal generation circuit generates the level switching signal according to the second base drive delay signal obtained by delaying the base drive signal according to the second delay amount, and the first delay amount and the second delay amount can be set in the first storage unit independently of each other. Therefore, it is easy to set the first and second delay amounts in consideration of the delay time of the drive signal so that the level switching signal switches from the first potential to the second potential during the period when the voltage of the drive signal rises, and the level switching signal switches from the second potential to the first potential during the period when the voltage of the drive signal falls. Therefore, with this drive circuit, the risk of the waveform of the drive signal being distorted due to a shift in the timing at which the potential of the level switching signal is switched is reduced, and the waveform accuracy of the drive signal can be improved.

[0139] In one embodiment of the drive circuit, The level switching signal generating circuit includes: When the level switching signal is at the first potential, the level switching signal may be switched from the first potential to the second potential in response to an increase in the value of the second unit drive delay signal, and then switched from the second potential to the first potential, and further switched from the first potential to the second potential.

[0140] In this drive circuit, after switching the level switching signal from the first potential to the second potential, the level switching signal generating circuit outputs a counter pulse to reduce waveform distortion of the drive signal caused by this switching. If the counter pulse is output during a period in which the voltage of the drive signal is constant, the counter pulse may conversely cause distortion in the waveform of the drive signal. In contrast, according to this drive circuit, it is easy to set the first delay amount and the second delay amount so that the counter pulse is output during a period in which the voltage of the drive signal is increasing, so that waveform distortion of the drive signal is reduced and the waveform accuracy of the drive signal can be improved.

[0141] In one embodiment of the drive circuit, The level switching signal generating circuit includes: When the level switching signal is at the second potential, the level switching signal may be switched from the second potential to the first potential in response to a decrease in the value of the second unit drive delay signal, and then switched from the first potential to the second potential, and further switched from the second potential to the first potential.

[0142] In this drive circuit, after switching the level switching signal from the second potential to the first potential, the level switching signal generating circuit outputs a counter pulse to reduce waveform distortion of the drive signal caused by this switching. If a counter pulse is output during a period in which the voltage of the drive signal is constant, the counter pulse may conversely cause distortion in the waveform of the drive signal. In contrast, according to this drive circuit, it is easy to set the first delay amount and the second delay amount so that a counter pulse is output during a period in which the voltage of the drive signal decreases, so that waveform distortion of the drive signal is reduced and the waveform accuracy of the drive signal can be improved.

[0143] One aspect of the drive circuit is a second storage unit that stores a first threshold value and a second threshold value different from the first threshold value; The level switching signal generating circuit includes: when the value of the second drive delay signal increases and becomes greater than the first threshold while the level switching signal is at the first potential, the level switching signal is switched from the first potential to the second potential; When the level switching signal is at the second potential, if the value of the second drive delay signal decreases and becomes smaller than the second threshold, the level switching signal may be switched from the second potential to the first potential.

[0144] If the threshold for switching the level switching signal from the first potential to the second potential and the threshold for switching from the second potential to the first potential are the same, it may be difficult to set the threshold so that the level switching signal switches from the first potential to the second potential during the period when the voltage of the drive signal rises and the level switching signal switches from the second potential to the first potential during the period when the voltage of the drive signal falls, taking into account the delay time of the drive signal. In contrast, in this drive circuit, the first threshold for switching the level switching signal from the first potential to the second potential and the second threshold for switching from the second potential to the first potential can be set independently of each other in the second storage unit. Therefore, it is easy to set the first threshold so that the level switching signal switches from the first potential to the second potential during the period when the voltage of the drive signal rises, and the second threshold so that the level switching signal switches from the second potential to the first potential during the period when the voltage of the drive signal falls, taking into account the delay time of the drive signal. Therefore, according to this drive circuit, the risk of the waveform of the drive signal being distorted due to a shift in the timing at which the potential of the level switching signal is switched is reduced, and the waveform accuracy of the drive signal can be improved.

[0145] In one embodiment of the drive circuit, The first delay amount stored in the first storage unit may be rewritable.

[0146] According to this drive circuit, the first delay amount can be adjusted to an appropriate value from the outside in accordance with the circuit delays of the modulation circuit, the amplification circuit, and the level shift circuit.

[0147] In one embodiment of the drive circuit, The second delay amount stored in the first storage unit may be rewritable.

[0148] According to this drive circuit, the second delay amount can be adjusted to an appropriate value from the outside in accordance with the circuit delays of the modulation circuit, the amplifier circuit, and the level shift circuit.

[0149] In one embodiment of the drive circuit, The second delay amount may be greater than the first delay amount.

[0150] According to this drive circuit, taking into consideration that the circuit delay of the modulation circuit, the amplification circuit, and the level shift circuit is larger than the circuit delay of the level switching signal, it is easy to set the first delay amount and the second delay amount so that the level switching signal switches from the first potential to the second potential during the period when the voltage of the drive signal increases, and the level switching signal switches from the second potential to the first potential during the period when the voltage of the drive signal decreases.

[0151] One aspect of the liquid ejection device is A discharge unit that discharges liquid; A drive circuit that outputs a drive signal for driving the ejection unit; Equipped with The drive circuit includes: a first storage unit in which the first delay amount and the second delay amount are stored; a first delay circuit that outputs a first master drive delay signal obtained by delaying a master drive signal on which the drive signal is based according to the first delay amount; a second delay circuit that outputs a second master drive delay signal obtained by delaying the master drive signal according to the second delay amount; a modulation circuit that modulates the first group drive delay signal and outputs a modulated signal; an amplifier circuit that amplifies the modulated signal and outputs a first amplified modulated signal; a level switching signal generating circuit that generates a level switching signal, which is a digital signal including a first potential and a second potential higher than the first potential, in response to the second unit drive delay signal; a level shift circuit that outputs the first amplified modulated signal as a second amplified modulated signal when the level switching signal is at the first potential, and outputs a signal obtained by shifting a potential of the first amplified modulated signal as the second amplified modulated signal when the level switching signal is at the second potential; a demodulation circuit that demodulates the second amplified modulated signal and outputs the drive signal; Equipped with.

[0152] In this liquid ejection device, in the drive circuit, the modulation circuit modulates a first master drive delay signal obtained by delaying the master drive signal according to a first delay amount to output a modulated signal, and the level switching signal generation circuit generates a level switching signal according to a second master drive delay signal obtained by delaying the master drive signal according to a second delay amount, and the first delay amount and the second delay amount can be set independently in the first storage unit. Therefore, in consideration of the delay time of the drive signal, it is easy to set the first delay amount and the second delay amount so that the level switching signal switches from the first potential to the second potential during the period when the voltage of the drive signal rises, and the level switching signal switches from the second potential to the first potential during the period when the voltage of the drive signal falls. Therefore, according to this liquid ejection device, the risk of the waveform of the drive signal being distorted due to a shift in the timing at which the potential of the level switching signal is switched in the drive circuit is reduced, and the waveform accuracy of the drive signal can be improved.

[0153] In one aspect of the liquid ejection device, The level switching signal generating circuit includes: When the level switching signal is at the first potential, the level switching signal may be switched from the first potential to the second potential in response to an increase in the value of the second unit drive delay signal, and then switched from the second potential to the first potential, and further switched from the first potential to the second potential.

[0154] In one aspect of the liquid ejection device, The level switching signal generating circuit includes: When the level switching signal is at the second potential, the second drive delay signal is decreased in value. The level switching signal may be switched from the second potential to the first potential, and then from the first potential to the second potential, and further from the second potential to the first potential.

[0155] One aspect of the liquid ejection device is a second storage unit that stores a first threshold value and a second threshold value different from the first threshold value; The level switching signal generating circuit includes: when the value of the second drive delay signal increases and becomes greater than the first threshold while the level switching signal is at the first potential, the level switching signal is switched from the first potential to the second potential; When the level switching signal is at the second potential, if the value of the second drive delay signal decreases and becomes smaller than the second threshold, the level switching signal may be switched from the second potential to the first potential.

[0156] In one aspect of the liquid ejection device, The first delay amount stored in the first storage unit may be rewritable.

[0157] In one aspect of the liquid ejection device, The second delay amount stored in the first storage unit may be rewritable.

[0158] In one aspect of the liquid ejection device, The second delay amount may be greater than the first delay amount. [Explanation of symbols]

[0159] 1...liquid ejection device, 2...moving body, 3...moving unit, 4...transport unit, 10...control unit, 11...power supply circuit, 20...head unit, 21...liquid ejection head, 24...carriage, 31...carriage motor, 32...carriage guide shaft, 33...timing belt, 40...platen, 41...transport motor, 42...transport roller, 50...drive circuit, 60...piezoelectric element, 100...control unit, 190...cable, 210...selection control unit, 230...selection unit, 510...D / A conversion circuit, 511...adder, 520...pulse modulation circuit, 521...inverter, 530...gate drive circuit, 531, 532...gate driver, 550...amplification circuit, 560...demodulation circuit, 561...inductor, 562...capacitor, 570 ...feedback circuit, 600...ejection section, 601...piezoelectric body, 611, 612...electrodes, 621...diaphragm, 631...cavity, 632...nozzle plate, 641...reservoir, 651...nozzle, 700...first memory section, 702...second memory section, 704...first delay circuit, 706...second delay circuit, 710...level switching signal generating circuit, 721...inverter, 730...gate drive circuit, 731, 732...gate driver, 750...level shift circuit, 800...amplification level shift circuit, BS...bootstrap circuit, C1...capacitor, C11 to C13...capacitors, OP1...first output point, OP2...second output point, D1...diode, D11 to D13...diode, L...nozzle row, M1 to M4...transistor, P...medium

Claims

1. A drive circuit that outputs a drive signal to drive a drive unit, a first storage unit in which the first delay amount and the second delay amount are stored; a first delay circuit that outputs a first master drive delay signal obtained by delaying a master drive signal on which the drive signal is based according to the first delay amount; a second delay circuit that outputs a second master drive delay signal obtained by delaying the master drive signal according to the second delay amount; a modulation circuit that modulates the first group drive delay signal and outputs a modulated signal; an amplifier circuit that amplifies the modulated signal and outputs a first amplified modulated signal; a level switching signal generating circuit that generates a level switching signal, which is a digital signal including a first potential and a second potential higher than the first potential, in response to the second unit drive delay signal; a level shift circuit that outputs the first amplified modulated signal as a second amplified modulated signal when the level switching signal is at the first potential, and outputs a signal obtained by shifting a potential of the first amplified modulated signal as the second amplified modulated signal when the level switching signal is at the second potential; a demodulation circuit that demodulates the second amplified modulated signal and outputs the drive signal; Equipped with A drive circuit comprising:

2. The level switching signal generating circuit includes: when the level switching signal is at the first potential, the level switching signal is switched from the first potential to the second potential in response to an increase in the value of the second drive delay signal, and then switched from the second potential to the first potential, and further switched from the first potential to the second potential; 2. The drive circuit according to claim 1 .

3. The level switching signal generating circuit includes: when the level switching signal is at the second potential, the level switching signal is switched from the second potential to the first potential in response to a decrease in the value of the second drive delay signal, and then switched from the first potential to the second potential, and further switched from the second potential to the first potential; 2. The drive circuit according to claim 1 .

4. a second storage unit that stores a first threshold value and a second threshold value different from the first threshold value; The level switching signal generating circuit includes: when the value of the second drive delay signal increases and becomes greater than the first threshold while the level switching signal is at the first potential, the level switching signal is switched from the first potential to the second potential; when the value of the second drive delay signal decreases and becomes smaller than the second threshold while the level switching signal is at the second potential, the level switching signal is switched from the second potential to the first potential.

2. The drive circuit according to claim 1 .

5. The first delay amount stored in the first storage unit is rewritable.

2. The drive circuit according to claim 1 .

6. The second delay amount stored in the first storage unit is rewritable.

2. The drive circuit according to claim 1 .

7. The second delay amount is greater than the first delay amount.

2. The drive circuit according to claim 1 .

8. A discharge unit that discharges liquid; A drive circuit that outputs a drive signal for driving the ejection unit; Equipped with The drive circuit includes: a first storage unit in which the first delay amount and the second delay amount are stored; a first delay circuit that outputs a first master drive delay signal obtained by delaying a master drive signal on which the drive signal is based according to the first delay amount; a second delay circuit that outputs a second master drive delay signal obtained by delaying the master drive signal according to the second delay amount; a modulation circuit that modulates the first group drive delay signal and outputs a modulated signal; an amplifier circuit that amplifies the modulated signal and outputs a first amplified modulated signal; a level switching signal generating circuit that generates a level switching signal, which is a digital signal including a first potential and a second potential higher than the first potential, in response to the second unit drive delay signal; a level shift circuit that outputs the first amplified modulated signal as a second amplified modulated signal when the level switching signal is at the first potential, and outputs a signal obtained by shifting a potential of the first amplified modulated signal as the second amplified modulated signal when the level switching signal is at the second potential; a demodulation circuit that demodulates the second amplified modulated signal and outputs the drive signal; Equipped with A liquid ejection device comprising:

9. The level switching signal generating circuit includes: when the level switching signal is at the first potential, the level switching signal is switched from the first potential to the second potential in response to an increase in the value of the second drive delay signal, and then switched from the second potential to the first potential, and further switched from the first potential to the second potential; 9. The liquid ejection device according to claim 8.

10. The level switching signal generating circuit includes: when the level switching signal is at the second potential, the level switching signal is switched from the second potential to the first potential in response to a decrease in the value of the second drive delay signal, and then switched from the first potential to the second potential, and further switched from the second potential to the first potential; 9. The liquid ejection device according to claim 8.

11. a second storage unit that stores a first threshold value and a second threshold value different from the first threshold value; The level switching signal generating circuit includes: when the value of the second drive delay signal increases and becomes greater than the first threshold while the level switching signal is at the first potential, the level switching signal is switched from the first potential to the second potential; when the value of the second drive delay signal decreases and becomes smaller than the second threshold while the level switching signal is at the second potential, the level switching signal is switched from the second potential to the first potential.

9. The liquid ejection device according to claim 8.

12. The first delay amount stored in the first storage unit is rewritable.

9. The liquid ejection device according to claim 8.

13. The second delay amount stored in the first storage unit is rewritable.

9. The liquid ejection device according to claim 8.

14. The second delay amount is greater than the first delay amount.

9. The liquid ejection device according to claim 8.

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