Wiring structure and amplifier

Abstract

To suppress a local increase of an electric field in a MIM capacitor and reduce the number of overall wiring layers in a wiring structure, which includes the MIM capacitor and spiral wiring, and an amplifier.SOLUTION: A wiring structure comprises a MIM capacitor and spiral wiring. The wiring structure includes: a substrate including a principal surface and a rear surface; and a plurality of wiring layers successively laminated on the principal surface. The plurality of wiring layers include: a first wiring layer which is a wiring layer closest to the substrate; a second wiring layer provided on the first wiring layer; and a third wiring layer provided on the second wiring layer. The MIM capacitor includes: a first electrode included in the second wiring layer; a second electrode included in the third wiring layer; and a first insulation layer provided between the first electrode and the second electrode. The spiral wiring includes: first wiring included in the first wiring layer; second wiring included in the second wiring layer; and third wiring included in the third wiring layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a wiring structure and an amplifier.

Background Art

[0002] Patent Document 1 discloses an inductor formed across a plurality of wiring layers on a substrate. This inductor is formed by connecting a plurality of C-shaped wirings included in the plurality of wiring layers to each other.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] For example, in a semiconductor device such as a semiconductor amplifier, a MIM (Metal-Insulator-Metal) capacitor and a spiral wiring as an inductor may be formed using a plurality of wiring layers on a substrate. In that case, when the lower electrode of the MIM capacitor is formed using the first wiring layer, the flatness of the lower electrode may be impaired. When the flatness of the lower electrode is impaired, the variation in the thickness of the insulating layer formed between the lower electrode and the upper electrode increases, and the electric field at some locations where the thickness of the insulating layer is small locally increases. This leads to variations in the characteristics of the semiconductor device and a decrease in the reliability of the semiconductor device. In addition, spiral wiring as an inductor often requires more wiring layers than a MIM capacitor, but as the number of wiring layers increases, the manufacturing time becomes longer, so it is desirable to reduce the total number of wiring layers.

[0005] The present disclosure has been made in view of such problems, and in a wiring structure and an amplifier including a MIM capacitor and a spiral wiring, an object thereof is to suppress a local increase in an electric field in the MIM capacitor and to reduce the total number of wiring layers.

Means for Solving the Problems

[0006] In order to solve the above-described problems, a wiring structure according to the present disclosure is a wiring structure including a MIM capacitor and a spiral wiring, and includes a substrate having a front surface and a back surface, and a plurality of wiring layers sequentially stacked on the front surface. The plurality of wiring layers include a first wiring layer that is the wiring layer closest to the substrate, a second wiring layer provided on the first wiring layer, and a third wiring layer provided on the second wiring layer. The MIM capacitor includes a first electrode included in the second wiring layer, a second electrode included in the third wiring layer, and a first insulating layer provided between the first electrode and the second electrode. The spiral wiring includes a first wiring included in the first wiring layer, a second wiring included in the second wiring layer, and a third wiring included in the third wiring layer.

Effects of the Invention

[0007] According to the wiring structure and the amplifier according to the present disclosure, in a wiring structure including a MIM capacitor and a spiral wiring, a local increase in an electric field in the MIM capacitor can be suppressed, and the total number of wiring layers can be reduced.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

MODE FOR CARRYING OUT THE INVENTION

[0009] [Description of Embodiments of the Present Disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. [1] A wiring structure according to one aspect of the present disclosure is a wiring structure including a MIM capacitor and a spiral wiring, and includes a substrate having a front surface and a back surface, and a plurality of wiring layers sequentially stacked on the front surface. The plurality of wiring layers include a first wiring layer that is the wiring layer closest to the substrate, a second wiring layer provided on the first wiring layer, and a third wiring layer provided on the second wiring layer. The MIM capacitor includes a first electrode included in the second wiring layer, a second electrode included in the third wiring layer, and a first insulating layer provided between the first electrode and the second electrode. The spiral wiring includes a first wiring included in the first wiring layer, a second wiring included in the second wiring layer, and a third wiring included in the third wiring layer.

[0010] In this wiring structure, the first electrode (lower electrode) of the MIM capacitor is not included in the first wiring layer which is the bottommost layer among the plurality of wiring layers on the substrate, but is included in the second wiring layer provided on the first wiring layer. Usually, an insulating layer is interposed between the first wiring layer and the second wiring layer. The unevenness on the surface of the first wiring layer is gradually eliminated on the surface of the insulating layer when the insulating layer is laminated. Therefore, since the first electrode is included in the second wiring layer, the surface of the first electrode can be made flatter compared to the case where the first electrode is included in the first wiring layer. Thus, the variation in the thickness of the first insulating layer formed between the first electrode and the second electrode is reduced, and the local increase in the electric field in the MIM capacitor is suppressed. Also, the spiral wiring (inductor) is composed of the first wiring of the first wiring layer which is the bottommost layer among the plurality of wiring layers, and the second wiring and the third wiring respectively included in the second wiring layer and the third wiring layer which are also used for the MIM capacitor. Therefore, the total number of wiring layers can be reduced.

[0011] [2] The wiring structure of [1] above may be further provided with a fourth wiring included in the first wiring layer and one or more first vias connecting the first electrode to the fourth wiring between the MIM capacitor and the substrate. In that case, the first electrode can be electrically connected to the fourth wiring included in the first wiring layer with low inductance.

[0012] [3] The wiring structure of [2] above may be further provided with a metal film provided on the back surface and a second via provided to penetrate between the front surface and the back surface of the substrate and connecting the metal film to the fourth wiring. The second via may overlap the MIM capacitor and the fourth wiring when viewed from a direction perpendicular to the front surface. In that case, the first electrode of the MIM capacitor can be electrically connected to the metal film (for example, a reference potential line) provided on the back surface. In addition, compared to the case where the second via is provided at a position where it does not overlap the MIM capacitor when viewed from a direction perpendicular to the front surface, the area on the front surface required for the wiring structure can be reduced, and the wiring structure can be miniaturized.

[0013] [4] In the wiring structure of [1] to [3] above, the spiral wiring may further include a plurality of third vias that are distributed over the entire areas of the second wiring and the third wiring and connect the second wiring to the third wiring. In that case, the potential of the second wiring and the potential of the third wiring approach uniformly over the entire area. Therefore, since the wiring capacitance generated by the potential difference between the second wiring and the third wiring can be reduced, the capacitance component (parasitic capacitance) of the spiral wiring (inductor) can be reduced. In addition, the bias of the current flow can be reduced between the second wiring and the third wiring. Furthermore, by integrating the second wiring and the third wiring, even if the thicknesses of the second wiring and the third wiring are reduced, a decrease in the allowable current density and an increase in the wiring resistance can be suppressed.

[0014] [5] In the wiring structure of [4] above, the thicknesses of the second wiring and the third wiring may be smaller than the thickness of the first wiring. In that case, by connecting the second wiring to the third wiring through a plurality of third vias as in [4] above, a partial increase in the current density of the spiral wiring (inductor) can be suppressed. Also, by reducing the thicknesses of the second wiring and the third wiring, the wiring formation time can be shortened.

[0015] [6] In the wiring structure of [5] above, the thickness of the wiring in the second wiring layer may be smaller than the thickness of the wiring in the third wiring layer. In that case, the risk of disconnection of the wiring in the third wiring layer extending from the second electrode of the MIM capacitor can be reduced, and the wiring in the second wiring layer can be made thinner to shorten the formation time of the second wiring layer.

[0016] [7] In the wiring structure of [5] above, the sum of the thicknesses of the second wiring and the third wiring may be equal to the thickness of the first wiring. In that case, the current density of the spiral wiring (inductor) can be made uniform.

[0017] [8] In the wiring structure of [4] above, the plurality of wiring layers may further include a fourth wiring layer laminated on the third wiring layer. The spiral wiring may be further configured to include a fifth wiring included in the fourth wiring layer. In that case, the design of the spiral wiring (inductor) having a larger inductance can be facilitated.

[0018] [9] In the wiring structure of [8] above, the thickness of the fifth wiring may be equal to or greater than the thickness of the first wiring. Since the fifth wiring is included in the fourth wiring layer which is the uppermost layer, even if the fifth wiring is formed thick, the formation time of the insulating layer will not be prolonged. By forming the fifth wiring thick, the current density of the fifth wiring can be made sufficiently small.

[0019]

[10] In the wiring structure of [8] above, the first wiring, the second wiring, the third wiring, and the fourth wiring each exhibit an annular shape having a gap in part, and are arranged such that the centers of the annular shapes are located on a common axis perpendicular to the main surface, and the gaps of the second wiring and the third wiring may be arranged in a direction perpendicular to the main surface. The wiring structure may further include a fourth via connecting the end of the first wiring and the end of the second wiring, and a fifth via connecting the second end of the third wiring located on the opposite side of the first end of the third wiring located on the end of the second wiring and the end of the fourth wiring. For example, with such a structure, spiral wiring can be formed.

[0020]

[11] In the wiring structure of [1] to [7] above, the plurality of wiring layers may further include a fourth wiring layer laminated on the third wiring layer. The fourth wiring layer may include a sixth wiring provided on the MIM capacitor. For example, in this way, by also providing the wiring in the fourth wiring layer on the MIM capacitor, the area on the main surface required for the wiring structure can be reduced, and the wiring structure can be miniaturized.

[0021]

[12] The wiring structure of [1] to

[11] above may further include a second insulating layer interposed between the first wiring layer and the second wiring layer, and a third insulating layer interposed between the second wiring layer and the third wiring layer. The thickness of the first insulating layer may be smaller than the thicknesses of the second insulating layer and the third insulating layer. The dielectric constant of the first insulating layer may be larger than the dielectric constants of the second insulating layer and the third insulating layer. In that case, the capacitance of the MIM capacitor per unit area can be increased. Therefore, the area on the main surface required for the wiring structure can be reduced, and the wiring structure can be miniaturized.

[0022]

[13] An amplifier according to one aspect of the present disclosure includes any one of the wiring structures of [1] to

[12] above and a transistor provided on a substrate common to the wiring structure. According to this amplifier, by providing any one of the above wiring structures, a local increase in the electric field in the MIM capacitor can be suppressed, and the total number of wiring layers can be reduced.

[0023] [Details of Embodiments of the Present Disclosure] Specific examples of the wiring structure and the amplifier of the present disclosure will be described below with reference to the drawings. Note that the present invention is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims. In the following description, the same reference numerals are assigned to the same elements in the description of the drawings, and duplicate descriptions are omitted.

[0024] [First Embodiment] FIG. 1 is a diagram showing a cross-sectional structure of a wiring structure 10A according to the present embodiment. As shown in FIG. 1, the wiring structure 10A includes a substrate 20 having a main surface 21 and a back surface 22, and an insulating film 40. The substrate 20 is, for example, a semiconductor substrate. The substrate 20 is, for example, a III-V compound semiconductor substrate or a substrate on which a III-V compound semiconductor can be grown. The main surface 21 and the back surface 22 are parallel to each other and both are flat. The substrate 20 has a hole 23 penetrating the substrate 20 from the main surface 21 to the back surface 22.

[0025] The insulating film 40 is provided on the main surface 21 of the substrate 20 and is in contact with the main surface 21. The insulating film 40 is mainly composed of a silicon compound such as SiO 2 or SiN. The insulating film 40 has an opening communicating with the hole 23.

[0026] The wiring structure 10A further includes a plurality of wiring layers including a first wiring layer 50, a second wiring layer 60, a third wiring layer 70, and a fourth wiring layer 80. In the illustrated example, the plurality of wiring layers are composed of a first wiring layer 50, a second wiring layer 60, a third wiring layer 70, and a fourth wiring layer 80. In other words, the wiring structure 10A does not include wiring layers other than the first wiring layer 50, the second wiring layer 60, the third wiring layer 70, and the fourth wiring layer 80. The first wiring layer 50 is the wiring layer closest to the substrate 20 among the plurality of wiring layers. The insulating film 40 is interposed between the first wiring layer 50 and the main surface 21 and is in contact with both the first wiring layer 50 and the main surface 21. The second wiring layer 60 is provided on the first wiring layer 50. The third wiring layer 70 is provided on the second wiring layer 60. The fourth wiring layer 80 is provided on the third wiring layer 70. The wiring in the first wiring layer 50, the wiring in the second wiring layer 60, the wiring in the third wiring layer 70, and the wiring in the fourth wiring layer 80 are composed of, for example, at least one metal material among Au, Ti, Al, Ta, W, Cu, Pt, Mo, Ni, Pd, and Cr.

[0027] The thickness TA2 of the wiring in the second wiring layer 60 is the same as or smaller than the thickness TA3 of the wiring in the third wiring layer 70. The ratio (TA2 / TA3) of the thickness TA2 of the wiring in the second wiring layer 60 to the thickness TA3 of the wiring in the third wiring layer 70 is, for example, 1 / 2 or more and 1 or less. In one embodiment, the thickness TA2 is 1 μm or 2 μm, and the thickness TA3 is 2 μm.

[0028] Also, the thickness TA2 of the wiring in the second wiring layer 60 and the thickness TA3 of the wiring in the third wiring layer 70 are smaller than the thickness TA1 of the wiring in the first wiring layer 50. The ratio (TA2 / TA1) of the thickness TA2 of the wiring in the second wiring layer 60 to the thickness TA1 of the wiring in the first wiring layer 50 is, for example, 1 / 4 or more and 1 / 2 or less. The ratio (TA3 / TA1) of the thickness TA3 of the wiring in the third wiring layer 70 to the thickness TA1 of the wiring in the first wiring layer 50 is, for example, 1 / 2 or more and 2 / 3 or less. In one embodiment, the thickness TA1 is 3 μm or 4 μm. The sum (TA2 + TA3) of the thickness TA2 of the wiring in the second wiring layer 60 and the thickness TA3 of the wiring in the third wiring layer 70 may be equal to the thickness TA1 of the wiring in the first wiring layer 50. The thickness TA4 of the fourth wiring layer 80 is equal to or greater than the thickness TA1 of the first wiring layer 50.

[0029] The wiring structure 10A further includes an insulating layer 31 (second insulating layer), an insulating layer 32 (first insulating layer), an insulating layer 33, and an insulating layer 34. The insulating layer 32 is provided on the insulating layer 31, the insulating layer 33 is provided on the insulating layer 32, and the insulating layer 34 is provided on the insulating layer 33. The insulating layer 31 is interposed between the first wiring layer 50 and the second wiring layer 60. In a portion where the wiring in the first wiring layer 50 is not provided, the insulating layer 31 is in contact with the insulating film 40. The insulating layers 32 and 33 are interposed between the second wiring layer 60 and the third wiring layer 70. In a portion where the wiring in the second wiring layer 60 is not provided, the insulating layer 32 is in contact with the insulating layer 31. The insulating layer 33 is provided on the insulating layer 32 and is in contact with the insulating layer 32. The insulating layer 34 is interposed between the third wiring layer 70 and the fourth wiring layer 80. In a portion where the wiring in the third wiring layer 70 is not provided, the insulating layer 34 is in contact with the insulating layer 33. The dielectric constant of the insulating layer 32 is smaller than the dielectric constants of the insulating layers 31, 33, and 34. The insulating layers 31, 33, and 34 are composed of a dielectric including an insulating material containing Si such as SiO 2 , SiN, SiON, or a resin material such as polyimide. The insulating layer 32 is, for example, SiO 2 , an insulating material containing Si such as SiN, SiON, a resin material such as polyimide, or hafnium oxide (HfO) or aluminum oxide (Al 2 O 3) It is composed of a dielectric such as a metal oxide. Also, the thickness TB2 of the insulating layer 32 is smaller than the thicknesses TB1, TB3, and TB4 of the insulating layers 31, 33, and 34, respectively. The thickness TB1 of the insulating layer 31 is larger than the thicknesses TB2, TB3, and TB4 of the insulating layers 32, 33, and 34, respectively. The ratio (TB2 / TB1) of the thickness TB2 of the insulating layer 32 to the thickness TB1 of the insulating layer 31 is, for example, 0.001 or more and 0.5 or less. In one embodiment, the thicknesses TB1, TB2, TB3, and TB4 are 6 μm, 0.23 μm, 3 μm, and 4 μm, respectively.

[0030] The wiring structure 10A includes a wiring portion 12, a MIM capacitor 13, and an inductor 14 which is a spiral wiring. And separately from the wiring structure 10A, a transistor 11 is provided. The transistor 11, the wiring portion 12, the MIM capacitor 13, and the inductor 14 are provided in different regions when viewed from a direction perpendicular to the main surface 21.

[0031] The transistor 11 of this embodiment is a HEMT (High Electron Mobility Transistor). The transistor 11 has a source electrode 41, a drain electrode 42, a gate electrode 43, and a field plate 44. Also, the substrate 20 has a channel layer and an electron supply layer (not shown). The source electrode 41 and the drain electrode 42 are respectively provided in a source opening and a drain opening formed in the insulating film 40, and make an ohmic contact with the channel layer or the electron supply layer of the substrate 20. The gate electrode 43 is provided in a gate opening formed in the insulating film 40 and makes a Schottky contact with the substrate 20. The field plate 44 is insulated from the gate electrode 43 and is provided on the gate electrode 43 and between the gate electrode 43 and the drain electrode 42.

[0032] Transistor 11 further has a source wiring 51 and a drain wiring 52. Both the source wiring 51 and the drain wiring 52 are included in the first wiring layer 50. The source wiring 51 is provided on the source electrode 41 and is in contact with the source electrode 41. The drain wiring 52 is provided on the drain electrode 42 and is in contact with the drain electrode 42.

[0033] The wiring portion 12 has wirings 53, 61, 71, and 81, one or more vias 101, one or more vias 111, and one or more vias 121. The wiring 53 is included in the first wiring layer 50. The wiring 61 is included in the second wiring layer 60. The via 101 penetrates the insulating layer 31 and connects the wiring 61 to the wiring 53. The wiring 71 is included in the third wiring layer 70. The via 111 penetrates the insulating layers 32 and 33 and connects the wiring 71 to the wiring 61. The wiring 81 is included in the fourth wiring layer 80. The via 121 penetrates the insulating layer 34 and connects the wiring 81 to the wiring 71. Note that the wiring portion 12 shown in FIG. 1 schematically represents the wiring of other portions in the wiring structure 10A excluding the transistor 11, the MIM capacitor 13, and the inductor 14.

[0034] The MIM capacitor 13 includes a lower electrode 62 (first electrode), an upper electrode 72 (second electrode), and an insulating layer 32. The lower electrode 62 is included in the second wiring layer 60. The upper electrode 72 is included in the third wiring layer 70. The insulating layer 32 is provided between the lower electrode 62 and the upper electrode 72. The capacitance of the MIM capacitor 13 depends on the opposing area between the lower electrode 62 and the upper electrode 72, the dielectric constant of the insulating layer 32, and the thickness of the insulating layer 32.

[0035] The upper electrode 72 is integrally formed with the wiring 71 included in the third wiring layer 70. Specifically, an opening is formed in the region on the lower electrode 62 in the insulating layer 33, and the upper electrode 72 is formed on the side surface of the opening and on the bottom surface of the opening, that is, on the insulating layer 32 exposed from the insulating layer 33. A part of the wiring 71 covers a part of the upper electrode 72, and a part of the upper electrode 72 is in contact with the wiring 71. Therefore, although the upper electrode 72 protrudes from the wiring 71 toward the substrate 20 and is provided at the same height as the insulating layer 33, since it is connected to the wiring 71, it is considered to be included in the third wiring layer 70 here.

[0036] The wiring structure 10A of the present embodiment further includes a wiring 53 (fourth wiring), one or more vias 102 (first vias), a wiring 82 (sixth wiring), a metal film 91, and a via 92 (second via).

[0037] The wiring 53 is included in the first wiring layer 50. The wiring 53 is provided between the MIM capacitor 13 and the substrate 20. The via 102 penetrates the insulating layer 31 between the lower electrode 62 and the wiring 53 and connects the lower electrode 62 to the wiring 53. When viewed from a direction perpendicular to the main surface 21 of the substrate 20, the via 102 overlaps the lower electrode 62 and the wiring 53.

[0038] The metal film 91 is provided on the back surface 22 of the substrate 20. The metal film 91 is joined to a reference wire on a wiring board on which the wiring structure 10A is mounted, for example, by a conductive bonding material (e.g., silver paste), and is defined to the reference potential. The via 92 is provided so as to penetrate between the main surface 21 and the back surface 22 of the substrate 20. In the illustrated example, the via 92 is provided on the side surface of a hole 23 formed in the substrate 20 and in the opening of an insulating film 40 communicating with the hole 23. The via 92 extends from the back surface 22 of the substrate 20 to the surface of the insulating film 40. One end of the via 92 is connected to the wiring 54 by contacting the wiring 54, and the other end of the via 92 is connected to the metal film 91 by contacting the metal film 91. Thereby, the via 92 connects the metal film 91 to the wiring 54. The via 92 is provided at a position overlapping the MIM capacitor 13 and the wiring 54 when viewed from a direction perpendicular to the main surface 21.

[0039] The wiring 82 is included in the fourth wiring layer 80. The wiring 82 is part of many wirings that connect various circuit elements provided in the wiring structure 10A. The wiring 82 is provided on the MIM capacitor 13. In other words, when viewed from a direction perpendicular to the main surface 21, the wiring 82 is provided at a position overlapping the MIM capacitor 13.

[0040] The inductor 14 is composed of including the wiring 55 (first wiring), the wiring 63 (second wiring), the wiring 73 (third wiring), and the wiring 83 (fifth wiring). The wiring 55 is included in the first wiring layer 50. The wiring 63 is included in the second wiring layer 60. The wiring 73 is included in the third wiring layer 70. The wiring 73 has the same planar shape as the planar shape of the wiring 63 and overlaps the wiring 63 when viewed from a direction perpendicular to the main surface 21. The wiring 83 is included in the fourth wiring layer 80. Therefore, the thickness TA2 of the wiring 63 is the same as or smaller than the thickness TA3 of the wiring 73. Also, the thickness TA2 of the wiring 63 and the thickness TA3 of the wiring 73 are smaller than the thickness TA1 of the wiring 53. The sum (TA2 + TA3) of the thickness TA2 of the wiring 63 and the thickness TA3 of the wiring 73 may be equal to the thickness TA1 of the wiring 55. The thickness TA4 of the wiring 83 is equal to or greater than the thickness TA1 of the wiring 55. The thicknesses of each of the wirings 55, 63, 73, and 83 are determined according to the frequency used.

[0041] The inductor 14 further includes one or more vias 103, a plurality of vias 112 (third vias), and one or more vias 122. The via 103 penetrates the insulating layer 31 between the wiring 63 and the wiring 55. The via 103 connects one end of the wiring 63 to one end of the wiring 55. The via 122 penetrates the insulating layer 34 between the wiring 83 and the wiring 73. The via 122 connects one end of the wiring 83 to one end of the wiring 73. The plurality of vias 112 are dispersedly arranged over the entire regions of the wiring 63 and the wiring 73 and connect the wiring 63 to the wiring 73. The entire regions of the wiring 63 and the wiring 73 refer to the entire regions mainly in the extending directions of the wiring 63 and the wiring 73, and more specifically, refer to regions corresponding to 95% or more of the lengths of the wiring 63 and the wiring 73 in the extending directions. In other words, the plurality of vias 112 integrate the wiring 63 and the wiring 73 as a single wiring.

[0042] FIG. 2 is a perspective view showing the three-dimensional structure of the inductor 14. As shown in FIG. 2, by connecting the wiring 55, the via 103, the wirings 63 and 73, the via 112, and the wiring 83 in this order, the inductor 14 composed of a helical wiring is configured. Specifically, the wirings 55, 63, 73, and 83 each exhibit an annular shape having a part of a gap. And the wirings 55, 63, 73, and 83 are arranged such that the annular centers are located on a common axis perpendicular to the main surface 21. The gap 631 of the wiring 63 and the gap 731 of the wiring 73 are arranged in a direction perpendicular to the main surface 21. The via 103 connects the end 552 of the wiring 55 and the end 632 of the wiring 63. The via 122 connects the end 733 (second end) of the wiring 73 located on the opposite side of the end 732 (first end) of the wiring 73 located on the end 632 of the wiring 63 to the end 832 of the wiring 83.

[0043] FIG. 3 is a circuit diagram showing the configuration of the amplifier 1 including the wiring structure 10A. The amplifier 1 includes a transistor 11, an input terminal 191, an output terminal 192, capacitors 131 to 136, inductors 141 to 144, bias power supplies 151 and 152, and a reference potential line 16. The structure of the transistor 11 is as described above. The structure of at least one of the capacitors 131 to 136 is the same as that of the above-described MIM capacitor 13. The structure of at least one of the inductors 141 to 144 is the same as that of the above-described inductor 14.

[0044] The first electrode of the capacitor 132 is connected to the input terminal 191. The second electrode of the capacitor 132 is connected to the gate electrode 43 of the transistor 11. Thereby, the gate electrode 43 of the transistor 11 inputs a pre-amplification signal via the capacitor 132. The capacitor 132 acts as a coupling capacitor for the pre-amplification signal.

[0045] The first electrode of the capacitor 135 is connected to the drain electrode 42 of the transistor 11. The second electrode of the capacitor 135 is connected to the output terminal 192. Thereby, an amplified signal is output from the drain electrode 42 of the transistor 11 via the capacitor 135. The capacitor 135 acts as a coupling capacitor for the amplified signal.

[0046] The capacitor 131 and the inductor 141 are connected in parallel to each other between the input terminal 191 and the reference potential line 16. The capacitor 131 and the inductor 141 act as a filter for the pre-amplification signal. The capacitor 136 and the inductor 144 are connected in parallel to each other between the output terminal 192 and the reference potential line 16. The capacitor 136 and the inductor 144 act as a filter for the amplified signal.

[0047] The capacitor 133 is connected between the positive electrode of the bias power supply 151 and the reference potential line 16. The inductor 142 is connected between the positive electrode of the bias power supply 151 and the gate electrode 43 of the transistor 11. The capacitor 133 and the inductor 142 act as a filter for the input bias voltage supplied from the bias power supply 151 to the gate electrode 43. The capacitor 134 is connected between the positive electrode of the bias power supply 152 and the reference potential line 16. The inductor 143 is connected between the positive electrode of the bias power supply 152 and the drain electrode 42 of the transistor 11. The capacitor 134 and the inductor 143 act as a filter for the output bias voltage supplied from the bias power supply 152 to the drain electrode 42.

[0048] The effects obtained by the wiring structure 10A and the amplifier 1 of the present embodiment having the above configuration will be described together with a comparative example. FIG. 8 is a diagram showing a cross-sectional structure of a wiring structure according to a comparative example. In this comparative example, the lower electrode 62 of the MIM capacitor 13 is included in the first wiring layer 50. And the upper electrode 72 of the MIM capacitor 13 is included in the second wiring layer 60. In this case, the flatness of the lower electrode 62 may be impaired. When the flatness of the lower electrode 62 is impaired, the variation in the thickness of the insulating layer 32 formed between the lower electrode 62 and the upper electrode 72 becomes large, and the electric field locally increases at some locations where the thickness of the insulating layer 32 is small. This leads to variations in the characteristics of the semiconductor device and a decrease in the reliability of the semiconductor device.

[0049] In contrast, in the present embodiment, in the wiring structure 10A, the lower electrode 62 of the MIM capacitor 13 is not included in the first wiring layer 50 which is the bottommost layer among the plurality of wiring layers on the substrate 20, but is included in the second wiring layer 60 provided on the first wiring layer 50. Usually, an insulating layer 31 is interposed between the first wiring layer 50 and the second wiring layer 60. The unevenness on the surface of the first wiring layer 50 is gradually eliminated on the surface of the insulating layer 31 when the insulating layer 31 is laminated. Therefore, by including the lower electrode 62 in the second wiring layer 60, the surface of the lower electrode 62 can be made flatter compared to the case where the lower electrode 62 is included in the first wiring layer 50. Thus, the variation in the thickness of the insulating layer 32 formed between the lower electrode 62 and the upper electrode 72 is reduced, and the local increase in the electric field in the MIM capacitor 13 is suppressed.

[0050] In addition, in the present embodiment, the inductor 14 is composed of the wiring 55 of the first wiring layer 50 which is the bottommost layer among the plurality of wiring layers, and the wirings 63 and 73 included in the second wiring layer 60 and the third wiring layer 70 which are also used for the MIM capacitor 13, respectively. Therefore, in the wiring structure 10A including both the MIM capacitor 13 and the inductor 14, the total number of wiring layers can be reduced.

[0051] As in the present embodiment, the wiring structure 10A may be provided between the MIM capacitor 13 and the substrate 20, and may include the wiring 54 included in the first wiring layer 50 and one or a plurality of vias 102 connecting the lower electrode 62 to the wiring 54. In that case, the lower electrode 62 can be electrically connected to the wiring 54 included in the first wiring layer 50 with low inductance.

[0052] As in this embodiment, the wiring structure 10A may include a metal film 91 provided on the back surface 22 and a via 92 provided to penetrate between the front main surface 21 and the back surface 22 of the substrate 20 and connect the metal film 91 to the wiring 54. And the via 92 may overlap with the MIM capacitor 13 and the wiring 54 when viewed from a direction perpendicular to the front main surface 21. In that case, the lower electrode 62 of the MIM capacitor 13 can be electrically connected to a metal film 91 (for example, a reference potential line) provided on the back surface 22. In addition, compared with the case where the via 92 is provided at a position where it does not overlap with the MIM capacitor 13 when viewed from a direction perpendicular to the front main surface 21 (see FIG. 8), the area on the front main surface 21 required for the wiring structure 10A can be reduced, and the wiring structure 10A can be miniaturized.

[0053] As in this embodiment, the inductor 14 may include a plurality of vias 112 that are distributed over the entire area of the wiring 63 and the wiring 73 and connect the wiring 63 to the wiring 73. In that case, the potential of the wiring 63 and the potential of the wiring 73 approach uniformly over the entire area. Therefore, since the capacitance between the wirings generated by the potential difference between the wiring 63 and the wiring 73 can be reduced, the capacitance component (parasitic capacitance) of the inductor 14 can be reduced. In addition, the bias of the current flow can be reduced between the wiring 63 and the wiring 73. Furthermore, by integrating the wiring 63 and the wiring 73, even if the thickness TA2 of the wiring 63 and the thickness TA3 of the wiring 73 are reduced, a decrease in the allowable current density and an increase in the wiring resistance can be suppressed.

[0054] As in this embodiment, the thicknesses TA2 and TA3 of the wiring 63 and the wiring 73 may be smaller than the thickness TA1 of the wiring 55. In that case, by connecting the wiring 63 to the wiring 73 via a plurality of vias 112 as described above, a partial increase in the current density of the inductor 14 can be suppressed. Also, by reducing the thicknesses TA2 and TA3 of the wiring 63 and the wiring 73, the wiring formation time can be shortened.

[0055] As in this embodiment, the thickness TA2 of the wiring in the second wiring layer 60 may be smaller than the thickness TA3 of the wiring in the third wiring layer 70. In that case, the risk of disconnection of the wiring in the third wiring layer 70 extending from the upper electrode 72 of the MIM capacitor 13 can be reduced, and the formation time of the second wiring layer 60 can be shortened by thinning the wiring in the second wiring layer 60.

[0056] As in this embodiment, the sum (TA2 + TA3) of the thicknesses of the wiring 63 and the wiring 73 may be equal to the thickness TA1 of the wiring 55. In that case, the current density of the inductor 14 can be made uniform.

[0057] As in this embodiment, the plurality of wiring layers of the wiring structure 10A may include a fourth wiring layer 80 laminated on the third wiring layer 70. And the inductor 14 may be configured to include the wiring 83 included in the fourth wiring layer 80. In that case, the design of the inductor 14 having a larger inductance can be facilitated.

[0058] Here, FIG. 4 is a graph showing the relationship between the number of wiring layers and the area in the inductor, and the relationship between the number of wiring layers and the film formation time of the insulating layer in the inductor. In FIG. 4, the straight line G1 shows the relationship between the number of wiring layers and the area, and the straight line G2 shows the relationship between the number of wiring layers and the film formation time. As shown in the figure, the area of the inductor decreases as the number of wiring layers increases. On the other hand, the film formation time of the insulating layer increases as the number of wiring layers increases. And when the number of wiring layers is 3 (point A in the figure), the balance between the area and the film formation time is the best. That is, since the inductor 14 is composed of three wiring layers, namely, (1) the wiring 55, (2) the integrated wiring by the wirings 63 and 73, and (3) the wiring 83, the balance between the area and the film formation time is the best, and the manufacturing cost of the wiring structure 10A can be reduced.

[0059] As in this embodiment, the thickness TA4 of the wiring 83 may be equal to or greater than the thickness TA1 of the wiring 55. Since the wiring 83 is included in the fourth wiring layer 80 which is the topmost layer, even if the wiring 83 is formed thick, the formation time of the insulating layer will not become long. By forming the wiring 83 thick, the current density of the wiring 83 can be made sufficiently small.

[0060] As in this embodiment, the wirings 55, 63, 73, and 83 may each have an annular shape with a gap in part. And the wirings 55, 63, 73, and 83 may be arranged such that the centers of the annular shapes are located on a common axis perpendicular to the main surface 21. The gap 631 of the wiring 63 and the gap 731 of the wiring 73 may be arranged in a direction perpendicular to the main surface 21. The via 103 may connect the end 552 of the wiring 55 and the end 632 of the wiring 63. The via 122 may connect the end 733 (second end) of the wiring 73 located on the opposite side of the end 732 (first end) of the wiring 73 located on the end 632 of the wiring 63 and the end 832 of the wiring 83. For example, an inductor 14 can be formed by such a structure.

[0061] As in this embodiment, the fourth wiring layer 80 may include the wiring 82 provided on the MIM capacitor 13. For example, in this way, by also providing the wirings in the fourth wiring layer 80 on the MIM capacitor 13, the area on the main surface 21 required for the wiring structure 10A can be reduced, and the wiring structure 10A can be miniaturized.

[0062] As in this embodiment, the wiring structure 10A may include the insulating layer 31 interposed between the first wiring layer 50 and the second wiring layer 60, and the insulating layer 33 interposed between the second wiring layer 60 and the third wiring layer 70. The thickness TB2 of the insulating layer 32 may be smaller than the thicknesses TB1 and TB3 of the insulating layer 31 and the insulating layer 33. The dielectric constant of the insulating layer 32 may be larger than the dielectric constants of the insulating layer 31 and the insulating layer 33. In that case, the capacitance of the MIM capacitor 13 per unit area can be increased. Therefore, the area on the main surface 21 required for the wiring structure 10A can be reduced, and the wiring structure 10A can be miniaturized.

[0063] The amplifier 1 of this embodiment includes capacitors 131 to 136 having the same structure as the MIM capacitor 13 of the wiring structure 10A, inductors 141 to 144 having the same structure as the inductor 14 of the wiring structure 10A, and a transistor 11 provided on the same substrate 20 as the wiring structure 10A. According to this amplifier 1, a local increase in the electric field in the capacitors 131 to 136 can be suppressed, and the total number of wiring layers can be reduced.

[0064] [Second Embodiment] FIG. 5 is a circuit diagram of the passive element 2 according to the second embodiment. The passive element 2 is used, for example, as a matching circuit element connected to an amplifier. The passive element 2 includes an inductor 14 and two MIM capacitors 13A and 13B. One end of the inductor 14 is connected to the input terminal 201, and the other end of the inductor 14 is connected to the node 202. The first electrode of the MIM capacitor 13A is connected to the node 202. The second electrode of the MIM capacitor 13A is connected to the metal film 91 which is a reference potential line. The first electrode of the MIM capacitor 13B is connected to the node 202. The second electrode of the MIM capacitor 13B is connected to the output terminal 203.

[0065] FIG. 6 is a plan view of the wiring structure 10B included in the passive element 2. FIG. 7 is a diagram showing a cross-sectional structure of the wiring structure 10B. As shown in FIGS. 6 and 7, the inductor 14 and the two MIM capacitors 13A and 13B are arranged on the substrate 20 side by side in this order along a predetermined direction. The inductor 14 has the same structure as the inductor 14 of the first embodiment except for the following points. The inductor 14 of this embodiment includes a wiring 84 instead of the wiring 83. The wiring 84 is included in the fourth wiring layer 80. The thickness of the wiring 84 is equal to or greater than the thickness of the wiring 55.

[0066] The MIM capacitors 13A and 13B have the same structure as the MIM capacitor 13 of the first embodiment. On the MIM capacitor 13A, instead of the wiring 82 of the first embodiment, a wiring 84 extending from the inductor 14 is provided. The upper electrodes 72 of the MIM capacitors 13A and 13B are connected to the wiring 84 via the wiring 71 and the via 121. The lower electrodes 62 of the MIM capacitors 13A and 13B are connected to the wiring 54 via the via 102, similar to the first embodiment. Note that the wiring 54 connected to the MIM capacitor 13A is connected to the metal film 91 via the via 92, similar to the first embodiment. On the other hand, unlike the first embodiment, the via 92 is not connected to the wiring 54 connected to the MIM capacitor 13B.

[0067] The wiring 55 is connected to the input terminal 201 shown in FIG. 5. The wiring 54 connected to the MIM capacitor 13B is connected to the output terminal 203 shown in FIG. 5. The node 202 shown in FIG. 5 is included in the wiring 84.

[0068] According to the wiring structure 10B of the present embodiment, similar to the wiring structure 10A of the first embodiment, in the wiring structure including the MIM capacitors 13A and 13B and the inductor 14, it is possible to suppress a local increase in the electric field in the MIM capacitors 13A and 13B and reduce the total number of wiring layers.

[0069] The wiring structure and the amplifier according to the present disclosure are not limited to the above-described embodiments, and various other modifications are possible. For example, in the above embodiment, the relationship between the thicknesses of the first wiring layer 50, the second wiring layer 60, the third wiring layer 70, and the fourth wiring layer 80 was mentioned, but the relationship between these thicknesses is not limited to the above-described relationship. Also, in the above embodiment, the relationship between the thicknesses of the insulating layers 31, 32, 33, and 34 was mentioned, but the relationship between these thicknesses is not limited to the above-described relationship.

Explanation of Reference Numerals

[0070] 1... Amplifier 2... Passive element 10A, 10B... Wiring structure 11… Transistor 12… Wiring part 13, 13A, 13B… MIM capacitor 14… Inductor 16… Reference potential line 20… Substrate 21… Main surface 22… Back surface 23… Hole 31… Insulating layer (second insulating layer) 32… Insulating layer (first insulating layer) 33, 34… Insulating layer 40… Insulating film 41… Source electrode 42… Drain electrode 43… Gate electrode 44… Field plate 50… First wiring layer 51… Source wiring 52… Drain wiring 53… Wiring (fourth wiring) 54… Wiring 55… Wiring (first wiring) 60… Second wiring layer 61… Wiring 62… Lower electrode (first electrode) 63… Wiring (second wiring) 70… Third wiring layer 71… Wiring 72… Upper electrode (second electrode) 73… Wiring (third wiring) 80… Fourth wiring layer 81… Wiring 82… Wiring (sixth wiring) 83… Wiring (fifth wiring) 84… Wiring 91… Metal film 92… Via (second via) 101… Via 102… Via (first via) 103, 111… Via 112… Via (third via) 121, 122… Via 131, 132, 133, 134, 135, 136… Capacitor 141, 142, 143, 144… Inductor 151, 152… Bias power supply 191, 201… Input terminal 192, 203… Output terminal 202… Node 631, 731… Gap 552, 632, 732, 733, 832… End G1, G2… Straight line

Claims

1. 1. An interconnect structure comprising a MIM capacitor and a spiral interconnect, a substrate having a main surface and a back surface; A plurality of wiring layers laminated in sequence on the main surface; Equipped with the plurality of wiring layers include a first wiring layer that is a wiring layer closest to the substrate, a second wiring layer provided on the first wiring layer, and a third wiring layer provided on the second wiring layer; the MIM capacitor includes a first electrode included in the second wiring layer, a second electrode included in the third wiring layer, and a first insulating layer provided between the first electrode and the second electrode, A wiring structure, wherein the spiral wiring includes a first wiring included in the first wiring layer, a second wiring included in the second wiring layer, and a third wiring included in the third wiring layer.

2. a fourth wiring provided between the MIM capacitor and the substrate and included in the first wiring layer; one or more first vias connecting the first electrode to the fourth wiring; The wiring structure of claim 1 , further comprising:

3. A metal film provided on the back surface; a second via provided between the main surface and the back surface of the substrate and connecting the metal film to the fourth wiring; Further comprising:

3. The wiring structure according to claim 2, wherein said second via overlaps with said MIM capacitor and said fourth wiring when viewed in a direction perpendicular to said main surface.

4. 4. The wiring structure according to claim 1, wherein the spiral wiring further includes a plurality of third vias that are distributed throughout the second wiring and the third wiring and connect the second wiring to the third wiring.

5. The wiring structure according to claim 4 , wherein the thickness of the second wiring and the third wiring is smaller than the thickness of the first wiring.

6. 6. The wiring structure according to claim 5, wherein a thickness of the wiring in the second wiring layer is smaller than a thickness of the wiring in the third wiring layer.

7. 6. The wiring structure according to claim 5, wherein a sum of thicknesses of said second wiring and said third wiring is equal to a thickness of said first wiring.

8. the plurality of wiring layers further includes a fourth wiring layer stacked on the third wiring layer, 5. The wiring structure according to claim 4, wherein the spiral wiring further includes a fifth wiring included in the fourth wiring layer.

9. The wiring structure according to claim 8 , wherein the thickness of the fifth wiring is equal to or greater than the thickness of the first wiring.

10. the first wiring, the second wiring, the third wiring, and the fourth wiring each have a ring shape having a gap in a part thereof, and are arranged such that centers of the rings are positioned on a common axis perpendicular to the main surface; the gaps of the second wiring and the gaps of the third wiring are aligned in a direction perpendicular to the main surface, a fourth via connecting an end of the first wiring and an end of the second wiring; a fifth via that connects a second end of the third wiring located on the opposite side to a first end of the third wiring located on the end of the second wiring and an end of the fourth wiring; The wiring structure of claim 8 , further comprising:

11. the plurality of wiring layers further includes a fourth wiring layer stacked on the third wiring layer, 4. The wiring structure according to claim 1, wherein the fourth wiring layer includes a sixth wiring provided on the MIM capacitor.

12. a second insulating layer interposed between the first wiring layer and the second wiring layer; a third insulating layer interposed between the second wiring layer and the third wiring layer; Further comprising: a thickness of the first insulating layer is smaller than thicknesses of the second insulating layer and the third insulating layer; The wiring structure according to claim 1 , wherein the first insulating layer has a higher dielectric constant than the second insulating layer and the third insulating layer.

13. The wiring structure according to any one of claims 1 to 3, a transistor provided on the substrate common to the wiring structure; An amplifier comprising:

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