Circuit board and method for manufacturing circuit board

Abstract

To provide a circuit board and a method for manufacturing the circuit board that can secure the width of bonding pads to which bonding wires are connected while realizing bonding pads for mounting wire bonding chips in a fine pitch pattern.SOLUTION: The disclosed circuit board 100 includes: an insulating layer 110 having a first surface 110a and a second surface 110b facing each other; and a first connection pad 121 having a first portion 121a embedded in the insulating layer 110 and at least partially exposed from the insulating layer 110 on the first surface 110a and a second portion 121b even closer to the second surface 110b than the first portion 121a, and a first width w1 of the first portion 121a and a second width w2 of the second portion differ from each other in a width along a direction parallel to the first surface 110a.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a circuit board and a method for manufacturing the circuit board.

Background Art

[0002] In the semiconductor package manufacturing process using a lead frame, after the chip attach process of mounting a semiconductor chip on the lead frame, a wire bonding process is performed to electrically connect the semiconductor chip and the lead frame with a metal wire. The wire bonding process is performed, for example, by causing a local melting phenomenon in the metal pad layer of the semiconductor chip using ultrasonic waves to bond the metal wire.

[0003] As the electronics industry develops and the miniaturization and high functionality of electronic devices accelerate, the size of semiconductor packages also tends to become smaller. In order to cope with the miniaturization in package products, the size of the bonding pads on the printed circuit board (PCB) for wire bonding is also decreasing. On the other hand, in reality, an increase in the bonding pad width is required during the manufacturing of the printed circuit board in order to reduce the bonding failure rate during the wire bonding process.

Summary of the Invention

Problems to be Solved by the Invention

[0004] One aspect of the embodiment is to provide a circuit board and a method for manufacturing the circuit board that can secure the width of the bonding pad to which the bonding wire is connected while realizing the bonding pad for mounting the wire bonding chip in a fine pitch pattern.

[0005] However, the problems to be solved by the embodiments of the present invention are not limited to the above problems, and can be variously extended within the scope of the technical idea included in the present invention.

Means for Solving the Problem

[0006] A circuit board according to one embodiment includes an insulating layer having a first surface and a second surface facing each other, and a first connection pad embedded in the insulating layer and having a first portion exposed from the insulating layer at the first surface and a second portion closer to the second surface than the first portion. In the width along the direction parallel to the first surface, a first width of the first portion and a second width of the second portion are different from each other.

[0007] The first width may be even larger than the second width.

[0008] The first portion and the second portion can be configured to have a step.

[0009] The circuit board can further include a protective layer disposed on the first surface of the insulating layer and opened to expose the first connection pad.

[0010] The circuit board further includes a first circuit wiring embedded in the insulating layer and covered by the protective layer. In the thickness in the direction perpendicular to the first surface, the thickness of the first circuit wiring may be even thicker than the thickness of the first portion of the first connection pad.

[0011] The circuit board can further include a conductive layer disposed on the first connection pad.

[0012] The conductive layer can be disposed on the exposed portion of the first connection pad.

[0013] The conductive layer may protrude from the first surface of the insulating layer.

[0014] The width of the conductive layer in the direction parallel to the first surface may be even larger than the second width of the second portion of the first connection pad.

[0015] The conductive layer can include a gold (Au) plating layer.

[0016] The first connection pad can include copper (Cu).

[0017] The first connection pad can be disposed in a bond finger region.

[0018] The circuit board can further include a second connection pad disposed on the second surface of the insulating layer.

[0019] The insulating layer includes a plurality of insulating layers, and the plurality of insulating layers can include a plurality of circuit layers.

[0020] A method of manufacturing a circuit board according to another embodiment includes forming a first portion of a first connection pad with a first metal on a seed layer, patterning a plating resist covering the first portion and plating the first metal to form a second portion of the first connection pad having a width different from that of the first portion on the first portion, and forming an insulating layer so as to cover the first portion and the second portion.

[0021] The first width of the first portion can be formed to be even larger than the second width of the second portion.

[0022] The manufacturing method can further include removing the seed layer so that at least a part of the first portion is exposed from the insulating layer.

[0023] The manufacturing method can further include forming a conductive layer on the first portion exposed from the insulating layer.

[0024] The manufacturing method can further include forming a protective layer on the insulating layer so that the conductive layer is exposed.

Advantages of the Invention

[0025] According to the circuit board according to the embodiment, while realizing bonding pads for mounting wire bonding chips in a fine pitch pattern, it is possible to secure a wide width of the bonding pads to which the bonding wires are connected. By securing the width of the bonding pads, it is possible to improve the bonding pad miss defect during packaging progress. At the same time, the width of the pads embedded inside the insulating layer is designed to be relatively narrow to increase the design freedom and can cope with the fine pitch bond fingers due to miniaturization of the package.

[0026] According to the manufacturing method of the circuit board according to the embodiment, by manufacturing with the ETS (Embedded Trace Substrate) method, it is possible to secure the bonding wire connection surface width while maintaining the bonding pads in a fine pitch pattern.

Brief Description of the Drawings

[0027]

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Embodiments for Carrying Out the Invention

[0028] Hereinafter, embodiments of the present invention will be described in detail so that those having ordinary knowledge in the technical field to which the present invention pertains can easily implement it with reference to the attached drawings. In order to clearly explain the present invention in the drawings, parts that are unnecessary for the explanation are omitted, and the same reference numerals are given to the same or similar components throughout the specification. Also, in the attached drawings, some components are exaggerated, or omitted, or illustrated schematically, and the sizes of the components do not fully reflect the actual sizes.

[0029] The attached drawings are only for facilitating the understanding of the embodiments disclosed in this specification, and the technical idea disclosed in this specification is not limited by the attached drawings, and it must be understood that all modifications, equivalents, and alternatives included in the idea and technical scope of the present invention are included.

[0030] Terms including ordinal numbers such as first, second, etc. can be used to describe various components, but the components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

[0031] Also, when a part such as a layer, film, region, or plate is "on" or "above" another part, this includes not only the case where it is directly above the other part, but also the case where there are other parts in between. Conversely, when a part is "directly above" another part, it means that there are no other parts in between. Also, being "on" or "above" a reference part means being located above or below the reference part, and does not necessarily mean being located "on" or "above" in the direction opposite to gravity.

[0032] Throughout the specification, terms such as "comprising" or "having" are intended to specify the presence of the features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, and should not be construed as precluding the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof. Thus, when a part "comprises" a certain component, this means that it can further comprise other components rather than excluding other components, unless otherwise stated to the contrary.

[0033] Also, throughout the specification, when it is said "on a plane", this means when looking at the target part from above, and when it is said "in a cross-section", this means when looking at the cross-section obtained by vertically cutting the target part from the side.

[0034] Also, throughout the specification, when it is said "connected", this does not only mean that two or more components are directly connected, but also means that two or more components are indirectly connected through other components, physically connected, not only physically connected but also electrically connected, or can be meant to be integral although referred to by different names depending on their position or function.

[0035] FIG. 1 is a cross-sectional view showing a circuit board according to an embodiment.

[0036] Referring to FIG. 1, the circuit board 100 according to the present embodiment includes an insulating layer 110, and a first connection pad 121 and a first circuit wiring 122 embedded in the insulating layer 110. The insulating layer 110, the first connection pad 121, and the first circuit wiring 122 can form an embedded pattern substrate. The circuit board 100 can be used as a printed circuit board for a semiconductor package.

[0037] The insulating layer 110 has a first surface 110a and a second surface 110b facing each other, and can include a resin insulating layer. The insulating layer 110 can use a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin impregnated with a reinforcing material such as glass fiber or inorganic filler, for example, prepreg, and can include a thermosetting resin and / or a photocurable resin, etc., but is not limited thereto.

[0038] The first connection pad 121 is embedded in the insulating layer 110 and can have a form in which the widths of the upper part and the lower part are different from each other. The first connection pad 121 embedded in the insulating layer 110 can include a first portion 121a close to the first surface 110a of the insulating layer 110 and a second portion 121b close to the second surface 110b. The first portion 121a is at least partially exposed from the insulating layer 110 on the first surface 110a, and the second portion 121b may be arranged closer to the second surface 110b than the first portion 121a.

[0039] When the width measured along the direction parallel to the first surface 110a of the insulating layer 110 is used as a reference, the first width w1 of the first portion 121a may be even larger than the second width w2 of the second portion 121b. The first width w1 of the first portion 121a exposed from the insulating layer 110 may be even larger than the second width w2 of the second portion 121b. At this time, the first portion 121a and the second portion 121b of the first connection pad 121 may have a stepped structure with respect to each other. Thereby, the first connection pad 121 embedded in the insulating layer 110 can secure a wider width of the surface where wire bonding is performed while realizing a bonding pad with a fine pitch, and thus can reduce bonding errors.

[0040] The first conductive layer 141 may be laminated and disposed on the first connection pad 121. The first conductive layer 141 may be disposed on the first portion 121a of the first connection pad 121 exposed from the insulating layer 110. The exposed first portion 121a of the first connection pad 121 may be in the same plane as the first surface 110a of the insulating layer 110, or may be formed by slightly recessing from the first surface 110a of the insulating layer 110. The first conductive layer 141 laminated on the first connection pad 121 may at least partially protrude from the first surface 110a of the insulating layer 110.

[0041] The first connection pad 121 and the first circuit wiring 122 may include a copper (Cu) layer. The first conductive layer 141 may include a nickel (Ni) plating layer and a gold (Au) plating layer. The first conductive layer 141 may be formed by plating a nickel plating layer on the first connection pad 121 and then plating a gold plating layer on the nickel plating layer.

[0042] In this embodiment, the first conductive layer 141 can be formed by an electrolytic gold plating method. That is, the nickel plating layer and the gold plating layer can be formed by applying a current to the first connection pad 121 containing copper to form a nickel / gold metal film. As another example, the first conductive layer 141 can also be formed by an electroless gold plating method.

[0043] When viewed from the cross-section obtained by cutting the circuit board 100 in the thickness direction, the width of the first conductive layer 141 may be substantially the same as or even larger than the width of the first connection pad 121. The width of the first conductive layer 141 may be the same as or even larger than the width of the first connection pad 121 at the portion where the first conductive layer 141 contacts the first connection pad 121.

[0044] The first connection pad 121 can be a bond finger disposed in the bond finger region. Also, a plurality of first connection pads 121 can constitute a plurality of bond fingers. That is, the first connection pad 121 is composed of bond fingers for wire bonding pads, and a conductive wire may be joined thereto during wire bonding of the semiconductor chip.

[0045] A first protective layer 131 may be disposed on the first surface 110a of the insulating layer 110. The first protective layer 131 may be opened so as to expose the first connection pad 121. Also, the first protective layer 131 can overlap and cover the first circuit wiring 122 located inside the insulating layer 110. The first protective layer 131 can be a solder resist layer.

[0046] In the thickness along the direction perpendicular to the first surface 110a of the insulating layer 110, the thickness of the first circuit wiring 122 may be even thicker than the thickness of the first portion 121a of the first connection pad 121. Also, the thickness of the entire first connection pad 121 including the first portion 121a and the second portion 121b may be the same as the thickness of the first circuit wiring 122.

[0047] On the second surface 110b of the insulating layer 110, a second connection pad 125 and a second circuit wiring 126 may be further formed. The second connection pad 125 and the second circuit wiring 126 may protrude from the second surface 110b of the insulating layer 110 and can be connected to the first circuit wiring 122 through the via 123. A second protective layer 135 can be formed around the second connection pad 125 on the second surface 110b of the insulating layer 110. The second protective layer 135 can overlap and cover the second circuit wiring 126 and can be a solder resist layer.

[0048] The second connection pad 125 and the second circuit wiring 126 can include a copper (Cu) layer, and a second conductive layer 145 can be formed on the second connection pad 125. The second conductive layer 145 can include a nickel (Ni) plating layer and a gold (Au) plating layer. The nickel plating layer can be formed on the second connection pad 125, and the gold plating layer can be formed on the nickel plating layer.

[0049] On the other hand, although the circuit board 100 shown in FIG. 1 shows a structure having connection pads 121 and 125 on both surfaces of the insulating layer 110, the second connection pad 125 disposed on the second surface 110b of the insulating layer 110 can be omitted, and this also belongs to the scope of the present disclosure. Furthermore, the insulating layer 110 includes a plurality of insulating layers, and each of the plurality of insulating layers can include a circuit layer. Therefore, circuit layers can be formed in each of three or more insulating layers, and vias can extend in the thickness direction of the insulating layer so as to connect these circuit layers.

[0050] FIGS. 2 to 15 are process cross-sectional views showing a method of manufacturing the circuit board shown in FIG. 1. Hereinafter, a method of manufacturing a circuit board will be described with reference to FIGS. 2 to 15 and FIG. 1 together.

[0051] Referring to FIGS. 2 to 5, a carrier substrate 60 having a first seed layer 71 disposed on at least one surface is prepared, and a first portion 121a of the first connection pad 121 is formed on the first seed layer 71 through a circuit formation process. The carrier substrate 60 may be a substrate in which copper foil layers 62 are laminated on both surfaces of an insulating substrate 61, and the first seed layer 71 and the copper foil layer 62 can be separated from each other (see FIG. 2). The photoresist formed on the carrier substrate 60 can be exposed and developed to form a first photoresist pattern 83. The first photoresist pattern 83 can be formed by removing only the portion where the first portion 121a of the first connection pad 121 is formed (see FIG. 3). The first portion 121a of the first connection pad 121 can be formed by plating a conductive metal on the portion of the first seed layer 71 exposed through the opening of the patterned first photoresist pattern 83 (see FIG. 4). After the formation of the first portion 121a of the first connection pad 121, the first photoresist pattern 83 is removed (see FIG. 5).

[0052] The first seed layer 71 can be applied without limitation as long as it is used as a conductive metal for circuits in the circuit board field, and it is common to use copper (Cu). The first portion 121a of the first connection pad 121 can be connected to the first seed layer 71 of the carrier substrate 60 and can include the same type of metal as the first seed layer 71. For example, the first seed layer 71 and the first portion 121a of the first connection pad 121 can include copper (Cu).

[0053] Although this embodiment shows the formation of the first portion 121a of the first connection pad 121 on both surfaces of the carrier substrate 60, it is also possible to form the first portion 121a of the first connection pad 121 on only one surface of the carrier substrate 60, and this also belongs to the scope of the present disclosure.

[0054] Referring to FIGS. 6 and 7, a second plating resist pattern 85 can be formed on a carrier substrate 60 where a first portion 121a of the first connection pad 121 is formed, with a portion where a second portion 121b of the first connection pad 121 is to be formed removed through exposure and development. The second portion 121b of the first connection pad 121 can be formed by plating a conductive metal on the first portion 121a of the first connection pad 121 exposed through the opening of the patterned second plating resist pattern 85 (see FIG. 6). At this time, the second plating resist pattern 85 may also be opened at a portion of the first seed layer 71 where the first portion 121a of the first connection pad 121 is not formed. In this portion, a conductive metal can be plated on the first seed layer 71 to form the first circuit wiring 122. After the formation of the first circuit wiring 122 and the second portion 121b of the first connection pad 121, the second plating resist pattern 85 is removed (see FIG. 7).

[0055] Referring to FIG. 8, an insulating layer 110A is laminated so that the first connection pad 121 is embedded, and a second seed layer 73 is formed on the upper surface of the insulating layer 110A. The second seed layer 73 is provided for forming the second connection pad 125 and the second circuit wiring 126, and can be used without limitation as long as it is a conductive metal, but it is common to use copper (Cu).

[0056] The insulating layer 110A can include a resin insulating layer. The insulating layer 110A can use a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a resin impregnated with a reinforcing material such as glass fiber or an inorganic filler, for example, a prepreg. Also, the insulating layer 110A can include a thermosetting resin and / or a photocurable resin, etc., but is not limited thereto.

[0057] Referring to FIGS. 9 to 12, a wiring pattern layer 125A for forming a second connection pad 125 and a second circuit wiring 126 can be formed on the insulating layer 110 through a circuit forming process. The wiring pattern layer 125A can include the same kind of material as the first circuit wiring 122 and the first connection pad 121. At this time, the insulating layer 110 can be partially etched to expose a part of the first circuit wiring 122 in order to form a via 123 that connects the first circuit wiring 122 and the wiring pattern layer 125A to each other (see FIG. 9). Then, a third plating resist pattern 87 can be formed on the second seed layer 73 to form the wiring pattern layer 125A (see FIG. 10). In the third plating resist pattern 87, a portion where the wiring pattern layer 125A is to be formed is opened to expose the second seed layer 73. A plating process can be performed on the exposed second seed layer 73 and the part of the first circuit wiring 122 (see FIG. 11). After the formation of the wiring pattern layer 125A, the third plating resist pattern 87 is removed, and an embedded pattern substrate portion is completed on both sides of the carrier substrate 60 (see FIG. 12).

[0058] According to the illustrated embodiment, each embedded pattern substrate portion is shown as including one insulating layer 110 and two metal layers, i.e., the first circuit wiring 122 and the second circuit wiring 126. However, the present disclosure is not limited thereto, and it can further include a greater number of build-up insulating layers and a greater number of build-up wiring pattern layers, which also belong to the scope of the present disclosure.

[0059] Referring to FIG. 13, the first seed layer 71 and the carrier substrate 60 are separated to prepare an embedded pattern substrate. The first seed layer 71 formed on both surfaces of the carrier substrate 60 can be separated from the copper foil layer 62 to obtain a pair of embedded pattern substrates, and the processes can be individually applied to each of the pair of embedded pattern substrates.

[0060] Referring to FIG. 14, the embedded pattern substrate obtained in FIG. 13 is soft-etched to remove the first seed layer 71 and the second seed layer 73. After removing the first seed layer 71 and the second seed layer 73, a first connection pad 121 and a first circuit wiring 122 embedded in the insulating layer 110 and exposed on the first surface 110a are formed. The wiring pattern layer 125A disposed on the second surface 110b of the insulating layer 110 is separated from each other to form a second connection pad 125 and a second circuit wiring 126. By removing the first seed layer 71, a part of the first portion 121a of the first connection pad 121 is exposed from the insulating layer 110. In the process of removing the first seed layer 71, the surfaces of the first connection pad 121 and the first circuit wiring 122 exposed from the insulating layer 110 can also be partially etched to be recessed from the surface of the insulating layer 110.

[0061] Referring to FIG. 15, a first protective layer 131 and a second protective layer 135 are formed to cover the insulating layer 110 and the circuit wirings 122 and 126 on both surfaces of the embedded pattern substrate obtained in FIG. 14. The first protective layer 131 and the second protective layer 135 can include a solder resist layer. The first protective layer 131 may be patterned to expose the first connection pad 121 on the first surface 110a of the insulating layer 110 where the first connection pad 121 is exposed. The second protective layer 135 may be opened to cover the second circuit wiring 126 and expose the second connection pad 125 on the second surface 110b of the insulating layer 110 where the second connection pad 125 is disposed.

[0062] Referring back to FIG. 1, a first conductive layer 141 and a second conductive layer 145 can be formed on the first connection pad 121 and the second connection pad 125 exposed by the protective layers 131 and 135 in the embedded pattern substrate obtained in FIG. 15, respectively. The first conductive layer 141 and the second conductive layer 145 can be formed by an electrolytic gold plating method. A nickel plating layer and a gold plating layer can be formed by a method of applying a current to the first connection pad 121 or the second connection pad 125 containing copper to form a nickel / gold metal coating. Optionally, the first conductive layer 141 and the second conductive layer 145 can also be formed by an electroless gold plating method.

[0063] The preferred embodiments of the present invention have been described above. However, the present invention is not limited thereto, and various modifications can be made and implemented within the scope of the claims, the description of the invention, and the accompanying drawings, and it is natural that these also belong to the scope of the present invention.

Description of Reference Numerals

[0064] 100: Circuit board 110: Insulating layer 110a: First surface 110b: Second surface 121: First connection pad 122: First circuit wiring 125: Second connection pad 126: Second circuit wiring 131: First protective layer 135: Second protective layer 141: First conductive layer 145: Second conductive layer

Claims

1. an insulating layer having opposing first and second surfaces; and a first connection pad having a first portion embedded in the insulating layer and at least a portion exposed from the insulating layer at the first surface, and a second portion closer to the second surface than the first portion; Including, A circuit board, wherein a first width of the first portion and a second width of the second portion are different from each other in a width direction parallel to the first surface.

2. The circuit board of claim 1 , wherein the first width is greater than the second width.

3. The circuit board according to claim 1 , wherein the first portion and the second portion are configured to have a step.

4. The circuit board of claim 1 , further comprising a protective layer disposed on the first surface of the insulating layer and having an opening to expose the first connection pad.

5. a first circuit wiring embedded in the insulating layer and covered with the protective layer; The circuit board according to claim 4 , wherein the thickness of the first circuit wiring is greater than the thickness of the first portion of the first connection pad in a direction perpendicular to the first surface.

6. The circuit board of claim 1 , further comprising a conductive layer disposed over the first connection pad.

7. The circuit board of claim 6 , wherein the conductive layer is disposed on an exposed portion of the first connection pad.

8. The circuit board according to claim 6 , wherein the conductive layer protrudes from the first surface of the insulating layer.

9. 7. The circuit board of claim 6, wherein a width of the conductive layer in a direction parallel to the first surface is greater than the second width of the second portion of the first connection pad.

10. The circuit board according to claim 6 , wherein the conductive layer includes a gold (Au) plating layer.

11. The circuit board of claim 1 , wherein the first connection pad comprises copper (Cu).

12. The circuit board of claim 1 , wherein the first connection pad is located in a bond finger area.

13. The circuit board of claim 1 , further comprising a second connection pad disposed on the second surface of the insulating layer.

14. The insulating layer includes a plurality of insulating layers, The circuit board of claim 1 , wherein the plurality of insulating layers comprises a plurality of circuit layers.

15. forming a first portion of a first connection pad with a first metal on the seed layer; patterning the plating resist covering the first portion and plating the first metal to form a second portion of the first connection pad on the first portion, the second portion having a width different from that of the first portion; and An insulating layer is formed to cover the first portion and the second portion. A method for manufacturing a circuit board, comprising:

16. The method of claim 15 , wherein the first width of the first portion is greater than the second width of the second portion.

17. The method for manufacturing a circuit board according to claim 15 , further comprising removing the seed layer such that at least a portion of the first portion is exposed from the insulating layer.

18. The method for manufacturing a circuit board according to claim 15 , further comprising forming a conductive layer on the first portion exposed from the insulating layer.

19. The method for manufacturing a circuit board according to claim 18 , further comprising forming a protective layer on the insulating layer such that the conductive layer is exposed.

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