Wiring board and method of manufacturing wiring board

Abstract

To provide a wiring board capable of suppressing occurrence of a short-circuiting defect between adjacent wiring layers.SOLUTION: A wiring board 10 comprises a core substrate 20, an insulation layer 31 which is formed on a top face of the core substrate 20 so as to cover a wiring layer 22, a via hole 31X which penetrates the insulation layer 31 in a thickness direction and exposes a top face of the wiring layer 22, and a recess 31Y which is formed on a top face of the insulation layer 31. The wiring board 10 includes a via wire 41 which fills the via hole 31X and is electrically connected with the wiring layer 22, and a conductive layer 42 which fills the recess 31Y. The wiring board 10 comprises a wiring layer 32 which is electrically connected with the wiring layer 22 via the via wire 41 and formed on the top face of the insulation layer 31. The recess 31Y is formed so as not to penetrate the insulation layer 31 in the thickness direction. The recess 31Y is provided around the via hole 31X away from the via hole 31X, and provided so as to overlap the wiring layer 32 in a planar view.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a wiring board and a method for manufacturing a wiring board. [Background technology]

[0002] Conventionally, wiring boards for mounting electronic components such as semiconductor elements have been known in various shapes and structures. Known examples of this type of wiring board include a wiring board in which multiple wiring layers and multiple insulating layers are alternately stacked by a build-up method (see, for example, Patent Document 1). The multiple wiring layers are electrically connected to each other through via wirings formed in via holes that penetrate the insulating layers in the thickness direction. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2021-168348 Summary of the Invention [Problem to be solved by the invention]

[0004] In the above-mentioned wiring board, it is desirable to suppress the occurrence of short circuits between adjacent wiring layers. [Means for solving the problem]

[0005] According to one aspect of the present invention, a semiconductor device includes a first insulating layer, a first wiring layer formed on an upper surface of the first insulating layer, a second insulating layer formed on the upper surface of the first insulating layer so as to cover the first wiring layer, a via hole penetrating the second insulating layer in a thickness direction and exposing an upper surface of the first wiring layer, a recess formed on the upper surface of the second insulating layer, a via wiring filling the via hole and electrically connected to the first wiring layer, a conductive layer filling the recess, and a second wiring layer electrically connected to the first wiring layer via the via wiring and formed on the upper surface of the second insulating layer, wherein the recess is formed so as not to penetrate the second insulating layer in a thickness direction, and the recess is provided around the via hole at a distance from the via hole and is provided so as to overlap the second wiring layer in a planar view. [Effects of the Invention]

[0006] According to one aspect of the present invention, it is possible to suppress the occurrence of short-circuit defects between adjacent wiring layers. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic cross-sectional view (cross-sectional view taken along line 1-1 in FIG. 3) showing a wiring board according to one embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view showing an enlarged portion of the wiring board according to the embodiment. [Figure 3] FIG. 3 is a schematic cross-sectional view (cross-sectional view taken along line 3-3 in FIG. 2) showing a part of the wiring board according to one embodiment. [Figure 4] FIG. 4 is a schematic cross-sectional view (cross-sectional view taken along line 4-4 in FIG. 3) showing a part of the wiring board according to one embodiment. [Figure 5] FIG. 5 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 6] FIG. 6 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 7]FIG. 7(a) is a schematic plan view showing a method for manufacturing a wiring board according to one embodiment, and FIG. 7(b) is a schematic cross-sectional view (cross-sectional view taken along line 7b-7b in FIG. 7(a)) showing a method for manufacturing a wiring board according to one embodiment. [Figure 8] FIG. 8(a) is a schematic plan view showing a method for manufacturing a wiring board according to one embodiment, and FIG. 8(b) is a schematic cross-sectional view (cross-sectional view taken along line 8b-8b in FIG. 8(a)) showing a method for manufacturing a wiring board according to one embodiment. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 13] FIG. 13(a) is a schematic plan view showing a method for manufacturing a wiring board according to one embodiment, and FIG. 13(b) is a schematic cross-sectional view (cross-sectional view taken along line 13b-13b in FIG. 13(a)) showing a method for manufacturing a wiring board according to one embodiment. [Figure 14] FIG. 14(a) is a schematic plan view showing a method for manufacturing a wiring board according to one embodiment, and FIG. 14(b) is a schematic cross-sectional view (cross-sectional view taken along line 14b-14b in FIG. 14(a)) showing a method for manufacturing a wiring board according to one embodiment. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a method for manufacturing a wiring board according to an embodiment. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a wiring board according to a modified example. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a wiring board according to a modified example. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a wiring board according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0008] An embodiment will be described below with reference to the accompanying drawings. For convenience, the accompanying drawings may show characteristic portions enlarged to make the features easier to understand, and the dimensional ratios of each component may differ from one drawing to another. In addition, in the cross-sectional views, some components are hatched with a matte finish to make the cross-sectional structure of each component easier to understand, and some components are not hatched at all. In the plan views, some components are hatched to make the planar shape of each component easier to understand. Each drawing illustrates mutually orthogonal X-, Y-, and Z-axes. Each drawing illustrates a first direction X1, which is one direction in the X-axis direction along the X-axis, and a first opposite direction X2, which is the opposite direction of the first direction X1. Each drawing illustrates a second direction Y1, which is one direction in the Y-axis direction along the Y-axis, and a second opposite direction Y2, which is the opposite direction of the second direction Y1. Each drawing illustrates a third direction Z1, which is one direction in the Z-axis direction along the Z-axis, and a third opposite direction Z2, which is the opposite direction of the third direction Z1. In this specification, unless otherwise specified, "planar view" refers to viewing an object from the Z-axis direction. In this specification, unless otherwise specified, "planar shape" refers to the shape of an object viewed from the Z-axis direction. In this specification, "facing" refers to surfaces or components facing each other, and includes not only cases where they are completely facing each other, but also cases where they are partially facing each other. In this specification, "facing" refers not only to cases where two components are separated from each other, but also to cases where two components are in contact with each other.

[0009] (Overall configuration of wiring board 10) As shown in FIG. 1, wiring board 10 includes core substrate 20, wiring structure 30 laminated on the upper surface of core substrate 20, and wiring structure 50 laminated on the lower surface of core substrate 20. Wiring structure 30 is laminated on the upper surface of core substrate 20, and wiring structure 50 is laminated on the lower surface of core substrate 20.

[0010] The core substrate 20 may be, for example, a so-called glass epoxy substrate, which is made by impregnating a glass cloth (woven glass fabric) serving as a reinforcing material with a thermosetting resin containing epoxy resin as the main component and hardening the resin.

[0011] A plurality of through holes 20X are formed in the core substrate 20, penetrating the core substrate 20 in the thickness direction. A through electrode 21 is formed in each through hole 20X, penetrating the core substrate 20 in the thickness direction.

[0012] A wiring layer 22 is formed on the upper surface of the core substrate 20. A wiring layer 23 is formed on the lower surface of the core substrate 20. The wiring layers 22 and 23 are electrically connected to each other via through electrodes 21. The through electrodes 21 and the wiring layers 22 and 23 may be made of, for example, copper (Cu) or a copper alloy. The thickness of the wiring layers 22 and 23 may be, for example, about 5 μm to 20 μm.

[0013] The wiring structure 30 has a structure in which an insulating layer 31, a wiring layer 32, an insulating layer 33, a wiring layer 34, and a solder resist layer 35 are laminated in this order on the upper surface of the core substrate 20. The insulating layers 31 and 33 may be made of, for example, a thermosetting insulating resin. Examples of the thermosetting insulating resin include epoxy resin, polyimide resin, and cyanate resin. The insulating layers 31 and 33 may contain a filler such as silica or alumina. The thickness of each of the insulating layers 31 and 33 may be, for example, approximately 10 μm to 30 μm. The wiring layers 32 and 34 may be made of, for example, copper or a copper alloy. The thickness of each of the wiring layers 32 and 34 may be, for example, approximately 5 μm to 20 μm. The solder resist layer 35 may be made of, for example, an insulating resin whose main component is a photosensitive resin such as a phenolic resin or a polyimide resin. The solder resist layer 35 may contain a filler such as silica, alumina, etc. The thickness of the solder resist layer 35 may be set to, for example, about 10 μm to 30 μm.

[0014] The insulating layer 31 is laminated on the upper surface of the core substrate 20 so as to cover the wiring layer 22. The insulating layer 31 has a plurality of via holes 31X formed therein, which penetrate the insulating layer 31 in the thickness direction and expose the upper surface of the wiring layer 22. The insulating layer 31 has a plurality of recesses 31Y formed therein, which are recessed from the upper surface of the insulating layer 31 toward the core substrate 20 (i.e., toward the third opposite direction Z2).

[0015] The wiring layer 32 is laminated on the upper surface of the insulating layer 31. The wiring layer 32 is formed integrally with via wiring 41 formed in the via hole 31X, and is electrically connected to the wiring layer 22 through the via wiring 41. The wiring layer 32 is formed integrally with a conductive layer 42 formed in the recess 31Y. The wiring layer 32 has, for example, a pad 32P. The pad 32P is formed to overlap the via hole 31X and the recess 31Y in a planar view. Here, the via wiring 41 is formed to fill the via hole 31X. The conductive layer 42 is formed to fill the recess 31Y. The conductive layer 42 is electrically connected to the wiring layer 32 and is also electrically connected to the via wiring 41 through the wiring layer 32.

[0016] The insulating layer 33 is laminated on the upper surface of the insulating layer 31 so as to cover the wiring layer 32. A plurality of via holes 33X are formed in the insulating layer 33 so as to penetrate the insulating layer 33 in the thickness direction and expose the upper surface of the wiring layer 32. The via holes 33X are formed so as to expose part of the upper surface of the pad 32P of the wiring layer 32.

[0017] The wiring layer 34 is laminated on the upper surface of the insulating layer 33. The wiring layer 34 is formed integrally with a via wiring formed in the via hole 33X, and is electrically connected to the wiring layer 32 through the via wiring.

[0018] A solder resist layer 35 that covers the wiring layer 34 is laminated on the upper surface of the insulating layer 33. The solder resist layer 35 is the outermost insulating layer of the wiring board 10 (here, the uppermost layer).

[0019] The solder resist layer 35 has a plurality of openings 35X formed therein to expose portions of the upper surface of the wiring layer 34 as connection pads P1. The connection pads P1 are pads for connecting to electronic components such as semiconductor elements, for example.

[0020] A surface treatment layer is formed, if necessary, on the upper surface of the wiring layer 34 exposed at the bottom of the opening 35X. Examples of the surface treatment layer include a gold (Au) layer, a nickel (Ni) layer / Au layer (a metal layer formed by laminating a Ni layer and an Au layer in this order), and a Ni layer / palladium (Pd) layer / Au layer (a metal layer formed by laminating a Ni layer, a Pd layer, and an Au layer in this order). Other examples of the surface treatment layer include a Ni layer / Pd layer (a metal layer formed by laminating a Ni layer and a Pd layer in this order) and a Pd / Au layer (a metal layer formed by laminating a Pd layer and an Au layer in this order). Here, the Au layer is a metal layer made of Au or an Au alloy, the Ni layer is a metal layer made of Ni or an Ni alloy, and the Pd layer is a metal layer made of Pd or a Pd alloy. The Au layer, Ni layer, and Pd layer may be, for example, a metal layer formed by electroless plating (electroless plated layer) or a metal layer formed by electrolytic plating (electroplated layer). Alternatively, the surface treatment layer may be an OSP (Organic Solderability Preservative) film formed by applying an anti-oxidation treatment such as an OSP treatment to the upper surface of the wiring layer 34. The OSP film may be, for example, an organic coating of an azole compound, an imidazole compound, or the like. When a surface treatment layer is formed on the upper surface of the wiring layer 34, the surface treatment layer functions as the connection pad P1.

[0021] The wiring structure 50 has a structure in which an insulating layer 51, a wiring layer 52, an insulating layer 53, a wiring layer 54, and a solder resist layer 55 are laminated in this order on the lower surface of the core substrate 20. The insulating layers 51 and 53 may be made of, for example, a thermosetting insulating resin. Examples of the thermosetting insulating resin include epoxy resin, polyimide resin, and cyanate resin. The insulating layers 51 and 53 may contain a filler such as silica or alumina. The thickness of each of the insulating layers 51 and 53 may be, for example, approximately 10 μm to 30 μm. The wiring layers 52 and 54 may be made of, for example, copper or a copper alloy. The thickness of each of the wiring layers 52 and 54 may be, for example, approximately 5 μm to 20 μm. The solder resist layer 55 may be made of, for example, an insulating resin whose main component is a photosensitive resin such as a phenolic resin or a polyimide resin. The solder resist layer 55 may contain a filler such as silica, alumina, etc. The thickness of the solder resist layer 55 may be, for example, about 10 μm to 30 μm.

[0022] The insulating layer 51 is laminated on the lower surface of the core substrate 20 so as to cover the wiring layer 23. A plurality of via holes 51X are formed in the insulating layer 51, penetrating the insulating layer 51 in the thickness direction to expose the lower surface of the wiring layer 23. A plurality of recesses 51Y are formed in the insulating layer 51, recessing from the lower surface of the insulating layer 51 toward the core substrate 20 (i.e., toward the third direction Z1). The via holes 51X are formed in the same structure as the via holes 31X, and the recesses 51Y are formed in the same structure as the recesses 31Y.

[0023] The wiring layer 52 is laminated on the lower surface of the insulating layer 51. The wiring layer 52 is formed integrally with via wiring 61 formed in the via hole 51X, and is electrically connected to the wiring layer 23 through the via wiring 61. The wiring layer 52 is formed integrally with a conductive layer 62 formed in the recess 51Y. The wiring layer 52 has, for example, a pad 52P. The pad 52P is formed to overlap the via hole 51X and the recess 51Y in a planar view. Here, the via wiring 61 is formed to fill the via hole 51X. The conductive layer 62 is formed to fill the recess 51Y. The conductive layer 62 is electrically connected to the wiring layer 52 and is also electrically connected to the via wiring 61 through the wiring layer 52.

[0024] The insulating layer 53 is laminated on the lower surface of the insulating layer 51 so as to cover the wiring layer 52. A plurality of via holes 53X are formed in the insulating layer 53 so as to penetrate the insulating layer 53 in the thickness direction and expose the lower surface of the wiring layer 52. The via holes 53X are formed so as to expose part of the lower surface of the pads 52P of the wiring layer 52.

[0025] The wiring layer 54 is laminated on the lower surface of the insulating layer 53. The wiring layer 54 is formed integrally with a via wiring formed in the via hole 53X, and is electrically connected to the wiring layer 52 through the via wiring.

[0026] A solder resist layer 55 that covers the wiring layer 54 is laminated on the lower surface of the insulating layer 53. The solder resist layer 55 is the outermost insulating layer of the wiring board 10 (here, the bottom layer).

[0027] A plurality of openings 55X are formed in the solder resist layer 55 to expose portions of the lower surface of the wiring layer 54 as external connection pads P2. External connection terminals (not shown) used when mounting the wiring board 10 on a mounting board such as a motherboard are connected to the external connection pads P2.

[0028] If necessary, a surface treatment layer is formed on the lower surface of the wiring layer 54 exposed at the bottom of the opening 55X. Examples of the surface treatment layer include a metal layer such as an Au layer, a Ni layer / Au layer, a Ni layer / Pd layer / Au layer, a Ni layer / Pd layer, or a Pd layer / Au layer, and an OSP film.

[0029] In this example, an external connection terminal is provided on the underside of the wiring layer 54, but the wiring layer 54 itself exposed at the bottom of the opening 55X, or if a surface treatment layer is formed on the underside of the wiring layer 54, the surface treatment layer itself may also be used as the external connection terminal.

[0030] Next, the structures of the via hole 31X, the recess 31Y, the via wiring 41, the conductive layer 42, and the wiring layer 32 will be described with reference to Figures 2 to 4. Note that Figures 2 to 4 omit illustration of the structure above the wiring layer 32, specifically the insulating layer 33, the wiring layer 34, and the solder resist layer 35.

[0031] (Structure of via hole 31X) 2, the via hole 31X is formed so as to expose a portion of the upper surface of the wiring layer 22. The via hole 31X is formed in a tapered shape such that the opening width (opening diameter) decreases from the upper side (i.e., the third direction Z1 side) to the lower side (i.e., the third opposite direction Z2 side) in FIG. 2. The inner wall surface of the via hole 31X is formed, for example, to be inclined so as to approach the center of the plane of the via hole 31X from the upper surface of the insulating layer 31 toward the wiring layer 22. Note that the inner wall surface of the via hole 31X does not need to be flat, and a portion or all of the inner wall surface of the via hole 31X may be a convexly curved surface or a concavely curved surface.

[0032] 3, the via hole 31X has a planar shape, for example, a circular shape. The planar shape of the via hole 31X is not limited to a circular shape and can be any shape. The via hole 31X is provided so as to overlap the pad 32P of the wiring layer 32 in a planar view. The planar size of the via hole 31X is smaller than the planar size of the pad 32P. The via hole 31X is provided, for example, at the planar center of the pad 32P.

[0033] (Structure of recess 31Y) As shown in FIG. 2, the recess 31Y is formed so as not to penetrate the insulating layer 31 in the thickness direction. In other words, the bottom surface of the recess 31Y is provided at a central position in the thickness direction of the insulating layer 31. The recess 31Y is formed shallower than the via hole 31X. The recess 31Y is formed in a tapered shape such that the opening width (opening diameter) decreases from the upper side (i.e., the third direction Z1 side) to the lower side (i.e., the third opposite direction Z2 side) in FIG. 2. The inner wall surface of the recess 31Y is formed, for example, to be inclined so as to approach the center of the plane of the recess 31Y as it moves from the upper surface of the insulating layer 31 toward the core substrate 20. Note that the inner wall surface of the recess 31Y does not need to be flat, and a part or all of the inner wall surface of the recess 31Y may be a convexly curved surface or a concavely curved surface.

[0034] As shown in FIGS. 2 and 3, each of the plurality of recesses 31Y is provided corresponding to each of the plurality of via holes 31X. As shown in FIG. 3, in this embodiment, one recess 31Y is provided for one via hole 31X. Each recess 31Y is provided around the corresponding via hole 31X. Each recess 31Y is provided in a position close to the corresponding via hole 31X. Each recess 31Y is provided at a distance from the corresponding via hole 31X. Each recess 31Y is provided at a position overlapping, in plan view, with the wiring layer 32 that is provided so as to overlap, in plan view, with the corresponding via hole 31X. In other words, the via hole 31X and the recess 31Y provided corresponding to that via hole 31X are provided so as to overlap, in plan view, with the common wiring layer 32.

[0035] Each recess 31Y is provided at a position spaced apart from the corresponding via hole 31X in the first direction X1. The recesses 31Y are provided spaced apart from the corresponding via hole 31X in a fixed direction (here, the first direction X1). That is, the recesses 31Y are all spaced apart from the via hole 31X in the same direction, here, the first direction X1.

[0036] Each recess 31Y extends, for example, in a second direction Y1 perpendicular to the first direction X1. The dimension of each recess 31Y along the second direction Y1 is, for example, equal to or greater than the dimension of the via hole 31X along the second direction Y1. For example, the dimension of each recess 31Y along the second direction Y1 is equal to or greater than the diameter of the via hole 31X. Each recess 31Y is formed to face only a portion of the outer periphery of the via hole 31X in a plan view. Each recess 31Y is formed to face continuously with the outer periphery of the via hole 31X in a plan view. Each recess 31Y is formed to face continuously with half the circumference of the outer periphery of the via hole 31X, for example. Here, in this specification, the term "half circumference" does not only refer to the periphery of a semicircle obtained by dividing a circle into two equal parts, but also includes, for example, a circular arc longer or shorter than the periphery of a semicircle obtained by dividing a circle into two equal parts. The planar shape of each recess 31Y is formed in an arc shape that follows the outer periphery of the via hole 31X as a whole. The planar shape of each recess 31Y is formed as a semicircular arc along the outer periphery of the via hole 31X as a whole. The length direction of each recess 31Y coincides with, for example, the circumferential direction of the via hole 31X.

[0037] The outer edge shape of each recess 31Y is formed, for example, in a shape having a plurality of projections and recesses in a plan view. The outer edge shape of each recess 31Y has a plurality of projections A1 and a plurality of recesses A2. The outer edge shape of each recess 31Y is formed by a plurality of projections A1 and a plurality of recesses A2 arranged alternately one by one. The outer edge shape of each projection A1 and the outer edge shape of each recess A2 are formed in a curved shape that is curved like an arc in a plan view. In other words, the outer edge shape of each recess 31Y is formed only in a curved shape in a plan view. Specifically, the outer edge shape of each recess 31Y is formed by a plurality of curved shapes that are continuously connected in a plan view.

[0038] As shown in Fig. 4, the bottom surface of each recess 31Y is formed into a shape having a plurality of projections and recesses in a cross-sectional view. Fig. 4 is a cross-sectional view of each recess 31Y taken along the length direction of the recess 31Y. Note that Fig. 4 does not show a metal film 43, which will be described later.

[0039] Each recess 31Y has a first recess B1 and a second recess B2 that is shallower than the first recess B1. In each recess 31Y, the first recess B1 and the second recess B2 are formed continuously. The bottom surface of the first recess B1 is located closer to the core substrate 20 than the bottom surface of the second recess B2. In other words, the bottom surface of the first recess B1 is located closer to the third opposite direction Z2 than the bottom surface of the second recess B2. The bottom surface of each recess 31Y is uneven due to, for example, a step between the bottom surface of the first recess B1 and the bottom surface of the second recess B2.

[0040] (Structure of via wiring 41) 2, the via wiring 41 is formed to fill the via hole 31X. Therefore, the via wiring 41 has the same shape as the via hole 31X. The via wiring 41 has, for example, a metal film 43 that covers the entire inner surface of the via hole 31X, and a metal layer 44 that fills the via hole 31X on the inner side of the metal film 43.

[0041] The metal film 43 is formed, for example, so as to cover the entire inner wall surface of the via hole 31X and the entire upper surface of the wiring layer 22 exposed from the via hole 31X. The metal film 43 is, for example, a seed layer. The material of the metal film 43 can be, for example, copper or a copper alloy. The metal film 43 can be, for example, a metal film formed by electroless plating, i.e., an electroless plated film. The metal film 43 can also be, for example, a metal film formed by sputtering, i.e., a sputtered film. The thickness of the metal film 43 can be, for example, approximately 0.3 μm to 2 μm.

[0042] The metal layer 44 is formed, for example, so as to fill the via hole 31X located on the inner side of the metal film 43. For example, copper or a copper alloy can be used as the material of the metal layer 44. For example, a metal layer formed by electrolytic plating, that is, an electrolytic plated layer can be used as the metal layer 44.

[0043] The via wiring 41 is configured by the metal film 43 and the metal layer 44 formed in the via hole 31X described above. (Structure of conductive layer 42) The conductive layer 42 is formed to fill the recess 31Y. Therefore, the conductive layer 42 has the same shape as the recess 31Y. The conductive layer 42 has, for example, a metal film 43 that covers the entire inner surface of the recess 31Y, and a metal layer 45 that fills the recess 31Y on the inner side of the metal film 43. The metal film 43 is formed, for example, to cover the entire inner wall surface and the entire bottom surface of the recess 31Y.

[0044] The metal layer 45 is formed, for example, so as to fill the recess 31Y located inside the metal film 43. For example, copper or a copper alloy can be used as the material of the metal layer 45. For example, an electroplated layer can be used as the metal layer 45.

[0045] The conductive layer 42 is composed of the metal film 43 and the metal layer 45 formed in the recess 31Y as described above. (Structure of wiring layer 32) The wiring layer 32 is formed on the insulating layer 31, the via wiring 41, and the conductive layer 42. The wiring layer 32 has, for example, a metal film 43 and a metal layer 46 formed on the metal film 43.

[0046] The metal film 43 is formed so as to cover the upper surface of the insulating layer 31 located around the via hole 31X. The metal film 43 is formed so as to cover the upper surface of the insulating layer 31 located around the recess 31Y. The metal film 43 is formed so as to cover the upper surface of the insulating layer 31 located between the via hole 31X and the recess 31Y. The metal film 43 of this embodiment is formed so as to continuously cover the upper surface of the insulating layer 31, the inner wall surface of the via hole 31X, the upper surface of the wiring layer 22 exposed from the via hole 31X, the inner wall surface of the recess 31Y, and the bottom surface of the recess 31Y.

[0047] The metal layer 46 is formed on the metal film 43 formed on the upper surface of the insulating layer 31, on the via wiring 41 (metal layer 44), and on the conductive layer 42 (metal layer 45). The metal layer 46 is formed continuously and integrally with the metal layer 44 and the metal layer 45. The metal layer 45 is formed integrally with the metal layer 44 through the metal layer 46. The material of the metal layer 46 can be, for example, copper or a copper alloy. The metal layer 46 can be, for example, an electroplated layer.

[0048] The wiring layer 32 is composed of the metal film 43 and the metal layer 46 formed on the upper surface of the insulating layer 31 described above. For example, recesses 32X and 32Y are formed on the upper surface of the wiring layer 32. The recesses 32X and 32Y are formed so as to recess from the upper surface of the wiring layer 32 toward the core substrate 20. The recess 32X is provided, for example, at a position overlapping with the via hole 31X in a planar view. The inner surface of the recess 32X is formed, for example, as a curved surface curved in an arc shape. The recess 32Y is provided, for example, at a position overlapping with the recess 31Y in a planar view. The inner surface of the recess 32Y is formed, for example, as a curved surface curved in an arc shape.

[0049] The wiring board 10 can be used upside down or placed at any angle. (Method of manufacturing wiring board 10) Next, a method for manufacturing the wiring board 10 will be described with reference to Figures 5 to 15. Here, a detailed description will be given of the manufacturing methods of the insulating layer 31, the via holes 31X, the recesses 31Y, the via wiring 41, the conductive layer 42, and the wiring layer 32. For ease of explanation, the parts that will ultimately become the components of the wiring board 10 will be described using the reference numerals of the final components.

[0050] 5, a structure is prepared in which a wiring layer 22 is formed on the upper surface of a core substrate 20. This structure can be manufactured by a known manufacturing method, and therefore a detailed description thereof will be omitted here.

[0051] Next, in the step shown in FIG. 6 , an insulating layer 31 is formed on the upper surface of the core substrate 20 so as to entirely cover the wiring layer 22. For example, when an insulating resin film is used as the insulating layer 31, the insulating resin film is laminated on the upper surface of the core substrate 20. Then, the insulating resin film is pressed and heat-treated at a temperature equal to or higher than the curing temperature (for example, about 130°C to 200°C) to harden it, thereby forming the insulating layer 31. Note that, as the insulating resin film, for example, a film of a thermosetting resin containing an epoxy resin as a main component can be used. Also, when a liquid or paste insulating resin is used as the insulating layer 31, the liquid or paste insulating resin is applied to the upper surface of the core substrate 20 by a spin coating method or the like. Then, the applied insulating resin is hardened by heat-treating it at a temperature equal to or higher than the curing temperature, thereby forming the insulating layer 31. Note that, as the liquid or paste insulating resin, for example, a thermosetting resin containing an epoxy resin as a main component can be used.

[0052] 7(a) and 7(b), a via hole 31X is formed in the insulating layer 31, exposing a portion of the upper surface of the wiring layer 22. The via hole 31X can be formed, for example, by irradiating the insulating layer 31 with laser light. That is, the via hole 31X can be formed by a laser processing method. A CO2 laser or a UV-YAG laser can be used as a laser light source used for irradiating the laser light.

[0053] Here, the intensity (energy) of the laser light irradiated onto the insulating layer 31 is set to a value sufficient to form a via hole 31X of a desired opening diameter in one shot, i.e., one irradiation. For example, when forming a via hole 31X in an insulating layer 31 containing an inorganic filler, the insulating layer 31 not containing an inorganic filler is irradiated multiple times (e.g., three or more times) with laser light having energy sufficient to form the via hole 31X. The total energy of such multiple laser beams is used as the energy of one irradiation.

[0054] By irradiating the insulating layer 31 with such laser light, a via hole 31X is formed that penetrates the insulating layer 31 in the thickness direction and exposes a part of the upper surface of the wiring layer 22. Next, in the process shown in FIGS. 8(a) and 8(b), a recess 31Y is formed around the via hole 31X in the insulating layer 31, recessed from the upper surface of the insulating layer 31 toward the core substrate 20. The recess 31Y is provided at a position away from the via hole 31X in the first direction X1. The depth of the recess 31Y is formed to be shallower than the depth of the via hole 31X. The recess 31Y can be formed, for example, by laser processing. For example, a CO2 laser or a UV-YAG laser can be used as a laser light source in the laser processing.

[0055] As shown in FIG. 8(a), the recess 31Y extends, for example, along a longitudinal direction extending parallel to the circumferential direction of the via hole 31X. Such a recess 31Y can be formed, for example, by sequentially performing laser processing along the longitudinal direction of the recess 31Y so that each laser shot partially overlaps. As a result, portions of multiple shots are connected to form a single recess 31Y. At this time, multiple uneven portions are formed on the outer edge shape of the recess 31Y, and multiple uneven portions are formed on the bottom surface of the recess 31Y. Note that, in the laser processing method used to form the recess 31Y, for example, a laser power is set to be smaller than the laser power used to form one via hole 31X.

[0056] The via hole 31X and the recess 31Y may be formed simultaneously by adjusting the laser irradiation conditions in the laser processing method. Subsequently, in the case where the via holes 31X are formed by laser processing, a desmearing process is carried out to remove resin smears adhering to the exposed surfaces of the wiring layer 22 exposed from the via holes 31X.

[0057] Next, in the step shown in FIG. 9 , a metal film 43 is formed to continuously cover the upper surface of the insulating layer 31, the inner surfaces of the via holes 31X, and the inner surfaces of the recesses 31Y. The metal film 43 is formed to continuously cover the entire upper surface of the insulating layer 31, the entire inner wall surfaces of the via holes 31X, the entire upper surface of the wiring layer 22 exposed from the via holes 31X, the entire inner wall surfaces of the recesses 31Y, and the entire bottom surface of the recesses 31Y. The metal film 43 can be formed, for example, by electroless plating. For example, the metal film 43 can be formed by electroless copper plating using a plating solution containing a mixture of copper sulfate, sodium hydroxide, a carboxylate, nickel sulfate, and formaldehyde. The metal film 43 can also be formed, for example, by sputtering or vapor deposition.

[0058] 10, a resist layer 70 is formed on the metal film 43. The resist layer 70 is formed so as to cover the entire upper surface of the metal film 43. The resist layer 70 is formed, for example, so that the portions overlapping with the via holes 31X in a planar view hang down. The resist layer 70 is formed, for example, so that the portions overlapping with the recesses 31Y in a planar view hang down. A photosensitive dry film resist can be used as the material for the resist layer 70. For example, a dry film resist such as a novolac resin or an acrylic resin can be used as the dry film resist. An example of a method for manufacturing the resist layer 70 will be described below.

[0059] 11, first, a resist layer 70, which is a dry film resist, is laminated on the upper surface of the metal film 43. At this time, voids 71 ​​(air bubbles) may occur in the resist layer 70. For example, in the example shown in FIG. 11, the voids 71 ​​occur in the portion that overlaps with the via hole 31X in a plan view.

[0060] Next, the resist layer 70 is heated and pressed by a roller 80 moving along the first direction X1. In this process, the heated roller 80 presses the resist layer 70 toward the metal film 43. This process is performed to improve the adhesion of the resist layer 70 to the metal film 43. However, if the above-mentioned voids 71 ​​are present, the voids 71 ​​may expand due to heating by the roller 80, and the expanded voids 71 ​​may be pushed out by the roller 80 in the first direction X1, which is the direction of movement of the roller 80. The pushed-out voids 71 ​​may cause the resist layer 70 to float from the metal film 43, that is, a cavity may be formed between the resist layer 70 and the metal film 43. In this case, if the cavity formed between the resist layer 70 and the metal film 43 spreads to an adjacent wiring formation region, a short circuit may occur between the via wiring 41 (see FIG. 2) filled in the via hole 31X and the adjacent wiring. That is, a cavity between the resist layer 70 and the metal film 43 may cause a short circuit between adjacent wiring layers.

[0061] In contrast to this, in this embodiment, the recess 31Y is provided around the via hole 31X, specifically at a position away from the via hole 31X in the first direction X1, which is the direction in which the roller 80 moves.

[0062] 12, when the voids 71 ​​are pushed out in the first direction X1 by the heated roller 80, the pushed-out voids 71 ​​can escape into the recessed portions 31Y. That is, the voids 71 ​​pushed out by the roller 80 can be trapped in the recessed portions 31Y. Therefore, the voids 71 ​​can be suitably prevented from spreading further in the first direction X1 than the recessed portions 31Y. As a result, the formation of voids between the resist layer 70 and the metal film 43 can be suitably prevented in the region closer to the first direction X1 than the recessed portions 31Y.

[0063] 13(a) and 13(b), an opening pattern 70X that exposes the via hole 31X and the recess 31Y is formed in the resist layer 70. As shown in FIG. 13(a), the opening pattern 70X is formed so as to overlap the entire via hole 31X in a planar view. The opening pattern 70X is formed so as to overlap the entire recess 31Y in a planar view. As shown in FIG. 13(b), the opening pattern 70X is formed so as to penetrate the resist layer 70 in the thickness direction. The opening pattern 70X can be formed, for example, by patterning the resist layer 70 using photolithography.

[0064] Next, in the step shown in FIG. 14(b), electrolytic plating is performed on the metal film 43 using the resist layer 70 as a plating mask, utilizing the metal film 43 as a plating power supply layer. That is, electrolytic plating (e.g., copper electrolytic plating) is performed on the upper surface of the metal film 43 exposed from the opening pattern 70X of the resist layer 70. This step forms a metal layer 44 filling the via hole 31X located inside the metal film 43, and a metal layer 45 filling the recess 31Y located inside the metal film 43. Furthermore, as shown in FIGS. 14(a) and 14(b), this step forms a metal layer 46 within the opening pattern 70X. At this time, as shown in FIG. 14(b), recesses 32X and 32Y, for example, are formed on the upper surface of the metal layer 46. Furthermore, the metal layer 46 is formed integrally and continuously with the metal layer 44 and the metal layer 45.

[0065] Next, in the step shown in FIG. 15, the resist layer 70 shown in FIGS. 14(a) and 14(b) is removed with an alkaline remover, such as an organic amine remover, caustic soda, acetone, or ethanol.

[0066] Next, the unnecessary metal film 43 is removed by etching using the metal layer 46 as an etching mask. Through the above manufacturing steps, via wiring 41 is formed, which is made up of metal film 43 and metal layer 44 formed in via hole 31X. Also, conductive layer 42 is formed, which is made up of metal film 43 and metal layer 45 formed in recess 31Y. Furthermore, wiring layer 32 is formed, which is made up of metal film 43 and metal layer 46 formed on insulating layer 31.

[0067] Next, the effects of this embodiment will be described. (1) The wiring board 10 includes a core substrate 20, a wiring layer 22 formed on the upper surface of the core substrate 20, and an insulating layer 31 formed on the upper surface of the core substrate 20 so as to cover the wiring layer 22. The wiring board 10 includes via holes 31X that penetrate the insulating layer 31 in the thickness direction and expose the upper surface of the wiring layer 22, and recesses 31Y formed on the upper surface of the insulating layer 31. The wiring board 10 includes via wirings 41 that fill the via holes 31X and are electrically connected to the wiring layer 22, and a conductive layer 42 that fills the recesses 31Y. The wiring board 10 includes a wiring layer 32 that is electrically connected to the wiring layer 22 through the via wirings 41 and is formed on the upper surface of the insulating layer 31. The recesses 31Y are formed so as not to penetrate the insulating layer 31 in the thickness direction. The recesses 31Y are provided around the via holes 31X and spaced apart from the via holes 31X, and are provided so as to overlap the wiring layer 32 in a plan view.

[0068] According to this configuration, the recess 31Y, which does not penetrate the insulating layer 31 in the thickness direction, i.e., the recess 31Y formed shallower than the via hole 31X, is provided around the via hole 31X and spaced apart from the via hole 31X. This prevents the void 71 from spreading to an adjacent wiring formation region, even if the void 71 occurs in the resist layer 70 formed on the metal film 43 during the manufacturing process of the wiring substrate 10, for example. Specifically, when the resist layer 70 is heated and pressurized by the roller 80 with the void 71 generated in the portion of the resist layer 70 overlapping the via hole 31X in a planar view, the void 71 pushed out in the planar direction by the roller 80 can be trapped by the recess 31Y. This effectively prevents the void 71 from spreading beyond the recess 31Y to an adjacent wiring formation region located outside the recess 31Y. Therefore, it is possible to suitably prevent short circuits from occurring between adjacent wiring layers due to voids formed between the resist layer 70 and the metal film 43 .

[0069] (2) Furthermore, since the recess 31Y is formed shallower than the via hole 31X, it is possible to suitably prevent the generation of voids 71 ​​in the portion of the resist layer 70 that overlaps with the recess 31Y in a plan view when the resist layer 70 is laminated on the metal film 43. In other words, it is possible to suitably prevent the recess 31Y from becoming a source of the voids 71.

[0070] (3) In a plan view, the recess 31Y is located at a distance from the via hole 31X in the first direction X1. With this configuration, for example, during the manufacturing process of the wiring substrate 10, the void 71 pushed out from the via hole 31X in the first direction X1 by the roller 80 moving along the first direction X1 can be trapped in the recess 31Y. This can effectively prevent the void 71 from spreading further in the first direction X1 than the recess 31Y. As a result, it can effectively prevent the cavity formed between the resist layer 70 and the metal film 43 from extending to an adjacent wiring formation region located further in the first direction X1 than the recess 31Y. This can effectively prevent short-circuit defects between adjacent wiring layers due to the cavity formed between the resist layer 70 and the metal film 43.

[0071] (4) The dimension of the recess 31Y along the second direction Y1 is equal to or greater than the diameter of the via hole 31X. With this configuration, the recess 31Y can be opposed to the via hole 31X over the entire length of the via hole 31X in the second direction Y1. This allows the voids 71 ​​extruded from the via hole 31X in the first direction X1 to be suitably trapped in the recess 31Y. As a result, the occurrence of short-circuit defects between adjacent wiring layers can be suitably suppressed.

[0072] (5) Incidentally, when recesses 31Y are formed so as to intermittently face the outer periphery of via hole 31X, there is a possibility that voids 71 ​​will spread further in the first direction X1 than recesses 31Y through portions where recesses 31Y are not formed. In contrast, in wiring board 10 of this embodiment, recesses 31Y are formed so as to continuously face the outer periphery of via hole 31X. This makes it possible to suitably prevent portions where recesses 31Y are not formed from being formed in regions closer to via hole 31X in the first direction X1 than via hole 31X and facing via hole 31X. Therefore, it is possible to suitably prevent voids 71 ​​from spreading further in the first direction X1 than recesses 31Y.

[0073] (6) Incidentally, the recess 31Y is formed shallower than the via hole 31X, and therefore is less likely to be a source of voids 71 ​​than the via hole 31X. However, compared to the solid portion of the resist layer 70 where the recess 31Y is not formed, the portion where the recess 31Y is formed is more likely to generate voids 71. Therefore, in the wiring board 10 of this embodiment, the recess 31Y is formed so as to face only a portion of the outer periphery of the via hole 31X. This configuration can reduce the area where the recess 31Y is formed. This can suitably suppress the likelihood of voids 71 ​​being generated due to the formation of the recess 31Y.

[0074] (7) The outer edge of the recess 31Y is formed into a shape having multiple projections and recesses in a plan view. This configuration increases the surface area of ​​the outer edge of the recess 31Y, thereby increasing the contact area between the inner wall surface of the recess 31Y and the outer surface of the conductive layer 42. This improves the adhesion between the insulating layer 31 and the conductive layer 42 that form the recess 31Y.

[0075] (8) The recess 31Y is formed so that the first recess B1 and the second recess B2, which are shallower than the first recess B1, are continuous. With this configuration, an uneven portion is formed on the bottom surface of the recess 31Y. This increases the surface area of ​​the bottom surface of the recess 31Y, thereby increasing the contact area between the bottom surface of the recess 31Y and the lower surface of the conductive layer 42. This improves the adhesion between the insulating layer 31 and the conductive layer 42 that form the recess 31Y.

[0076] (Example of change) The above embodiment can be modified as follows: The above embodiment and the following modifications can be combined with each other within the scope of technical compatibility.

[0077] The structure of the recess 31Y in the above embodiment can be modified as needed. 16, the outer edge shape of the recess 31Y may be changed to a shape without any irregularities. For example, the outer edge of the recess 31Y facing the via hole 31X is formed in an arc shape that follows the outer edge of the via hole 31X in a plan view.

[0078] 17, the planar shape of the recess 31Y may be modified to extend linearly along the second direction Y1. In this case, the length of the recess 31Y coincides with the second direction Y1. In this modification, the dimension of the recess 31Y along the second direction Y1 is preferably equal to or greater than the diameter of the via hole 31X.

[0079] For example, as shown in Fig. 18, the recess 31Y may be formed to face the via hole 31X along the entire circumferential circumference of the outer periphery of the via hole 31X in a plan view. In this case, the recess 31Y is formed to surround the entire circumferential circumference of the outer periphery of the via hole 31X in a plan view. The planar shape of the recess 31Y in this modification is, for example, an annular shape.

[0080] In the above embodiment, the bottom surface of the recess 31Y may be changed to a shape that does not have any irregularities. The inner wall surface of the recess 31Y in the above embodiment may be formed to extend perpendicularly to the upper surface of the insulating layer 31 in a cross-sectional view.

[0081] In the above embodiment, the recess 31Y is provided in the insulating layer 31, and the recess 51Y is provided in the insulating layer 51. However, the positions where the recesses 31Y and 51Y are formed are not limited to this. For example, the recess 31Y may be provided in the insulating layer 33. For example, the recess 51Y may be provided in the insulating layer 53. For example, the recess 51Y provided in the insulating layer 51 may be omitted.

[0082] In the above embodiment, a plurality of recesses 31Y, 51Y are provided in one insulating layer 31, 51. However, this is not limiting. For example, only one recess 31Y, 51Y may be provided in one insulating layer 31, 51.

[0083] In the above embodiment, the recesses 31Y are provided for all the via holes 31X, but this is not limitative. For example, the recesses 31Y may be provided for only some of the via holes 31X.

[0084] The planar shape of the via hole 31X in the above embodiment can be changed as appropriate. The inner wall surface of the via hole 31X in the above embodiment may be formed to extend perpendicularly to the upper surface of the insulating layer 31 in a cross-sectional view.

[0085] The structure of the wiring layer 32 in the above embodiment can be modified as appropriate. For example, at least one of the recesses 32X and 32Y may be omitted. In the above embodiment, the metal film 43 is embodied as a seed layer having a single layer structure, but the metal film 43 may be embodied as a seed layer having a multi-layer structure (for example, a two-layer structure). An example of a seed layer having a two-layer structure is a seed layer having a structure in which a titanium (Ti) layer and a Cu layer are stacked in this order.

[0086] In the method for manufacturing the wiring board 10 according to the above embodiment, the via holes 31X are formed by laser processing, but the present invention is not limited to this. For example, the via holes 31X may be formed by a method other than laser processing.

[0087] In the method for manufacturing the wiring board 10 according to the above embodiment, the recess 31Y is formed by laser processing, but this is not limiting. For example, the recess 31Y may be formed by a method other than laser processing.

[0088] The structure of the wiring board 10 of the above embodiment can be modified as needed. For example, the number of wiring layers 32, 34 and insulating layers 31, 33 in the wiring structure 30, the wiring layout, and the like can be modified or changed in various ways. For example, the number of wiring layers 52, 54 and insulating layers 51, 53 in the wiring structure 50, the wiring layout, and the like can be modified or changed in various ways. For example, the wiring board 10 may be changed to a coreless board that does not have a core substrate 20. In this case, for example, a first insulating layer is formed below the insulating layer 31, instead of the core substrate 20.

[0089] The solder resist layers 35 and 55 in the above embodiment may be omitted. The wiring board 10 of the above embodiment may be embodied as a wiring board used in a package such as a CSP (Chip Size Package) or a SON (Small Outline Non-Lead Package). [Explanation of symbols]

[0090] 10. Wiring board 20 Core substrate (first insulating layer) 22 Wiring layer (1st wiring layer) 31 Insulating layer (second insulating layer) 31X Via Hole 31Y Recess 32 Wiring layer (2nd wiring layer) 32P Pad 41 Via wiring 42 Conductive layer 43 Metal Film 44 Metal layer (first metal layer) 45 Metal layer (second metal layer) 46 Metal layer (third metal layer) 70 resist layer 70X aperture pattern 71 Void 80 Laura A1 convex part A2 recess B1 First recess B2 Second recess X1 1st direction Y1 2nd direction

Claims

1. a first insulating layer; a first wiring layer formed on an upper surface of the first insulating layer; a second insulating layer formed on the upper surface of the first insulating layer so as to cover the first wiring layer; a via hole that penetrates the second insulating layer in a thickness direction and exposes an upper surface of the first wiring layer; a recess formed on an upper surface of the second insulating layer; a via wiring that fills the via hole and is electrically connected to the first wiring layer; a conductive layer filling the recess; a second wiring layer electrically connected to the first wiring layer through the via wiring and formed on the upper surface of the second insulating layer; the recess is formed so as not to penetrate the second insulating layer in a thickness direction, The recess is provided around the via hole at a distance from the via hole and is provided so as to overlap the second wiring layer in a plan view.

2. the recess is provided at a position spaced apart from the via hole in a first direction in a plan view, The wiring board according to claim 1 , wherein a dimension of the recess along a second direction perpendicular to the first direction is equal to or greater than a dimension of the via hole along the second direction.

3. the wiring substrate has a plurality of the via holes and a plurality of the recesses, each of the plurality of recesses is provided corresponding to each of the plurality of via holes; The wiring board according to claim 2 , wherein each of the plurality of recesses is provided at a position spaced apart from the corresponding via hole in the first direction.

4. The via hole has a circular planar shape, a dimension of the recess along the second direction is equal to or greater than a diameter of the via hole; the recess is formed so as to be continuously opposed to the outer periphery of the via hole in a plan view, The wiring board according to claim 2 , wherein the recess is formed in an arc shape along an outer periphery of the via hole in a plan view.

5. The wiring board according to claim 4 , wherein the recess is formed so as to face only a part of an outer periphery of the via hole in a plan view.

6. The outer edge of the recess has a shape having a plurality of projections and recesses in a plan view, The wiring board according to claim 1 , wherein the projections and recesses are formed by curved lines.

7. The wiring board according to claim 1 , wherein the recessed portion comprises a first recessed portion and a second recessed portion formed shallower than the first recessed portion, the second recessed portion being formed continuously.

8. the second wiring layer has a pad, The wiring board according to claim 1 , wherein the recess is provided so as to overlap the pad in a plan view.

9. a metal film continuously covering an upper surface of the second insulating layer, an inner surface of the via hole, and an inner surface of the recess; a first metal layer filling the via hole on the inner side of the metal film; a second metal layer filling the recessed portion on the inner side of the metal film; a third metal layer formed integrally with the first metal layer and the second metal layer and formed on the first metal layer and the second metal layer; the via wiring is composed of the metal film covering the inner surface of the via hole and the first metal layer, the conductive layer is composed of the metal film covering the inner surface of the recess and the second metal layer, 2. The wiring board according to claim 1, wherein the second wiring layer is composed of the metal film covering the upper surface of the second insulating layer and the third metal layer.

10. forming a first wiring layer on an upper surface of the first insulating layer; forming a second insulating layer on the upper surface of the first insulating layer so as to cover the first wiring layer; forming a via hole that penetrates the second insulating layer in a thickness direction and exposes an upper surface of the first wiring layer; forming a recess in an upper surface of the second insulating layer that does not penetrate the second insulating layer in a thickness direction; forming a metal film that continuously covers an upper surface of the second insulating layer, an inner surface of the via hole, and an inner surface of the recess; forming a resist layer on the upper surface of the metal film; forming an opening in the resist layer to expose the via hole and the recess; forming a via wiring filling the via hole, a conductive layer filling the recess, and a second wiring layer formed on the upper surface of the second insulating layer by electrolytic plating using the resist layer as a plating mask; and removing the resist layer. The step of forming the resist layer includes: laminating the resist layer, which is a dry film resist, on an upper surface of the metal film; and heating and pressing the resist layer by a roller moving along a first direction, The method for manufacturing a wiring substrate, wherein the recess is provided around the via hole in a plan view and at a position spaced apart from the via hole in the first direction.

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