Interposer substrate and semiconductor package

Abstract

To provide an interposer substrate and a semiconductor package that reduce an occurrence of a warpage defect.SOLUTION: An interposer substrate of the present invention comprises: a core part including a first surface and a second surface facing each other, and constructed so as to contain glass while having a via penetrating from the first surface to the second surface; and a conductive member filling a part of the via. The via includes: a first part penetrating from the first surface to a part of the core part to provide a space in which a connection member is disposed; and a second part penetrating from the second surface to another part of the core part to be connected to the first part to dispose the conductive member.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an interposer substrate and a semiconductor package. [Background technology]

[0002] As electronic components are required to be more highly functional, lighter, thinner, shorter, and smaller, the circuit boards mounted inside the electronic components are also required to be more highly functional, lighter, thinner, shorter, and smaller. To achieve this, the circuit patterns on circuit boards are designed with fine detail, and semiconductor elements that perform various functions are arranged inside the circuit boards to achieve high functionality.

[0003] Printed circuit boards on which chips are mounted are stacked one on top of the other to form a semiconductor package, such as a stacked package or package-on-package (POP). A stacked package is a structure in which upper and lower packages are stacked with a certain gap maintained between them depending on the thickness of the chips, and structures such as metal posts are used to maintain the gap.

[0004] Meanwhile, the interposer market is growing due to the high specification of sets and the adoption of HBM (High Bandwidth Memory).Currently, organic materials are the mainstream for interposer materials due to the traditional substrate manufacturing method, but methods using glass materials are also being developed.

[0005] For high-speed HBM, it is necessary to be able to form small, dense vias. Glass substrates have better warpage characteristics and flatness than substrates made of organic materials, and are known to have fewer problems during internal processing and are advantageous for reducing L / S (Line and Space). Therefore, there is a need to develop an interposer substrate using glass. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2020-21932 Summary of the Invention [Problem to be solved by the invention]

[0007] The present invention has been made in view of the above-mentioned conventional techniques, and an object of the present invention is to provide an interposer substrate and a semiconductor package that reduce the occurrence of warpage defects. [Means for solving the problem]

[0008] In order to achieve the above-mentioned object, an interposer substrate according to one embodiment of the present invention includes a first surface and a second surface facing each other, a core portion having a via penetrating from the first surface to the second surface and configured to contain glass, and a conductive material filled in a portion of the via, wherein the via includes a first portion that penetrates from the first surface through a portion of the core portion to provide space for a connecting member to be arranged, and a second portion that penetrates from the second surface through another portion of the core portion and in which the conductive member is arranged to be connected to the first portion.

[0009] The core portion may have a cavity on the second surface, and a plurality of vias may be provided around the cavity. The plurality of vias may be arranged along the periphery of the cavity. The interposer substrate may further include a heat dissipation portion extending from the first surface to the cavity. The heat dissipation portion may be provided in a plurality of parts, and the plurality of heat dissipation portions may be spaced apart from each other. The first surface and the second surface may face each other in a first direction, and the heat dissipation portion may have a plate shape that extends in a direction perpendicular to the first direction. The device may further include a protective portion configured to cover a side surface of the cavity and to shield against electromagnetic interference. The first and second portions may have a width at one outer end of the core portion greater than a width at the other inner end of the core portion. The first and second portions may have symmetrical shapes. The conductive member may be disposed so as to contact the connecting member.

[0010] An interposer substrate according to another aspect of the present invention, which has been made to achieve the above-mentioned object, includes a first surface and a second surface facing each other, a core portion having a via penetrating from the first surface to the second surface and a cavity on the second surface and configured to contain glass, a conductive material filled in a portion of the via, and a heat dissipation portion extending from the first surface to the cavity, wherein the via includes a first portion penetrating from the first surface through a portion of the core portion, and a second portion in which the conductive material is arranged, penetrating from the second surface through another portion of the core portion so as to connect to the first portion.

[0011] The vias may be provided in plurality around the periphery of the cavity. The plurality of vias may be arranged along a periphery of the cavity. The heat dissipation portion may be provided in a plurality of parts, and the plurality of heat dissipation portions may be spaced apart from each other. The first surface and the second surface may face each other in a first direction, and the heat dissipation portion may extend in a direction perpendicular to the first direction. The first and second portions may have a width at one outer end of the core portion greater than a width at the other inner end of the core portion. The first and second portions may have symmetrical shapes.

[0012] In order to achieve the above-mentioned object, one aspect of the present invention provides a semiconductor package comprising an interposer substrate, an upper package including a first circuit board located on one side of the interposer substrate and including an insulating layer and a circuit layer, and a connection member located on one side of the interposer substrate and connecting the upper package to the interposer substrate, wherein the interposer substrate has a first surface and a second surface facing each other, and includes a core portion configured to include glass and having a via penetrating from the first surface to the second surface, and a conductive member filled in a portion of the via, and the via includes a first portion that penetrates from the first surface through a portion of the core portion to provide space for the connection member to be disposed, and a second portion that penetrates from the second surface through another portion of the core portion to connect to the first portion and in which the conductive member is disposed.

[0013] The semiconductor package may further include a lower package disposed on the other side of the interposer substrate and including a second circuit board including an insulating layer and a circuit layer. The core portion may further include a heat dissipation portion having a cavity in the second surface and extending from the first surface to the cavity. [Effects of the Invention]

[0014] According to the interposer substrate and semiconductor package of the present invention, by inserting a glass core between the upper package and the lower package, it is possible to reduce the occurrence of warpage defects, by forming vias in the glass core, it is possible to increase thermal stability and the number of signals and improve power transmission characteristics, and by forming connecting members inside the vias, it is possible to reduce the overall height of the semiconductor package.

[0015] In addition, the heat generated from the electronic element placed in the cavity can be efficiently transferred and dispersed to the outside of the interposer substrate via the heat dissipation portion, and the heat dissipation efficiency can be improved by increasing the planar area of ​​the heat dissipation portion and expanding the surface area of ​​the heat dissipation portion that comes into contact with the electronic element. Furthermore, the protective portion that shields electromagnetic interference can provide an interposer substrate that is advantageous for electromagnetic wave shielding, and additional interposers can be easily placed as needed without significantly changing the height of the entire semiconductor package. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a cross-sectional view of a first example of a semiconductor package according to an embodiment. [Figure 2] 1 is a cross-sectional view showing a portion of a first example of a semiconductor package according to an embodiment. [Figure 3] 1 is a perspective view of a first example of an interposer substrate according to one embodiment. [Figure 4] FIG. 10 is a cross-sectional view showing a portion of a second example of a semiconductor package according to an embodiment. [Figure 5] FIG. 10 is a perspective view of a second example of an interposer substrate according to one embodiment. [Figure 6] FIG. 10 is a cross-sectional view showing a portion of a third example of a semiconductor package according to an embodiment. [Figure 7] FIG. 10 is a perspective view of a third example of an interposer substrate according to an embodiment. [Figure 8] FIG. 10 is a cross-sectional view showing a portion of a fourth example of a semiconductor package according to an embodiment. [Figure 9] FIG. 10 is a cross-sectional view of a semiconductor package according to another embodiment. [Figure 10] 5A to 5C are cross-sectional views illustrating a first example of a method for manufacturing a semiconductor package according to an embodiment. [Figure 11] 5A to 5C are cross-sectional views illustrating a first example of a method for manufacturing a semiconductor package according to an embodiment. [Figure 12] 5A to 5C are cross-sectional views illustrating a first example of a method for manufacturing a semiconductor package according to an embodiment. [Figure 13] 5A to 5C are cross-sectional views illustrating a first example of a method for manufacturing a semiconductor package according to an embodiment. [Figure 14] 5A to 5C are cross-sectional views illustrating a first example of a method for manufacturing a semiconductor package according to an embodiment. [Figure 15] 5A to 5C are cross-sectional views illustrating a first example of a method for manufacturing a semiconductor package according to an embodiment. [Figure 16] 5A to 5C are cross-sectional views showing a second example of a method for manufacturing a semiconductor package according to an embodiment. [Figure 17] 5A to 5C are cross-sectional views showing a second example of a method for manufacturing a semiconductor package according to an embodiment. [Figure 18] 5A to 5C are cross-sectional views showing a second example of a method for manufacturing a semiconductor package according to an embodiment. [Figure 19] 5A to 5C are cross-sectional views showing a second example of a method for manufacturing a semiconductor package according to an embodiment. [Figure 20] 5A to 5C are cross-sectional views showing a second example of a method for manufacturing a semiconductor package according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0017] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific examples of embodiments of the present invention will be described in detail with reference to the drawings.

[0018] In the drawings, parts unnecessary for the explanation are omitted in order to clearly explain the present invention, and the same reference numerals are used throughout the specification to refer to the same or similar components. In addition, in the drawings, some components are exaggerated, omitted, or shown in a schematic manner, and the size of each component does not entirely reflect the actual size.

[0019] The drawings are intended to facilitate understanding of the embodiments disclosed in this specification, and are not intended to limit the technical ideas disclosed in this specification, but should be understood to include all modifications, equivalents, or alternatives included in the idea and technical scope of the present invention.

[0020] Terms including ordinal numbers such as first, second, etc. are used to describe various components, but the components are not limited by the terms. The terms are used only to distinguish one component from another.

[0021] Furthermore, when a layer, film, region, plate, or other part is said to be "on" or "above" another part, this does not only mean that it is "directly on" that other part, but also includes cases where there is another part in between. Conversely, when a part is said to be "directly on" another part, it means that there is no other part in between. Furthermore, being "on" or "above" a reference part means being located above or below the reference part, and does not necessarily mean being located "on" or "above" in the opposite direction of gravity.

[0022] Throughout the specification, the use of terms such as "comprises" or "having" is intended to specify the presence of a stated feature, number, step, operation, component, part, or combination thereof, but should be understood as not precluding the possible presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof. Thus, when a part is said to "comprise" a certain component, this does not mean that it may further include other components, but does not exclude other components, unless specifically stated to the contrary.

[0023] Also, throughout the specification, "on a plane" means a view of the subject part from above, and "on a cross section" means a view of the subject part cut vertically from the side.

[0024] Throughout this specification, when a part is referred to as being "coupled" to another part, this includes not only "direct or physical coupling" but also "indirect or non-contact coupling" via another element in between.

[0025] Furthermore, throughout the specification, when the term "connected" is used, it does not only mean that two or more components are directly connected, but also that two or more components are indirectly connected via other components, that they are not only physically connected but also electrically connected, or that they are referred to by different names depending on their position or function but are nonetheless one unit.

[0026] FIG. 1 is a cross-sectional view of a first example of a semiconductor package according to one embodiment, FIG. 2 is a cross-sectional view showing a portion of the first example of a semiconductor package according to one embodiment, and FIG. 3 is a perspective view of a first example of an interposer substrate according to one embodiment.

[0027] 1 to 3, the semiconductor package 10 according to this embodiment includes an interposer substrate 100, an upper package 200 arranged on one side of the interposer substrate 100, a lower package 300 arranged on the other side of the interposer substrate 100, a first electronic element 400 connected to the lower package 300 and arranged in a cavity 102 of the interposer substrate 100, a first connecting member 11 arranged on one side of the interposer substrate 100 and connecting the interposer substrate 100 and the upper package 200, a second connecting member 12 connecting the interposer substrate 100 and the lower package 300, and a third connecting member 13 connecting the lower package 300 to the outside.

[0028] The interposer substrate 100 according to this embodiment includes a core portion 101 having at least one via 110 penetrating the interposer substrate 100, and a conductive member 120 filling a portion of the via 110. The core portion 101 has a cavity 102 on one surface.

[0029] The upper package 200 includes a first circuit board 201 and a second electronic component 202 mounted on the first circuit board 201. Although not shown in FIG. 1, the first circuit board 201 includes an insulating layer, a conductive layer, and a via layer. The insulating layer of the first circuit board 201 is made of at least one resin selected from epoxy resin, polyimide (PI) resin, BT resin, liquid crystal polymer (LCP), etc., and specifically includes prepreg (PPG), ABF film, etc. The insulating layer of the first circuit board 201 also includes glass fiber, filler, etc. Meanwhile, although not shown in FIG. 1, the insulating layer of the first circuit board 201 is made of multiple layers, and the number of layers is not limited.

[0030] The insulating layer of the first circuit board 201 includes a conductive layer that forms a circuit therein. The conductive layer of the first circuit board 201 provides a path for transmitting an electrical signal and is made of at least one of copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), and platinum (Pt).

[0031] For example, the first circuit board 201 does not include a cavity. In this case, the second electronic element 202 is mounted on the upper surface of the first circuit board 201. For example, the second electronic element 202 is mounted on the first circuit board 201 by wire bonding, flip-chip mounting, or the like.

[0032] The second electronic element 202 is at least one of an active element, a passive element, and an integrated circuit. The upper package 200 is connected to the interposer substrate 100 via a first connection member 11. The first connection member 11 is a solder ball or the like.

[0033] The lower package 300 includes a second circuit board 301. The second circuit board 301 includes an insulating layer, a conductive layer, and a via layer. The insulating layer of the second circuit board 301 is made of at least one resin selected from epoxy resin, polyimide (PI) resin, BT resin, liquid crystal polymer (LCP), etc., and specifically includes prepreg (PPG), ABF film, etc. The insulating layer of the second circuit board 301 also includes glass fiber, filler, etc. Meanwhile, although not shown in FIG. 1, the insulating layer of the second circuit board 301 is made of multiple layers, and the number of layers is not limited.

[0034] The insulating layer of the second circuit board 301 includes a conductive layer that forms a circuit therein. The conductive layer of the second circuit board 301 provides a path for transmitting an electrical signal and is made of at least one of copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), and platinum (Pt).

[0035] The lower package 300 is connected to the interposer substrate 100 via a second connection member 12. The lower package 300 is connected to a first electronic element 400 via the second connection member 12. The second connection member 12 is a solder ball or the like. The first electronic element 400 is at least one of an active element, a passive element, and an integrated circuit.

[0036] If necessary, a conductive film 401 is disposed between the first electronic element 400 and the core portion 101. The conductive film 401 bonds the first electronic element 400 to the core portion 101. A molding material 402 is disposed in the space of the cavity 102 where the first electronic element 400 is not disposed. The molding material 402 fixes the first electronic element 400.

[0037] The interposer substrate 100 will be described in detail below with reference to FIGS.

[0038] 2 and 3, the core unit 101 is a glass substrate. The core unit 101 has a first surface and a second surface facing each other in a first direction. For example, an upper package 200 is disposed on an upper portion of the interposer substrate 100 in the first direction. A lower package 300 is disposed on a lower portion of the interposer substrate 100 in the first direction. The first surface is a surface of the semiconductor package 10 facing the upper package 200.

[0039] The via 110 penetrates from the first surface to the second surface of the core portion 101. A plurality of vias 110 are provided. The cavity 102 is located on the second surface of the core portion 101. The cavity 102 has a shape recessed from the second surface in the first direction. The via 110 is located on one side of the cavity 102. For example, a plurality of vias 110 are arranged along the periphery of the cavity 102. The plurality of vias 110 are arranged along one peripheral region of the cavity 102. The via 110 includes a first portion 111 that penetrates a portion of the core portion 101 from the first surface, and a second portion 112 that penetrates a remaining portion of the core portion 101 from the second surface to be connected to the first portion 111.

[0040] The first portion 111 has an opening on the first surface. The width of the first portion 111 at one outer end of the core portion 101 along the first direction is larger than the width of the other inner end of the core portion 101. The first portion 111 has a shape in which the width in a direction perpendicular to the first direction increases toward the outside of the core portion 101. The first portion 111 has a shape in which the width increases toward the first surface along the first direction.

[0041] The second portion 112 has an opening on the second surface. The width of the second portion 112 at one outer end of the core portion 101 along the first direction is larger than the width of the other inner end of the core portion 101. The second portion 112 has a shape in which the width in a direction perpendicular to the first direction increases toward the outside of the core portion 101. The second portion 112 has a shape in which the width increases toward the second surface along the first direction.

[0042] The first portion 111 and the second portion 112 are symmetrical with respect to a reference plane perpendicular to the first direction, but are not limited thereto, and the heights (thicknesses) of the first portion 111 and the second portion 112 may be different from each other.

[0043] A portion of the via 110 is filled with a conductive member 120. At least a portion of the second portion 112 is filled with the conductive member 120. The conductive member 120 is disposed in the second portion 112. As a result, a groove having an opening on the first surface is formed, with the first portion 111 forming an inner wall and the conductive member 120 forming a bottom surface. Although FIGS. 2 and 3 illustrate the second portion 112 as being filled entirely with the conductive member 120, this is not limitative, and the conductive member 120 may be disposed by filling only a portion of the second portion 112. Also, the conductive member 120 may be additionally filled in a portion of the first portion 111. For example, the conductive member 120 includes copper (Cu).

[0044] The first portion 111 provides a space for the first connection member 11 to be disposed therein. The first connection member 11 is disposed inside the first portion 111. In other words, at least a portion of the first connection member 11 is accommodated in the groove space of the core portion 101 formed by the first portion 111 of the via 110. The first connection member 11 is disposed so as to be connected to the conductive member 120. The first connection member 11 is disposed inside the first portion 111 so as to be in contact with the conductive member 120. The first connection member 11 is disposed so as to be in contact with one surface of the conductive member 120 exposed on the upper side along the first direction. The first connection member 11 connects the upper package 200 and the interposer substrate 100.

[0045] The second connection member 12 is arranged so as to be connected to the conductive member 120. The second connection member 12 is arranged so as to be in contact with the other surface of the conductive member 120 exposed on the lower side along the first direction. The second connection member 12 connects the lower package 300 and the interposer substrate 100.

[0046] According to the interposer substrate and semiconductor package according to the above-described embodiments, the glass core is located between the upper package and the lower package, thereby reducing the occurrence of warpage defects, and the vias are located in the glass core, thereby increasing thermal stability, increasing the number of signals, and improving power transmission characteristics. Furthermore, the connection members are located inside the vias, thereby reducing the overall height of the semiconductor package.

[0047] Hereinafter, a second example of the interposer substrate 100 and the semiconductor package 10 according to an embodiment will be described with reference to FIGS.

[0048] FIG. 4 is a cross-sectional view showing a portion of a second example of a semiconductor package according to an embodiment, and FIG. 5 is a perspective view of a second example of an interposer substrate according to an embodiment.

[0049] 4 and 5, the interposer substrate 100 according to this embodiment is similar to the interposer substrate 100 according to the embodiment described with reference to Figures 2 and 3. A detailed description of the same components will be omitted.

[0050] 4 and 5, the interposer substrate 100 according to this embodiment further includes a heat dissipation portion 130 connected to the cavity 102, compared to the interposer substrate 100 according to the embodiment shown in FIGS. 2 and 3. The heat dissipation portion 130 extends from the first surface of the core portion 101 to the cavity 102. The heat dissipation portion 130 contacts the first electronic element 400 arranged in the cavity 102 (or the conductive film 401 if a conductive film 401 is arranged between the first electronic element 400 and the core portion 101, as necessary).

[0051] A plurality of heat dissipation parts 130 are provided. The heat dissipation parts 130 are located on one side of the cavity 102 in the first direction. For example, the plurality of heat dissipation parts 130 are arranged in one region of the core part 101 corresponding to the cavity 102. The plurality of heat dissipation parts 130 include portions arranged in one direction. The plurality of heat dissipation parts 130 are arranged spaced apart from each other.

[0052] The heat dissipation part 130 includes at least one of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof.

[0053] According to the interposer substrate and semiconductor package according to the above-described embodiment, heat generated from the electronic element disposed in the cavity can be efficiently transferred and dispersed to the outside of the interposer substrate via the heat dissipation portion.

[0054] Hereinafter, a third example of the interposer substrate 100 and the semiconductor package 10 according to an embodiment will be described with reference to FIGS.

[0055] FIG. 6 is a cross-sectional view showing a portion of a third example of a semiconductor package according to an embodiment, and FIG. 7 is a perspective view of a third example of an interposer substrate according to an embodiment.

[0056] 6 and 7, the interposer substrate 100 according to this embodiment is similar to the interposer substrate 100 according to the embodiment described with reference to Figures 4 and 5. A detailed description of the same components will be omitted.

[0057] 6 and 7, the interposer substrate 100 according to this embodiment has a heat dissipation portion 130 with a larger planar area than the interposer substrate 100 according to the embodiment shown in FIGS. 4 and 5. The heat dissipation portion 130 is positioned to penetrate from the first surface of the core portion 101 to the cavity 102. The heat dissipation portion 130 contacts the first electronic component 400 disposed in the cavity 102 (or the conductive film 401, if necessary, disposed between the first electronic component 400 and the core portion 101). The heat dissipation portion 130 has a plate shape that extends to an area corresponding to the inner area of ​​the cavity 102. The heat dissipation portion 130 extends in a direction perpendicular to the first direction. For example, the heat dissipation portion 130 has a plate shape that extends to a plane perpendicular to the first direction.

[0058] The heat dissipation part 200 includes at least one of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof.

[0059] According to the interposer substrate and semiconductor package of the above-described embodiment, the heat dissipation efficiency can be improved by increasing the planar area of ​​the heat dissipation portion and widening the surface area of ​​the heat dissipation portion facing the electronic element.

[0060] Hereinafter, a fourth example of the interposer substrate 100 according to an embodiment will be described with reference to FIG.

[0061] FIG. 8 is a cross-sectional view showing a part of a fourth example of a semiconductor package according to an embodiment.

[0062] 8, the interposer substrate 100 according to the present embodiment is similar to the semiconductor package 10 according to the embodiment described with reference to Figures 2 and 3. A detailed description of the same components will be omitted.

[0063] 8, the interposer substrate 100 according to this embodiment further includes a protective portion 140 covering the side surfaces of the cavity 102, as compared to the interposer substrate 100 according to the embodiment shown in FIGS. 2 and 3. The protective portion 140 is configured to cover the side surfaces of the cavity 102 along a first direction and along a direction perpendicular to the first direction to shield Electro Magnetic Interference (EMI). The protective portion 140 includes at least one of a magnetic material and a metal.

[0064] According to the interposer substrate and semiconductor package according to the above-described other embodiments, it is possible to provide an interposer substrate that is advantageous in shielding electromagnetic waves.

[0065] Hereinafter, a semiconductor package according to another embodiment will be described with reference to FIG.

[0066] FIG. 9 is a cross-sectional view of a semiconductor package according to another embodiment.

[0067] 9, the semiconductor package 10 according to the present embodiment is similar to the semiconductor package 10 according to the embodiment described with reference to FIG 1. A detailed description of the same components will be omitted.

[0068] Referring to Figure 9, compared to the semiconductor package 10 according to the embodiment shown in Figure 1, the semiconductor package 10 according to this embodiment further includes a third circuit board 500 located on the interposer substrate 100, and a fourth connecting member 14 connecting the third circuit board 500 and the upper package 200.

[0069] Although not shown in FIG. 8, the third circuit board 500 includes an insulating layer, a conductive layer, and a via layer. The third circuit board 500 functions as an interposer. The upper package 200 is connected to the third circuit board 500 via a fourth connection member 14. The fourth connection member 14 is a solder ball or the like. The first connection member 11 connects the interposer substrate 100 and the third circuit board 500.

[0070] According to the interposer substrate and semiconductor package of the above-described embodiment, an additional interposer can be easily arranged as needed without significantly changing the height of the entire semiconductor package.

[0071] A first example of a method for manufacturing the interposer substrate 100 and the semiconductor package 10 according to an embodiment will be described below with reference to FIGS.

[0072] 10 to 15 are cross-sectional views showing a first example of a method for manufacturing a semiconductor package according to an embodiment.

[0073] 10 and 11, a portion of a glass substrate 1011 is etched to form a core portion 101 having a cavity 102. The cavity 102 is formed in the glass substrate 1011 by an etching process such as wet etching or physical etching.

[0074] 12, a second portion 112 is formed so as to penetrate a part of the core portion 101 from the second surface of the core portion 101. The second portion 112 is formed by laser drilling.

[0075] 13, the inside of the second portion 112 is filled with a conductive member 120. In FIG. 13, the conductive member 120 is illustrated as filling the entire second portion 112, but this is not limiting, and the conductive member 120 may fill only a portion of the second portion 112.

[0076] 14, a via 110 including the second portion 112 and the first portion 111 is formed by forming a first portion 111 that penetrates another part of the core portion 101 so as to connect from a first surface of the core portion 101 to the second portion 112. The first portion 111 is formed by laser drilling. For example, the first portion 111 is formed to have a shape symmetrical to the second portion 112. The first portion 111 and the second portion 112 are formed so that the width in a direction perpendicular to the first direction increases toward the outside of the core portion 101.

[0077] Referring to FIG. 14, the interposer substrate 100 according to the embodiment described above with reference to FIGS. 1 to 3, including the core portion 101, the cavity 102, and the conductive member 120, is formed.

[0078] 15, a first electronic element 400 is placed in the cavity 102. If necessary, a conductive film 401 is placed between the first electronic element 400 and the core part 101. The conductive film 401 bonds the first electronic element 400 to the core part 101. A molding material 402 is placed in the space of the cavity 102 where the first electronic element 400 is not placed. The molding material 402 fixes the first electronic element 400.

[0079] 1, a first connection member 11 is formed inside the first portion 111, and an upper package 200 is disposed on the first connection member 11. A second connection member 12 is formed on the conductive member 120 and the first electronic component 400 filled in the second portion 112, and a lower package 300 is disposed on the second connection member 12. In this way, a first example of a semiconductor package 10 according to an embodiment described above with reference to FIG. 1 is formed.

[0080] According to the semiconductor package manufacturing method of the above-described embodiment, by inserting a glass core between the upper package and the lower package, it is possible to reduce the occurrence of warpage defects, by forming vias in the glass core, it is possible to increase thermal stability and the number of signals, and it is possible to improve power transmission characteristics, and by forming connecting members inside the vias, it is possible to reduce the overall height of the semiconductor package, and by forming vias connecting through holes formed symmetrically on both sides of the glass core, it is possible to easily form a via structure including first and second portions.

[0081] Hereinafter, a second example of a method for manufacturing the interposer substrate 100 and the semiconductor package 10 according to an embodiment will be described with reference to FIGS.

[0082] 16 to 20 are cross-sectional views showing a second example of a method for manufacturing a semiconductor package according to an embodiment.

[0083] 11 and 12, the core portion 101 having the cavity 102 and the second portion 112 is formed. Now, referring to Fig. 16, a through-hole 1301 is formed, penetrating from the first surface of the core portion 101 to the cavity 102. The through-hole 1301 is formed by laser drilling.

[0084] 17, the inside of the second portion 112 is filled with a conductive member 120. Also, the inside of the through hole 1301 is filled with a heat dissipation material to form the heat dissipation part 130.

[0085] In FIG. 17, the conductive member 120 is illustrated as filling the entire second portion 112, but this is not limited thereto, and the conductive member 120 may fill only a portion of the second portion 112.

[0086] 18, a first portion 111 is formed penetrating from a first surface of the core portion 101 to another portion of the core portion 101, thereby forming a via 110 including a second portion 112 and the first portion 111. The first portion 111 is formed by laser drilling. For example, the first portion 111 is formed to have a shape symmetrical to the second portion 112. The first portion 111 and the second portion 112 are formed so that the width in a direction perpendicular to the first direction increases toward the outside of the core portion 101.

[0087] Referring to FIG. 18, an interposer substrate 100 according to the embodiment described above with reference to FIGS. 4 and 5, including a core portion 101, a cavity 102, a conductive member 120, and a heat dissipation portion 130, is formed.

[0088] 19, a first electronic element 400 is placed in the cavity 102. If necessary, a conductive film 401 is placed between the first electronic element 400 and the core portion 101. The conductive film 401 bonds the first electronic element 400 to the core portion 101. A molding material 402 is placed in the space of the cavity 102 where the first electronic element 400 is not placed. The molding material 402 fixes the first electronic element 400.

[0089] 20, a first connection member 11 is formed inside the first portion 111, and an upper package 200 is disposed on the first connection member 11. In addition, a second connection member 12 is formed on the conductive member 120 filled in the second portion 112 and the first electronic element 400, and a lower package 300 is disposed on the second connection member 12. In this way, a second example of a semiconductor package 10 according to an embodiment is formed.

[0090] According to the semiconductor package manufacturing method according to the above-described embodiment, by inserting a glass core between the upper package and the lower package, it is possible to reduce the occurrence of warpage defects, by forming vias in the glass core, it is possible to increase thermal stability and the number of signals, and to improve power transmission characteristics, and by forming connecting members inside the vias, it is possible to reduce the overall height of the semiconductor package, by forming vias connecting through holes formed symmetrically on opposite sides of the glass core, it is possible to easily form a via structure including first and second portions, and it is possible to efficiently transfer and dissipate heat generated from an electronic device disposed in a cavity to the outside of the interposer substrate via a heat dissipation portion.

[0091] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical concept of the present invention. [Explanation of symbols]

[0092] 10 Semiconductor Package 11, 12, 13, 14 First to fourth connecting members 100 Interposer board 101 Core 102 Cavity 110 Beer 111, 112 1st and 2nd parts 120 Conductive material 130 Heat radiation part 140 Protection Department 200, 300 upper and lower packages 201, 301, 500 1st~3rd circuit board 202, 400 Second and first electronic elements 401 Conductive film 402 Molding material 1011 glass substrate 1301 Through Hole

Claims

1. a core portion including a first surface and a second surface facing each other, the core portion having a via penetrating from the first surface to the second surface and configured to contain glass; a conductive member filled in a portion of the via; The via is a first portion that provides a space for a connecting member to be disposed through a portion of the core portion from the first surface; a second portion in which the conductive member is disposed, passing through another part of the core portion so as to be connected from the second surface to the first portion.

2. the core portion has a cavity on the second surface, The interposer substrate according to claim 1 , wherein a plurality of the vias are provided around the periphery of the cavity.

3. The interposer substrate according to claim 2 , wherein the plurality of vias are arranged along the periphery of the cavity.

4. The interposer substrate according to claim 2 , further comprising a heat dissipation portion extending from the first surface to the cavity.

5. The heat dissipation portion is provided in plurality, The interposer substrate according to claim 4 , wherein the plurality of heat dissipation portions are arranged spaced apart from one another.

6. the first surface and the second surface face each other in a first direction, The interposer substrate according to claim 4 , wherein the heat dissipation portion has a plate shape that extends in a direction perpendicular to the first direction.

7. The interposer substrate according to claim 2 , further comprising a protective portion configured to cover a side surface of the cavity and to shield against electromagnetic interference.

8. 2. The interposer substrate according to claim 1, wherein the width of one outer end of the core portion of the first portion and the second portion is larger than the width of the other inner end of the core portion.

9. The interposer substrate according to claim 1 , wherein the first portion and the second portion have symmetrical shapes.

10. The interposer substrate according to claim 1 , wherein the conductive member is disposed so as to be in contact with the connecting member.

11. a core portion including a first surface and a second surface facing each other, the core portion having a via penetrating from the first surface to the second surface and a cavity in the second surface, the core portion configured to contain glass; a conductive member filling a portion of the via; a heat dissipation portion extending through the first surface to the cavity, The via is a first portion that penetrates from the first surface through a part of the core portion; a second portion in which the conductive member is disposed, passing through another part of the core portion so as to be connected from the second surface to the first portion.

12. The interposer substrate according to claim 11 , wherein a plurality of the vias are provided around the periphery of the cavity.

13. The interposer substrate of claim 12 , wherein the plurality of vias are arranged along the periphery of the cavity.

14. The heat dissipation portion is provided in plurality, The interposer substrate according to claim 11 , wherein the plurality of heat dissipation portions are spaced apart from one another.

15. the first surface and the second surface face each other in a first direction, The interposer substrate of claim 11 , wherein the heat dissipation portion extends in a direction perpendicular to the first direction.

16. The interposer substrate according to claim 11 , wherein the width of one outer end of the core portion of the first portion and the second portion is larger than the width of the other inner end of the core portion.

17. The interposer substrate according to claim 11 , wherein the first portion and the second portion have symmetrical shapes.

18. an interposer substrate; an upper package including a first circuit board positioned on one side of the interposer substrate and including an insulating layer and a circuit layer; a connecting member disposed on one surface of the interposer substrate to connect the upper package and the interposer substrate, The interposer substrate is a core portion including a first surface and a second surface facing each other, the core portion having a via penetrating from the first surface to the second surface and configured to contain glass; a conductive member filling a portion of the via; The via is a first portion that provides a space for the connection member to be disposed by passing through a portion of the core portion from the first surface; a second portion in which the conductive member is disposed, passing through another part of the core portion so as to be connected to the first portion from the second surface.

19. 20. The semiconductor package of claim 18, further comprising a lower package including a second circuit board disposed on the other side of the interposer substrate and including an insulating layer and a circuit layer.

20. the core portion has a cavity on the second surface, The semiconductor package of claim 18 , further comprising a heat dissipation portion extending from the first surface to the cavity.

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