How to design a trigger unit

Abstract

This application discloses a method for designing a trigger unit, which includes the steps of: analyzing a signal delay of a clock control signal in a digital circuit; selecting a clock gating circuit from a plurality of different types of clock gating circuits according to the signal delay of the clock control signal; and combining at least one edge triggered flip-flop and the selected clock gating circuit into a trigger unit, in which the plurality of different types of clock gating circuits enable or disable a first clock signal according to the clock control signal to generate a second clock signal, and the edge triggered flip-flop transmits data at an edge of the second clock signal. The design method for the trigger unit selects a clock gating circuit from a plurality of different types of clock gating circuits according to the delay condition of the clock control signal, which can not only eliminate glitches in the clock signal generated by the clock gating circuit, but also reduce the number of logic elements of the clock gating circuit, reduce the power consumption of the clock gating circuit, and is suitable for a flip-flop group with any number of edge triggered flip-flops.

Description

[Technical field]

[0001] This application claims priority to a Chinese patent application bearing application number 202210107336.2 and entitled "Design Method for Trigger Unit", filed on January 28, 2022, and hereby incorporates by reference all of the specification, claims, accompanying drawings and abstract of the above-mentioned Chinese patent application.

[0002] The present invention relates to integrated circuit technology, and more particularly to a method for designing a trigger unit. [Background technology]

[0003] Electronic design automation software (EDA) is an important tool for the processes of functional design, integration, verification, physical design, etc. of integrated circuits. In digital circuit design EDA, standard cell libraries are a fundamental part of the back-end design process of integrated circuit chips. Using pre-designed optimized library units, automatic logic integration and layout routing can be performed to enhance design efficiency. Through the optimized library units, the performance of the circuit can be improved and power consumption can be reduced.

[0004] In the digital part of an integrated circuit, a gate circuit is used to perform combinational logic on multiple signals to generate a logical operation result, and an edge-triggered flip-flop is used to store the logical operation result. According to the difference in logical operation, the gate circuit can be divided into AND gate, OR gate, NOT gate, NAND gate, ANDOR gate, XOR gate, etc. The logical operation result of the gate circuit is, for example, a pulse signal, and a steady level signal according to the logical state is generated based on this pulse signal.

[0005] An edge-triggered flip-flop is an information storage device with a memory function, and is used to store the result of a memory logic operation. For example, an edge-triggered flip-flop is the most basic logic unit that constitutes various sequence digital circuit modules, and is an important unit circuit in a digital circuit module. Referring to FIG. 1 and FIG. 2, depending on the type of edge-triggered flip-flop, the edge-triggered flip-flop 110 is triggered by the rising edge or the falling edge of a clock signal, and allows the input data to be transmitted from the input end to the output end to obtain the output data. The edge-triggered flip-flop 110 is, for example, a D-type flip-flop. For example, the D-type flip-flop transmits data at the trigger edge of the clock signal and holds the data unchanged until the next trigger edge.

[0006] The power consumption of an edge-triggered flip-flop can be divided into static power consumption and dynamic power consumption. The static power consumption is mainly caused by leakage current, and the dynamic power consumption is mainly caused by power consumption due to signal inversion. The inversion of the data signal of the edge-triggered flip-flop causes additional data power consumption in the downstream combinational logic, and the inversion of the clock signal also causes clock power consumption of the edge-triggered flip-flop itself. Therefore, it is necessary to optimize the design of edge-triggered flip-flops in digital circuit EDA standard cell libraries, and it is expected to further reduce the dynamic power consumption of edge-triggered flip-flops. Summary of the Invention

[0007] In view of the above problems, the present invention provides a method for designing a trigger unit, which selects a clock gating circuit from a plurality of different types of clock gating circuits depending on the delay conditions of a clock control signal, reduces the number of logical elements in the clock gating circuit, and reduces the power consumption of the clock gating circuit.

[0008] According to the present invention, a method for designing a trigger unit is provided, the method including the steps of: analyzing a signal delay of a clock control signal in a digital circuit; selecting a clock gating circuit from a plurality of different types of clock gating circuits according to the signal delay of the clock control signal; and combining at least one edge-triggered flip-flop and the selected clock gating circuit into a trigger unit, wherein the plurality of different types of clock gating circuits enable or disable a first clock signal according to the clock control signal to generate a second clock signal, and the edge-triggered flip-flop transmits data at an edge of the second clock signal.

[0009] Preferably, the plurality of different types of clock gating circuits include at least one of a first clock gating circuit and a second clock gating circuit, and the first clock gating circuit and the second clock gating circuit maintain the second clock signal at a predetermined level at least in a clock cycle in which the clock control signal is inverted from an enabled state to an disabled state.

[0010] Preferably, in a clock cycle in which the clock control signal maintains an invalid state, the first clock gating circuit and the second clock gating circuit maintain the second clock signal at the predetermined level.

[0011] Preferably, in a clock cycle in which the clock control signal inverts from an invalid state to an valid state, the first clock gating circuit and the second clock gating circuit copy the first clock signal as the second clock signal.

[0012] Preferably, in clock cycles in which the clock control signal remains valid, the first clock gating circuit and the second clock gating circuit copy the first clock signal as the second clock signal.

[0013] Preferably, the first clock gating circuit performs a logical OR operation on an inverted signal of the clock control signal and the first clock signal to generate the second clock signal.

[0014] Preferably, the second clock gating circuit performs a logical AND operation on the clock control signal and the first clock signal to generate the second clock signal.

[0015] Preferably, the plurality of different types of clock gating circuits further includes a third clock gating circuit, which maintains the second clock signal at a predetermined level at least in the next clock cycle in which the clock control signal inverts from an enabled state to an disabled state.

[0016] Preferably, the third clock gating circuit performs a logical AND operation on the latched signal of the clock control signal and the first clock signal to generate the second clock signal.

[0017] Preferably, the signal delay of the clock control signal varies within a range between a minimum delay and a maximum delay.

[0018] Preferably, when the minimum delay and the maximum delay are both in a first level phase of the first clock signal, one of the first clock gating circuit and the second clock gating circuit is selected according to a starting edge of the first level phase.

[0019] Preferably, when the starting edge of the first level step is a rising edge, the selected clock gating circuit is the first clock gating circuit.

[0020] Preferably, when the starting edge of the first level step is a falling edge, the selected clock gating circuit is the second clock gating circuit.

[0021] Preferably, the predetermined level is the level of the first level stage.

[0022] Preferably, when the minimum delay and the maximum delay are in a first level stage and a second level stage of the first clock signal, respectively, the selected clock gating circuit is a third clock gating circuit.

[0023] Preferably, the predetermined level is a level of the second level stage.

[0024] Preferably, the step of combining with a trigger unit selects a clock cycle for data transmission by said edge triggered flip-flop according to a selected type of clock gating circuit or a type of said edge triggered flip-flop.

[0025] Preferably, if the starting edge of the first level stage is the same as the trigger edge of the edge-triggered flip-flop, then in a clock cycle in which the clock control signal is inverted, the second clock signal provides the trigger edge of the edge-triggered flip-flop.

[0026] Preferably, when the starting edge of the first level stage is opposite the trigger edge of the edge-triggered flip-flop, the second clock signal provides the trigger edge of the edge-triggered flip-flop in the clock cycle preceding the clock cycle in which the clock control signal is inverted.

[0027] Preferably, the step of combining with a trigger unit includes the step of inverting said second clock signal to generate a third clock signal.

[0028] Preferably, if the starting edge of the first level stage is the same as the trigger edge of the edge-triggered flip-flop, then in a clock cycle in which the clock control signal is inverted, the second clock signal provides the trigger edge of the edge-triggered flip-flop.

[0029] Preferably, when the starting edge of the first level stage is opposite the trigger edge of the edge-triggered flip-flop, the third clock signal provides the trigger edge of the edge-triggered flip-flop in a clock cycle in which the clock control signal is inverted.

[0030] Preferably, a high level of the clock control signal indicates a valid state, and a low level indicates an invalid state.

[0031] According to an embodiment of the present invention, in a method for designing a trigger unit, a clock gating circuit is selected from a plurality of different types of clock gating circuits according to a delay condition of a clock control signal. By utilizing the circuit characteristics of the different types of clock gating circuits under different delay conditions of the clock control signal, glitches in the clock signal generated by the clock gating circuit can be eliminated. In a clock cycle in which the clock control signal maintains an invalid state, a second clock signal generated by the clock gating circuit can disable clock inversion and data transmission of the edge triggered flip-flop, thereby reducing the dynamic power consumption of the edge triggered flip-flop.

[0032] In a preferred embodiment, when the range of the minimum delay and the maximum delay of the clock control signal are both in a single level step and the starting edge of the level step is a rising edge, a first clock gating circuit is selected, and the first clock gating circuit performs a logical OR operation on the inverted signal of the clock control signal and the first clock signal to generate the second clock signal. The clock signal generated by the clock gating circuit can be deglitched, and in the clock cycle in which the clock control signal inverts from an active state to an inactive state, the second clock signal generated by the clock gating circuit can disable the clock inversion of the edge-triggered flip-flop, thereby reducing the dynamic power consumption of the edge-triggered flip-flop.

[0033] In a preferred embodiment, when the range of the minimum delay and the maximum delay of the clock control signal are both in a single level step and the starting edge of the level step is a falling edge, a second clock gating circuit is selected, and the second clock gating circuit performs a logical AND operation on the clock control signal and the first clock signal to generate the second clock signal. The clock gating circuit can eliminate glitches in the clock signal generated. In a clock cycle in which the clock control signal inverts from an active state to an inactive state, the second clock signal generated by the clock gating circuit can disable the clock inversion of the edge triggered flip-flop, thereby reducing the dynamic power consumption of the edge triggered flip-flop.

[0034] In a preferred embodiment, when the first clock gating circuit and the second clock gating circuit are selected, even if the latch is omitted, the glitch of the clock signal generated by the clock gating circuit can be eliminated. Therefore, less hardware logic is used in the clock gating circuit, and the operation power consumption of the clock gating circuit itself is lower. Any number of edge-triggered flip-flops in the trigger unit can share the clock gating circuit to form a flip-flop group. When the flip-flop group includes any number of edge-triggered flip-flops, for example, one, two, or more, the increase in power consumption due to the power consumption of the clock gating circuit itself is much smaller than the reduction in power consumption of the edge-triggered flip-flops due to clock gating, so the trigger unit can always achieve a reduction in power consumption.

[0035] Furthermore, the circuit design method for the trigger unit optimizes the combination of a clock gating circuit and an edge trigger flip-flop, enabling simplification and reduction in layout area, and the combination circuit of the clock gating circuit and the edge trigger flip-flop is used as a library unit of a standard cell library and applied under various conditions to improve the performance and design efficiency of digital circuits. [Brief description of the drawings]

[0036] Hereinafter, embodiments of the present invention will be described with reference to the drawings, whereby the above and other objects, features and advantages of the present invention will become more apparent.

[0037] [Figure 1] 1 and 2 show a schematic circuit diagram and waveform diagrams, respectively, of an edge-triggered flip-flop in an integrated circuit. [Diagram 2] 1 and 2 show a schematic circuit diagram and waveform diagrams, respectively, of an edge-triggered flip-flop in an integrated circuit. [Diagram 3] FIG. 3 shows a schematic circuit diagram of the trigger unit. [Figure 4] 4 and 5 show a schematic circuit diagram and waveform diagrams, respectively, of a prior art clock gating circuit. [Diagram 5] 4 and 5 show a schematic circuit diagram and waveform diagrams, respectively, of a prior art clock gating circuit. [Figure 6] 6, 7a and 7b respectively show a schematic circuit diagram and waveform diagrams of a clock gating circuit according to a first embodiment of the present invention. [Figure 7a] 6, 7a and 7b respectively show a schematic circuit diagram and waveform diagrams of a clock gating circuit according to a first embodiment of the present invention. [Figure 7b] 6, 7a and 7b respectively show a schematic circuit diagram and waveform diagrams of a clock gating circuit according to a first embodiment of the present invention. [Figure 8] 8, 9a and 9b respectively show a schematic circuit diagram and waveform diagrams of a clock gating circuit according to a second embodiment of the present invention. [Figure 9a] 8, 9a and 9b respectively show a schematic circuit diagram and waveform diagrams of a clock gating circuit according to a second embodiment of the present invention. [Figure 9b] 8, 9a and 9b respectively show a schematic circuit diagram and waveform diagrams of a clock gating circuit according to a second embodiment of the present invention. [Figure 10] FIG. 10 shows a flowchart of a method for designing a trigger unit according to a third embodiment of the present invention. [Figure 11] FIG. 11 shows a method of combining a clock gating circuit and an edge trigger flip-flop in the design method of the trigger unit shown in FIG. [Figure 12] FIG. 12 shows another combination method of the clock gating circuit and the edge trigger flip-flop in the design method of the trigger unit shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0038] The present invention will now be described in more detail with reference to the accompanying drawings, in which like elements are designated by similar reference numerals in the various drawings, and in which, for clarity, parts of the drawings are not drawn to scale, and some well-known components may not be shown.

[0039] In order to provide a clearer understanding of the present invention, numerous specific details of the invention are set forth below, such as device structures, materials, dimensions, processing and techniques, etc. However, as will be appreciated by those skilled in the art, the present invention may be practiced without these specific details.

[0040] The present invention may be embodied in a variety of forms, some examples of which are set forth below.

[0041] 3 shows a schematic circuit diagram of a trigger unit. The trigger unit 200 includes an edge-triggered flip-flop 110 and a clock gating circuit 130. The clock gating circuit 130 is used to gate the clock signal CK of the edge-triggered flip-flop 110. In this embodiment, the edge-triggered flip-flop 110 is, for example, a D-type flip-flop.

[0042] The edge-triggered flip-flop 110 includes a data input end, a data output end, and a clock input end. The clock gating circuit 130 includes an input end, an output end, and a control terminal. The input end of the clock gating circuit 130 receives a clock signal CLK, the output end provides a clock signal CK, and the control terminal receives a clock control signal EN. The data input end of the edge-triggered flip-flop 110 receives input data Di, the clock input end receives the clock signal CK, and the data output end provides output data Do.

[0043] At a trigger edge, such as a rising edge, of the clock signal CK, the edge-triggered flip-flop 110 transmits the input data from the data input to the data output. Therefore, the signal level corresponding to the output data of the data output of the edge-triggered flip-flop 110 depends on the signal level of the input data at the data input before the trigger edge of the clock signal CK arrives, and does not change in the clock cycle after the trigger edge of the clock signal CK. The data output of the edge-triggered flip-flop 110 can include two complementary outputs.

[0044] The clock gating circuit 130 performs a logical operation on the clock control signal EN and the clock signal CLK to generate the clock signal CK for the edge triggered flip-flop 110 .

[0045] In the trigger unit, a clock gating circuit 130 controls the transmission of a clock signal according to the state of a clock control signal EN.

[0046] In clock cycles in which the clock control signal EN remains in an enabled state, the clock gating circuit 130 copies the clock signal CLK to the clock signal CK and provides the clock signal CK to the clock input terminal of the edge-triggered flip-flop 110, and in clock cycles in which the clock control signal EN remains in an disabled state, the clock gating circuit 130 disables the clock signal CLK and maintains the clock signal CK at a predetermined level.

[0047] When the clock signal CK is maintained at a predetermined level, the clock signal CK cannot provide a trigger edge for the edge-triggered flip-flop 110, and thus can disable the clock inversion and data transmission of the edge-triggered flip-flop 110. Furthermore, the edge-triggered flip-flop 110 can prevent data from entering the downstream digital circuitry, thereby avoiding additional data power consumption due to the inversion of the data signal in the downstream combinational logic.

[0048] 4 shows a schematic circuit diagram of a clock gating circuit according to the prior art. Referring to FIG. 3, the clock gating circuit 130 and the edge triggered flip-flop 110 together form a trigger unit, and the clock gating circuit 130 provides a clock signal CK to the edge triggered flip-flop 110.

[0049] The clock gating circuit 130 includes a latch 131 and an AND gate 132. The latch 131 latches the clock control signal EN at a first level stage T1 of the clock signal CLK and transmits the clock control signal EN at a second level stage T2 of the clock signal CLK, and the AND gate performs a logical AND operation on the latch signal EN_a and the clock signal CLK to generate a clock signal CK.

[0050] The latch 131 includes a first input end, a second input end, and an output end. The AND gate 132 includes a first input end, a second input end, and an output end. The first input end of the latch 131 receives the clock signal CLK, and the second input end receives the clock control signal EN. The first input end of the AND gate 132 receives the clock signal CLK, the second input end is connected to the output end of the latch 131, and the output end provides the clock signal CK.

[0051] Taking an edge-triggered flip-flop triggered by a rising edge as an example, the clock control signal EN is described with a high level indicating an active state and a low level indicating an inactive state. Each clock cycle of the clock signal CLK includes a first level stage T1 and a second level stage T2 having a high level and a low level, respectively, between adjacent rising edges. The clock signal CK provides a trigger edge for the edge-triggered flip-flop 110, and the edge-triggered flip-flop 110 transfers input data from the input end to the output end at the trigger edge.

[0052] 5, the input data Di and the clock control signal EN each have a signal delay Td relative to the edge of the clock signal. The areas between the minimum delay Tdmin and the maximum delay Tdmax of the signal delay Td are represented by the shaded areas. The signal delay Td of the clock control signal EN varies between the minimum delay Tdmin and the maximum delay Tdmax.

[0053] As shown in FIG. 5, the minimum delay Tdmin and the maximum delay Tdmax are in the first level stage T1 and the second level stage T2, respectively, and the inversion operation of the clock control signal EN may occur in the first level stage T1 of the clock signal CLK and may also occur in the second level stage T2 of the clock signal CLK.

[0054] At time t0, the clock signal CLK reaches the first rising edge and the clock control signal EN is valid. In the clock cycle starting at time t0, the clock control signal EN flips from an valid state to an invalid state. At the first level stage T1 of the clock signal CLK, the signal level of the latch signal EN_a at the output end of the latch 131 maintains its previous state, i.e., a high level. At the second level stage T2 of the clock signal CLK, the latch 131 transmits the clock control signal EN from the input end to the output end.

[0055] When the signal delay Td of the clock control signal EN is less than or equal to the first level step T1 of the clock signal CLK, the latch signal EN_a is a copy version of the clock signal CLK in the clock cycle in which the clock control signal is inverted. When the signal delay Td of the clock control signal EN is greater than the first level step T1 of the clock signal CLK, a glitch appears in the latch signal EN_a in the second level step T2 of the clock signal CLK. The clock signal CK is the AND operation result of the clock signal CLK and the latch signal EN_a, which can eliminate the glitch of the latch signal EN_a in the second level step T2 of the clock signal CLK.

[0056] Therefore, in the clock cycle starting from time t0, the clock gating circuit 130 copies the clock signal CLK to the clock signal CK and provides the rising edge of the clock signal CK. The signal level of the output data Do of the edge-triggered flip-flop 110 matches the signal level of the input data Di at time t0, for example, the low level shown in FIG.

[0057] At time t1, the clock signal CLK reaches a second rising edge and the clock control signal EN is in an invalid state. In the clock cycle starting from time t1, the clock control signal EN maintains its invalid state. In the first level stage T1 of the clock signal CLK, the signal level of the latch signal EN_a at the output end of the latch 131 maintains its previous state, i.e., a low level. In the second level stage T2 of the clock signal CLK, the latch 131 transmits the clock control signal EN from the input end to the output end. In this clock cycle, since the clock control signal EN maintains a low level state, EN_a also maintains a low level, and the clock signal CK maintains a low level due to the product operation of the clock signal CLK and the latch signal EN_a.

[0058] At time t2, the clock signal CLK reaches the third rising edge, and the clock control signal EN is in an invalid state. In the clock cycle starting at time t2, the clock control signal EN inverts from an invalid state to an valid state. In the first level step T1 of the clock signal CLK, the signal level of the latch signal EN_a at the output end of the latch 131 maintains its previous state, i.e., a low level. In the second level step T2 of the clock signal CLK, the latch 131 transmits the clock control signal EN from the input end to the output end. If the signal delay Td of the clock control signal EN is less than or equal to the first level step T1 of the clock signal CLK, in the clock cycle in which the clock control signal inverts, the latch signal EN_a is a copy version of the clock signal CLK. If the signal delay Td of the clock control signal EN is greater than the first level step T1 of the clock signal CLK, a glitch appears in the latch signal EN_a in the second level step T2 of the clock signal CLK. The clock signal CK is a logical AND operation result of the clock signal CLK and the latch signal EN_a, and the logical AND operation can eliminate the glitch of the latch signal EN_a at the second level stage T2 of the clock signal CLK.

[0059] Therefore, in the two clock cycles starting from time t1, the clock gating circuit 130 disables the clock signal CLK and does not provide a rising edge of the clock signal CK, and the signal level of the output data Do of the edge-triggered flip-flop 110 matches the signal level of the previous clock cycle, for example, a low level as shown in FIG. 5.

[0060] The above-mentioned clock gating circuit 130 controls the transmission of the clock signal according to the state of the clock control signal EN.

[0061] In the clock cycle when the clock control signal EN flips from an active state to an inactive state, the clock gating circuit 130 copies the clock signal CLK to the clock signal CK. At this time, the clock signal CK provides a trigger edge for the edge-triggered flip-flop 110. The clock gating circuit 130 enables clock inversion and data transmission for the edge-triggered flip-flop 110. The output data Do 110 provided by the edge-triggered flip-flop 110 is the input data Di of the current trigger edge.

[0062] In a clock cycle in which the clock control signal EN is inverted from an invalid state to an valid state, the clock gating circuit 130 disables the clock signal CLK and maintains the clock signal CK at a predetermined level. At this time, the clock signal CK cannot provide a trigger edge for the edge-triggered flip-flop 110, and the clock gating circuit 130 disables the clock inversion and data transmission of the edge-triggered flip-flop 110. The edge-triggered flip-flop 110 holds the input data Di of the previous trigger edge, so that the dynamic power consumption of the edge-triggered flip-flop 110 can be reduced.

[0063] The above-mentioned clock gating circuit 130 does not have high timing requirements for the clock control signal EN. If it is desired to disable data transmission at a predetermined time, the clock control signal EN can be inverted from an active state to an inactive state in the last complete clock cycle before the predetermined time, and the clock control signal EN can be inverted from an inactive state to an active state in the last clock cycle starting from the predetermined time.

[0064] The inventors have noted that the trigger unit provided in the standard cell library of the digital circuit EDA uses the above-mentioned clock gating circuit 130. The clock gating circuit 130 includes a latch 131 for removing glitches that may appear in the clock signal CK of the edge trigger flip-flop 110.

[0065] However, a lot of hardware logic is used in the latch 131, and the operation power consumption of the clock gating circuit 130 itself becomes too high. The operation power consumption of the clock gating circuit 130 itself may even exceed the power consumption of the edge triggered flip-flops reduced by clock gating. In the trigger unit, the clock gating circuit 130 can provide a clock signal CK to multiple edge triggered flip-flops 110 in a flip-flop group. When using the clock gating circuit 130, the circuit design restriction is that the number of edge triggered flip-flops in the flip-flop group is 3 to 8 or more, so that the operation power consumption of the clock gating circuit 130 itself in the trigger unit 200 can be reliably smaller than the power consumption of some edge triggered flip-flops 110 reduced by the clock gating circuit 130.

[0066] Furthermore, the inventor noted that most conventional EDA tools can obtain the signal delay Td of the clock control signal EN, and the signal delay Td of the clock control signal EN can be calculated and set using optimized circuit design and circuit simulation, so that the range of the minimum delay Tdmin and maximum delay Tdmax of the signal delay Td is in the selected level step of the clock signal CLK.

[0067] The inventors have designed the clock gating circuit 230 and the clock gating circuit 330 described below, and different clock gating circuits can be selected according to the delay conditions of the clock control signal EN, and the same function as the clock gating circuit 130 can be obtained without using a latch. In the standard cell library of the digital circuit EDA, the clock gating circuit 230 and the clock gating circuit 330 can be used in the redesigned trigger unit. Therefore, the power consumption of the integrated circuit can be further reduced, the cost of the trigger unit can be reduced, and the power consumption of the clock gating circuit itself can be reduced, and the above-mentioned circuit design limitations can be broken through.

[0068] 6 shows a schematic circuit diagram of a clock gating circuit according to a first embodiment of the present invention. Referring to FIG. 3, the clock gating circuit 230 and the edge triggered flip-flop 110 together form a trigger unit, and the clock gating circuit 230 provides a clock signal CK to the edge triggered flip-flop 110.

[0069] The clock gating circuit 230 includes a NOT gate 231 and an OR gate 232. In the clock gating circuit 230, the clock signal CK is the result of a logical OR operation between the clock signal CLK and an inverted signal EN_a of the clock control signal EN.

[0070] The OR gate 232 includes a first input terminal, a second input terminal, and an output terminal. The NOT gate 231 includes an input terminal and an output terminal. The first input terminal of the OR gate 232 receives the clock signal CLK. The second input terminal of the OR gate 232 is connected to the output terminal of the NOT gate 231 and receives an inverted signal EN_a of the clock control signal EN through the NOT gate 231. The output terminal of the OR gate 232 provides the clock signal CK.

[0071] In this embodiment, an edge-triggered flip-flop triggered by a rising edge is taken as an example, and the clock control signal EN is described with a high level indicating an active state and a low level indicating an inactive state. Each clock cycle of the clock signal CLK includes a first level stage T1 and a second level stage T2 having a high level and a low level, respectively, between adjacent rising edges. The clock signal CK provides a trigger edge for the edge-triggered flip-flop 110, and the edge-triggered flip-flop 110 transmits input data from the input end to the output end at the trigger edge.

[0072] In this embodiment, the input data Di and the clock control signal EN each have a signal delay Td relative to an edge of the clock signal. The areas between the minimum delay Tdmin and the maximum delay Tdmax of the signal delay Td are represented by the shaded areas. The signal delay Td of the clock control signal EN varies between the minimum delay Tdmin and the maximum delay Tdmax.

[0073] 7a, the minimum delay Tdmin and the maximum delay Tdmax of the clock control signal EN are both in the first level stage T1, and the inversion operation of the clock control signal EN can only occur in the first level stage T1 of the clock signal CLK. The starting edge of the first level stage T1 is a rising edge.

[0074] At time t0, the clock signal CLK reaches the first rising edge and the clock control signal EN is valid. In the clock cycle starting at time t0, the clock control signal EN inverts from a valid state to an invalid state. The clock signal CK is the result of a logical OR operation of the clock signal CLK and the inverted signal EN_a. In the first level stage T1 of the clock signal CLK, the clock signal CK is always at a high level. In the second level stage T2 of the clock signal CLK, the clock signal CK is always at a high level. Therefore, if the signal delay Td of the clock control signal EN is less than or equal to the first level stage T1 of the clock signal CLK, in the clock cycle in which the clock control signal inverts from a valid state to an invalid state, the clock signal CK maintains a high level.

[0075] Therefore, when the signal delay Td of the clock control signal EN is less than or equal to the first level step T1 of the clock signal CLK, in the clock cycle starting from time t0, the clock gating circuit 230 disables the clock signal CLK and provides a rising edge of the clock signal CK, and after the setup time after the rising edge has elapsed, the signal level of the output data Do provided by the edge-triggered flip-flop 110 matches the signal level of the input data Di at time t0, for example, a low level as shown in FIG. 7a.

[0076] At time t1, the clock signal CLK reaches a second rising edge, and the clock control signal EN is invalid. In the clock cycle starting from time t1, the clock control signal EN remains invalid, for example, at a low level as shown in FIG. 7a. The clock signal CK is the logical OR operation result of the clock signal CLK and the inverted signal EN_a. In this clock cycle, since the clock control signal EN is always low, the inverted signal EN_a is always high, and the result of the OR operation, i.e., the clock signal CK, is also always high. Since the clock signal CK does not provide a rising edge, the signal level of the output data Do of the edge-triggered flip-flop 110 is consistent with the signal level of the previous clock cycle, for example, at a low level as shown in FIG. 7a.

[0077] At time t2, the clock signal CLK reaches its third rising edge and the clock control signal EN is disabled. In the clock cycle starting at time t2, the clock control signal EN inverts from an disabled state to an enabled state. The clock signal CK is the logical OR result of the clock signal CLK and the inverted signal EN_a. In the first level stage T1 of the clock signal CLK, the clock signal CK is always at a high level. In the second level stage T2 of the clock signal CLK, the clock signal CK is always at a low level. Thus, if the signal delay Td of the clock control signal EN is less than or equal to the first level stage T1 of the clock signal CLK, in the clock cycle in which the clock control signal inverts from an disabled state to an enabled state, the clock signal CK is a copy version of the clock signal CLK.

[0078] Therefore, when the signal delay Td of the clock control signal EN is less than or equal to the first level step T1 of the clock signal CLK, in the clock cycle starting from time t2, the clock gating circuit 230 copies the clock signal CLK to the clock signal CK, but does not provide a rising edge of the clock signal, and the signal level of the output data Do of the edge-triggered flip-flop 110 matches the signal level of the previous clock cycle, for example, a low level as shown in FIG. 7a.

[0079] Further, at time t3, the clock signal CLK reaches the fourth rising edge. The clock control signal EN is valid during the entire clock cycle starting from time t3, and the clock signal CK is a copy version of the clock signal CLK. The clock gating circuit 230 copies the clock signal CLK to the clock signal CK and provides the rising edge of the clock signal CK, thereby enabling the clock signal and data transmission of the edge-triggered flip-flop. After the setup time has elapsed after the rising edge, the signal level of the output data Do provided by the edge-triggered flip-flop 110 matches the signal level of the input data Di at time t3, i.e., high level. After time t3, the clock control signal EN remains valid, and the clock signal CK is a copy version of the clock signal CLK, and when the clock signal CLK transitions, the edge-triggered flip-flop 110 receives the input data of the data input terminal and transmits it to the data output terminal at the trigger edge of the second clock signal.

[0080] 7b, the minimum delay Tdmin and the maximum delay Tdmax of the clock control signal EN are both in the second level stage T2, and the inversion operation of the clock control signal EN can only occur in the second level stage T1 of the clock signal CLK. The starting edge of the second level stage T2 is a falling edge.

[0081] At time t0, the clock signal CLK reaches the first rising edge and the clock control signal EN is valid. In the clock cycle starting at time t0, the clock control signal EN inverts from an active state to an inactive state. The clock signal CK is the logical OR result of the clock signal CLK and the inverted signal EN_a. In the first level stage T1 of the clock signal CLK, the clock signal CK is always at a high level. In the second level stage T2 of the clock signal CLK, the signal level of the clock signal CK is related to the signal delay of the clock control signal EN. If the signal delay Td of the clock control signal EN is greater than the first level stage T1 of the clock signal CLK, in the second level stage T2 of the clock signal CLK, the clock signal CK inverts from a high level to a low level at the start time of the second level stage T2, and then inverts from a low level to a high level at a time after the time ta of the second level stage T2, and the transition may be repeated, resulting in a glitch.

[0082] Thus, if the signal delay Td of the clock control signal EN is greater than the first level step T1 of the clock signal CLK, a glitch appears in the clock signal CK generated by the clock gating circuit 230 in the clock cycle starting at time t0. The glitch provides an additional rising edge that changes with the clock control signal EN, and after a setup time has elapsed after the additional rising edge, the signal level of the output data Do provided by the edge-triggered flip-flop 110 coincides with the signal level of the input data Di at the additional rising edge. On the one hand, the input data Di of the edge-triggered flip-flop 110 is in an uncertain state due to its own signal delay, and on the other hand, the additional rising edge provided by the glitch of the clock signal CK overlaps with the uncertain state of the input data Di. Thus, after a setup time has elapsed after the additional rising edge, the output data Do provided by the edge-triggered flip-flop 110 coincides with the signal level of the additional rising edge and is in the uncertain state of, for example, FIG. 7b.

[0083] At time t1, the clock signal CLK reaches a second rising edge and the clock control signal EN is invalid. Similar to Fig. 7a, in the clock cycle starting from time t1, the clock signal CK remains at a high level and does not provide a rising edge or a falling edge. The signal level of the output data Do of the edge-triggered flip-flop 110 matches the signal level of the previous clock cycle and is in an uncertain state, for example, as shown in Fig. 7b.

[0084] At time t2, the clock signal CLK reaches the third rising edge and the clock control signal EN is invalid. In the clock cycle starting at time t2, the clock control signal EN inverts from an invalid state to an valid state. The clock signal CK is the logical OR result of the clock signal CLK and the inverted signal EN_a. At the first level stage T1 of the clock signal CLK, the clock signal CK is always at a high level. At the second level stage T2 of the clock signal CLK, the signal level of the clock signal CK is related to the signal delay of the clock control signal EN. If the signal delay Td of the clock control signal EN is greater than the first level stage T1 of the clock signal CLK, at the second level stage T2 of the clock signal CLK, it will be the same as the inversion time of the clock control signal EN, and the clock signal CK will invert from a high level state to a low level state, causing a glitch.

[0085] Therefore, if the signal delay Td of the clock control signal EN is greater than the first level step T1 of the clock signal CLK, a glitch will occur in the clock signal CK generated by the clock gating circuit 230 in the clock cycle starting from time t2. However, the glitch can only provide an additional falling edge that changes with the clock control signal EN and may transition to provide a trigger edge of the edge-triggered flip-flop 110. Therefore, the signal level of the output data Do of the edge-triggered flip-flop 110 will match the signal level of the previous clock cycle and will be in the uncertain state shown in, for example, FIG. 7b.

[0086] Further, at time t3, the clock signal CLK reaches the fourth rising edge. The clock control signal EN is valid for the entire clock cycle starting from time t3, and the clock signal CK is a copy version of the clock signal CLK. The clock gating circuit 230 copies the clock signal CLK to the clock signal CK and provides the rising edge of the clock signal CK, so that the edge-triggered flip-flop can enable the clock signal and data transmission. After the setup time has elapsed after the rising edge, the signal level of the output data Do provided by the edge-triggered flip-flop 110 matches the signal level of the input data Di at time t3, i.e., high level. After time t3, the clock control signal EN remains valid, and the clock signal CK is a copy version of the clock signal CLK, and when the clock signal CLK transitions, the edge-triggered flip-flop 110 receives the input data of the data input terminal and transmits it to the data output terminal at the trigger edge of the second clock signal.

[0087] The above-mentioned clock gating circuit 230 has different circuit characteristics when the delay condition of the clock control signal EN is different. Under the condition that the minimum delay Tdmin and the maximum delay Tdmax of the clock control signal EN are both in the first level stage T1 and the start edge of the first level stage T1 is a rising edge, the clock gating circuit 230 shown in FIG. 6 is selected instead of the clock gating circuit 130 shown in FIG. 4.

[0088] In clock cycles in which the clock control signal EN remains in an enabled state, the clock gating circuit 230 copies the clock signal CLK to the clock signal CK and provides the clock signal CK to the clock input of the edge-triggered flip-flop 110, and in clock cycles in which the clock control signal EN remains in an disabled state, the clock gating circuit 230 disables the clock signal CLK. Thus, the clock gating circuit 230 can be used to disable the clock inversion and data transmission of the edge-triggered flip-flop 110.

[0089] In the clock cycle when the clock control signal EN inverts from an active state to an inactive state, the clock gating circuit 230 disables the clock signal CLK and maintains the clock signal CK at a predetermined level. At this time, the clock signal CK still provides a trigger edge for the edge-triggered flip-flop 110, the clock gating circuit 230 enables the data transmission of the edge-triggered flip-flop 110, and the output data Do provided by the edge-triggered flip-flop 110 is the input data Di of the current trigger edge. The clock gating circuit 230 disables the clock inversion of the edge-triggered flip-flop 110, thereby reducing the dynamic power consumption of the edge-triggered flip-flop 110 caused by the inversion of the clock signal CK.

[0090] In a clock cycle in which the clock control signal EN inverts from an invalid state to an valid state, the clock gating circuit 230 copies the clock signal CLK to the clock signal CK, enabling clock inversion of the edge triggered flip-flop 110. At this time, the clock signal CK cannot provide a trigger edge for the edge triggered flip-flop 110, so the clock gating circuit 230 disables the data transmission of the edge triggered flip-flop 110, causing the edge triggered flip-flop 110 to maintain the input data Di of the previous trigger edge, thereby reducing the dynamic power consumption of the edge triggered flip-flop 110 due to data transmission.

[0091] The timing requirement of the clock gating circuit 230 for the clock control signal EN is that the inversion of the clock control signal EN occurs at a level step after the trigger edge of one clock cycle of the clock signal CLK, in this example the first level step T1. If it is desired to disable data transmission at a given time, the inversion operation of the clock control signal EN from an enabled state to an disabled state is completed within the first level step T1 of the last complete clock cycle before the given time, and the inversion operation of the clock control signal EN from an disabled state to a enabled state is completed within the first level step T1 of the clock signal CLK of the last clock cycle starting from the given time.

[0092] Compared with the clock gating circuit 130 shown in Fig. 4, the clock gating circuit 230 according to the present embodiment omits a latch, and less hardware logic is used in the clock gating circuit 230, and the clock gating circuit 230 consumes less operating power. In the trigger unit, any number of edge triggered flip-flops 110 can share the clock gating circuit 230 to form a flip-flop group. When the flip-flop group includes any number of edge triggered flip-flops 110, the increase in power consumption due to the power consumption of the clock gating circuit 230 itself is much smaller than the power consumption of the edge triggered flip-flops 110 reduced by clock gating, and therefore the power consumption of the trigger unit can be constantly reduced.

[0093] 8 shows a schematic circuit diagram of a clock gating circuit according to a second embodiment of the present invention. Referring to FIG. 3, the clock gating circuit 330 and the edge triggered flip-flop 110 together form a trigger unit, and the clock gating circuit 330 provides a clock signal CK to the edge triggered flip-flop 110.

[0094] The clock gating circuit 330 includes an AND gate 331. In the clock gating circuit 330, the clock signal CK is the result of a logical AND operation between the clock signal CLK and the clock control signal EN.

[0095] The AND gate 331 includes a first input terminal, a second input terminal and an output terminal, the first input terminal of the AND gate 331 receives a clock signal CLK, the second input terminal receives a clock control signal EN, and the output terminal provides a clock signal CK.

[0096] In this embodiment, an edge-triggered flip-flop triggered by a falling edge is taken as an example, and the clock control signal EN is described with a high level indicating an active state and a low level indicating an inactive state. Each clock cycle of the clock signal CLK includes a first level stage T1 and a second level stage T2 having a low level and a high level, respectively, between adjacent falling edges. The clock signal CK provides a trigger edge for the edge-triggered flip-flop 110, and the edge-triggered flip-flop 110 transmits input data from the input end to the output end at the trigger edge.

[0097] In this embodiment, the input data Di and the clock control signal EN each have a signal delay Td relative to an edge of the clock signal. The areas between the minimum delay Tdmin and the maximum delay Tdmax of the signal delay Td are represented by the shaded areas. The signal delay Td of the clock control signal EN varies between the minimum delay Tdmin and the maximum delay Tdmax.

[0098] 9a, the minimum delay Tdmin and the maximum delay Tdmax of the clock control signal EN are both in the first level stage T1, and the inversion operation of the clock control signal EN can only occur in the first level stage T1 of the clock signal CLK. The starting edge of the first level stage T1 is a falling edge.

[0099] At time t0, the clock signal CLK reaches the first falling edge and the clock control signal EN is valid. In the clock cycle starting at time t0, the clock control signal EN inverts from an valid state to an invalid state. The clock signal CK is the result of a logical AND operation of the clock signal CLK and the clock control signal EN. In the first level stage T1 of the clock signal CLK, the clock signal CK is always at a low level. In the second level stage T2 of the clock signal CLK, the clock signal CK is always at a low level. Therefore, if the signal delay Td of the clock control signal EN is less than or equal to the first level stage T1 of the clock signal CLK, the clock signal CK maintains a low level in the clock cycle in which the clock control signal inverts from an valid state to an invalid state.

[0100] Therefore, when the signal delay Td of the clock control signal EN is less than or equal to the first level step T1 of the clock signal CLK, in the clock cycle starting from time t0, the clock gating circuit 330 disables the clock signal CLK, but provides a falling edge of the clock signal CK, and after the setup time has elapsed after the falling edge, the signal level of the output data Do provided by the edge-triggered flip-flop 110 matches the signal level of the input data Di at time t0, for example, a low level as shown in FIG. 9a.

[0101] At time t1, the clock signal CLK reaches a second falling edge, and the clock control signal EN is invalid. In the clock cycle starting from time t1, the clock control signal EN remains invalid and is at a low level as shown in FIG. 9a. The clock signal CK is the logical AND operation result of the clock signal CLK and the clock control signal EN. In this clock cycle, the clock control signal EN is always low, so the result of the AND operation, i.e., the clock signal CK, is also always low. The clock signal CK does not provide a falling edge, and the signal level of the output data Do of the edge-triggered flip-flop 110 is consistent with the signal level of the previous clock cycle, e.g., the low level as shown in FIG. 9a.

[0102] At time t2, the clock signal CLK reaches the third falling edge and the clock control signal EN is disabled. In the clock cycle starting at time t2, the clock control signal EN flips from the disabled state to the enabled state. The clock signal CK is the logical AND operation result of the clock signal CLK and the clock control signal EN. In the first level stage T1 of the clock signal CLK, the clock signal CK is always at a low level. In the second level stage T2 of the clock signal CLK, the clock signal CK is always at a high level. Thus, the signal delay Td of the clock control signal EN is, for the case below the first level stage T1 of the clock signal CLK, in the clock cycle in which the clock control signal flips from the disabled state to the enabled state, the clock signal CK is a copy version of the clock signal CLK.

[0103] Therefore, when the signal delay Td of the clock control signal EN is less than or equal to the first level step T1 of the clock signal CLK, in the clock cycle starting from time t2, the clock gating circuit 330 copies the clock signal CLK to the clock signal CK, but does not provide a falling edge of the clock signal, and the signal level of the output data Do of the edge-triggered flip-flop 110 matches the signal level of the previous clock cycle, for example, a low level as shown in FIG. 9a.

[0104] Further, at time t3, the clock signal CLK reaches the fourth falling edge. The clock control signal EN is valid for the entire clock cycle starting from time t3, and the clock signal CK is a copy version of the clock signal CLK. The clock gating circuit 330 copies the clock signal CLK to the clock signal CK and provides the falling edge of the clock signal CK, thereby enabling the clock signal and data transmission of the edge-triggered flip-flop. After the setup time has elapsed after the falling edge, the signal level of the output data Do provided by the edge-triggered flip-flop 110 matches the signal level of the input data Di at time t3, i.e., high level. After time t3, the clock control signal EN can continue to be valid, and the clock signal CK is a copy version of the clock signal CLK, and when the clock signal CLK transitions, the edge-triggered flip-flop 110 receives the input data of the data input terminal and transmits it to the data output terminal at the trigger edge of the second clock signal.

[0105] 9b, the minimum delay Tdmin and maximum delay Tdmax of the clock control signal EN are both in the second level stage T2, and the inversion operation of the clock control signal EN can only occur in the second level stage T2 of the clock signal CLK. The starting edge of the second level stage T2 is a rising edge.

[0106] At time t0, the clock signal CLK reaches the first falling edge and the clock control signal EN is valid. In the clock cycle starting at time t0, the clock control signal EN inverts from an valid state to an invalid state. The clock signal CK is the logical AND operation result of the clock signal CLK and the clock control signal EN. In the first level stage T1 of the clock signal CLK, the clock signal CK is always at a low level. In the second level stage T2 of the clock signal CLK, the signal level of the clock signal CK is related to the signal delay of the clock control signal EN. If the signal delay Td of the clock control signal EN is greater than the first level stage T1 of the clock signal CLK, in the second level stage T2 of the clock signal CLK, the clock signal CK may invert from a low level to a high level at the start time of the second level stage T2, and invert from a high level to a low level at some time after the time ta of the second level stage T2, resulting in a transition, thus causing a glitch.

[0107] Thus, if the signal delay Td of the clock control signal EN is greater than the first level step T1 of the clock signal CLK, a glitch appears in the clock signal CK generated by the clock gating circuit 330 in the clock cycle starting at time t0. The glitch provides an additional falling edge that changes with the clock control signal EN, and after the setup time has elapsed after the additional falling edge, the signal level of the output data Do provided by the edge-triggered flip-flop 110 coincides with the signal level of the input data Di at the additional falling edge. On the one hand, the input data Di of the edge-triggered flip-flop 110 is in an uncertain state due to its own signal delay, and on the other hand, the additional falling edge provided by the glitch of the clock signal CK overlaps with the uncertain state of the input data Di. Thus, after the setup time has elapsed after the additional falling edge, the output data Do provided by the edge-triggered flip-flop 110 coincides with the signal level of the additional falling edge and is in the uncertain state of, for example, FIG. 9b.

[0108] At time t1, the clock signal CLK reaches a second falling edge and the clock control signal EN is invalid. Similar to Fig. 9a, in the clock cycle starting from time t1, the clock signal CK remains at a low level and does not provide a rising edge or a falling edge. The signal level of the output data Do of the edge-triggered flip-flop 110 matches the signal level of the previous clock cycle and is in an uncertain state as shown in Fig. 9b, for example.

[0109] At time t2, the clock signal CLK reaches the third falling edge and the clock control signal EN is disabled. In the clock cycle starting at time t2, the clock control signal EN inverts from the disabled state to the enabled state. The clock signal CK is the logical AND operation result of the clock signal CLK and the clock control signal EN. In the first level stage T1 of the clock signal CLK, the clock signal CK is always at a low level. In the second level stage T2 of the clock signal CLK, the signal level of the clock signal CK is related to the signal delay of the clock control signal EN. If the signal delay Td of the clock control signal EN is greater than the first level stage T1 of the clock signal CLK, the clock signal CK inverts from a low level state to a high level state at the second level stage T2 of the clock signal CLK, similar to the inversion time of the clock control signal EN, and thus a glitch occurs.

[0110] Therefore, if the signal delay Td of the clock control signal EN is greater than the first level step T1 of the clock signal CLK, a glitch will appear in the clock signal CK generated by the clock gating circuit 330 in the clock cycle starting from time t2. However, the glitch can only provide an additional rising edge that changes with the clock control signal EN, and the transition may provide a trigger edge of the edge-triggered flip-flop 110. Therefore, the signal level of the output data Do of the edge-triggered flip-flop 110 will match the signal level of the previous clock cycle and will be in the uncertain state shown in FIG. 9b, for example.

[0111] Further, at time t3, the clock signal CLK reaches the fourth falling edge. The clock control signal EN is valid for the entire clock cycle starting from time t3, and the clock signal CK is a copy version of the clock signal CLK. The clock gating circuit 330 copies the clock signal CLK to the clock signal CK and provides the falling edge of the clock signal CK, thereby enabling the clock signal and data transmission of the edge-triggered flip-flop. After the setup time has elapsed after the falling edge, the signal level of the output data Do provided by the edge-triggered flip-flop 110 matches the signal level of the input data Di at time t3, i.e., high level. After time t3, the clock control signal EN can continue to be valid, and the clock signal CK is a copy version of the clock signal CLK, and when the clock signal CLK transitions, the edge-triggered flip-flop 110 receives the input data of the data input terminal and transmits it to the data output terminal at the trigger edge of the second clock signal.

[0112] The above-mentioned clock gating circuit 330 has different circuit characteristics when the delay condition of the clock control signal EN is different. Under the condition that the minimum delay Tdmin and the maximum delay Tdmax of the clock control signal EN are both in the first level stage T1 and the start edge of the first level stage T1 is a falling edge, the clock gating circuit 330 shown in FIG. 8 is selected instead of the clock gating circuit 130 shown in FIG. 4.

[0113] In clock cycles in which the clock control signal EN remains in an enabled state, the clock gating circuit 330 copies the clock signal CLK to the clock signal CK and provides the clock signal CK to the clock input of the edge-triggered flip-flop 110, and in clock cycles in which the clock control signal EN remains in an disabled state, the clock gating circuit 330 disables the clock signal CLK. Thus, the clock gating circuit 330 can be used to disable clock inversion and data transmission of the edge-triggered flip-flop 110.

[0114] In the clock cycle when the clock control signal EN inverts from an active state to an inactive state, the clock gating circuit 330 disables the clock signal CLK and maintains the clock signal CK at a predetermined level. At this time, the clock signal CK still provides a trigger edge for the edge-triggered flip-flop 110, the clock gating circuit 330 enables the data transmission of the edge-triggered flip-flop 110, and the output data Do provided by the edge-triggered flip-flop 110 is the input data Di of the current trigger edge. The clock gating circuit 330 disables the clock inversion of the edge-triggered flip-flop 110, thereby reducing the dynamic power consumption of the edge-triggered flip-flop 110 caused by the inversion of the clock signal CK.

[0115] In a clock cycle in which the clock control signal EN inverts from an invalid state to an valid state, the clock gating circuit 330 copies the clock signal CLK to the clock signal CK, enabling clock inversion of the edge triggered flip-flop 110. At this time, the clock signal CK cannot provide a trigger edge for the edge triggered flip-flop 110, so the clock gating circuit 330 disables the data transmission of the edge triggered flip-flop 110, causing the edge triggered flip-flop 110 to maintain the input data Di of the previous trigger edge, thereby reducing the dynamic power consumption of the edge triggered flip-flop 110 due to data transmission.

[0116] The timing requirement of the clock gating circuit 330 for the clock control signal EN is that the inversion of the clock control signal EN occurs at a level step after the trigger edge of one clock cycle of the clock signal CLK, in this example the first level step T1. If it is desired to disable data transmission at a given time, the inversion operation of the clock control signal EN from an enabled state to an disabled state is completed within the first level step T1 of the last complete clock cycle before the given time, and the inversion operation of the clock control signal EN from an disabled state to a enabled state is completed within the first level step T1 of the clock signal CLK of the last clock cycle starting from the given time.

[0117] 4, the clock gating circuit 330 according to the present embodiment omits a latch, and the clock gating circuit 330 uses less hardware logic, and consumes less operating power. In the trigger unit, any number of edge triggered flip-flops 110 can share the clock gating circuit 330 to form a flip-flop group. When the flip-flop group includes any number of edge triggered flip-flops 110, the increase in power consumption due to the power consumption of the clock gating circuit 330 itself is much smaller than the power consumption of the edge triggered flip-flops 110 reduced by clock gating, and therefore the power consumption of the trigger unit can be constantly reduced.

[0118] FIG. 10 shows a flowchart of a method for designing a trigger unit according to a third embodiment of the present invention.

[0119] The method for designing the trigger unit includes steps S01 to S07.

[0120] In step S01, the signal delay Td of the clock control signal EN in the digital circuit is analyzed.

[0121] The signal delay of the clock control signal EN is the calculation time from the clock edge until the clock control signal is stable and inverted when a digital circuit generates the clock control signal. Most existing EDA tools can obtain the signal delay Td of the clock control signal EN. The signal delay Td varies within a range between a minimum delay Tdmin and a maximum delay Tdmax, for example.

[0122] Next, a clock gating circuit of an edge trigger flip-flop is selected from a plurality of different types of clock gating circuits according to the signal delay Td of the clock control signal EN.

[0123] A better solution for low power consumption is realized by selecting from several different types of clock gating circuits according to the signal delay Td of the clock control signal EN and applying a combination of the multiple different types of clock gating circuits. The clock gating circuit performs a logic operation on the clock control signal EN and the clock signal CLK to generate the clock signal CK.

[0124] Each clock cycle of the clock signal CLK includes successive first and second level steps T1 and T2, each having a first level and a second level that are inverted from each other, and when the first level is a high level, the starting edge of the first level step T1 is a rising edge, and when the first level is a low level, the starting edge of the first level step T1 is a falling edge.

[0125] In step S02, it is determined whether the delay range of the clock control signal is at the first level.

[0126] In this step, either the first clock gating circuit or the second clock gating circuit is selected according to the type of delay range of the clock control signal EN.

[0127] The signal delay Td of the clock control signal EN varies between a minimum delay Tdmin and a maximum delay Tdmax. The minimum delay Tdmin and the maximum delay Tdmax of the clock control signal EN are compared with the first-level stage T1 of the clock signal CLK to determine whether the delay range of the clock control signal EN is within the first-level stage.

[0128] When the signal delay Td of the clock control signal EN satisfies the conditions Tdmin < T1 and Tdmax < T1, the delay range of the clock control signal EN is within the first-level stage. At this time, the inversion operation of the clock control signal EN can occur only at a single-level stage of the clock signal CLK. Further, step S03 is executed, and either the first clock gating circuit shown in FIG. 6 or the second clock gating circuit shown in FIG. 8 is selected.

[0129] When the signal delay Td of the clock control signal EN satisfies the conditions Tdmin < T1 and Tdmax > T1, the delay range of the clock control signal EN includes the period in which the first-level stage and the second-level stage are adjacent to each other. At this time, the inversion operation of the clock control signal EN can occur at any level stage of the clock signal CLK. Further, step S06 is executed, and the third clock gating circuit shown in FIG. 4 is selected.

[0130] In step S03, further, the type of the start edge of the first-level stage is determined.

[0131] In this step, either the first clock gating circuit or the second clock gating circuit is selected according to the type of the start edge of the first-level stage T1.

[0132] When the start edge of the first-level stage T1 is a rising edge, step S04 is executed, and the first clock gating circuit shown in FIG. 6 is selected.

[0133] As mentioned above, in the clock gating circuit shown in FIG. 6, in a clock cycle in which the clock control signal EN is inverted from an enabled state to an disabled state, the clock signal CK of the clock gating circuit disables the clock signal CLK, but provides a rising edge of the clock signal CK. In a clock cycle in which the clock control signal EN is inverted from an disabled state to a enabled state, the clock gating circuit copies the clock signal CLK to the clock signal CK, but does not provide a rising edge of the clock signal. Therefore, as long as the clock control signal EN is inverted at the first level stage T1 of the clock signal CLK, and the starting edge of the first level stage T1 is a rising edge, the glitch of the clock signal of the edge trigger flip-flop can be eliminated, so that the edge trigger flip-flop can operate normally.

[0134] If the starting edge of the first level stage T1 is a falling edge, execute step S05 to select the second clock gating circuit shown in FIG.

[0135] As described above, in the clock gating circuit shown in FIG. 8, in the clock cycle when the clock control signal EN is inverted from the valid state to the invalid state, the clock signal CK of the clock gating circuit masks the clock signal CLK, but provides the falling edge of the clock signal CK. In the clock cycle when the clock control signal EN is inverted from the invalid state to the valid state, the clock gating circuit copies the clock signal CLK to the clock signal CK, but does not provide the falling edge of the clock signal. Therefore, as long as the clock control signal EN is inverted at the first level stage T1 of the clock signal CLK, and the starting edge of the first level stage T1 is the falling edge, the glitch of the clock signal of the edge trigger flip-flop can be removed, so that the edge trigger flip-flop can operate normally.

[0136] In step S06, the third clock gating circuit shown in FIG. 4 is selected.

[0137] As described above, the clock gating circuit shown in FIG. 4 includes a latch and can remove glitches in the clock signal of the edge-triggered flip-flop regardless of whether the clock control signal EN inverts at the first level stage T1 or the second level stage T2 of the clock signal CLK, thereby allowing the edge-triggered flip-flop to operate normally.

[0138] In step S07, combine at least one edge-triggered flip-flop and the selected clock gating circuit into a trigger unit.

[0139] For example, the output terminal of the selected clock gating circuit is coupled to the clock input terminal of at least one edge-triggered flip-flop to be combined with a trigger unit.

[0140] FIG. 11 shows a method of combining a clock gating circuit and an edge trigger flip-flop in the design method of the trigger unit shown in FIG.

[0141] Take the first clock gating circuit shown in Figure 6 as an example. In a clock cycle in which the clock control signal EN is inverted from an enabled state to an disabled state, the clock signal CK of the clock gating circuit of the first clock gating circuit masks the clock signal CLK but provides a rising edge of the clock signal CK.

[0142] According to the trigger edge of the edge-triggered flip-flop 110, the type of the edge-triggered flip-flop 110 can be divided into rising edge triggered or falling edge triggered. After selecting the type of the clock gating circuit, the edge-triggered flip-flop and the clock gating circuit are combined into a trigger unit. The first clock gating circuit and the second clock gating circuit directly generate the second clock signal to provide the trigger edge for any type of edge-triggered flip-flop.

[0143] A trigger unit is formed by combining a selected clock gating circuit with an edge-triggered flip-flop to provide a trigger edge using a triggering method corresponding to the type of edge-triggered flip-flop.

[0144] 11, the method for combining trigger units includes steps S11 to S14. In step S11, a first clock gating circuit is selected. In step S12, it is further determined whether the type of the selected edge trigger flip-flop is rising edge or falling edge.

[0145] If the edge-triggered flip-flop is rising edge triggered, execute step S13. In step S13, the first clock gating circuit takes the rising edge provided by the second clock signal CK generated in the clock cycle in which the clock control signal EN inverts from an active state to an inactive state as the trigger edge of the edge-triggered flip-flop, that is, at the trigger edge of the current clock cycle in which the clock control signal CK inverts, the edge-triggered flip-flop can transmit data.

[0146] If the edge-triggered flip-flop is a falling-edge-triggered flip-flop, execute step S14. In step S14, the first clock gating circuit takes the falling edge provided by the second clock signal CK generated in the clock cycle before the clock cycle in which the clock control signal EN inverts from an enabled state to an disabled state as the trigger edge of the edge-triggered flip-flop, that is, the edge-triggered flip-flop can transmit data at the trigger edge of the clock cycle before the clock cycle in which the clock control signal CK inverts.

[0147] FIG. 12 shows a method of combining a clock gating circuit and an edge trigger flip-flop in the design method of the trigger unit shown in FIG.

[0148] Take the first clock gating circuit shown in Fig. 6 as an example. In the first clock gating circuit, in a clock cycle in which the clock control signal EN is inverted from an enabled state to an disabled state, the clock signal CK of the clock gating circuit masks the clock signal CLK but provides a rising edge of the clock signal CK.

[0149] According to the trigger edge of the edge-triggered flip-flop 120, the type of the edge-triggered flip-flop 120 can be divided into rising edge trigger and falling edge trigger. After selecting the type of the clock gating circuit, the edge-triggered flip-flop and the clock gating circuit are combined into a trigger unit. The first clock gating circuit and the second clock gating circuit can directly generate the second clock signal, and invert the second clock signal to generate the third clock signal, providing a trigger edge for any type of edge-triggered flip-flop.

[0150] When the selected clock gating circuit and the edge-triggered flip-flop are combined into a trigger unit, a trigger edge is provided for the triggering method corresponding to the type of the edge-triggered flip-flop.

[0151] 12, another method for combining trigger units includes steps S21 to S24. In step S21, a first clock gating circuit is selected. In step S22, it is further determined whether the type of the selected edge trigger flip-flop is rising edge or falling edge.

[0152] If the edge-triggered flip-flop is rising edge triggered, execute step S23. In step S23, the first clock gating circuit takes the rising edge provided by the second clock signal CK generated in the clock cycle in which the clock control signal EN inverts from an enabled state to an disabled state as the trigger edge of the edge-triggered flip-flop, that is, at the trigger edge of the current clock cycle in which the clock control signal CK inverts, the edge-triggered flip-flop can transmit data.

[0153] If the edge-triggered flip-flop is falling edge triggered, execute step S24. In step S24, the second clock signal is inverted to generate a third clock signal, the first clock gating circuit generates a second clock signal CK in a clock cycle in which the clock control signal EN inverts from an enabled state to an disabled state, and the falling edge provided by the inverted signal of the second clock signal CK is taken as the trigger edge of the edge-triggered flip-flop, i.e., the trigger edge of the current clock cycle in which the clock control signal CK is inverted, so that the edge-triggered flip-flop can transmit data.

[0154] The above design method of the trigger unit describes one of three types of clock gating circuits of the edge triggered flip-flop according to the signal delay of the clock control signal. In the design of the digital circuit, the clock control signal can be controlled to be inverted only at the first level stage of the clock signal CLK. Therefore, according to the type of the edge triggered flip-flop, the clock gating circuit of the edge triggered flip-flop can be selected from two types of clock gating circuits.

[0155] In the above trigger unit, the flip-flop triggered by the rising edge and the falling edge of the clock signal is taken as an example, but the edge-triggered flip-flop in the trigger unit shows only one structure. However, the present invention is not limited thereto. It is understood that other edge-triggered flip-flops, such as edge-triggered flip-flops with a reset function, can also be technically improved by applying the present invention.

[0156] It should be noted that in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another and do not necessarily require or imply that an actual relationship or sequence exists between those entities or operations. Furthermore, the terms "comprise", "contain", or any other variation thereof are intended to cover a non-exclusive inclusion, whereby a process, method, article, or device that includes a set of elements includes not only those elements, but also other elements not expressly listed, or elements inherent to the process, method, article, or device. Without further limitation, an element defined by the statement "comprises..." does not exclude the presence of additional identical elements in the process, method, article, or device that includes said element.

[0157] According to the above-mentioned embodiments of the present invention, these embodiments are not exhaustively described in detail, nor are they intended to limit the invention to the specific embodiments described. In light of the above description, it is apparent that many modifications and variations are possible. These embodiments have been selected and described in detail herein in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can effectively utilize the present invention and make modifications based on the present invention. The present invention is limited only by the claims, their full scope and equivalents.

Claims

1. A step of analyzing a signal delay of a clock control signal in a digital circuit, and a step of selecting a clock gating circuit from a plurality of different types of clock gating circuits according to the signal delay of the clock control signal; combining at least one edge-triggered flip-flop and the selected clock gating circuit into a trigger unit. A method for designing a trigger unit, wherein the multiple different types of clock gating circuits enable or disable a first clock signal according to the clock control signal to generate a second clock signal, and the edge-triggered flip-flop transmits data on an edge of the second clock signal.

2. 2. The design method of claim 1, wherein the plurality of different types of clock gating circuits include at least one of a first clock gating circuit and a second clock gating circuit, and the first clock gating circuit and the second clock gating circuit maintain the second clock signal at a predetermined level at least in a clock cycle in which the clock control signal inverts from an active state to an inactive state.

3. 3. The design method according to claim 2, wherein in a clock cycle in which the clock control signal maintains an invalid state, the first clock gating circuit and the second clock gating circuit maintain the second clock signal at the predetermined level.

4. 3. The design method of claim 2, wherein in a clock cycle in which the clock control signal inverts from an invalid state to an valid state, the first clock gating circuit and the second clock gating circuit copy the first clock signal as the second clock signal.

5. 3. The design method of claim 2, wherein the first clock gating circuit and the second clock gating circuit copy the first clock signal as the second clock signal during clock cycles in which the clock control signal remains valid.

6. 3. The design method according to claim 2, wherein the first clock gating circuit performs a logical OR operation on an inverted signal of the clock control signal and the first clock signal to generate the second clock signal.

7. 3. The design method according to claim 2, wherein the second clock gating circuit performs a logical AND operation on the clock control signal and the first clock signal to generate the second clock signal.

8. 3. The design method of claim 2, wherein the plurality of different types of clock gating circuits further includes a third clock gating circuit, the third clock gating circuit maintaining the second clock signal at a predetermined level at least in a next clock cycle in which the clock control signal inverts from an active state to an inactive state.

9. 9. The design method according to claim 8, wherein the third clock gating circuit performs a logical AND operation on the latched signal of the clock control signal and the first clock signal to generate the second clock signal.

10. The design method of claim 8 , wherein the signal delay of the clock control signal varies within a range between a minimum delay and a maximum delay.

11. 11. The design method of claim 10, further comprising the steps of: selecting one of the first clock gating circuit and the second clock gating circuit according to a starting edge of the first level phase when the minimum delay and the maximum delay are both in a first level phase of the first clock signal.

12. 12. The design method of claim 11, wherein if the starting edge of the first-level stage is a rising edge, the selected clock gating circuit is the first clock gating circuit.

13. 12. The design method of claim 11, wherein if the starting edge of the first-level stage is a falling edge, the selected clock gating circuit is the second clock gating circuit.

14. The design method according to claim 11 , wherein the predetermined level is a level of the first level stage.

15. 11. The design method of claim 10, wherein the selected clock gating circuit is a third clock gating circuit when the minimum delay and the maximum delay are at a first level phase and a second level phase of the first clock signal, respectively.

16. The design method according to claim 15 , wherein the predetermined level is a level of the second level stage.

17. 3. The design method according to claim 2, wherein the step of combining with a trigger unit includes the step of selecting a clock cycle for data transmission by the edge trigger flip-flop according to a type of a selected clock gating circuit and a type of the edge trigger flip-flop.

18. 18. The design method of claim 17, wherein, if the starting edge of the first level stage is the same as the trigger edge of the edge-triggered flip-flop, the second clock signal provides the trigger edge of the edge-triggered flip-flop in a clock cycle in which the clock control signal is inverted.

19. 18. The design method of claim 17, wherein the second clock signal provides the trigger edge of the edge-triggered flip-flop in a clock cycle prior to the clock cycle in which the clock control signal inverts if the starting edge of the first level stage is opposite the trigger edge of the edge-triggered flip-flop.

20. 3. The design method of claim 2, wherein the step of combining with a trigger unit includes the step of inverting the second clock signal to generate a third clock signal.

21. 21. The design method of claim 20, wherein, if the starting edge of the first level stage is the same as the trigger edge of the edge-triggered flip-flop, the second clock signal provides the trigger edge of the edge-triggered flip-flop in a clock cycle in which the clock control signal is inverted.

22. 21. The design method of claim 20, wherein the third clock signal provides the trigger edge of the edge-triggered flip-flop in a clock cycle in which the clock control signal is inverted if the starting edge of the first level stage is opposite the trigger edge of the edge-triggered flip-flop.

23. 2. The design method according to claim 1, wherein a high level of the clock control signal indicates a valid state and a low level of the clock control signal indicates an invalid state.

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