Method and apparatus for forming backside power rails - Patents.com

Abstract

A method for forming a sacrificial fill material that can be selectively removed to form a backside contact via for a transistor backside power rail. In some embodiments, the method can include performing an etching process on a substrate having an opening conformally covered with an oxide layer, the etching process being an anisotropic dry etching process using chlorine gas to remove the oxide layer from the field of the substrate and from only a bottom portion of the opening, the etching process forming a partial oxide spacer in the opening and increasing the depth of the opening, and epitaxially growing a sacrificial fill material in the opening by flowing hydrogen chloride gas at a rate of about 60 sccm to about 90 sccm at a chamber pressure of about 1 Torr to about 100 Torr.

Description

[Technical field]

[0001] FIELD OF THE PREFERRED EMBODIMENTS Embodiments of the present principles relate generally to semiconductor processing of semiconductor substrates. [Background technology]

[0002] Transistors used in logic and memory require a power source to operate. Power is typically provided by power rails that connect each transistor to a power source. Configurations that include a front side power grid have power rails intermingled with the signal lines used by the transistors, creating a complex network and a delicate balance between the interleaved power rails and signal lines. Traditional back side power sources may utilize vias that extend into the transistors, which makes the transistor area larger. Similarly, buried power rails that connect to the transistors also increase the area used by the transistors.

[0003] Thus, the inventors have provided an improved method and apparatus for forming power distribution rails that supply power to transistors without requiring an increase in transistor area, simplifying the transistor configuration and formation process while increasing transistor density. Summary of the Invention [Problem to be solved by the invention]

[0004] A method and apparatus for forming a backside power supply structure is provided herein. [Means for solving the problem]

[0005] In some embodiments, a method for forming a sacrificial fill material can include performing an etching process on a substrate having an opening conformally coated with an oxide layer, where the etching process is an anisotropic dry etching process using chlorine gas that removes the oxide layer from the field of the substrate and from only a bottom portion of the opening, where the etching process forms a partial oxide spacer in the opening and increases the depth of the opening, and epitaxially growing a sacrificial fill material in the opening by flowing hydrogen chloride gas at a rate of about 60 sccm to about 90 sccm at a chamber pressure of about 1 Torr to about 100 Torr.

[0006] In some embodiments, the method further comprises the step of: the sacrificial fill material is silicon, silicon germanium, silicon oxide, silicon nitride, silicon carbide, aluminum oxide, or hafnium oxide, the silicon or silicon germanium including a dopant of boron, phosphorous, carbon, oxygen, or antimony, the sacrificial fill material being SiGe 0.4 And, <110> Crystal plane for silicon materials <100> epitaxially growing a sacrificial fill material using a selective epitaxial growth process having selectivity for a crystalline face of silicon material; <100> Crystal plane silicon material: <110> The method may further include epitaxially growing a silicon substrate having a crystal plane silicon material selectivity of about 4:1 or greater, performing the method in an integrated cluster tool without an air break or intermediate wet pre-clean process, and a hydrogen chloride gas rate of about 70 sccm, performing the method in a process of forming backside power vias for a transistor structure, and / or forming self-aligned epitaxial source / drain structures of the transistor on the sacrificial fill material.

[0007] In some embodiments, a method of forming a backside power rail contact for a source / drain epitaxial (Epi) structure of a transistor includes forming an opening in a substrate, depositing a conformal layer of oxide on the substrate and within the opening, and performing an etching process on the substrate and the opening, the etching process being an anisotropic dry etching process using chlorine gas that removes the conformal layer of oxide from the fields of the substrate and from only a bottom portion of the opening, the etching process forming a partial oxide spacer in the opening and increasing the depth of the opening, and performing an etching process at a chamber pressure of about 1 Torr to about 100 Torr. The method may include epitaxially growing a sacrificial fill material in the openings by flowing hydrogen chloride gas at a rate of about 60 sccm to about 90 sccm at 4000 sq. ft., forming source / drain Epi structures on the sacrificial fill material, forming a gate material on the source / drain Epi structures, forming at least one interconnect signal line on the gate material, flipping the substrate over to expose a backside of the substrate, removing material of the substrate to expose the sacrificial fill material, selectively etching the sacrificial fill material to remove the sacrificial fill material, and forming self-aligned backside power rail contacts to the source / drain Epi structures.

[0008] In some embodiments, the method includes: the sacrificial fill material is silicon germanium (SiGe); <110> Crystal plane for silicon materials <100> epitaxially growing a sacrificial fill material using a selective epitaxial growth process having selectivity for a crystalline face of silicon material; <100> Crystal plane silicon material: <110> The method can further include epitaxially growing where the selectivity of the crystalline plane silicon material is about 4:1 or greater, the conformal layer of oxide is an aluminum oxide material, and / or the rate of hydrogen chloride gas is about 70 sccm.

[0009] In some embodiments, there is a non-transitory computer readable medium having instructions stored thereon that, when executed, cause a method for forming a sacrificial fill material to be performed, the method including performing an etching process on a substrate having an opening conformally coated with an oxide layer, the etching process being an anisotropic dry etching process using chlorine gas that removes the oxide layer from the field of the substrate and from only a bottom portion of the opening, the etching process forming a partial oxide spacer in the opening and increasing a depth of the opening; and epitaxially growing a sacrificial fill material in the opening by flowing hydrogen chloride gas at a rate of about 60 sccm to about 90 sccm at a chamber pressure of about 1 Torr to about 100 Torr.

[0010] In some embodiments, a method based on a non-transitory computer readable medium includes: <110> Crystal plane for silicon materials <100> epitaxially growing a sacrificial fill material using a selective epitaxial growth process having selectivity for a crystalline face of silicon material; <100> Crystal plane silicon material: <110> The selectivity of the crystal plane silicon material is about 4:1 or greater, and the hydrogen chloride gas rate is about 70 sccm, and the method is performed in an integrated cluster tool without air break or intermediate wet pre-clean processes, or the method is performed in a process of forming backside power vias for the transistor structures, and may further include epitaxially growing and / or forming self-aligned epitaxial source / drain structures of the transistor on the sacrificial fill material.

[0011] Other and further embodiments are disclosed below.

[0012] Embodiments of the present principles, briefly summarized above and discussed in more detail below, can be understood by reference to exemplary embodiments of the present principles as illustrated in the accompanying drawings, which, however, depict only typical embodiments of the principles and are therefore not to be considered limiting in scope, since the principles are susceptible of other equally effective embodiments. [Brief description of the drawings]

[0013] [Figure 1] 1A-1D are diagrams of methods of forming a sacrificial fill material in a substrate, in accordance with some embodiments of the present principles; [Diagram 2] 1A-1C are diagrams of methods of forming backside power rail contacts, in accordance with some embodiments of the present principles; [Diagram 3] 1A-1C are cross-sectional views of openings in a substrate undergoing etching and filling processes in accordance with certain embodiments of the present principles. [Figure 4] 1 is an isometric view of a substrate in preparation for forming a transistor structure, in accordance with some embodiments of the present principles; [Diagram 5] FIG. 1 shows a graph of flow rate versus growth rate, in accordance with some embodiments of the present principles. [Figure 6] 1A-1C are cross-sectional views of sacrificial material fillings formed in openings of transistor structures, in accordance with some embodiments of the present principles. [Figure 7] 1A-1C are cross-sectional views of transistor structures using sacrificial material fillers in accordance with some embodiments of the present principles. [Figure 8] 1 is a cross-sectional view of a flipped substrate, in accordance with some embodiments of the present principles; [Figure 9] 1A-1C are cross-sectional views of transistor structures, in accordance with some embodiments of the present principles; [Figure 10] FIG. 1 is a top-down view of an integrated tool, in accordance with some embodiments of the present principles. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] For ease of understanding, wherever possible, the same reference numbers have been used to designate identical elements common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0015] The method and apparatus provide high density transistor structures with simplified formation processes. The backside power rail configuration integration and unit process utilizes selective bottom-up sacrificial fill to form high density transistor structures. This technique co-optimizes the starting etch and clean process sequence with the epitaxial growth process. In some embodiments, the sacrificial fill material can be silicon or silicon germanium with or without dopants such as, but not limited to, boron, phosphorus, carbon, oxygen, antimony, and the like. In some embodiments, the sacrificial fill material can be a dielectric such as, but not limited to, silicon oxide, silicon nitride, silicon carbide, aluminum oxide, or hafnium oxide, and the like. The present principles have the advantage of using a bottom-up fill process to prevent pinch-off voids due to undesired growth from the sidewalls of the structure, and further the advantage of using a selective fill process to prevent selectivity loss that induces nodule defects on the surface and sidewalls of the structure.

[0016] Backside Power Rail (BPR) based configurations are new processes being considered for advanced nodes in the near future and beyond. The present principles can be utilized to enable front-to-back type connections by using sacrificial fill on the wafer front side. The sacrificial fill can then be replaced with a self-aligned power via formation process on the wafer back side. The present principles further enable these processes by performing a selective bottom-up fill process for the sacrificial fill. Additional advantages of this technique include an etching process that eliminates the need for a post-etch wet clean process. The etching process can be performed without the use of oxides (e.g., AlO x ) preserves the inner spacer and avoids sidewall kinking that can later result in undesired pinch-off growth during the epitaxial (Epi) growth process. Another advantage is that the surrounding dielectric (e.g., SiN, SiO 2 , Al 2 O 3 A new Epi growth process that fills the structure without losing selectivity (e.g.,

[0017] FIG. 1 is a method 100 of forming a sacrificial fill material in a substrate 302 according to some embodiments as shown in FIG. 3 and FIG. 4. The substrate 302 can be formed from a material such as, for example, but not limited to, silicon. In the example, the substrate 302 is prepared for forming a transistor, but the techniques of the present principles can also be used to form a sacrificial material for other applications. As such, the example is not meant to be limiting in the context of the formation of the sacrificial fill material and the associated processes. In the diagram 300A of FIG. 3, the substrate 302 is formed with a first dielectric layer 304 and a second dielectric layer 306. The first dielectric layer 304 can be formed from, for example, but not limited to, silicon oxide. The second dielectric layer 306 can be formed from, for example, but not limited to, silicon nitride. An oxide layer 312A is conformally formed on the field 320 of the substrate 302 and within an opening 308 having a first depth 316. The oxide layer 312A may be formed from, for example, but not limited to, aluminum oxide, etc. In block 102 of the method 100, an etching process is performed on the substrate 302. The etching process is a dry etching process using chlorine gas that is anisotropic and removes portions of the oxide layer from the field 320 of the substrate 302 and only the bottom portion of the oxide layer in the opening 308, as shown in diagram 300B of FIG. 3. The etching process further increases the depth of the opening 308 to a second depth 314 that is greater than the first depth 316.

[0018] After the etching process removes the oxide layer 312A from the field 320 of the substrate 302 and the bottom of the opening 308, the spacers 312 remain in a portion of the opening 308. In conventional approaches, the portion of the oxide layer on the sidewalls 324 of the opening 308 is etched away from the inside of the opening 308, thereby leaving a ledge 322 that creates a pinch-off point and results in a void in the opening 308 when attempting to fill the opening 308. The method of the present principles uses an anisotropic etch that advantageously retains the spacers 312 on the sidewalls 324 of the opening 308, thereby preventing the formation of a pinch-off point and preventing void formation during filling of the opening 308. The dry etch process of method 100 uses a chlorine gas etch process, which advantageously eliminates the need for a wet pre-clean process in the integrated flow required in conventional processes that use a fluorine-based anisotropic etch process. In some embodiments, the dry etch process is performed with a plasma source power of about 100 Watts to about 3000 Watts and a bias source power of zero to about 500 Watts. In some embodiments, the chlorine gas can be flowed at a rate of about 10 sccm to about 500 sccm. In some embodiments, the chlorine gas can be flowed with oxygen, argon, helium, or nitrogen gas, etc. In some embodiments, the chamber pressure of the dry etch process can be about 1 mTorr to about 100 mTorr.

[0019] The use of an etching process based solely on chlorine gas prior to filling provides a clean, suitable surface at the bottom of the opening 308 for bottom-up Epi nucleation. In block 104, a sacrificial fill material is epitaxially grown in the opening 308 using a selective process based on flowing hydrogen chloride gas. The inventors have discovered that by flowing hydrogen chloride gas at a specific rate, the selectivity of the epitaxial growth can be maintained while maintaining a fast growth rate. The bottom of the opening 308 is adjacent to the substrate 302. <100> The crystal faces are exposed, while the side walls are <110> The crystal face is exposed. The hydrogen chloride gas velocity is <100> Selective Epi growth on the crystal face (bottom of the opening) while <110> The present inventors have found that at hydrogen chloride gas rates 512 of about 60 sccm or higher, as shown in graph 500 of FIG. <100> It was found that Epi growth on the crystal planes was sufficiently selective, while at hydrogen chloride gas rates 514 below 90 sccm, Epi growth occurred at a sufficient deposition rate.

[0020] Epi growth rate (Angstroms / min) is shown on the Y-axis 504 and hydrogen chloride gas flow rate (sccm) is shown on the X-axis 502. Recipe line 506 shows flow rate versus growth rate for a particular deposition recipe profile. At a first point 508, the selectivity was sufficient to prevent Epi growth from occurring on the field or top surface of the substrate (growth only at the bottom of the openings). At a second point 510, the deposition rate was deemed sufficient for the desired yield in the particular structure formation process. The inventors have also discovered that the selectivity can be improved by reducing the pressure during Epi growth from conventional pressures to a pressure of about 5 Torr. In some embodiments, the hydrogen chloride gas flow rate is about 70 sccm and the pressure is about 5 Torr; <100> Crystal plane Epi growth: <110> The selectivity of the crystal plane Epi growth is about 4:1 or greater. In some embodiments, the chamber pressure during Epi growth can be from about 1 Torr to about 100 Torr. In some embodiments, the chamber pressure during Epi growth can be from about 1 Torr to about 40 Torr. In some embodiments, the chamber pressure during Epi growth can be from about 3 Torr to about 20 Torr. The inventors have found that gases such as silane reduce selectivity and that high pressures are undesirable. <110> It has also been found to increase the Epi growth rate on the crystal planes and further reduce the selectivity. In some embodiments, the etch process of block 102 and the sacrificial fill process of block 104 of method 100 can be performed in an integrated tool 1000 of FIG. 10, which allows for a wet-free integration process by, for example, eliminating exposure of the substrate 302 to air breakdown during the process. By maintaining the substrate 302 in a vacuum for the etch and fill process, oxides due to air exposure that need to be removed are not formed on the surface prior to the Epi bottom-up fill.

[0021] In FIG. 3, the sacrificial fill material 310 provided by Epi growth is shown as a bottom-up fill. The amount of fill can be adjusted based on the context in which the method 100 is performed. In some embodiments, the oxide layer 312A and the spacers 312 may not be formed prior to the etching process of block 102 and the sacrificial material fill of block 104. FIG. 4 is an isometric view 400 of preparation for forming a bank of transistors. An opening is formed in the substrate 302 through the second dielectric layer 306, the first dielectric layer 304, and into the substrate 302. The etching process of block 102 of the method 100 has created the spacers 312 in the opening 308, and the sacrificial fill process of block 104 of the method 100 has created the sacrificial fill material 310 at the bottom of the opening 308. The formation of source / drain Epi structures on the sacrificial fill material 310, along with the gate material and interconnect lines, will be discussed below for transistor specific structures. The etching and formation of a sacrificial fill material of method 100 can be used for other structures that benefit from a sacrificial fill material for further backside processing of the structure.

[0022] In FIG. 2, a method 200 of forming a backside power rail contact for a transistor structure is shown. In block 202, an opening is etched and a sacrificial fill material is epitaxially grown in the opening of a substrate. The etching of the opening is performed as described above in block 102 of the method 100, and the sacrificial fill material is deposited as described above in block 104 of the method 100. In the cross-sectional view 600 of FIG. 6, an opening 612 in a substrate 602 is partially filled with a sacrificial fill material 610. The opening 612 penetrates a first dielectric layer 604 and a second dielectric layer 606. Alternating layers 608 of Epi structures are formed on the sacrificial fill material 610. In block 204, a source / drain of a transistor is formed on the sacrificial fill material 610. In the cross-sectional view 700 of FIG. 7, an Epi source / drain structure 706 is formed on the sacrificial fill material 610. In block 206, a gate 708 is formed on the Epi source / drain structure 706, and an interconnect signal line 702 is formed over the transistor to complete the front side structure of the transistor 704 as shown in cross-sectional view 700 of FIG. 7. In block 208, the substrate 602 is flipped over to expose the backside of the substrate 602 as shown in view 800 of FIG. 8. In block 210, the substrate material is removed to expose the sacrificial fill material. The substrate material may be removed by chemical mechanical polishing (CMP), or the like. In block 212, the sacrificial fill material is selectively etched to remove the sacrificial fill material. In block 214, a self-aligned backside power rail via or contact 802 for the Epi source / drain structure 706 is formed by depositing a conductive material in place of the removed sacrificial fill material. The transistor structure 704, along with other power vias and backside power rails and connections thereto, may undergo further processing, such as an additional layer of insulating material on the backside.

[0023] FIG. 9 is a cross-sectional view 900 of a transistor structure 704 shown with a backside power rail 904 and a backside insulating layer 910. The backside power rail 904 is electrically connected to a backside power rail or contact 802 of the Epi source / drain structure 706 of the transistor structure 704 through several redistribution layers (RDLs) 906 and vias 908. The backside power rail or contact 802 is self-aligned to and located directly below the Epi source / drain structure 706, thereby allowing for a significant reduction in the transistor area on the substrate. The reduction in the area required for the transistor structure 704 allows for substantially higher transistor density. Additionally, the removal of the power rail above the transistor structure 704 allows for unobstructed interconnect signal lines 902, eliminating possible crosstalk and noise from the power lines. The removal of the power rail from above the transistor structure 704 can also advantageously increase the interconnect signal line density.

[0024] The methods described herein can be performed in individual process chambers, which may be provided in a stand-alone configuration or as part of a cluster tool, such as an integrated tool 1000 (i.e., a cluster tool) described below with respect to FIG. 10. The advantage of using the integrated tool 1000 is that there is no vacuum break and therefore no need to degas and pre-clean the substrate before treatment in the epitaxial growth chamber after the etching process. The integrated tool 1000 includes a vacuum-tight processing platform 1001, a factory interface 1004, and a system controller 1002. The processing platform 1001 includes multiple processing chambers, such as 1014A, 1014B, 1014C, 1014D, 1014E, and 1014F, operably coupled to a vacuum substrate transfer chamber (transfer chambers 1003A, 1003B). The factory interface 1004 is operably coupled to the transfer chamber 1003A by one or more load lock chambers (two load lock chambers, such as 1006A and 1006B shown in FIG. 10).

[0025] In some embodiments, the factory interface 1004 includes at least one docking station 1007 and at least one factory interface robot 1038 to facilitate transfer of semiconductor substrates. The docking station 1007 is configured to receive one or more Front Opening Unified Pods (FOUPs). Four FOUPs, such as 1005A, 1005B, 1005C, and 1005D, are shown in the embodiment of FIG. 10. The factory interface robot 1038 is configured to transfer substrates from the factory interface 1004 through load lock chambers, such as 1006A and 1006B, to the processing platform 1001. Each of the load lock chambers 1006A and 1006B has a first port coupled to the factory interface 1004 and a second port coupled to the transfer chamber 1003A. The load lock chambers 1006A and 1006B are coupled to a pressure control system (not shown) that pumps down and evacuates the load lock chambers 1006A and 1006B to facilitate passing substrates between the vacuum environment of the transfer chamber 1003A and the substantially ambient (e.g., atmospheric) environment of the factory interface 1004. The transfer chambers 1003A, 1003B have vacuum robots 1042A, 1042B disposed in the respective transfer chambers 1003A, 1003B. The vacuum robot 1042A can transfer substrates 1021 between the load lock chambers 1006A, 1006B, the processing chambers 1014A and 1014F, and the cooling station 1040 or the pre-cleaning station 1042. The vacuum robot 1042B can transfer the substrate 1021 between the cooling station 1040 or the pre-cleaning station 1042 and the processing chambers 1014B, 1014C, 1014D, and 1014E.

[0026] In some embodiments, the processing chambers 1014A, 1014B, 1014C, 1014D, 1014E, and 1014F are coupled to the transfer chambers 1003A, 1003B. The processing chambers 1014A, 1014B, 1014C, 1014D, 1014E, and 1014F include at least an epitaxial growth deposition chamber and an etch chamber. In some embodiments, the integrated tool 1000 may further include an atomic layer deposition (ALD) process chamber and a physical vapor deposition (PVD) process chamber. Additional chambers may be provided, such as a CVD chamber, an annealing chamber, and the like. The epitaxial growth deposition chamber and the etch chamber may include any chamber suitable for performing all or a portion of the methods described herein as discussed above. In some embodiments, one or more optional service chambers (shown as 1016A and 1016B) may be coupled to the transfer chamber 1003A. Service chambers 1016A and 1016B may be configured to perform other substrate processes such as degassing, orientation, substrate metrology, cooling, etc.

[0027] The system controller 1002 controls the operation of the tool 1000 using direct control of the process chambers 1014A, 1014B, 1014C, 1014D, 1014E, and 1014F, or alternatively, by controlling the process chambers 1014A, 1014B, 1014C, 1014D, 1014E, and 1014F and a computer (or controller) associated with the tool 1000. During operation, the system controller 1002 enables data collection and feedback from the respective chambers and systems to optimize the performance of the tool 1000. The system controller 1002 generally includes a central processing unit (CPU) 1030, a memory 1034, and support circuits 1032. The CPU 1030 can be any form of general-purpose computer processor that can be used in an industrial environment. The support circuits 1032 are conventionally coupled to the CPU 1030 and can include cache, clock circuits, input / output subsystems, power supplies, etc. Software routines, such as the methods described above, may be stored in memory 1034 and executed by CPU 1030 to transform CPU 1030 into a special purpose computer (system controller) 1002 to perform the methods described above. Software routines may also be stored and / or executed by a second controller (not shown) located remotely from tool 1000.

[0028] Embodiments according to the present principles may be implemented in hardware, firmware, software, or any combination thereof. Embodiments may also be implemented as instructions stored using one or more computer-readable media, which may be read and executed by one or more processors. A computer-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing platform, or a "virtual machine" running on one or more computing platforms). For example, a computer-readable medium may include any suitable form of volatile or non-volatile memory. In some embodiments, a computer-readable medium may include a non-transitory computer-readable medium.

[0029] While the forgoing is directed to embodiments of the present principles, other and further embodiments of the present principles may be devised without departing from the basic scope thereof.

Claims

1. 1. A method for forming a sacrificial filler material, comprising: performing an etching process on a substrate having an opening conformally covered with an oxide layer, the etching process being an anisotropic dry etching process using chlorine gas to remove the oxide layer from the field of the substrate and from only a bottom portion of the opening, the etching process forming a partial oxide spacer in the opening and increasing the depth of the opening; epitaxially growing the sacrificial fill material in the opening by flowing hydrogen chloride gas at a rate of about 60 sccm to about 90 sccm at a chamber pressure of about 1 Torr to about 100 Torr; A method comprising:

2. The method of claim 1 , wherein the sacrificial fill material is silicon, silicon germanium, silicon oxide, silicon nitride, silicon carbide, aluminum oxide, or hafnium oxide.

3. The method of claim 2 , wherein the silicon or silicon germanium includes a dopant of boron, phosphorus, carbon, oxygen, or antimony.

4. The sacrificial fill material is SiGe 0.4 The method according to claim 2, wherein

5. epitaxially growing said sacrificial fill material using a selective epitaxial growth process having selectivity for <100> crystalline plane silicon material relative to <110> crystalline plane silicon material. The method of claim 1 further comprising:

6. 6. The method of claim 5, wherein the selectivity of <100> crystal plane silicon material:<110> crystal plane silicon material is about 4:1 or greater.

7. 10. The method of claim 1, performed in an integrated cluster tool without air break or intermediate wet pre-clean processes.

8. 2. The method of claim 1, wherein the hydrogen chloride gas rate is about 70 sccm.

9. 10. The method of claim 1 performed in a process for forming a backside power via for a transistor structure.

10. forming a self-aligned epitaxial source / drain structure of a transistor on said sacrificial fill material; The method of claim 1 further comprising:

11. 1. A method for forming a backside power rail contact for a transistor source / drain epitaxial (Epi) structure, comprising: forming an opening in a substrate; depositing a conformal layer of oxide over the substrate and within the opening; performing an etching process on the substrate and the opening, the etching process being an anisotropic dry etching process using chlorine gas to remove the conformal layer of oxide from the field of the substrate and from only a bottom portion of the opening, the etching process forming a partial oxide spacer in the opening and increasing a depth of the opening; epitaxially growing a sacrificial fill material in the opening by flowing hydrogen chloride gas at a rate of about 60 sccm to about 90 sccm at a chamber pressure of about 1 Torr to about 100 Torr; forming source / drain Epi structures on the sacrificial fill material; forming a gate material over the source / drain Epi structure; forming at least one interconnect signal line over the gate material; turning the substrate over to reveal a backside of the substrate; removing material of the substrate to expose the sacrificial fill material; Selectively etching the sacrificial fill material to remove the sacrificial fill material; and forming the backside power rail contacts self-aligned to the source / drain Epi structures; A method comprising:

12. The method of claim 11 , wherein the sacrificial fill material is silicon germanium (SiGe).

13. epitaxially growing said sacrificial fill material using a selective epitaxial growth process having selectivity for <100> crystalline plane silicon material relative to <110> crystalline plane silicon material. The method of claim 11 further comprising:

14. 14. The method of claim 13, wherein the selectivity of <100> crystal plane silicon material:<110> crystal plane silicon material is about 4:1 or greater.

15. The method of claim 11 , wherein the conformal layer of oxide is an aluminum oxide material.

16. 12. The method of claim 11, wherein the hydrogen chloride gas rate is about 70 sccm.

17. A non-transitory computer readable medium having instructions stored thereon that, when executed, cause a method for forming a sacrificial fill material to be performed, the method comprising: performing an etching process on a substrate having an opening conformally covered with an oxide layer, the etching process being an anisotropic dry etching process using chlorine gas that removes the oxide layer from the field of the substrate and from only a bottom portion of the opening, the etching process forming a partial oxide spacer in the opening and increasing the depth of the opening; epitaxially growing the sacrificial fill material in the opening by flowing hydrogen chloride gas at a rate of about 60 sccm to about 90 sccm at a chamber pressure of about 1 Torr to about 100 Torr; A non-transitory computer readable medium comprising:

18. The method further comprising: epitaxially growing the sacrificial fill material using a selective epitaxial growth process having a selectivity of <100> crystal plane silicon material to <110> crystal plane silicon material, wherein the selectivity of <100> crystal plane silicon material:<110> crystal plane silicon material is about 4:1 or greater.

20. The non-transitory computer-readable medium of claim 17, further comprising:

19. 20. The non-transitory computer-readable medium of claim 17, wherein the rate of the hydrogen chloride gas is about 70 sccm and the method is performed in an integrated cluster tool without an air break or intermediate wet pre-clean process, or the method is performed in a process of forming backside power vias for a transistor structure.

20. The method further comprising: forming a self-aligned epitaxial source / drain structure of a transistor on said sacrificial fill material; 20. The non-transitory computer-readable medium of claim 17, further comprising:

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