Board frame design for 3D laminated electronic assemblies.

Abstract

In 3D laminated electronic assemblies, to reduce stress on the substrate, the substrate frame can be divided into multiple frame sections, separated by spaces between them. These separations allow the substrate to expand and contract in response to temperature fluctuations and other environmental conditions, generally allowing the substrate to move in one or more axes. The separations between substrate sections can be design-specific for each substrate design. The placement of IC packages on both sides of the substrate can be analyzed to identify areas of maximum warpage through physical measurements, physical model simulations, or using trained neural networks. Spaces in the substrate frame can then be positioned adjacent to or aligned with the areas of maximum warpage to reduce stress on the substrate.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of and priority to U.S. Non-Provisional Application No. 17 / 851,754, filed June 28, 2022, and entitled "SUBSTRATE FRAME DESIGN FOR THREE-DIMENSIONAL STACKED ELECTRONIC ASSEMBLIES," the entire contents of which are incorporated herein by reference for all purposes.

[0002] This disclosure generally describes a substrate frame design for three-dimensional (3D) stacked electronic assemblies. More particularly, this disclosure describes a substrate frame design that is divided into multiple frame sections to reduce stress on the electronic assembly. [Background technology]

[0003] Chiplets are modular integrated circuits specially designed to work with other similar modular chiplets to form larger, more complex processing systems. This allows functional blocks to be divided into different chiplets in a design, providing greater flexibility and modularity during the design process. In contrast to traditional monolithic integrated circuit (IC) designs, chiplet-based designs use smaller, independent dies connected to each other. Each chiplet can be specially designed to perform an individual function, such as a processing core, a graphics processing unit, a math coprocessor, or a hardware accelerator. Chiplet-based designs also reduce the cost of manufacturing because larger dies can be divided into smaller chiplets to improve yield and binning. Due to rising costs and the slowdown of Moore's Law, traditional monolithic chip development is also becoming less attractive because chiplets offer less expensive and faster time-to-market production. The emergence of a relatively new chiplet-based ecosystem is beginning to enable alternative ways to design complex systems by integrating pre-tested chiplet dies into larger packages.

[0004] To accommodate an increasing number of chiplet-based or multi-IC designs, manufacturers are turning to 3D packaging as a solution for space-efficient footprints for electronic assemblies. 3D packaging involves the 3D integration of multiple substrates in a vertical stack, connected through traditional interconnect methods. 3D packaging can include 3D system-in-package (SiP), 3D wafer-level packaging (3D WLP), among other emerging package designs. However, while vertical stacking in 3D assemblies can reduce the footprint of the overall assembly, these vertical stacks can increase the mechanical stress experienced by individual substrates. Therefore, improvements are needed in the art. Summary of the Invention

[0005] In some embodiments, a three-dimensional (3D) laminated electronic assembly may include a printed circuit board, a package substrate, a plurality of integrated circuit (IC) packages attached to the package substrate, and a substrate frame disposed between the printed circuit board and the package substrate in the 3D laminated electronic assembly. The substrate frame may define a cavity inside the substrate frame and between the printed circuit board and the package substrate. The plurality of IC packages may be attached to the package substrate inside the cavity. The substrate frame may be divided into a plurality of frame sections, the plurality of frame sections being separated by spaces between the plurality of frame sections.

[0006] In some embodiments, a substrate frame for a 3D stacked electronic assembly can include a first side with first interconnects configured to attach to a first substrate, the first side having a plurality of integrated circuit (IC) packages attached to the first substrate. The assembly can also include a second side with second interconnects configured to attach to a second substrate, such that the substrate frame can be disposed between the first and second substrates in the 3D stacked electronic assembly, and a cavity can be defined inside the substrate frame and between the first and second substrates with the plurality of integrated IC packages attached. The assembly can also include a plurality of frame sections, the plurality of frame sections separated by spaces between the plurality of frame sections.

[0007] In some embodiments, a method for assembling a three-dimensional (3D) laminated electronic assembly may include attaching a plurality of integrated circuit (IC) packages to a first substrate and connecting a substrate frame to the first substrate and to a second substrate. The substrate frame may define a cavity inside the substrate frame and between the first substrate and the second substrate. The plurality of IC packages may be attached to the first substrate inside the cavity. The substrate frame may be divided into a plurality of frame sections, the plurality of frame sections being separated by spaces between the plurality of frame sections.

[0008] In any embodiment, any and all of the following features may be implemented in any combination, without limitation. The assembly may also include a second plurality of IC packages. The package substrate may include a first side inside the cavity to which the plurality of IC packages are attached. The package substrate may include a second side to which the second plurality of IC packages are attached. The second plurality of IC packages may be attached to the second side of the package substrate within the footprint of the cavity. The second plurality of IC packages may include fewer IC packages than the plurality of IC packages, which may cause warpage in the package substrate. Spaces between the frame sections of the substrate frame may be located next to warpage in the package substrate to reduce warpage. The printed circuit board may extend beyond the footprint of the package substrate. The assembly may also include a second package substrate that may be attached to the printed circuit board through the second substrate frame. The substrate frame may have a rectangular shape. Spaces separating the frame sections may be located on sides of the substrate frame. Spaces separating the frame sections may be located at corners of the substrate frame. The width of the plurality of frame sections may be maintained across the spaces between the plurality of frame sections. The spaces between the plurality of frame sections may be positioned within the substrate frame such that the substrate frame is symmetrical about an axis. The width of the plurality of frame sections may be at least five times greater than the length of the spaces between the plurality of frame sections. Identifying an area of the first substrate having warpage may include measuring a displacement of the area of the first substrate after attaching the plurality of IC packages to the first substrate relative to a displacement of the area of the first substrate before attaching the plurality of IC packages to the first substrate. The method / operations may also include measuring a displacement of the area of the first substrate after connecting the substrate frame to the first substrate to determine whether the displacement of the area is reduced by attaching the first substrate to the substrate frame. Identifying an area of the first substrate having warpage may include simulating a 3D model of the first substrate with the plurality of IC packages attached to the first substrate.The method / operations may also include simulating a 3D model of a substrate frame connected to the 3D model of the first substrate to determine whether adding the 3D model of the substrate frame reduces warpage in the area. The method / operations may also include determining locations of spaces between multiple frame sections in the substrate frame based on identifying areas of the first substrate having warpage. The method / operations may also include determining locations of spaces between multiple frame sections in the substrate frame based on output provided by a machine learning model trained to receive locations of multiple IC packages and output locations of the spaces.

[0009] A further understanding of the nature and advantages of various embodiments may be realized by reference to the remaining portions of the specification and the drawings, in which like reference numerals are used throughout the several views to refer to like components. In some instances, a sub-label is associated with a reference numeral to indicate one of multiple similar components. When reference is made to a reference numeral without specification to an existing sub-label, it is intended to refer to all such multiple similar components. [Brief explanation of the drawings]

[0010] [Figure 1] 1 illustrates a 3D stacked electronic assembly, according to some embodiments. [Figure 2] 1 is an overhead view of a 3D stacked electronic assembly, according to some embodiments. [Figure 3] 1A-1C illustrate views of a 3D stacked electronic assembly that uses a substrate frame divided into multiple frame sections, according to some embodiments. [Figure 4] FIG. 10 illustrates a view of the space between two frame sections, according to some embodiments. [Figure 5] 1 illustrates a 3D stacked electronic assembly with an additional frame section, according to some embodiments. [Figure 6] 1A-1C illustrate a 3D stacked electronic assembly with spaces at the corners of the package substrate, according to some embodiments. [Figure 7] 10A-10C illustrate alternative geometries for a substrate frame according to some embodiments. [Figure 8A] 1A-1C illustrate simulations or measurements showing package substrate warpage according to some embodiments. [Figure 8B] 10A-10C illustrate designing a substrate frame based on a warp map, according to some embodiments. [Figure 9] 1 is a flowchart of a method for assembling a 3D stacked electronic assembly, according to some embodiments. [Figure 10] 1 is a flow diagram for identifying spatial locations in a substrate frame using a neural network, according to some embodiments. [Figure 11] FIG. 1 illustrates an exemplary computer system in which various embodiments may be implemented. DETAILED DESCRIPTION OF THE INVENTION

[0011] Three-dimensional (3D) laminated electronic assemblies can stack multiple substrates on top of each other, typically with integrated circuit (IC) packages attached to both sides of the substrates. To create space between the substrates in the laminated electronic assembly, substrate frames can be placed between and around the substrates to create cavities between the substrates for the IC packages. Each of these substrates can be subject to internal stresses that can cause warpage in the substrates. This warpage can be exacerbated when IC packages are not symmetrically attached to the top and bottom of the substrate or when a different number of IC packages are attached to each side of the substrate. Because the substrate frame is a rigid, continuous member, it tends to restrict the expansion and contraction of the connected substrates in all directions, thus further amplifying the warpage of the substrates. Board warpage can lead to manufacturing defects, reliability issues, and reduced lifespan of the electronic assembly.

[0012] In 3D laminated electronic assemblies, to reduce stress on the substrate, the substrate frame can be divided into multiple frame sections, separated by spaces between them. These separations allow the substrate to expand and contract in response to temperature fluctuations and other environmental conditions, generally allowing the substrate to move in one or more axes. The separations between substrate sections can be design-specific for each substrate design. The placement of IC packages on both sides of the substrate can be analyzed to identify areas of maximum warpage through physical measurements, physical model simulations, or using trained neural networks. Spaces in the substrate frame can then be positioned adjacent to or aligned with the areas of maximum warpage to reduce stress on the substrate.

[0013] As traditional monolithic-based designs become increasingly more expensive to manufacture, chiplets and modular ICs have emerged as successful alternatives in system architectures to improve yield, reduce manufacturing costs, and improve design modularity. Each IC may include a separate die fabricated from a silicon wafer. Instead of forcing all functions of a system (e.g., a central processing unit (CPU), memory, a graphics processing unit (GPU), various peripherals, etc.) to be fabricated on one large monolithic die, a modular system separates these functions into separate dies that can then be packaged together to perform the same overall function. By making the individual dies smaller, yield and manufacturing costs are reduced for the overall system.

[0014] FIG. 1 illustrates a 3D stacked electronic assembly 100 according to some embodiments. The view of assembly 100 illustrated in FIG. 1 may represent a cross-sectional view of assembly 100. Assembly 100 may include multiple substrates arranged in a vertical stack. As used herein, “substrate” may include any material to which electronic components may be attached. For example, assembly 100 may include a first substrate, such as a package substrate 122, fabricated from an organic material, a silicon wafer, a glass layer, and / or any other type of substrate material suitable for attaching chiplets or IC dies. Additionally, assembly 100 may include a second substrate, such as a printed circuit board 108. Printed circuit board 108 may serve as the bottom-most layer in 3D stacked electronic assembly 100. Although not explicitly shown in FIG. 1 , other substrates may be attached to printed circuit board 108 in addition to package substrate 122. For example, additional package substrates may be attached next to package substrate 102 to form additional 3D vertical stacks on printed circuit board 108. Thus, the area of the printed circuit board 108 may extend outside the footprint 128 of the package substrate 122. In this disclosure, any type of substrate, including the package substrate 122, the printed circuit board 108, and / or any other substrate that may be mounted on the package substrate 122 or at other locations on the printed circuit board 108, may be referred to collectively as a first substrate, a second substrate, etc.

[0015] A plurality of IC packages may be attached to the package substrate 122. In general, IC packages may be attached to both sides of the package substrate 122. For example, the package substrate 122 may include a first side (e.g., a bottom side) to which a first plurality of IC packages 104 are attached. The package substrate 122 may also include a second side (e.g., a top side) to which a second plurality of IC packages 105 are attached. In some designs, the first plurality of IC packages 104 and the second plurality of IC packages 105 may be attached such that they are unequal in number, location, and / or size relative to each other at the top and bottom of the package substrate 122. For example, FIG. 1 shows that the top side of the package substrate 122 may include fewer IC packages 105 than the IC packages 104 at the bottom of the package substrate 122. Furthermore, the IC packages 105 on the top side of the package substrate 122 may be sized differently from the packages 104 on the bottom side of the package substrate 122. The IC package 105 on the top side may also be positioned in a different location compared to the IC package 104 on the bottom side, such that the layout of the IC package 105 on the top of the package substrate 122 and the resulting signal routing and open space are different from the layout, signal routing and open space on the bottom of the package substrate 122.

[0016] The term “IC package” as used herein may refer to any integrated circuit attached to a substrate in the 3D stacked electronic assembly 100. For example, the IC package may include individual integrated circuit dies, chiplets, and / or any other similar components. For example, the IC packages 104, 105 may be fabricated as separate dies from one or more silicon wafers. The IC packages 104, 105 may also perform multiple different functions, such as application-specific systems-on-chip (SOCs), GPUs, digital signal processors (DSPs), artificial intelligence (AI) accelerators, various codecs, Wi-Fi communication modules, memory controllers, memory caches, input / output (I / O) peripherals, etc. Although fabricated on separate dies, each of these IC packages 104, 105 may be connected to one another using various interconnect architectures to perform substantially the same functions that would be performed by a similar monolithic design, but in a distributed manner.

[0017] For example, the package substrate 122 may include a high-density interposer layer. The high-density interposer layer may include high-density routing inside the interposer that connects to pads on the bottom side of the package on the package substrate 122. The high-density interposer layer may be fabricated using organic materials, glass, silicon, and / or any other interposer material. The IC packages 104, 105 may communicate with each other through the interposer layer without requiring traffic to pass through vertical interconnects between different substrates.

[0018] A substrate frame 112 may be disposed between the package substrate 122 and the printed circuit board 108. The substrate frame 112 may perform several different functions. First, the substrate frame 112 may provide a vertical interconnect solution between the package substrate 122 and the printed circuit board 108. For example, the substrate frame 112 may include a first side (e.g., a top side) with first interconnects 157. The first interconnects 157 may be configured to attach to a first substrate, such as the bottom of the package substrate 122. The substrate frame 112 may also include a second side (e.g., a bottom side) with second interconnects 159. The second interconnects 159 may be configured to attach to a second substrate, such as the top side of the printed circuit board 108.

[0019] To provide interconnections between the package substrate 122 and the printed circuit board 108, some embodiments of the substrate frame 112 may include through-hole interconnects that pass directly between locations on the package substrate 122 and locations on the printed circuit board 108. For example, the substrate frame 112 may be formed from an alternative or other molded material to enclose vertical interconnects that extend through the substrate frame 112. In other embodiments, the substrate frame 112 may alternatively or additionally include one or more routing or interconnect layers that route connections from the top of the substrate frame 112 to different locations on the bottom of the substrate frame 112. Some embodiments may include a silicon layer 113 that includes a metal layer that provides this routing function. The silicon layer 113 may also include other integrated circuits or circuit components that perform functions using signals transmitted through the interconnects. Thus, the substrate frame 112 may enable the IC packages 104, 105 to communicate with other components and / or systems attached to the printed circuit board 108.

[0020] Another function performed by the substrate frame 112 may be to define a cavity 106 inside the substrate frame 112 and between the package substrate 122 and the printed circuit board 108. The cavity 106 may provide a location for an IC package 104 attached to the bottom side of the package substrate 122. Although not explicitly shown in FIG. 1 , some designs may also include an IC package attached to the top side of the printed circuit board 108. Thus, the height of the substrate frame 112 may be sized sufficiently to provide space between the IC package 104 at the bottom of the package substrate 122 and the IC package attached to the top side of the printed circuit board 108. In some embodiments, the cavity 106 may enclose a first plurality of IC packages 104 attached to the bottom side of the package substrate 122. Additionally, a second plurality of IC packages 105 mounted on the top side of package substrate 102 are not enclosed within cavity 106, but may be mounted within the footprint 120 of cavity 106 defined by substrate frame 112 in some designs. The vertical thickness of substrate frame 112 may depend on the vertical thickness of the IC package. For example, IC package 104 may be from about 50 μm to about 750 μm thick, depending on the package. The vertical thickness of substrate frame 112, including the interconnects to provide cavity 106, may be designed to be at least 50 μm thicker.

[0021] 2 shows an overhead view of a 3D laminated electronic assembly 100, according to some embodiments. This overhead view of the assembly 100 illustrates how the substrate frame 112 can be fabricated as a single continuous member. A cavity 106 defined by the substrate frame 112 surrounds the IC package 104, which is attached to the bottom of a printed circuit board. Generally, the substrate frame 112 can form an extremely rigid structure attached to the periphery of the package substrate 122.

[0022] As shown in FIGS. 1-2 , IC packages 104 may include IC packages having various sizes, pin counts, mounting locations, mounting techniques, orientations, and / or other physical characteristics. Furthermore, IC packages 104 on the bottom of package substrate 122 may differ from IC packages 105 on the top of package substrate 122. These differences in properties between IC packages 104 on the bottom of package substrate 122 and IC packages 105 on the top of package substrate 122 may cause a stress difference between the top and bottom of package substrate 122. This stress difference may cause warpage in package substrate 122. As used herein, “warpage” may generally refer to a displacement or deflection of a substrate from a baseline flat profile. For example, attaching more IC packages to one side of package substrate 122 compared to the other side may cause package substrate 122 to bend, resulting in a displacement between the center of package substrate 122 and the edges or corners of package substrate 122. Warpage in the package substrate 122 can cause reliability issues for the overall assembly 100. For example, the warpage can cause problems such as weakened or separated solder joints, misalignment between the mounting pads of the IC package and the package substrate 122, stress on the IC package itself, and / or several other mechanical issues that can cause the assembly 100 to fail, either during the manufacturing process or later in use. Therefore, minimizing warpage and stress on the package substrate 122 represents a technical challenge in this area of electronic assembly manufacturing.

[0023] It has been discovered that the addition of the substrate frame 112 tends to amplify or exacerbate stresses and warpage in the package substrate 122. For example, a mismatch between the Young's modulus and / or thermal expansion coefficient of the material used to make the substrate frame 112 compared to the material used in the package substrate 122 can cause the package substrate 122 and the substrate frame 112 to expand / contract very differently in response to changing environmental conditions. In particular, it has been discovered that the rigidity and monolithic construction of the substrate frame 112 may not allow sufficient movement for the package substrate 122 in response to changes in temperature, humidity, etc. For example, when the substrate frame is all one piece, it can represent a rigid structure that changes the warpage of the package substrate, and in some cases, it has been discovered that it can actually create a warpage profile in the package substrate or extend the existing warpage of the package substrate. For example, without the substrate frame, a test package substrate may exhibit a warpage of approximately 100 μm, and with the frame, this warpage may increase to approximately 250-300 μm.

[0024] FIG. 3 shows a view of a 3D stacked electronic assembly 300 using a substrate frame divided into multiple frame sections, according to some embodiments. In this example, a substrate frame 312 is divided into two frame sections 312-1 and 312-2. A space separates these two frame sections 312-1 and 312-2. The location of the space corresponds to a midpoint along the side of the substrate frame 312. When the substrate frame 312 has a rectangular shape, as shown in FIG. 3, the space between the two frame sections 312-1 and 312-2 may be located at a midpoint on two of the parallel edges of the rectangular shape. While this particular example places the space between the two frame sections 312-1 and 312-2 at a midpoint on the edges of the substrate frame, this location is not limiting. Other embodiments may place the space at any point along the edge of the substrate frame 312, such that the substrate frame 312 is divided into two frame sections.

[0025] Some embodiments may position the space between the two frame sections 312-1, 312-2 so that the two frame sections 312-1, 312-2 are symmetrical about an axis that passes through the center of the substrate frame 312. For example, the space between the two frame sections 312-1, 312-2 in FIG. 3 may be aligned so that the two frame sections 312-1, 312-2 are symmetrical about a vertical axis 330 as well as a horizontal axis (not shown). Other embodiments may position the space between the frame sections according to other axes that pass through the center of the assembly 300. For example, location 334 for the space between the frame sections may be used in alignment with axis 332 shown in FIG. 3. This axis 332 may be rotated through the center of the assembly 300 to position location 334 at any symmetrical location.

[0026] 4 shows a view of the space 403 between two frame sections 312-1, 312-2, according to some embodiments. In some embodiments, the substrate frame 312 may be distinct from individual risers or interconnects that are not part of a unified frame design. For example, the substrate frame 312 may maintain the same width 404 across the space 403 that divides one frame section from another (i.e., the top and bottom of the frame sections may be aligned across the space 403). Thus, the footprint 410 of the substrate frame 312, which extends through the space 403, may still define the boundary of a cavity within which an IC package is mounted.

[0027] In some embodiments, the length 402 of the space 403 can be about 1 mm. Alternatively, some embodiments may use a space that is less than about 2 mm, less than about 3 mm, less than about 5 mm, less than about 7 mm, less than about 10 mm, less than about 15 mm, less than about 20 mm, etc., depending on the embodiment. The width 404 of the substrate frame 312 can be about 5 mm. In some embodiments, the width 404 of the substrate frame 312 can also be between about 5 mm and about 10 mm, between about 10 mm and about 15 mm, between about 15 mm and about 20 mm, between about 20 mm and about 25 mm, between about 25 mm and about 30 mm, between about 30 mm and about 35 mm, between about 35 mm and about 40 mm, and / or greater than about 40 mm, depending on the embodiment. The length 402 of the space 403 can be defined relative to the width 404 of the substrate frame 312. For example, the width 404 of the substrate frame 312 can be greater than or about 5.0 times the length 402 of the space 403. In other embodiments, the width 404 can be greater than or about 2.5 times, greater than or about 7.5 times, greater than or about 10 times, and / or greater than or about 15 times the length 402. These measurement ranges for the width 404 and length 402 are provided by way of example only and are not limiting.

[0028] Depending on the embodiment, number of interconnects, interconnect density, cavity size, and other design-dependent characteristics, each of these ranges may be more or less suitable for different assemblies. However, test data has revealed that while increasing the length 402 of the space 403 may continue to relieve stress, there is diminishing return after a certain length. For example, some embodiments show the greatest incremental reduction in warpage in the first 1 mm of the length 402 of the space 403. The incremental reduction in warpage tends to have a diminishing effect on package substrate warpage after the first 1 mm. Thus, some embodiments may use optimal spacing between about 1 mm and about 2 mm, between about 1 mm and 3 mm, and between about 1 mm and about 5 mm, depending on the size of the substrate frame and package substrate, to relieve warpage without unduly restricting the area of the substrate frame for providing interconnections between the substrates.

[0029] FIG. 5 illustrates a 3D stacked electronic assembly 500 with additional frame sections, according to some embodiments. The two frame sections 312-1, 312-2 illustrated above in FIG. 3 are provided by way of example only and are not limiting. Other embodiments may use additional frame sections and additional locations for the spaces between those frame sections. In the example of FIG. 5 , the substrate frame 512 is divided into four individual frame sections 512-1, 512-2, 512-3, and 512-4. Other embodiments may include more than four frame sections, such as five frame sections, six frame sections, or ten frame sections. As described above, some embodiments may arrange the spaces between the frame sections so that the frame sections are symmetrical about the horizontal, vertical, and / or diagonal axes of the assembly 500.

[0030] While multiple frame sections may be used, it has been discovered that the greatest reduction in package substrate stress / warpage may occur with two frame sections (with two corresponding spaces between the frame sections). While adding additional frame sections may continue to reduce package substrate stress / warpage, the effect of adding additional frame sections (i.e., adding more space to the substrate frame) decreases, and thus the improvement is not additive and therefore exhibits diminishing improvement as more frame sections are added. For example, adding the first two spaces to the substrate frame 512 may initially result in a large reduction in package substrate stress / warpage. However, while adding two additional spaces to a substrate frame that already has four or six spaces may continue to reduce package substrate stress / warpage, the incremental improvement may not be as large. Thus, electronic assembly designers may balance the improvement provided by adding more space to the substrate frame 512 with the area required for interconnections, manufacturing and assembly difficulties, and / or other competing priorities. For example, designs generally use a minimum area for through interconnects between the package substrate and the printed circuit board, so space can be added to the substrate frame 512 in some embodiments until the space begins to interfere with the interconnect routing.

[0031] Some embodiments may also prioritize maintaining a cavity 506 to protect or isolate the IC package 504 on the bottom side of the package substrate 522. For example, a cryptographic processor or other sensitive electronic components may be placed in the cavity 506 to protect them from external inspection and to prevent unwanted electronic data transmissions from entering or exiting the cavity 506. Thus, the length of the space and the number of frame sections may be limited to, for example, two frame sections or four frame sections to preserve the integrity of the cavity 506.

[0032] 6 shows a 3D stacked electronic assembly 600 with spaces at the corners of a substrate frame 612, according to some embodiments. This embodiment shows how the spaces between substrate frame sections can be positioned at any location on the substrate frame 612. In this example, the spaces can be positioned at the corners of the substrate frame 612. This arrangement can still maintain a symmetrical arrangement of the frame sections 612-1, 612-2, 612-3, 612-4.

[0033] 7 shows alternative geometries for a substrate frame 712, according to some embodiments. In this example, a package substrate 722 may include a single large IC package 704 mounted in the center of the package substrate 722. The substrate frame 712 may be expanded to fill the remaining space on the package substrate 722, if necessary, while still providing a cavity 706 for the IC package 704. The substrate frame 712 is divided into four quarters 712-1, 712-2, 712-3, and 712-4, and the length of the space between the frame sections may be optionally expanded as the width of the substrate frame 712 increases. This design may be advantageous when the IC package 704 includes numerous interconnects that may require a larger area for the substrate frame 712 to route the interconnects between substrates.

[0034] FIG. 8A shows a simulation or measurement indicating the warpage of a package substrate 830, according to some embodiments. As described above, the warpage of the package substrate 830 may be measured by the displacement from a baseline flat position for the substrate 830. For example, the substrate 830 may be relatively flat before IC packages are mounted thereon. Measuring the resulting warpage may include measuring the displacement at various locations on the package substrate 830. For example, when designing a substrate frame, a prototype of the package substrate 830 may be fabricated with IC packages mounted thereon. A warpage map 800 may be generated using a displacement sensor that measures the displacement from the baseline location. The individual measurements are then compiled into the warpage map 800, which may then be used to design a substrate frame for a design to be used in mass manufacturing.

[0035] Alternatively, instead of physically measuring the displacement of the prototype package substrate 830, some embodiments may simulate the physics using a model of the package substrate 830 to generate the warpage map 800. For example, a 3D model of the package substrate 830 and the IC package mounted thereon may be simulated using standard simulation software to produce the warpage map 800 resulting from internal and induced stresses on the package substrate 830.

[0036] After generating warpage map 800, locations on package substrate 830 having warpage exceeding a threshold amount can be identified. For example, area 802 corresponds to a first area having warpage above a first threshold, and area 803 corresponds to a second area having warpage below a second threshold. In this example, the pattern of warpage on package substrate 830 can represent "cupping" of the substrate.

[0037] 8B shows a design of a substrate frame 812 based on the warpage map 800, according to some embodiments. To avoid exacerbating the warpage of the package substrate 830, voids in the substrate frame 812 may be located next to areas 802, 803 on the package substrate 830 that exhibit the greatest warpage. For example, voids on the sides of the substrate frame 812 may be next to area 802 in the center of the package substrate 830. Additionally, voids may be added at the corners of the substrate frame 812 near area 803. In some embodiments, the locations of the voids may be identified such that they align with the areas of warpage on the vertical, horizontal, and / or diagonal axes.

[0038] FIG. 9 shows a flowchart 900 of a method for assembling a 3D stacked electronic assembly, according to some embodiments. The method may include attaching (902) a plurality of IC packages to a first substrate. As described above, the first substrate may include a package substrate or any other type of substrate. The plurality of IC packages may be attached to a first or bottom side of the first substrate. Additionally, a second plurality of IC packages may be attached to a second or top side of the first substrate. These packages may be mounted within a footprint or cavity defined by a substrate frame.

[0039] In some embodiments, spaces may be placed in the substrate frame to divide the substrate into multiple frame sections according to a predetermined design. Alternatively, some embodiments may use an automated process to identify locations for the spaces in the substrate frame that optimally reduce warpage in the package substrate. For example, some embodiments may optionally include identifying an area of the first substrate that has warpage (910). This area may be identified through the simulation process described above. This area may also be identified by performing warpage measurements on a package substrate with an attached IC package, or a prototype version of the same. This area with warpage may be one area among multiple areas on the substrate that have warpage, each of which may be considered when identifying locations for the spaces in the substrate frame. Some embodiments may identify warpage by comparing the amount of displacement to a threshold value that is either above or below the baseline location. The method may optionally identify or determine locations for the spaces between multiple frame sections in the substrate frame based on identifying areas of the substrate that have warpage (912). For example, an automated process may place two, three, four, or some predetermined number of spaces in the substrate frame so that they are adjacent to or aligned with an area having warpage. As described above, the spaces may be aligned on a horizontal or vertical axis that intersects the area having warpage. Other embodiments may simulate multiple locations for the spaces in the substrate frame to identify an optimal placement that minimizes warpage of the package substrate.

[0040] After determining locations for the spaces dividing the sections of the substrate frame, the method may include connecting the substrate frame to the first substrate and to a second substrate (904). The second substrate may include another package substrate, an interposer, an intermediate layer, a printed circuit board, and / or any other type of substrate.

[0041] Alternatively, some embodiments may optionally use a machine learning process with a neural network to identify spatial locations in the substrate frame based on the positions of the IC packages (914). FIG. 10 shows a flow diagram 1000 for identifying spatial locations in a substrate frame using a neural network 1006, according to some embodiments. The neural network 1006 may be trained to receive locations 1004 (e.g., coordinates) of IC packages on a package substrate 1002. Alternatively, some embodiments may instead train the neural network 1006 as a classification network to receive an image or bitmap of the package substrate 1002 and identify the locations 1004 of the IC packages. This identification may be performed in an initial layer of the neural network 1006. Thus, the training process may set the internal weights and parameters of the first layer of the neural network 1006 to identify or classify the locations 1004 of the IC packages.

[0042] The final layer of the neural network 1006 can be trained to output scores for different locations 1008 in the substrate frame where spaces should be located to minimize warpage on the package substrate 1002. For example, multiple different locations can correspond to outputs on the neural network 1006, with each output generating a score (e.g., between 0.0 and 1.0) indicating the neural network's 1006 preference for locating the spaces at that location. The locations 1008 of the spaces can be provided as outputs to a systems engineer to design the substrate frame. Alternatively, the locations 1008 of the spaces can instead be provided as inputs to a computer system that controls an automated process to fabricate the substrate frame. The neural network 1006 can include parameters or constants that can be adjusted to limit the number of spaces or the locations of the spaces based on design constraints. For example, some designs may restrict spaces from being placed in certain locations based on interconnect requirements. These areas can be provided as parameters to the neural network 1006 so that spaces are not placed in those areas.

[0043] The neural network 1006 may be trained using labeled training data from a measured physical design or from a simulated model. For example, some embodiments may generate training data by arranging IC packages on the package substrate 1002 in multiple different configurations. Simulations may then be performed using different spatial locations to separate frame sections of the substrate frame. The resulting simulations may determine whether warpage of the package substrate 1002 has been sufficiently reduced. The reduction in warpage may be used to label each set of locations as training data for the neural network 1006. Alternatively, the same process may be performed using a physical prototype with data captured from a displacement sensor.

[0044] It should be appreciated that the specific steps illustrated in FIG. 9 provide a particular method of assembling a 3D stacked electronic assembly according to various embodiments. Other sequences of steps may be performed according to alternative embodiments. For example, alternative embodiments may perform the steps outlined above in a different order. Moreover, individual steps illustrated in FIG. 9 may include multiple sub-steps that may be performed in various sequences as appropriate for the individual step. Furthermore, additional steps may be added or removed depending on the particular application. Many variations, modifications, and alternatives are within the scope of the present disclosure.

[0045] Each of the methods described herein may be implemented by a computer system. Each step of these methods may be performed automatically by the computer system and / or may be provided with input / output involving a user. For example, a user may provide input for each step in the method, and each of these inputs may be in response to a particular output requesting such input, which is generated by the computer system. Each input may be received in response to a corresponding requested output. Furthermore, input may be received from a user, received from another computer system as a data stream, retrieved from a memory location, retrieved over a network, requested from a web service, etc. Similarly, output may be provided to a user, provided to another computer system as a data stream, stored in a memory location, sent over a network, provided to a web service, etc. In short, each step of the methods described herein may be performed by a computer system and may involve any number of inputs, outputs, and / or requests to and from the computer system, which may or may not involve a user. Steps that do not involve a user may be said to be performed automatically by the computer system without human intervention. Thus, in light of this disclosure, it will be understood that each step of each method described herein may be modified to include input and output to and from a user, or may be performed automatically by a computer system without human intervention, with any decisions made by a processor. Additionally, some embodiments of each of the methods described herein may be implemented as a set of instructions stored on a tangible, non-transitory storage medium to form a tangible software product.

[0046] 9, including simulating warpage of the substrate frame, identifying locations for spaces in the substrate frame, running and / or training a neural network or other machine learning model, etc., may all be performed automatically by a computer system. An exemplary computer system for performing these steps is described below. For example, these steps may be embodied in a set of instructions stored in one or more memory devices (e.g., non-transitory computer-readable media) that cause one or more processors to perform the steps.

[0047] 11 illustrates an exemplary computer system 1100 upon which various embodiments may be implemented. System 1100 may be used to implement any of the computer systems described above. As shown in the figure, computer system 1100 includes a processing unit 1104 that communicates with several peripheral subsystems via a bus subsystem 1102. These peripheral subsystems may include a processing acceleration unit 1106, an I / O subsystem 1108, a storage subsystem 1118, and a communication subsystem 1124. Storage subsystem 1118 includes a tangible computer-readable storage medium 1122 and a system memory 1110.

[0048] Bus subsystem 1102 provides a mechanism for allowing the various components and subsystems of computer system 1100 to communicate with each other as intended. While bus subsystem 1102 is shown schematically as a single bus, alternative embodiments of the bus subsystem may utilize multiple buses. Bus subsystem 1102 may be any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, and a local bus using any of a variety of bus architectures. For example, such architectures may include an Industry Standard Architecture (ISA) bus, a MicroChannel Architecture (MCA) bus, an Enhanced ISA (EISA) bus, a Video Electronics Standards Association (VESA) local bus, and a Peripheral Component Interconnect (PCI) bus, which may be implemented as a mezzanine bus manufactured to the IEEE P1386.1 standard.

[0049] Processing unit 1104, which may be implemented as one or more integrated circuits (e.g., conventional microprocessors or microcontrollers), controls the operation of computer system 1100. One or more processors may be included in processing unit 1104. These processors may include single-core or multi-core processors. In some embodiments, processing unit 1104 is implemented as one or more independent processing units 1132 and / or 1134, each of which may include a single- or multi-core processor. In other embodiments, processing unit 1104 may also be implemented as a quad-core processing unit formed by integrating two dual-core processors on a single chip.

[0050] In various embodiments, processing unit 1104 may execute various programs in response to program code and may maintain multiple simultaneously executing programs or processes. At a given time, some or all of the program code to be executed may reside in processor(s) 1104 and / or in storage subsystem 1118. Through suitable programming, processor(s) 1104 may provide the various functions described above. Computer system 1100 may further include a processing acceleration unit 1106, which may include a digital signal processor (DSP), a special purpose processor, or the like.

[0051] The I / O subsystem 1108 may include user interface input devices and user interface output devices. User interface input devices may include a keyboard, a pointing device such as a mouse or trackball, a touchpad or touchscreen integrated into a display, a scroll wheel, a click wheel, a dial, buttons, switches, a keypad, an audio input device with a voice command recognition system, a microphone, and other types of input devices. User interface input devices may include, for example, a motion-sensing and / or gesture recognition device such as a Microsoft Kinect® motion sensor that allows a user to control and interact with an input device, such as a Microsoft Xbox® 360 game controller, through a natural user interface using gestures and spoken commands. User interface input devices may also include an eye gesture recognition device such as a Google Glass® blink detector that detects eye activity from a user (e.g., “blinking” while taking a picture and / or making a menu selection) and translates the eye gesture as input to an input device (e.g., Google Glass®). Additionally, the user interface input devices may include a voice recognition sensing device that allows a user to interact with a voice recognition system (e.g., the Siri® navigator) through voice commands.

[0052] User interface input devices may include, but are not limited to, three-dimensional (3D) mice, joysticks or pointing sticks, gamepads, and graphic tablets, as well as audio / visual devices such as speakers, digital cameras, digital camcorders, portable media players, webcams, image scanners, fingerprint scanners, barcode readers, 3D scanners, 3D printers, laser range finders, and eye-tracking devices. Additionally, user interface input devices may include medical imaging input devices, such as, for example, computed tomography, magnetic resonance imaging, position emission tomography, and medical ultrasound devices. User interface input devices may also include audio input devices, such as, for example, MIDI keyboards, digital musical instruments, and the like.

[0053] User interface output devices may include display subsystems, indicator lights, or non-visual displays such as audio output devices. Display subsystems may be flat-panel devices such as those using cathode ray tubes (CRTs), liquid crystal displays (LCDs), or plasma displays, projection devices, touch screens, etc. In general, use of the term "output device" is intended to include all conceivable types of devices and mechanisms for outputting information from computer system 1100 to a user or to another computer. For example, user interface output devices may include various display devices that visually convey text, graphics, and audio / video information, such as, but not limited to, monitors, printers, speakers, headphones, automobile navigation systems, plotters, voice output devices, and modems.

[0054] Computer system 1100 may include a storage subsystem 1118 that comprises software elements shown as currently residing in system memory 1110. System memory 1110 may store program instructions that are loadable and executable on processing unit 1104, as well as data generated during the execution of these programs.

[0055] Depending on the configuration and type of computer system 1100, system memory 1110 may be volatile (such as random access memory (RAM)) and / or non-volatile (such as read-only memory (ROM), flash memory, etc.). RAM typically contains data and / or program modules that are immediately accessible to and / or presently being operated on and executed by the processing unit 1104. In some implementations, system memory 1110 may include several different types of memory, such as static random access memory (SRAM) or dynamic random access memory (DRAM). In some implementations, a basic input / output system (BIOS), containing the basic routines that help to transfer information between elements within computer system 1100, such as during start-up, may typically be stored in ROM. By way of example and not limitation, system memory 1110 also illustrates application programs 1112, program data 1114, and operating system 1116, which may include client applications, a web browser, a mid-tier application, a relational database management system (RDBMS), etc. By way of example, operating system 1116 may include various versions of Microsoft Windows®, Apple Macintosh®, and / or Linux operating systems, various commercially available UNIX® or UNIX-like operating systems (including, but not limited to, various GNU / Linux operating systems, Google Chrome® OS, etc.), and / or mobile operating systems such as iOS, Windows® Phone, Android® OS, BlackBerry® 10 OS, and Palm® OS operating systems.

[0056] The storage subsystem 1118 may also provide a tangible computer-readable storage medium for storing the basic programming and data constructs that provide the functionality of some embodiments. Software (programs, code modules, instructions) that, when executed by a processor, provide the functionality described above may be stored in the storage subsystem 1118. These software modules or instructions may be executed by the processing unit 1104. The storage subsystem 1118 may also provide a repository for storing data used in accordance with some embodiments.

[0057] Storage subsystem 1100 may also include a computer-readable storage medium reader 1120, which may be further connected to a computer-readable storage medium 1122. Together with, and optionally in combination with, system memory 1110, computer-readable storage medium 1122 may collectively represent remote, local, fixed, and / or removable storage devices and media for containing, storing, transmitting, and retrieving computer-readable information on a temporary and / or more permanent basis.

[0058] The computer-readable storage medium 1122 containing the code, or portions of code, can include any suitable medium, including storage and communication media, such as, but not limited to, volatile and nonvolatile, removable and non-removable media, implemented in any method or technology for information storage and / or transmission. This can include tangible computer-readable storage media, such as RAM, ROM, Electronically Erasable Programmable ROM (EEPROM), flash memory or other memory technology, CD-ROM, digital versatile disk (DVD), or other optical storage, magnetic cassette, magnetic tape, magnetic disk storage, or other magnetic storage devices, or other tangible computer-readable media. This can also include non-tangible computer-readable media, such as a data signal, data transmission, or any other medium that can be used to transmit desired information and that can be accessed by computing system 1100.

[0059] By way of example, the computer-readable storage medium 1122 may include a hard disk drive that reads from or writes to non-removable, non-volatile magnetic media, a magnetic disk drive that reads from or writes to removable, non-volatile magnetic disks, and an optical disk drive that reads from or writes to removable, non-volatile optical disks, such as CD-ROMs, DVDs, and Blu-Ray® disks or other optical media. The computer-readable storage medium 1122 may include, but is not limited to, Zip® drives, flash memory cards, Universal Serial Bus (USB) flash drives, Secure Digital (SD) cards, DVD disks, digital video tapes, etc. The computer-readable storage media 1122 may also include flash memory-based solid-state drives (SSDs), enterprise flash drives, SSDs based on non-volatile memory such as solid-state ROM, solid-state RAM, dynamic RAM, static RAM, DRAM-based SSDs, SSDs based on volatile memory such as magnetoresistive RAM (MRAM) SSDs, and hybrid SSDs that use a combination of DRAM-based SSDs and flash memory-based SSDs. Disk drives and their associated computer-readable media may provide non-volatile storage of computer-readable instructions, data structures, program modules, and other data for the computer system 1100.

[0060] The communications subsystem 1124 provides an interface to other computer systems and networks. The communications subsystem 1124 serves as an interface for receiving data from other systems from the computer system 1100 and for transmitting data to other systems from the computer system 1100. For example, the communications subsystem 1124 may enable the computer system 1100 to connect to one or more devices via the Internet. In some embodiments, the communications subsystem 1124 may include radio frequency (RF) transceiver components, global positioning system (GPS) receiver components, and / or other components for accessing wireless voice and / or data networks (e.g., using cellular telephone technology, advanced data network technologies such as 3G, 4G, or EDGE (Enhanced Data Rates for Global Evolution), WiFi (IEEE 802.11 family of standards), or other mobile communications technologies, or any combination thereof). In some embodiments, the communications subsystem 1124 may provide wired network connectivity (e.g., Ethernet) in addition to or instead of a wireless interface.

[0061] In some embodiments, the communications subsystem 1124 may also receive incoming communications in the form of structured and / or unstructured data feeds 1126, event streams 1128, event updates 1130, etc., for one or more users who may be using the computer system 1100.

[0062] By way of example, the communications subsystem 1124 may be configured to receive data feeds 1126 in real time from users of social networks and / or other communications services, such as web feeds such as Twitter® feeds, Facebook® updates, Rich Site Summary (RSS) feeds, and / or real-time updates from one or more third-party information sources.

[0063] Additionally, the communications subsystem 1124 may also be configured to receive data in the form of a continuous data stream, which may include an event stream 1128 of real-time events and / or event updates 1130, which may be continuous or infinite in nature without an explicit end. Examples of applications that generate continuous data may include, for example, sensor data applications, financial tickers, network performance measurement tools (e.g., network monitoring and traffic management applications), clickstream analysis tools, automobile traffic monitoring, etc.

[0064] The communications subsystem 1124 may also be configured to output structured and / or unstructured data feeds 1126, event streams 1128, event updates 1130, etc. to one or more databases that may be in communication with one or more streaming data source computers coupled to the computer system 1100.

[0065] The computer system 1100 may be one of a variety of types, including a handheld portable device (e.g., an iPhone® cellular phone, an iPad® computing tablet, a PDA), a wearable device (e.g., a Google Glass® head-mounted display), a PC, a workstation, a mainframe, a kiosk, a server rack, or any other data processing system.

[0066] Due to the ever-changing nature of computers and networks, the description of computer system 1100 shown in the figure is intended as a specific example only. Many other configurations are possible, having more or fewer components than the system shown in the figure. For example, customized hardware could also be used, and / or particular elements could be implemented in hardware, firmware, software (including applets), or a combination. Additionally, connections to other computing devices, such as network input / output devices, could be employed. Based on the disclosure and teachings provided herein, other ways and / or methods for implementing various embodiments should be apparent.

[0067] As used herein, the terms "about" or "approximately" or "substantially" can be interpreted as being within the range that would be expected by a person skilled in the art in light of the present specification.

[0068] In the above description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments. It will be apparent, however, that some embodiments may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form.

[0069] The above description provides only exemplary embodiments and is not intended to limit the scope, applicability, or configuration of the present disclosure. Rather, the above description of various embodiments provides an enabling disclosure for implementing at least one embodiment. It should be understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of the several embodiments as set forth in the appended claims.

[0070] Specific details have been given in the above description to provide a thorough understanding of the embodiments. However, it will be understood that the embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in block diagram form in order to avoid obscuring the embodiments in unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail in order to avoid obscuring the embodiments.

[0071] Also, it should be noted that particular embodiments may be described as a process, which is depicted as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. While a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or concurrently. Moreover, the order of operations may be rearranged. A process terminates when its operations are completed, but may have additional steps not included in the diagram. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination may correspond to a return of the function to the calling function or the main function.

[0072] The term "computer-readable medium" includes, but is not limited to, portable or fixed storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or carrying instruction(s) and / or data. A code segment or machine-executable instruction may represent a procedure, a function, a subprogram, a program, a routine, a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements. A code segment may be coupled to another code segment or a hardware circuit by passing and / or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc. may be passed, forwarded, or transmitted via any suitable means including memory sharing, message passing, token passing, network transmission, etc.

[0073] Furthermore, embodiments may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware, or microcode, program code or code segments to perform the necessary tasks may be stored in a machine-readable medium. Processor(s) may perform the necessary tasks.

[0074] In the foregoing specification, features have been described with reference to specific embodiments thereof, but it should be recognized that not all embodiments are limited thereto. Various features and aspects of the several embodiments may be used individually or together. Moreover, the embodiments may be utilized in any number of environments and applications other than those described herein without departing from the broader spirit and scope of the specification. Accordingly, the specification and drawings should be regarded as illustrative rather than restrictive.

[0075] Furthermore, for purposes of explanation, the methods have been described in a particular order. It should be appreciated that in alternative embodiments, the methods may be performed in an order different from that described. It should also be appreciated that the methods described above may be performed by hardware components or may be embodied in a sequence of machine-executable instructions that can be used to cause a machine, such as a general-purpose or special-purpose processor or logic circuitry programmed with instructions, to perform the method. These machine-executable instructions may be stored on one or more machine-readable media, such as a CD-ROM or other type of optical disk, a floppy diskette, ROM, RAM, EPROM, EEPROM, a magnetic or optical card, flash memory, or other type of machine-readable medium suitable for storing electronic instructions. Alternatively, the methods may be performed by a combination of hardware and software.

Claims

1. 1. A three-dimensional (3D) laminated electronic assembly comprising: A printed circuit board; A package substrate; a plurality of integrated circuit (IC) packages attached to the package substrate; a substrate frame disposed between the printed circuit board and the package substrate in the 3D laminated electronic assembly; Equipped with the substrate frame defines a cavity inside the substrate frame and between the printed circuit board and the package substrate; the plurality of IC packages are attached to the package substrate inside the cavity; A three-dimensional (3D) laminated electronic assembly, wherein the substrate frame is divided into a plurality of frame sections, the plurality of frame sections being separated by spaces between the plurality of frame sections.

2. further comprising a second plurality of IC packages; the package substrate has a first side on which the plurality of IC packages are attached inside the cavity; the package substrate has a second side on which the second plurality of IC packages are mounted; the second plurality of IC packages mounted on the second side of the package substrate within the footprint of the cavity; The electronic assembly of claim 1 .

3. 3. The electronic assembly of claim 2, wherein the second plurality of IC packages comprises fewer IC packages than the first plurality of IC packages, thereby causing warpage in the package substrate.

4. The electronic assembly of claim 3 , wherein the spaces between the frame sections of the substrate frame are located adjacent the warp in the package substrate to reduce the warp.

5. The electronic assembly of claim 1 , wherein the printed circuit board extends beyond the footprint of the package substrate.

6. The electronic assembly of claim 1 , further comprising a second package substrate attached to the printed circuit board through a second substrate frame.

7. 1. A substrate frame for a three-dimensional (3D) laminated electronic assembly, the substrate frame comprising: a first side comprising a first interconnect configured to be attached to a first substrate, the first substrate having a plurality of integrated circuit (IC) packages attached thereto; a second side comprising a second interconnect configured to be attached to a second substrate, such that the substrate frame is disposed between the first substrate and the second substrate in the 3D stacked electronic assembly, and a cavity is defined inside the substrate frame and between the first substrate and the second substrate to which the plurality of integrated IC packages are attached; a plurality of frame sections separated by spaces between said plurality of frame sections; A substrate frame comprising:

8. The substrate frame of claim 7 , wherein the substrate frame has a rectangular shape.

9. The substrate frame of claim 7 , wherein the spaces separating the frame sections are located on sides of the substrate frame.

10. The substrate frame of claim 7 , wherein the spaces separating the frame sections are located at corners of the substrate frame.

11. The substrate frame of claim 7 , wherein a width of the frame sections is maintained across the space between the frame sections.

12. The base frame of claim 7 , wherein the spaces between the frame sections are located in the substrate frame such that the substrate frame is symmetrical about an axis.

13. The foundation frame of claim 7 , wherein the width of the frame sections is at least five times greater than the length of the space between the frame sections.

14. 1. A method of assembling a three-dimensional (3D) laminated electronic assembly, the method comprising: Attaching a plurality of integrated circuit (IC) packages to a first substrate; connecting a substrate frame to the first substrate and to a second substrate; Including, the substrate frame defines a cavity inside the substrate frame and between the first substrate and the second substrate; the plurality of IC packages are attached to the first substrate inside the cavity; The method wherein the substrate frame is divided into a plurality of frame sections, the plurality of frame sections being separated by spaces between the plurality of frame sections.

15. The method of claim 14 , further comprising identifying areas of the first substrate that have warpage.

16. 16. The method of claim 15, wherein identifying the area of the first substrate having the warp comprises measuring a displacement of the area of the first substrate after the plurality of IC packages are attached to the first substrate relative to a displacement of the area of the first substrate before the plurality of IC packages are attached to the first substrate.

17. 17. The method of claim 16, further comprising measuring the displacement of the area of the first substrate after connecting the substrate frame to the first substrate to determine whether the displacement of the area has been reduced by attaching the first substrate to the substrate frame.

18. 16. The method of claim 15, wherein identifying the areas of the first substrate having the warpage comprises simulating a 3D model of the first substrate with the plurality of IC packages attached to the first substrate.

19. 20. The method of claim 18, further comprising simulating a 3D model of the substrate frame connected to the 3D model of the first substrate to determine whether adding the 3D model of the substrate frame reduces the warpage in the area.

20. 15. The method of claim 14, further comprising determining locations for the spaces between the plurality of frame sections in the substrate frame based on output provided by a machine learning model trained to receive locations of the plurality of IC packages and to output the locations for the spaces.

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