Impedance matching array, matching method, radio frequency power supply and plasma radio frequency system

Abstract

This application relates to an impedance matching array, a matching method, a radio frequency power supply, and a plasma radio frequency system that solve the problem of impedance matching. The impedance matching array includes a plurality of reactance assemblies connected in parallel in stages between the input and output sides. Each stage of the reactance assembly includes a reactance unit, an input transistor, an output transistor, and a series-connected transistor. The input transistor of a given stage is connected between the input side of the impedance matching array and the input side of the reactance unit of the given stage. The output transistor of a given stage is connected between the output side of the reactance unit of the given stage and the output side of the impedance matching array. The series-connected transistor of a given stage is connected between the output side of the reactance unit of the given stage and the input side of the reactance unit of the next stage. By controlling the on / off states of the input transistors, output transistors, and series-connected transistors in each stage of the reactance assembly, a reactance combination is formed to achieve impedance matching. This application enables rapid impedance matching by switching each of the on / off transistors in the reactance assembly.

Description

[Technical Field]

[0001] The present application is in the technical field of radio frequency power sources, and more particularly, to impedance matching arrays, matching methods, radio frequency power sources, and plasma radio frequency systems. [Background technology]

[0002] The architecture of the integrated radio frequency plasma power supply system includes a radio frequency power supply, a matching box, and a chamber load. The radio frequency power supply outputs a power signal to the matching box, which performs impedance matching and transfers the power signal to the chamber load. During operation, the chamber load experiences load changes due to the execution of a process. The matching box adjusts the impedance in response to the load change, thereby stabilizing the combined impedance of the matching box and the chamber load to approach an ideal value.

[0003] A conventional matcher mainly includes a controller, a driving motor, and a variable reactance. The controller calculates the position where the variable reactance should be adjusted based on information received from the outside, and controls the driving motor to adjust the position of the variable reactance. Conventionally, the driving motor is a stepping motor, and the variable reactance can be a variable capacitor or a variable inductor according to design needs.

[0004] Variable reactance uses a stepper motor to adjust the impedance value. Due to the limited operating speed of the stepper motor, whether it is a capacitor or an inductor, the adjustment assembly displacement can only reach the s level at the fastest. For processes requiring high device precision and fast response, such as semiconductor manufacturing and high-precision coating, conventional matchers have difficulty meeting the demand for fast impedance matching in these processes. Summary of the Invention [Problem to be solved by the invention]

[0005] In view of the above analysis, the purpose of the present application is to disclose an impedance matching array, a matching method, a radio frequency power supply, and a plasma radio frequency system that can quickly meet the demands for impedance matching and can be applied to the impedance matching configurations of various matching networks. [Means for solving the problem]

[0006] One aspect of the present application discloses an impedance matching array connected in an impedance matching network, wherein a plurality of reactance assemblies connected in parallel in stages are included between an input side and an output side of the impedance matching array, and each stage of the reactance assembly includes a reactance unit, an input transistor, an output transistor, and a series-connected transistor, the input transistor of a predetermined stage is connected between the input side of the impedance matching array and the input side of the reactance unit of the predetermined stage, the output transistor of the predetermined stage is connected between the output side of the reactance unit of the predetermined stage and the output side of the impedance matching array, and the series-connected transistor of the predetermined stage is connected between the output side of the reactance unit of the predetermined stage and the input side of the reactance unit of the next stage, By controlling the on or off state of the input transistor, output transistor and series-connected transistor in the reactance assembly of each stage, a reactance combination is formed to achieve impedance matching.

[0007] Another aspect of the present application further discloses an impedance matching method based on the impedance matching array as described above, the method comprising: Step S1: creating an impedance combination lookup table for the impedance matching array, where each impedance matching value corresponds to a transistor combination scheme that can be switched on and off for each reactance assembly for the impedance matching array; Step S2: refer to the impedance combination lookup table based on the required impedance matching value, select a corresponding on / off transistor combination scheme, and control the connection scheme of the reactance units in the impedance matching array to achieve impedance matching; and step S3, if no matching reactance value exists in the impedance combination lookup table, performing approximate high-speed matching, generating control instructions for the on / off transistors, and controlling the connection method of the reactance units in the impedance matching array to achieve approximate impedance matching.

[0008] Another aspect of the present application further discloses a radio frequency power supply system including a radio frequency power supply, a matching box, and a load connected in series, wherein the matching box includes the above-mentioned impedance matching array, and impedance matching is performed by controlling each on / off transistor in a reactance assembly of each stage in the impedance matching array to form a reactance combination having a predetermined connection relationship and adjust the impedance.

[0009] Another aspect of the present application further discloses a plasma radio frequency system including a radio frequency power supply, a matching box, and a chamber load connected in series, wherein the matching box includes the above-mentioned impedance matching array, and when a load change occurs in the chamber load due to the execution of a process, the system controls each on / off transistor of each reactance assembly in the impedance matching array in response to the load change to form a corresponding reactance combination and adjust the impedance, thereby approximating and stabilizing the combined impedance of the matcher and the chamber load to an ideal value.

[0010] (beneficial effects) According to the present application, one of the following beneficial effects can be achieved.

[0011] The present invention achieves rapid impedance matching by switching on and off each transistor in the reactance assembly. The matcher adopts an array design, which is relatively simple to design and manufacture. If there is enough space and enough reactance units can be arranged, more impedance matching points can be accommodated, making the process impedance matching more efficient.

[0012] The drawings are only used to illustrate specific embodiments and are not to be considered as limitations on the present application. The same reference numerals are used in all drawings to denote the same parts. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a schematic diagram illustrating the configuration and connections of a power supply system according to an embodiment of the present application; [Figure 2] FIG. 1 is a schematic diagram illustrating an L-type network connection according to an embodiment of the present application. [Figure 3] FIG. 1 is a schematic diagram illustrating a T-type network connection according to an embodiment of the present application. [Figure 4] FIG. 1 is a schematic diagram illustrating a π-type network connection according to an embodiment of the present application. [Figure 5] 1 is a schematic diagram illustrating the configuration and connections of an impedance matching array according to an embodiment of the present application; [Figure 6] 1 is a schematic diagram illustrating the configuration and connection of a reactance assembly according to an embodiment of the present application. [Figure 7] 1 is a schematic diagram illustrating the configuration and connection of a reactance assembly array, using a capacitor as an example, according to an embodiment of the present application. FIG. [Figure 8] 1 is a schematic diagram illustrating the configuration and connection of a reactance assembly array, taking an inductor as an example, according to an embodiment of the present application. FIG. [Figure 9] FIG. 1 is a schematic diagram illustrating connections of a reactance assembly array in which capacitors and inductors are alternately arranged according to an embodiment of the present application. [Figure 10]FIG. 2 is a schematic diagram illustrating the configuration and connection of a reactance assembly including a bypass transistor according to an embodiment of the present application. [Figure 11] 1 is a schematic diagram illustrating the configuration and connection of a reactance assembly array, using a capacitor as an example, according to an embodiment of the present application. FIG. [Figure 12] 1 is a flowchart illustrating a method for impedance matching of an impedance matching array according to an embodiment of the present application. [Figure 13] FIG. 1 is a schematic diagram illustrating the configuration and connections of a plasma radio frequency power supply system according to an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0014] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which constitute a part hereof and, together with the embodiments thereof, serve to explain the principles of the present invention.

[0015] Example 1 One embodiment of the present application discloses an impedance matching array, which can be applied to, but is not limited to, a matcher of a radio frequency power system such as that shown in Fig. 1. The impedance matching array performs impedance matching in place of an adjustable reactance element in the impedance matching network of the matcher.

[0016] The impedance matching network may include an L-network as shown in FIG. 2, a T-network as shown in FIG. 3, or a π-network as shown in FIG. 4, or may include other types of impedance matching networks.

[0017] The impedance matching network may be designed to include adjustable reactive elements (adjustable capacitors, adjustable inductors) according to the matching needs, or may be designed to include both adjustable reactive elements (adjustable capacitors, adjustable inductors) and non-adjustable fixed elements (fixed capacitors, fixed inductors), in which the adjustable reactive elements may be replaced in whole or in part by corresponding impedance matching arrays to achieve fast impedance matching according to the design needs.

[0018] As shown in FIG. 5 , the impedance matching array connected in the impedance matching network disclosed in this embodiment includes a plurality of reactance assemblies connected in parallel in stages between its input side RFin and output side RFout, The number of stages of the reactance assembly is determined by the maximum impedance value that the impedance matching array can match, and the minimum impedance value in a single-stage reactance assembly is determined by the impedance matching accuracy of the impedance matching array.

[0019] As shown in FIG. 6, the reactance assemblies of each stage have the same configuration, and each may include a reactance unit Zj, an input transistor T1, an output transistor T2, and a series-connected transistor T3, where the input transistor T1 of a given stage is connected between the input side of the impedance matching array and the input side of the reactance unit of the given stage, the output transistor T2 of the given stage is connected between the output side of the reactance unit of the given stage and the output side of the impedance matching array, and the series-connected transistor T3 of the given stage is connected between the output side of the reactance unit of the given stage and the input side of the reactance unit of the next stage; By controlling the on or off state of the input transistor, output transistor and series-connected transistor in each stage of the reactance assembly, the impedance matching array is formed into a reactance combination with a predetermined connection relationship, and the corresponding reactance value is obtained to perform impedance matching.

[0020] Here, the on / off state of the input transistor T1 indicates whether the reactance unit to which it belongs is a receiving unit in the reactance combination, the on / off state of the series-connected transistor T3 indicates whether the reactance unit to which it belongs is connected in series with the reactance unit in the reactance assembly of the next stage, and the on / off state of the output transistor T2 indicates whether it is the output of the reactance combination formed by the reactance units.

[0021] Specifically, the reactance combinations formed include reactance series combinations, parallel combinations, or series and parallel combinations; the reactance units in each stage of the reactance assembly are connected consecutively according to the stage to form reactance series combinations; the reactance units in each stage of the reactance assembly are connected consecutively or intermittently to form reactance parallel combinations; and the series and parallel combinations are a collection of series and parallel combinations.

[0022] The reactance units included in the reactance assemblies of each stage are either capacitor units or inductor units.

[0023] A reactance assembly array using a capacitor as an example is shown in Figure 7. As can be seen from the figure, each reactance assembly is configured as a parallel connection with the same input / output, and a series-connected transistor is connected between the capacitor output side of the reactance assembly of the next stage and the input transistor of a given stage. Since there is no reactance assembly of the next stage, the series-connected transistor in the final stage reactance assembly is not used and is omitted.

[0024] By controlling the on or off states of the input transistor, the output transistor, and the series-connected transistor in the reactance assembly, the reactance combinations formed include combinations of series-connected capacitors, combinations of parallel-connected capacitors, or combinations of series-connected and parallel-connected capacitors.

[0025] In the case of series-connected capacitors, the stage numbers of the reactance assemblies in each stage must be consecutive. That is, among the consecutively numbered reactance assemblies, the input transistor of the first reactance assembly is turned on, the output transistor of the last reactance assembly is turned on, and the series-connected transistors of the remaining intermediate reactance assemblies are turned on to form a series-connected capacitor circuit.

[0026] In the case of parallel connection of capacitors, the numbers of the reactance assemblies of each stage connected in parallel do not need to be consecutive and can be selected according to need. The series-connected transistors between each parallel connection branch are turned off, and the input transistor and output transistor are turned on, forming a parallel connection of capacitors circuit.

[0027] In the case of series / parallel connection of capacitors, any branch constituting the parallel connection circuit may be a series connection branch, and within a series connection branch, capacitors with consecutive numbers are connected in series according to the control method for series connection of capacitors described above, and each series connection branch is connected in parallel according to the control method for parallel connection of capacitors, thereby constituting a series / parallel connection of capacitors.

[0028] In the figure, the series-connected circuits with consecutive numbers C5, C6, ... CA are formed by turning on the input transistor of C5, turning off the output transistor of CA, turning on the series-connected transistors between C5 and CA, and turning off the remaining transistors that can be turned on and off.

[0029] In the figure, the parallel-connected circuits with discontinuous numbers C3, C9, . . . CB are formed by turning on the input and output transistors C3, C9 to CB and turning off the series-connected transistors.

[0030] In the figure, among the parallel connection branches of the formed series / parallel connection circuit, In the first branch C10, the input and output transistors of C10 are turned on, and the series-connected transistors are turned off; In the second branch C14 to C16, the input transistor of C14 is turned on, the output transistor of C16 is turned on, the series-connected transistors of C14 and C15 are turned on, and the remaining transistors that can be turned on and off are turned off. …… In the last branch CC-3 to CC, the input transistor of CC-3 is on, the output transistor of CC is on, the series-connected transistor between CC-3 to CC is on, and the remaining transistors that can be turned on and off are off.

[0031] Based on the above analysis, the configuration rules for series and parallel connection combinations are as follows:

[0032] (1) Form one or more series-connected sections according to the demand for series connection; (2) forming a parallel connection of two or more branches with each other or with one or more independent capacitors; (3) The same reactance unit is limited to being used in one series connection, one parallel connection, or none at all.

[0033] In each of the above series connections, parallel connections, or combinations of both, the capacitors are not limited to being used from the top or bottom, as long as the combined result matches the target capacitance value.

[0034] In a preferred embodiment, a correspondence table between the switching states of the on / off transistors of each capacitor assembly in the capacitor assembly array and the capacitance value of the resulting capacitor array may be formed as a combination lookup table. The lookup table method is used to obtain the switch combination state corresponding to the capacitance value to be matched, and the switching of the capacitor assembly array is controlled to obtain the capacitance value to be matched.

[0035] A reactance assembly array using an inductor as an example is shown in Figure 8. As can be seen from the figure, each reactance assembly is configured as a parallel connection with the same input / same output, and a series-connected transistor is connected between the inductor output side of the reactance assembly of the next stage and the input transistor of a given stage. Since there is no reactance assembly of the next stage in the final stage, the series-connected transistor in the reactance assembly is not used and is omitted.

[0036] By controlling the on or off states of the input transistor, the output transistor, and the series-connected transistor in the reactance assembly, the reactance combinations formed include combinations of inductors connected in series, combinations of inductors connected in parallel, or combinations of inductors connected in series and in parallel.

[0037] In the case of series-connected inductors, the stage numbers of the reactance assemblies in each stage must be consecutive. That is, among the consecutively numbered reactance assemblies, the input transistor of the first reactance assembly is turned on, the output transistor of the last reactance assembly is turned on, and the series-connected transistors of the remaining intermediate reactance assemblies are turned on to form a series-connected inductor circuit.

[0038] In the case of parallel connection of inductors, the numbers of the reactance assemblies of each stage connected in parallel do not need to be consecutive and can be selected according to need. The series-connected transistors between each parallel-connected branch are turned off, and the input transistor and output transistor are turned on, forming a parallel-connected inductor circuit.

[0039] In the case of series / parallel connection of inductors, any branch constituting the parallel connection circuit may be a series connection branch, and within the series connection branch circuit, inductors with consecutive stage numbers are connected in series according to the control method for the series connection of inductors described above, and each series connection branch is connected in parallel according to the control method for the parallel connection of inductors, thereby constituting the series / parallel connection of inductors circuit.

[0040] In the figure, the series-connected circuits with consecutive numbers L5, L6, ... LA are formed by turning on the input transistor of L5, turning off the output transistor of LA, turning on the series-connected transistors between L5 and LA, and turning off the remaining transistors that can be turned on and off.

[0041] In the figure, the parallel-connected circuits with discontinuous numbers from L3, L9, . . . LB are formed by turning on the input and output transistors from L3, L9 to LB and turning off the series-connected transistors.

[0042] In the figure, among the parallel connection branches of the formed series / parallel connection circuit, In the first branch L1 to L2, the input transistor of L1 is turned on, the output transistor of L2 is turned on, the series-connected transistor of L1 is turned on, and the remaining transistors that can be turned on and off are turned off; In the second branch L10, the input and output transistors of L10 are turned on, and the series-connected transistors are turned off; …… In the last branch LC-3 to LC, the input transistor of CC-3 is on, the output transistor of LC is on, the series-connected transistor between LC-3 to LC is on, and the remaining transistors that can be turned on and off are off.

[0043] Based on the above analysis, the configuration rules for series and parallel connection combinations are as follows:

[0044] (1) Form one or more series-connected sections according to the demand for series connection; (2) forming a parallel connection of two or more branches with the series-connected sections, either with each other or with one or more independent inductors; (3) The same reactance unit is limited to being used in one series connection, one parallel connection, or none at all.

[0045] In each of the above series connections, parallel connections, or combinations of both, the inductor is not limited to being used from the highest or lowest inductor, as long as the combined result matches the target inductance value.

[0046] In a preferred embodiment, a correspondence table between the switching states of the on / off transistors of each inductor assembly in the inductor assembly array and the inductance value of the formed inductor array may be formed as a combination lookup table. The lookup table method is used to obtain the switch combination state corresponding to the inductance value to be matched, and the inductor assembly array is then controlled to obtain the inductance value to be matched.

[0047] Furthermore, the reactance units in the reactance assemblies connected in parallel in stages are arranged with capacitors and inductors alternately, so that if the reactance unit in a reactance assembly of a given stage is a capacitive element, the reactance unit in the reactance assembly of the next stage is an inductive element, and vice versa.

[0048] FIG. 9 shows a connection schematic diagram in which capacitors and inductors are alternately arranged.

[0049] As can be seen from the figure, each reactance assembly is configured as a parallel connection with the same input / same output, with capacitors and inductors arranged alternately, and if the reactance assembly of a given stage is a capacitive element, the reactance assembly of the next stage is an inductive element, and a series-connected transistor is connected between the inductor output side of the reactance assembly of the next stage and the input transistor of the given stage, and the series-connected transistor in the final stage reactance assembly is not used and is omitted because there is no reactance assembly of the next stage.

[0050] By controlling the on or off states of the input transistor, output transistor, and series-connected transistor in the reactance assembly, the reactance combinations formed include a parallel capacitor connection, a parallel inductor connection, a parallel capacitor-inductor connection, an alternating LC series connection, or a combination of a series connection and a parallel connection.

[0051] Here, in the case of parallel connection of capacitors, the series-connected transistors of the parallel-connected reactance assemblies of each stage including the capacitance elements are turned off, and the input transistor and output transistor are turned on, forming a parallel connection of capacitors circuit.

[0052] In the case of parallel connection of inductors, the series-connected transistors of the parallel-connected reactance assemblies of each stage including the inductance elements are turned off, and the input and output transistors are turned on, forming a parallel connection of inductors circuit.

[0053] In the case of a parallel connection of capacitors and inductors, the series-connected transistors of each stage of reactance assemblies including parallel-connected capacitance elements and inductance elements are turned off, and the input transistor and output transistor are turned on, forming a parallel connection of capacitors and inductors.

[0054] In the case of an LC alternating series connection, the stage numbers of the reactance assemblies in each stage must be consecutive. That is, among the consecutively numbered reactance assemblies, the input transistor of the first reactance assembly turns on, the output transistor of the last reactance assembly turns on, and the series-connected transistors of the remaining intermediate reactance assemblies turn on to form an inductor series-connected circuit.

[0055] When two consecutive reactance assemblies constitute an LC alternating series connection, an LC series connection circuit can be formed in which a capacitor is connected to an inductor, or an inductor is connected to a capacitor.

[0056] When three consecutive reactance assemblies form an LC alternating series connection, an LC series connection circuit can be formed in which a capacitor is connected to an inductor and then to a capacitor, or an inductor is connected to a capacitor and then to an inductor.

[0057] In this way, an LC alternating multi-stage LC series connection circuit can be formed.

[0058] In the case of a series / parallel connection, any branch constituting the parallel connection circuit may be an LC alternating series connection branch, and within the series connection branch circuit, consecutively numbered inductors and capacitors are alternately connected in series according to the control method for the LC alternating series connection described above, and each series connection branch is connected in parallel according to the control method for the parallel connection, thereby constituting a series / parallel connection circuit.

[0059] In each of the above series connections, parallel connections, or combinations of both, the capacitors or inductors are not limited to being used from the highest or lowest order, as long as the result of the combination matches the target reactance value.

[0060] In a preferred embodiment, a correspondence table between the switching states of the on / off transistors of each reactance assembly in the reactance assembly array and the reactance values ​​of the formed reactance array may be formed as a combination lookup table. The lookup table method is used to obtain the switch combination states corresponding to the reactance values ​​to be matched, and the reactance values ​​to be matched are obtained by controlling the switching of the reactance assembly array.

[0061] 10, the reactance assembly further includes a bypass transistor T4 in addition to the reactance unit Zj, the input transistor T1, the output transistor T2, and the series-connected transistor T3. The bypass transistor of a given stage is connected between the output side of the reactance unit of the given stage and the output side of the reactance unit of the next stage. By adding the bypass transistor T4, various series-parallel connection combinations can be realized, including series connection of reactance elements across stages.

[0062] Specifically, in an impedance matching array using a reactance assembly including a bypass transistor, the capacitance values ​​of the capacitive elements in each reactance assembly may be different, and the inductance values ​​of the inductance elements in each reactance assembly may be different, resulting in an array of reactance elements with different capacitance values ​​or inductance values.

[0063] The basic principle of an impedance matching array using a reactance assembly including a bypass transistor is similar to that of an impedance matching array using a reactance assembly without a bypass transistor. The difference between the two is that in an impedance matching array using a reactance assembly including a bypass transistor, when the bypass transistor is turned on, more impedance control is possible by controlling the transistor that can be turned on and off in the reactance unit of the next stage.

[0064] In the example of the impedance matching array using capacitance elements as shown in FIG. 11, examples of a plurality of series-parallel connections formed by controlling the bypass transistors to be on are given below.

[0065] (1) When the bypass transistor of capacitor C1 is on / series-connected transistor is off / output transistor is off, the input transistor of capacitor C2 is off / output transistor is off / bypass transistor is off / series-connected transistor is on, and the input transistor of capacitor C3 is off, capacitor C2 can be bypassed and capacitors C1 and C3 can be connected in series.

[0066] (2) When the bypass transistor of capacitor C1 is turned on / series-connected transistor is turned off / output transistor is turned off, the input transistor of capacitor C2 is turned on / series-connected transistor is turned on / bypass transistor is turned off / output transistor is turned off, and the input transistor of capacitor C3 is turned off, capacitors C1 and C2 are connected in parallel and then further connected in series with capacitor C3.

[0067] (3) When the bypass transistor of capacitor C1 is turned on / series-connected transistor is turned off / output transistor is turned off, the input transistor of capacitor C2 is turned off / series-connected transistor is turned on / bypass transistor is turned on / output transistor is turned off, the input transistor of capacitor C3 is turned on / series-connected transistor is turned on / bypass transistor is turned off / output transistor is turned off, and the input transistor of capacitor C4 is turned off, capacitors C1 and C3 are connected in parallel and then further connected in series with capacitor C4.

[0068] Otherwise, when all bypass transistors of an impedance matching array using a reactance assembly including bypass transistors are turned off, it is the same in use as an impedance matching array using a reactance assembly without bypass transistors, which makes it more flexible in use.

[0069] Specifically, when forming a series connection circuit from C4, C7, C9... to CA in the figure, First, a series connection between C4 and C7 is formed. When switching control is performed so that the input transistor of C4 is turned on, the bypass transistors of C4 and C5 are turned on, the series-connected transistor of C6 is turned on, and the remaining control transistors of C4 to C7 are turned off, a series connection relationship between C4 and C7 is formed.

[0070] Next, a series connection is formed between C7 and C9, and switching control is performed so that the bypass transistor of C7 is turned on, the series-connected transistor of C8 is turned on, and the remaining control transistors of C7 to C9 are turned off, thereby forming a series connection relationship between C7 and C9.

[0071] According to this control relationship, the capacitors are connected in series one by one, The output transistor of CA is turned on until CA is finally connected in series, and a series connection circuit is formed from the input side, C4, C7, C9, ... up to CA and to the output side.

[0072] In the figure, when forming a parallel-connected circuit from C3 to C8, C1, ... LB, the input transistors and output transistors from C3 to C8, C1, ... LB are turned on, and the series-connected transistors and bypass transistors are turned off, thereby forming parallel-connected inductors from C3 to C8, C1, ... LB.

[0073] In the diagram, when forming a series / parallel connection circuit, each branch connected in parallel must be numbered sequentially, and in each branch, the numbers of the series-connected capacitors included must be arranged in ascending order, and the maximum capacitor number included in the branch with the earlier number must be smaller than the minimum capacitor number included in the branch with the later number.

[0074] In each branch, when capacitors with non-consecutive numbers are connected in series, refer to the control method for connecting capacitors with non-consecutive numbers in series as described above to form a series-connected capacitor group; For multiple branches, refer to the control method for connecting capacitors with non-consecutive numbers in parallel described above, and connect each branch in parallel to form a series / parallel connection circuit.

[0075] Based on the above analysis, the configuration rules for series and parallel connection combinations are as follows:

[0076] (1) According to the needs of series connection, one or more series connection sections can be formed. The capacitors connected in series do not need to be consecutive, as long as the capacitor number of the previous section is smaller than that of the subsequent section. (2) forming a parallel connection of two or more branches with each other or with one or more independent capacitors; (3) The same reactance unit is limited to being used in one series connection, one parallel connection, or none at all.

[0077] In each of the above series connections, parallel connections, or combinations of both, the capacitors are not limited to being used from the top or bottom, as long as the combined result matches the target capacitance value.

[0078] In a preferred embodiment, a correspondence table between the switching states of the on / off transistors of each capacitor assembly in the capacitor assembly array and the capacitance value of the resulting capacitor array may be formed as a combination lookup table. The lookup table method is used to obtain the switch combination state corresponding to the capacitance value to be matched, and the switching of the capacitor assembly array is controlled to obtain the capacitance value to be matched.

[0079] Technical details of the impedance matching array composed of inductive elements, including bypass transistors, can be obtained by reference to the impedance matching array composed of capacitive elements described above.

[0080] Technical details of the impedance matching array of alternating inductors and capacitors including bypass transistors can also be obtained by combining the impedance matching array of alternating capacitors and inductors without bypass transistors with the impedance matching array composed of the above-mentioned capacitive elements.

[0081] Therefore, according to the embodiment of the present application, the impedance value can be quickly changed by switching each on / off transistor in the reactance assembly, thereby achieving rapid impedance matching. The adjustable reactance elements in the matcher are replaced with an impedance matching array, and an array design is adopted, which is relatively simple to design and manufacture. If there is enough space and enough reactance units can be arranged, more impedance matching points can be accommodated in the matcher, making the impedance matching process more efficient.

[0082] Example 2 An embodiment of the present application discloses an impedance matching method based on the impedance matching array described in embodiment 1, and as shown in FIG. 12 , the method includes: Step S1: creating an impedance combination lookup table for the impedance matching array, where each impedance matching value corresponds to a transistor combination scheme that can be switched on and off for each reactance assembly for the impedance matching array; Step S2: refer to the impedance combination lookup table based on the required impedance matching value, select a corresponding on / off transistor combination scheme, and control the connection scheme of the reactance units in the impedance matching array to achieve impedance matching; and step S3, if no matching reactance value exists in the impedance combination lookup table, performing approximate high-speed matching, generating control instructions for the on / off transistors, and controlling the connection method of the reactance units in the impedance matching array to achieve approximate impedance matching.

[0083] Specifically, in approximate fast matching, The present invention includes a method for creating an impedance combination lookup table in which the total number of impedance units is n, the method comprising the steps of: In a first cycle, one impedance unit is enabled; In the second cycle, two impedance units are enabled; (1) The maximum number of rows formed is 1, and the maximum number of series connections per row is 2; (2) The maximum number of rows formed is 2, and the maximum number of series connections per row is 1; In the third cycle, three impedance units are enabled; (1) The maximum number of rows formed is 1, and the maximum number of series connections per row is 3; (2) The maximum number of rows formed is 2, and the maximum number of series connections per row is 2; (3) The maximum number of rows formed is 3, and the maximum number of series connections per row is 1; … In the nth cycle, enable n impedance units; (1) The maximum number of rows formed is 1, and the maximum number of series connections per row is n, (2) The maximum number of rows formed is 2, and the maximum number of series connections per row is n-1. (3) The maximum number of rows formed is 3, and the maximum number of series connections per row is n-2; … (n-1) The number of rows formed is set to a maximum of n-1, and the number of series connections per row is set to a maximum of 2; (n) The maximum number of rows formed is n, and the maximum number of series connections per row is 1; During the execution of the cycle, the reactance values ​​formed at each execution are recorded, and for each enabled impedance unit, the switching states of the input transistors, output transistors, and series-connected transistors that match the reactance unit are correspondingly recorded for the number of parallel-connected rows and the number of series-connected rows to which the impedance unit belongs, and only one set of settings is left for the same reactance value.

[0084] Furthermore, if the reactance assembly further includes a bypass transistor, during execution of cycles in creating the impedance combination lookup table, the reactance values ​​formed for each execution are recorded, and for each enabled impedance unit, the number of parallel-connected rows and the number of series-connected rows to which it belongs are correspondingly recorded, along with the switching states of the input transistor, output transistor, series-connected transistor, and bypass transistor that match the reactance unit, so as to leave only one set of settings for the same reactance value.

[0085] Furthermore, in the approximate high-speed matching, when the reactance units in the impedance matching array are all capacitor units, the step S3 (1) converting the matching capacitance value into a fraction, the denominator of which can be divided into prime factors less than 10, and for a value having a numerator 1 / 4 smaller than the denominator and a mixed fraction of 1 or greater, borrowing 1 from the mixed fraction to form an improper fraction; (2) calculating all prime factors of the denominator, selecting the largest prime factor among the prime factors, and gradually increasing or decreasing the numerator to change it to the nearest multiple of the largest prime factor; (3) reducing the fraction to obtain an irreducible fraction, converting it into a mixed fraction if it is an improper fraction, and then performing a table lookup process; if the numerator of the proper fraction part of the mixed fraction is not 1, decomposing the proper fraction part into multiple fractions each having a numerator of 1, and then performing a table lookup process; (4) If a lookup table is not set, the integer parts of the mixed fraction are regarded as the number of capacitors connected in parallel, the numerator of the proper fraction is the number of rows, and the denominator is the number of capacitors connected in series per row. If the proper fraction can be further reduced, the step of reducing it to an irreducible fraction is included in order to reduce the number of capacitors that are activated.

[0086] Furthermore, in the approximate high-speed matching, when the reactance units in the impedance matching array are all inductor units, the step S3 (1) converting the matching inductance value into a fraction, the denominator of which can be divided into prime factors less than 10, and for a numerator that is 1 / 4 smaller than the denominator and has a mixed fraction of 1 or greater, borrowing 1 from the mixed fraction to form an improper fraction; (2) calculating all prime factors of the denominator, selecting the largest prime factor among the prime factors, and gradually increasing or decreasing the numerator to change it to the nearest multiple of the largest prime factor; (3) reducing the fraction to obtain an irreducible fraction, converting it into a mixed fraction if it is an improper fraction, and then performing a table lookup process; if the numerator of the proper fraction part of the mixed fraction is not 1, decomposing the proper fraction part into multiple fractions each having a numerator of 1, and then performing a table lookup process; (4) If a lookup table is not set, the integer part of the mixed fraction is regarded as the number of inductors connected in series, the numerator of the proper fraction part is the number of sets of inductors connected in parallel, and the denominator is the number of inductors connected in parallel per set. If the proper fraction part can be further reduced, the step of reducing it to an irreducible fraction in order to reduce the number of inductors that are activated.

[0087] For more specific technical details and beneficial effects of this embodiment, please refer to the above-mentioned Example 1, and therefore the description will be omitted here.

[0088] Example 3 One embodiment of the present application discloses a radio frequency power supply system including a radio frequency power supply, a matching box, and a load, The radio frequency power source outputs a power signal to the matcher, and an impedance matching network in the matcher performs impedance matching before transferring the power signal to the load.

[0089] Specifically, the adjustable reactance element included in the impedance matching network in the matching box can be replaced with the impedance matching array described in Example 1, During impedance matching, the reactance combinations with predetermined connection relationships are formed by switching on and off each of the transistors in the reactance assemblies of the impedance matching array, and the impedance is adjusted to achieve impedance matching.

[0090] For the specific technical details and beneficial effects of this embodiment, reference can be made to Example 1, and therefore the description will be omitted here.

[0091] Example 4 One embodiment of the present application discloses a plasma radio frequency system, as shown in FIG. 13, including a radio frequency power supply, a matching box, and a chamber load; The radio frequency power supply outputs a power signal to the matcher, and an impedance matching network within the matcher performs impedance matching before transferring the power signal to the chamber load.

[0092] Specifically, the adjustable reactance element included in the impedance matching network in the matching box can be replaced with the impedance matching array described in Example 1, During operation, if a load change occurs in the chamber load due to the execution of a process, the on / off transistors in each reactance assembly in the impedance matching array included in the inductance matching network can be controlled in response to the load change to form a corresponding reactance combination and adjust the impedance, thereby making the combined impedance of the matcher and the chamber load closer to an ideal value and stabilizing it.

[0093] For the specific technical details and beneficial effects of this embodiment, reference can be made to Example 1, and therefore the description will be omitted here.

[0094] The above description is merely a preferred specific embodiment of the present application, and the scope of protection of the present application is not limited thereto. A person skilled in the art can easily think of modifications or substitutions within the technical scope disclosed in the present application, and all of these should be considered to be included in the scope of protection of the present application.

Claims

1. An impedance matching array comprising: A plurality of reactance assemblies connected in parallel in stages are included between the input side and the output side of the impedance matching array, and each stage of the reactance assembly includes a reactance unit, an input transistor, an output transistor and a series-connected transistor; an input transistor of a given stage is connected between the input side of the impedance matching array and the input side of the reactance unit of the given stage; an output transistor of a given stage connected between an output side of the reactance unit of the given stage and an output side of the impedance matching array; the series-connected transistors of a given stage are connected between the output side of the reactance unit of the given stage and the input side of the reactance unit of the next stage; By controlling the on / off states of the input transistor, output transistor, and series-connected transistor in the reactance assembly of each stage, the impedance matching array is formed into a reactance combination having a predetermined connection relationship, thereby performing impedance matching.

1. An impedance matching array comprising:

2. The reactance combinations formed include a combination of series connections, a combination of parallel connections, or a combination of series connections and parallel connections; In the series combination, the reactance units in each stage of the reactance assembly are connected sequentially according to the stage; In the parallel combination, the reactance units in each stage of the reactance assembly include continuous connection or intermittent connection; A combination of series and parallel connections is a set of combinations of series connections and combinations of parallel connections.

2. The impedance matching array of claim 1.

3. The reactance units included in the reactance assembly of each stage are all capacitor units or all inductor units.

2. The impedance matching array of claim 1.

4. In the reactance assembly connected in parallel in stages, the reactance units are arranged with capacitors and inductors alternately; If the reactance unit in the reactance assembly of a given stage is a capacitive element, The reactance unit in the reactance assembly of the next stage is an inductance element.

2. The impedance matching array of claim 1.

5. the reactance assembly further comprises a bypass transistor; The bypass transistor of a given stage is connected between the output side of the reactance unit of the given stage and the output side of the reactance unit of the next stage. An impedance matching array according to any one of claims 1 to 4.

6. In the impedance matching array using the reactance assembly including the bypass transistor, The capacitance values ​​of the capacitive elements in each reactance assembly are different, The inductance values ​​of the inductance elements in each reactance assembly are different, An array of reactance elements with different capacitance or inductance values ​​is formed 6. An impedance matching array as claimed in claim 5.

7. Step S1: creating an impedance combination lookup table for the impedance matching array, in which each impedance matching value realized by the impedance matching array corresponds to a transistor combination scheme that can be turned on or off for each reactance assembly; Step S2: refer to the impedance combination lookup table based on the required impedance matching value, select a corresponding on / off transistor combination scheme, and control the connection scheme of the reactance units in the impedance matching array to achieve impedance matching; Step S3: if there is no matching reactance value in the impedance combination lookup table, perform approximate high-speed matching, generate control instructions for the on / off transistors, and control the connection manner of the reactance units in the impedance matching array to achieve approximate impedance matching; 7. An impedance matching method based on an impedance matching array according to any one of claims 1 to 6, comprising:

8. In the approximate fast matching, A method for creating an impedance combination lookup table in which the total number of impedance units is n is included, and the creation method includes: In a first cycle, one impedance unit is enabled; In a second cycle, two impedance units are enabled; (1) The maximum number of rows formed is 1, and the maximum number of series connections per row is 2; (2) The maximum number of rows formed is 2, and the maximum number of series connections per row is 1; In the third cycle, three impedance units are enabled; (1) The maximum number of rows formed is 1, and the maximum number of series connections per row is 3; (2) The maximum number of rows formed is 2, and the maximum number of series connections per row is 2; (3) The maximum number of rows formed is 3, and the maximum number of series connections per row is 1; … In the nth cycle, enabling n impedance units; (1) The maximum number of rows formed is 1, and the maximum number of series connections per row is n; (2) The maximum number of rows formed is 2, and the maximum number of series connections per row is n-1; (3) The maximum number of rows formed is 3, and the maximum number of series connections per row is n-2; … (n-1) The number of rows to be formed is set to a maximum of n-1, and the number of series connections per row is set to a maximum of 2; (n) The number of rows to be formed is set to a maximum of n, and the number of series connections per row is set to a maximum of 1; During the execution of the cycle, the reactance value formed at each execution is recorded, and for each enabled impedance unit, the switching states of the input transistors, output transistors, and series-connected transistors corresponding to the corresponding reactance unit are recorded for the number of parallel-connected rows and the number of series-connected rows to which the impedance unit belongs, and only one set of settings is left for the same reactance value.

8. The impedance matching method according to claim 7.

9. If the reactance assembly further includes a bypass transistor, during execution of the cycle for creating the impedance combination lookup table, the reactance value formed at each execution is recorded, and for each enabled impedance unit, the number of parallel connection rows and the number of series connections to which it belongs are recorded, and the switching states of the input transistor, output transistor, series-connected transistor, and bypass transistor that match the reactance unit are recorded, and only one set of settings is left for the same reactance value.

9. The impedance matching method according to claim 8.

10. In the approximate high-speed matching, when all the reactance units in the impedance matching array are capacitor units, step S3 (1) converting the matching capacitance value into a fraction, where the denominator can be divided into prime factors less than 10, the numerator is ¼ smaller than the denominator, and the value has a mixed fraction of 1 or more, by borrowing 1 from the mixed fraction to form an improper fraction; (2) calculating all prime factors of the denominator, selecting the largest prime factor among the prime factors, and gradually increasing or decreasing the numerator to change it to the nearest multiple of the largest prime factor; (3) reducing the fraction to obtain an irreducible fraction, converting it into a mixed fraction if it is an improper fraction, and then performing a table lookup process; if the numerator of the proper fraction part of the mixed fraction is not 1, decomposing the proper fraction part into multiple fractions each having a numerator of 1, and then performing a table lookup process; (4) if no lookup table is set, the integer part of the mixed fraction is regarded as the number of capacitors connected in parallel, the numerator of the proper fraction is the number of rows, and the denominator is the number of capacitors connected in series per row, and if the proper fraction can be further reduced, the step of reducing it to an irreducible fraction in order to reduce the number of capacitors to be activated; 8. The impedance matching method according to claim 7, further comprising:

11. In the approximate high-speed matching, when all the reactance units in the impedance matching array are inductor units, step S3 (1) converting the matching inductance value into a fraction, where the denominator can be divided into prime factors less than 10, the numerator is ¼ less than the denominator, and the value has a mixed fraction of 1 or greater, by borrowing 1 from the mixed fraction to form an improper fraction; (2) calculating all prime factors of the denominator, selecting the largest prime factor among the prime factors, and gradually increasing or decreasing the numerator to change it to the nearest multiple of the largest prime factor; (3) reducing the fraction to obtain an irreducible fraction, converting it into a mixed fraction if it is an improper fraction, and then performing a table lookup process; if the numerator of the proper fraction part of the mixed fraction is not 1, decomposing the proper fraction part into multiple fractions each having a numerator of 1, and then performing a table lookup process; (4) if no lookup table is set, the integer part of the mixed fraction is regarded as the number of inductors connected in series, the numerator of the proper fraction is the number of sets of inductors connected in parallel, and the denominator is the number of inductors connected in parallel per set, and if the proper fraction can be further reduced, the step of reducing it to an irreducible fraction in order to reduce the number of inductors to be activated; 8. The impedance matching method according to claim 7, further comprising:

12. 1. A radio frequency power system, comprising: A radio frequency power supply, a matching box, and a load are connected in series, The matching device includes the impedance matching array according to any one of claims 1 to 6, and performs impedance matching by controlling each transistor that can be turned on and off in a reactance assembly of each stage in the impedance matching array to form a reactance combination having a predetermined connection relationship and adjusting the impedance. A radio frequency power supply system comprising:

13. A radio frequency power supply, a matching box, and a chamber load are connected in series; The matching circuit includes the impedance matching array according to any one of claims 1 to 6, and when a load change occurs in the chamber load due to the execution of a process, the matching circuit controls each on / off transistor of each reactance assembly in the impedance matching array in response to the load change, forms a corresponding reactance combination, and adjusts the impedance, thereby approximating and stabilizing the impedance of the combination of the matching circuit and the chamber load to an ideal value. A plasma radio frequency system comprising:

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