Wiring board and method of manufacturing the same

Abstract

To improve adhesion between a first insulating layer covering an electronic component and a second insulating layer covering the upper surface of the first insulating layer in a wiring board having the electronic component arranged in a cavity.SOLUTION: A core layer, a first wiring layer formed on one surface of the core layer, a second wiring layer formed on the other surface of the core layer, a cavity penetrating the core layer, an electronic component disposed in the cavity, and an insulating layer covering the electronic component in the cavity and extending from the inside of the cavity to the one surface of the core layer, and a second insulating layer covering an upper surface of the first wiring layer and an upper surface of the first insulating layer, wherein the first insulating layer has a recess located on the cavity and recessed from the upper surface of the first insulating layer toward the electronic component, a deepest portion of the recess is located between a plane including the one surface of the core layer and a plane including the upper surface of the first wiring layer, and the second insulating layer fills the recess.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a wiring board and a manufacturing method thereof. [Background technology]

[0002] Wiring boards that accommodate electronic components in openings are known. In such wiring boards, for example, the gap between the electronic components and the inner wall of the opening is filled with a filling resin that is made of a resin different from the resin that constitutes the interlayer insulating layer. In such wiring boards, adhesion between the interlayer insulating layer and the filling resin is important. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-67858 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in consideration of the above points, and aims to improve the adhesion between a first insulating layer covering an electronic component and a second insulating layer covering the upper surface of the first insulating layer in a wiring board having an electronic component placed in a cavity. [Means for solving the problem]

[0005] This wiring board has a core layer, a first wiring layer formed on one surface of the core layer, a second wiring layer formed on the other surface of the core layer, a cavity penetrating the core layer, an electronic component placed in the cavity, a first insulating layer covering the electronic component within the cavity and extending from within the cavity to one surface of the core layer, covering the side surface of the first wiring layer and exposing its upper surface, and a second insulating layer covering the upper surface of the first wiring layer and the upper surface of the first insulating layer, wherein the first insulating layer is located above the cavity and has a recess recessed from the upper surface side of the first insulating layer toward the electronic component, the deepest part of the recess being located between a plane including one surface of the core layer and a plane including the upper surface of the first wiring layer, and the second insulating layer fills the recess. [Effects of the Invention]

[0006] According to the disclosed technology, in a wiring board having an electronic component placed in a cavity, it is possible to improve adhesion between a first insulating layer covering the electronic component and a second insulating layer covering the upper surface of the first insulating layer. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view illustrating a wiring substrate according to an embodiment of the present invention; [Figure 2] 1A to 1C are diagrams illustrating a manufacturing process of a wiring board according to the present embodiment (part 1). [Figure 3] 10A to 10C are diagrams (part 2) illustrating the manufacturing process of the wiring board according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant explanations may be omitted.

[0009] [Wiring board structure] 1 is a cross-sectional view illustrating a wiring board according to this embodiment. Referring to FIG. 1, the wiring board 1 is a wiring board in which wiring layers and insulating layers are laminated on both sides of a core layer 10.

[0010] Specifically, in the wiring board 1, a wiring layer 12, an insulating layer 13, a wiring layer 14, an insulating layer 15, a wiring layer 16, and a solder resist layer 17 are sequentially stacked on one surface 10a of the core layer 10. Furthermore, a wiring layer 22, an insulating layer 23, a wiring layer 24, an insulating layer 25, a wiring layer 26, and a solder resist layer 27 are sequentially stacked on the other surface 10b of the core layer 10. The numbers of wiring layers and insulating layers stacked on one surface 10a and the other surface 10b of the core layer 10 are not limited to the example in FIG. 1 .

[0011] In this embodiment, for convenience, the solder resist layer 17 side of the wiring board 1 is referred to as the upper side or one side, and the solder resist layer 27 side is referred to as the lower side or the other side. Furthermore, the surface of each part facing the solder resist layer 17 is referred to as one side or the upper side, and the surface facing the solder resist layer 27 is referred to as the other side or the lower side. However, the wiring board 1 can be used upside down or positioned at any angle. Furthermore, a planar view refers to viewing an object from the normal direction of one surface 10a of the core layer 10, and a planar shape refers to the shape of the object viewed from the normal direction of one surface 10a of the core layer 10.

[0012] The core layer 10 may be, for example, a so-called glass epoxy substrate obtained by impregnating glass cloth with an insulating resin such as an epoxy resin. Alternatively, the core layer 10 may be a substrate obtained by impregnating a woven or nonwoven fabric such as glass fiber, carbon fiber, or aramid fiber with an epoxy resin. The core layer 10 has a thickness of, for example, about 60 to 1600 μm. The core layer 10 has through holes 10x that penetrate the core layer 10 in the thickness direction. The planar shape of the through holes 10x is, for example, a circle.

[0013] The core layer 10 has a cavity 10z formed therein that penetrates the core layer 10 and exposes the upper surface of the insulating layer 23. An electronic component 30 is disposed within the cavity 10z. The electronic component 30 includes a main body 31 and an electrode 32 formed on the electrode-forming surface of the main body 31. The electronic component 30 is disposed face-down within the cavity 10z, with the electrode 32 facing the wiring layer 22. The lower surface of the electrode 32 is flush with the lower surface of the wiring layer 22, for example. The height from the lower surface of the wiring layer 22 to the upper surface of the main body 31 is lower than the height from the lower surface of the wiring layer 22 to one surface 10a of the core layer 10. The lower surface of the main body 31 may be located closer to the wiring layer 24 than the other surface 10b of the core layer 10.

[0014] The electronic component 30 may be a passive component or an active component. The electronic component 30 is, for example, an integrated passive device (IPD), a semiconductor chip, a capacitor, an inductor, a resistor, or the like. The planar shape of the cavity 10z is, for example, similar to the planar shape of the electronic component 30, and is larger than the electronic component 30. Multiple electronic components 30 may be arranged in the cavity 10z.

[0015] The wiring layer 12 is formed on one surface 10a of the core layer 10. The wiring layer 22 is formed on the other surface 10b of the core layer 10. The wiring layer 12 and the wiring layer 22 are electrically connected by through wirings 11 formed in the through holes 10x. In the illustrated example, a resin body 19 is filled in the center of the through wiring 11. The resin body 19 is, for example, cylindrical, with an upper end protruding into the wiring layer 12 and a lower end protruding into the wiring layer 22. The through wiring 11 does not necessarily have to have the resin body 19. In this case, the entire through hole 10x is filled with the through wiring 11.

[0016] The wiring layers 12 and 22 are each patterned into a predetermined planar shape. The wiring layers 12 and 22 and the through wires 11 may be made of, for example, copper (Cu). The thickness of the wiring layers 12 and 22 is, for example, about 25 to 45 μm. However, the wiring layer 12 may be thinner than the wiring layer 22 by several μm. The wiring layers 12, 22, and the through wires 11 may be formed integrally.

[0017] The insulating layer 13 includes a first insulating layer 13a and a second insulating layer 13b. The first insulating layer 13a is a buried insulating layer disposed in the cavity 10z. The first insulating layer 13a covers the electronic component 30 in the cavity 10z, extends from the cavity 10z to one surface 10a of the core layer 10, covers the side surfaces of the wiring layer 12, and exposes the upper surface. The first insulating layer 13a may extend from the cavity 10z to a portion of the other surface 10b of the core layer 10. However, in the electronic component 30, a portion of the electrode formation surface of the main body 31 may not be covered by the first insulating layer 13a but may be covered by the insulating layer 23. The region of the electrode formation surface of the main body 31 covered by the insulating layer 23 may be the entire region located between adjacent electrodes 32, or may be a portion of the region located between adjacent electrodes 32.

[0018] The first insulating layer 13a has a recess 13z located above the cavity 10z and recessed from the upper surface side of the first insulating layer 13a toward the electronic component 30. At least a portion of the recess 13z is located so as to overlap with the cavity 10z in a planar view. For example, the outer periphery of the recess 13z does not have to be located so as to overlap with the cavity 10z in a planar view. The outer periphery of the recess 13z may be located outside the cavity 10z in a planar view. The recess 13z is, for example, bowl-shaped. Here, the bowl-shaped recess is a shape whose depth gradually deepens from the periphery toward the center, with an R-shaped inner wall surface.

[0019] The recess 13z is provided within the thickness T of the wiring layer 12. That is, the deepest part of the recess 13z is located between a plane including one surface 10a of the core layer 10 and a plane including the upper surface of the wiring layer 12. The deepest part of the recess 13z does not extend further toward the electronic component 30 than the plane including one surface 10a of the core layer 10. The depth D of the recess 13z is, for example, not less than 1 μm and not more than 30 μm. That is, the distance between the plane including the upper surface of the wiring layer 12 and the deepest part of the recess 13z is not less than 1 μm and not more than 30 μm.

[0020] The first insulating layer 13a located on one surface 10a of the core layer 10 covers the side surfaces of the wiring layer 12 and exposes its upper surface. The upper surface of the first insulating layer 13a is, for example, flush with the upper surface of the wiring layer 12. The thickness of the first insulating layer 13a located on one surface 10a of the core layer 10 is approximately the same as the thickness of the wiring layer 12.

[0021] The second insulating layer 13b covers the upper surface of the wiring layer 12 and the upper surface of the first insulating layer 13a. The second insulating layer 13b fills the recesses 13z. The upper surface of the second insulating layer 13b is preferably flat. The thickness of the second insulating layer 13b located on one surface 10a of the core layer 10 can be, for example, about 30 to 40 μm.

[0022] The second insulating layer 13b may be made of an insulating resin containing, for example, an epoxy resin or a polyimide resin as a main component. The second insulating layer 13b may contain a filler such as silica (SiO2). The first insulating layer 13a is preferably made of an insulating resin with higher fluidity than the second insulating layer 13b.

[0023] The second insulating layer 13b is provided with a via hole 13x that penetrates the second insulating layer 13b and exposes the upper surface of the wiring layer 12. The via hole 13x can be a recessed portion in the shape of an inverted truncated cone, with the diameter of the opening that opens on the insulating layer 15 side being larger than the diameter of the bottom of the opening formed by the upper surface of the wiring layer 12.

[0024] The wiring layer 14 is formed on one side of the insulating layer 13. The wiring layer 14 is configured to include via wirings filled in the via holes 13x and a wiring pattern formed on the upper surface of the insulating layer 13. The wiring pattern is electrically connected to the wiring layer 12 through the via wirings. The material of the wiring layer 14 and the thickness of the wiring pattern can be the same as those of the wiring layer 22, for example.

[0025] The insulating layer 15 is formed on the upper surface of the insulating layer 13 so as to cover the wiring layer 14. The material and thickness of the insulating layer 15 may be the same as those of the second insulating layer 13b, for example. The insulating layer 15 may contain a filler such as silica (SiO2).

[0026] The insulating layer 15 is provided with via holes 15x that penetrate the insulating layer 15 and expose the upper surface of the wiring layer 14. The via holes 15x can be recesses in the shape of inverted truncated cones, with the diameter of the opening on the solder resist layer 17 side being larger than the diameter of the bottom of the opening formed by the upper surface of the wiring layer 14.

[0027] The wiring layer 16 is formed on one side of the insulating layer 15. The wiring layer 16 is configured to include via wirings filled in the via holes 15x and a wiring pattern formed on the upper surface of the insulating layer 15. The wiring pattern is electrically connected to the wiring layer 14 through the via wirings. The material of the wiring layer 16 and the thickness of the wiring pattern can be the same as those of the wiring layer 22, for example.

[0028] The solder resist layer 17 is a protective insulating layer located on the outermost side of one side of the wiring board 1, and is formed on the upper surface of the insulating layer 15 so as to cover the wiring layer 16. The solder resist layer 17 can be formed from, for example, a photosensitive epoxy insulating resin or an acrylic insulating resin. The thickness of the solder resist layer 17 is, for example, about 15 to 35 μm.

[0029] The solder resist layer 17 has openings 17x. The openings 17x penetrate the solder resist layer 17 and expose the upper surface of the wiring layer 16. The wiring layer 16 exposed in the openings 17x can be used as pads for electrical connection to electronic components such as semiconductor chips, for example.

[0030] Note that a metal layer may be formed on the surface of the wiring layer 16 exposed in the opening 17x, or an organic coating may be formed by performing an anti-oxidation treatment such as an OSP (Organic Solderability Preservative) treatment. Examples of the metal layer include an Au layer, a Ni / Au layer (a metal layer formed by laminating a Ni layer and a Au layer in this order), a Ni / Pd / Au layer (a metal layer formed by laminating a Ni layer, a Pd layer, and a Au layer in this order), and a Sn layer.

[0031] The insulating layer 23 is formed on the other surface 10b of the core layer 10 so as to cover the wiring layer 22. The insulating layer 23 also covers the lower surface of the first insulating layer 13a that extends to the other surface 10b of the core layer 10. The material and thickness of the insulating layer 23 may be the same as those of the second insulating layer 13b, for example. The insulating layer 23 may contain a filler such as silica (SiO2).

[0032] The insulating layer 23 is provided with a via hole 23x that penetrates the insulating layer 23 and exposes the lower surface of the wiring layer 22. The insulating layer 23 is also provided with a via hole 23y that penetrates the insulating layer 23 and exposes the lower surface of the electrode 32 of the electronic component 30. The via holes 23x and 23y can be truncated cone-shaped recesses in which the diameter of the opening that opens on the insulating layer 25 side is larger than the diameter of the bottom of the opening formed by the lower surface of the wiring layer 22 and the lower surface of the electrode 32.

[0033] The wiring layer 24 is formed on the lower surface side of the insulating layer 23. The wiring layer 24 is configured to include via wiring filled in the via holes 23x, via wiring filled in the via holes 23y, and a wiring pattern formed on the lower surface of the insulating layer 23. A part of the wiring pattern is electrically connected to the wiring layer 22 through the via wiring filled in the via holes 23x. Another part of the wiring pattern is electrically connected to the electrode 32 through the via wiring filled in the via hole 23y. The material of the wiring layer 24 and the thickness of the wiring pattern can be the same as those of the wiring layer 22, for example.

[0034] Insulating layer 25 is formed on the lower surface of insulating layer 23 so as to cover wiring layer 24. The material and thickness of insulating layer 25 may be the same as those of second insulating layer 13b, for example. Insulating layer 25 may contain a filler such as silica (SiO2).

[0035] The insulating layer 25 is provided with via holes 25x that penetrate the insulating layer 25 and expose the lower surface of the wiring layer 24. The via holes 25x can be truncated cone-shaped recesses whose openings on the solder resist layer 27 side have a diameter larger than the diameter of the bottom of the openings formed by the lower surface of the wiring layer 24.

[0036] The wiring layer 26 is formed on the other side of the insulating layer 25. The wiring layer 26 is configured to include via wirings filled in the via holes 25x and a wiring pattern formed on the lower surface of the insulating layer 25. The wiring pattern is electrically connected to the wiring layer 24 through the via wirings. The material of the wiring layer 26 and the thickness of the wiring pattern can be the same as those of the wiring layer 22, for example.

[0037] The solder resist layer 27 is a protective insulating layer located at the outermost position on the other side of the wiring board 1, and is formed on the lower surface of the insulating layer 25 so as to cover the wiring layer 26. The material and thickness of the solder resist layer 27 may be, for example, the same as those of the solder resist layer 17. The solder resist layer 27 has openings 27x, and a portion of the lower surface of the wiring layer 26 is exposed in the openings 27x. The planar shape of the openings 27x may be, for example, circular. The wiring layer 26 exposed in the openings 27x can be used as a pad for electrically connecting to a mounting substrate such as a motherboard. If necessary, the aforementioned metal layer may be formed on the lower surface of the wiring layer 26 exposed in the openings 27x, or an anti-oxidation treatment such as OSP treatment may be performed.

[0038] Thus, in wiring board 1, first insulating layer 13a covering electronic component 30 in cavity 10z has recess 13z recessed from the upper surface side of first insulating layer 13a toward electronic component 30, and second insulating layer 13b fills recess 13z. By providing recess 13z and having second insulating layer 13b fill recess 13z, the area of ​​contact between first insulating layer 13a and second insulating layer 13b increases, thereby improving adhesion between first insulating layer 13a and second insulating layer 13b.

[0039] For example, gas contained in first insulating layer 13a may try to escape to second insulating layer 13b in the manufacturing process of wiring board 1. In this case, if the adhesion between first insulating layer 13a and second insulating layer 13b is poor, there is a concern that the pressure of the gas may cause swelling in second insulating layer 13b. However, in wiring board 1, the adhesion between first insulating layer 13a and second insulating layer 13b is good, so the occurrence of swelling can be suppressed.

[0040] Furthermore, in the wiring substrate 1, the deepest part of the recess 13z is located between a plane including one surface 10a of the core layer 10 and a plane including the upper surface of the wiring layer 12. This prevents the recess 13z from becoming too deep, and therefore prevents the upper surface of the second insulating layer 13b from conforming to the shape of the recess 13z and losing the flatness of the upper surface of the second insulating layer 13b.

[0041] Furthermore, in the wiring board 1, a portion of the electrode-forming surface of the electronic component 30 is covered with the insulating layer 23. This creates an anchor effect, and can improve the adhesion between the insulating layer 23 and the electronic component 30 and between the insulating layer 23 and the first insulating layer 13a.

[0042] Furthermore, in the wiring board 1, the upper surface of the wiring layer 12 is exposed from the first insulating layer 13a and is covered with the second insulating layer 13b. A resin material with excellent insulating properties and moisture resistance can be selected for the second insulating layer 13b without considering the filling ability into the cavity 10z, thereby improving the reliability of the wiring board 1. Note that for the first insulating layer 13a, the filling ability into the cavity 10z takes priority over the insulating properties and moisture resistance.

[0043] [Method of manufacturing wiring board] 2 and 3 are diagrams illustrating the manufacturing process of the wiring board according to this embodiment, and are cross-sectional views corresponding to Fig. 1. Here, an example of the process for manufacturing one wiring board is shown, but the process may also be such that multiple parts that will become the wiring board are manufactured and then separated into individual wiring boards.

[0044] 2(a), a core layer 10 is prepared, which includes a wiring layer 12 on one surface 10a, a wiring layer 22 on the other surface 10b, and through-holes 10x with through-wires 11 and resin bodies 19 in the through-holes 10x. Specifically, a laminate is prepared, such as a so-called glass epoxy substrate, on which unpatterned, plain copper foil is formed on one and the other surfaces of the core layer 10. Then, through-holes 10x are formed in the prepared laminate by laser processing using a CO2 laser or the like, penetrating the core layer 10 and the copper foil on each surface. If necessary, a desmear process is performed to remove any resin residue from the core layer 10 adhering to the inner wall surfaces of the through-holes 10x.

[0045] Next, a seed layer (copper, etc.) is formed on each surface by electroless plating, sputtering, or the like, covering the copper foil on each surface and the inner wall surfaces of the through holes 10x. Then, an electrolytic plating layer (copper, etc.) is formed on the seed layer by electrolytic plating using the seed layer as a power supply layer. At this time, through holes are formed inside the electrolytic plating layer, and these through holes are filled with an epoxy resin or the like to form a resin body 19. As a result, the through holes 10x are filled with the electrolytic plating layer formed on the seed layer, forming through wirings 11, and further, a resin body 19 is formed inside the through wirings 11. Metal layers made of copper or the like are formed on the through wirings 11 and the resin body 19 on both surfaces by electroless plating and electrolytic plating. Wiring layers 12 and 22, each composed of a copper foil, a seed layer, an electrolytic plating layer, and a metal layer, are formed on one surface 10a and the other surface 10b of the core layer 10. Next, the wiring layers 12 and 22 are patterned into a predetermined planar shape by a subtractive method or the like. At this point, the wiring layer 12 has the same thickness as the wiring layer 22.

[0046] 2(b), a cavity 10z is formed in the core layer 10, penetrating from one surface 10a to the other surface 10b. The cavity 10z can be formed by, for example, laser processing or router processing. If necessary, a desmearing process is performed to remove any resin residue from the core layer 10 adhering to the inner wall surface of the cavity 10z.

[0047] Next, in the step shown in FIG. 2(c), an electronic component 30 is placed in the cavity 10z. Specifically, first, a support film 100 is laminated on the lower surface of the wiring layer 22 so as to close the cavity 10z. For example, a resin film with low adhesive strength can be used as the support film 100. Next, an electronic component 30 equipped with electrodes 32 is placed face down on the upper surface of the support film 100 exposed in the cavity 10z. For example, a component mounter can be used to place the electronic component 30.

[0048] Next, in the step shown in FIG. 2(d), a first insulating layer 13a is formed in the cavity 10z. The first insulating layer 13a covers the electronic component 30 in the cavity 10z, extends from the cavity 10z onto one surface 10a of the core layer 10, and covers the top and side surfaces of the wiring layer 12. The first insulating layer 13a extends from the cavity 10z onto a portion of the other surface 10b of the core layer 10. The first insulating layer 13a can be formed, for example, by applying and curing a liquid or paste-like epoxy resin or the like so that the resin covers the electronic component 30 and extends from the cavity 10z onto one surface 10a of the core layer 10. In this process, the viscosity, application amount, application time, etc. of the insulating resin that will become the first insulating layer 13a are adjusted to form a void S in a portion of the electrode-forming surface of the body 31 of the electronic component 30 that is not covered by the first insulating layer 13a. The height of the gap S, that is, the height of the electrode 32, can be set to, for example, about 10 μm. Thereafter, the support film 100 is peeled off.

[0049] Next, in the step shown in FIG. 3(a), the upper surface of the first insulating layer 13a is polished to expose the upper surface of the wiring layer 12 and form a recess 13z located above the cavity 10z and recessed from the upper surface of the first insulating layer 13a toward the electronic component 30. The amount of polishing is adjusted so that the deepest portion of the recess 13z is located between a plane including one surface 10a of the core layer 10 and a plane including the upper surface of the wiring layer 12, i.e., so that the deepest portion of the recess 13z does not extend beyond the one surface 10a of the core layer 10 toward the electronic component 30. For example, a buffing machine can be used for polishing. Since the upper surface of the wiring layer 12 is also polished, the thickness of the wiring layer 12 is thinner than the thickness of the wiring layer 22 by several micrometers. Furthermore, the roughness of the upper surface of the wiring layer 12 is less than that of the lower surface of the wiring layer 22. For example, the roughness of the upper surface of the wiring layer 12 is Ra 300 nm or more and 500 nm or less, and the roughness of the lower surface of the wiring layer 22 is Ra 400 nm or more and 600 nm or less.

[0050] Next, in the step shown in FIG. 3(b), a second insulating layer 13b is formed to cover the upper surfaces of the wiring layer 12 and the first insulating layer 13a. Specifically, for example, a semi-cured film-like epoxy resin or the like is laminated to cover the upper surfaces of the wiring layer 12 and the first insulating layer 13a and then cured to form the second insulating layer 13b. The second insulating layer 13b fills the recesses 13z. The second insulating layer 13b is preferably formed so that its upper surface is flat. Furthermore, a semi-cured film-like epoxy resin or the like is laminated on the other surface 10b of the core layer 10 to cover the wiring layer 22 and then cured to form the insulating layer 23. The insulating layer 23 is formed to cover the lower surfaces of the electrodes 32 of the electronic component 30 and fill the voids S. Note that instead of laminating a film-like epoxy resin or the like, the second insulating layer 13b and the insulating layer 23 may be formed by applying a liquid or paste-like epoxy resin or the like and then curing it.

[0051] Next, in the step shown in FIG. 3(c), wiring layers 14 and 24 are formed. Specifically, first, a via hole 13x is formed in the second insulating layer 13b, penetrating the second insulating layer 13b and exposing the upper surface of the wiring layer 12. Furthermore, a via hole 23x is formed in the insulating layer 23, penetrating the insulating layer 23 and exposing the lower surface of the wiring layer 22, and a via hole 23y is formed in the insulating layer 23, penetrating the insulating layer 23 and exposing the lower surface of the electrode 32 of the electronic component 30. The via holes 13x, 23x, and 23y can be formed by laser processing using, for example, a CO laser. After the via holes 13x, 23x, and 23y are formed, a desmear process is preferably performed to remove resin residues adhering to the surfaces of the wiring layer 12, the wiring layer 22, and the electrode 32, respectively, exposed at the bottoms of the via holes 13x, 23x, and 23y.

[0052] Next, a wiring layer 14 is formed on one side of the insulating layer 13. The wiring layer 14 includes via wirings filled in the via holes 13x and a wiring pattern formed on the upper surface of the second insulating layer 13b. The wiring layer 14 is electrically connected to the wiring layer 12 exposed at the bottom of the via holes 13x.

[0053] Also, a wiring layer 24 is formed on the other side of the insulating layer 23. The wiring layer 24 is configured to include via wiring filled in the via holes 23x, via wiring filled in the via holes 23y, and a wiring pattern formed on the lower surface of the insulating layer 23. A part of the wiring pattern is electrically connected to the wiring layer 22 through the via wiring filled in the via holes 23x. Another part of the wiring pattern is electrically connected to the electrode 32 through the via wiring filled in the via hole 23y.

[0054] The wiring layers 14 and 24 can be formed using various wiring formation methods, such as semi-additive and subtractive methods. For example, when forming the wiring layer 14 using the semi-additive method, a seed layer is formed by electroless copper plating on the surface of the second insulating layer 13b, including the inner walls of the via holes 13x, and on the surface of the wiring layer 12 exposed in the via holes 13x. Next, a plating resist pattern having openings corresponding to the shape of the wiring pattern constituting the wiring layer 14 is formed on the seed layer. Next, an electroplated layer is deposited on the seed layer exposed in the openings of the plating resist pattern by electroplating copper using power supplied from the seed layer. Next, the plating resist pattern is removed, and then etching is performed using the electroplated layer as a mask to remove the seed layer exposed from the electroplated layer, thereby obtaining the wiring layer 14 having via wiring and a wiring pattern. The wiring layer 24 can also be formed using a similar method.

[0055] Next, in the step shown in Figure 3(d), an insulating layer 15 is formed on the upper surface of the insulating layer 13 so as to cover the wiring layer 14. Furthermore, an insulating layer 25 is formed on the lower surface of the insulating layer 23 so as to cover the wiring layer 24. The insulating layers 15 and 25 can be formed, for example, by the same method as that for the second insulating layer 13b. Next, similar to Figure 3(c), a wiring layer 16 is formed on one side of the insulating layer 15, and a wiring layer 26 is formed on the other side of the insulating layer 25.

[0056] Next, a solder resist layer 17 is formed on the upper surface of the insulating layer 15 so as to cover the wiring layer 16. Furthermore, a solder resist layer 27 is formed on the lower surface of the insulating layer 25 so as to cover the wiring layer 26. The solder resist layer 17 can be formed, for example, by applying a liquid or paste-like photosensitive epoxy insulating resin or acrylic insulating resin to the upper surface of the insulating layer 15 by screen printing, roll coating, spin coating, or the like so as to cover the wiring layer 16. Alternatively, for example, the solder resist layer 17 may be formed by laminating a film-like photosensitive epoxy insulating resin or acrylic insulating resin on the upper surface of the insulating layer 15 so as to cover the wiring layer 16. The method for forming the solder resist layer 27 is the same as that for the solder resist layer 17.

[0057] Next, the solder resist layers 17 and 27 are exposed and developed to form openings 17x in the solder resist layer 17 that expose a portion of the upper surface of the wiring layer 16 (photolithography). Also, openings 27x are formed in the solder resist layer 27 that expose a portion of the lower surface of the wiring layer 26 (photolithography). The planar shape of each of the openings 17x and 27x may be, for example, circular. The diameter of each of the openings 17x and 27x can be arbitrarily designed to suit the connection target (such as a semiconductor chip or a motherboard).

[0058] In this step, the above-mentioned metal layer may be formed by, for example, electroless plating on the upper surface of the wiring layer 16 exposed at the bottom of the opening 17x and the lower surface of the wiring layer 26 exposed at the bottom of the opening 27x. Alternatively, instead of forming a metal layer, an anti-oxidation treatment such as OSP treatment may be performed. Through the above steps, the wiring board 1 is completed.

[0059] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. [Explanation of symbols]

[0060] 1. Wiring board 10 Core Layer 10a One side 10b The other side 10x through holes 10z cavity 11 Through wiring 12,14,16,22,24,26 wiring layer 13,15,23,25 Insulation layer 13a First insulating layer 13b Second insulating layer 13x, 15x, 23x, 23y, 25x via holes 13z Recess 17,27 Solder resist layer 17x,27x opening 19 Resin body 30 Electronic Components 31 Main Unit 32 electrodes 100 Support Film

Claims

1. A core layer; a first wiring layer formed on one surface of the core layer; a second wiring layer formed on the other surface of the core layer; a cavity penetrating the core layer; an electronic component disposed within the cavity; a first insulating layer that covers the electronic component in the cavity, extends from the cavity to one surface of the core layer, covers a side surface of the first wiring layer, and exposes an upper surface thereof; a second insulating layer covering an upper surface of the first wiring layer and an upper surface of the first insulating layer; the first insulating layer has a recessed portion located above the cavity and recessed from an upper surface side of the first insulating layer toward the electronic component, the deepest part of the recess is located between a plane including one surface of the core layer and a plane including an upper surface of the first wiring layer, The second insulating layer fills the recess.

2. The wiring board according to claim 1 , wherein the first wiring layer is thinner than the second wiring layer.

3. The wiring board according to claim 2 , wherein the upper surface of the first wiring layer has a roughness smaller than that of the lower surface of the second wiring layer.

4. The wiring board according to claim 2 , wherein an upper surface of the first wiring layer is flush with an upper surface of the first insulating layer.

5. a third insulating layer covering the second wiring layer on the other surface of the core layer; the electronic component has an electrode formation surface on which electrodes are formed, and is placed in the cavity with the electrodes facing the second wiring layer side; The wiring board according to claim 1 , wherein a part of the electrode formation surface is covered with the third insulating layer.

6. 5. The wiring board according to claim 1, wherein a distance between a plane including an upper surface of the first wiring layer and a deepest portion of the recess is 1 [mu]m or more and 30 [mu]m or less.

7. preparing a core layer having a first wiring layer on one side and a second wiring layer on the other side; forming a cavity through the core layer; placing an electronic component within the cavity; forming a first insulating layer that covers the electronic component in the cavity, extends from the cavity to one surface of the core layer, and covers an upper surface and a side surface of the first wiring layer; polishing the upper surface of the first insulating layer to expose the upper surface of the first wiring layer and form a recess located above the cavity and recessed from the upper surface of the first insulating layer toward the electronic component; forming a second insulating layer covering an upper surface of the first wiring layer and an upper surface of the first insulating layer; the deepest part of the recess is located between a plane including one surface of the core layer and a plane including an upper surface of the first wiring layer, The second insulating layer fills the recess.

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