Wiring board and method for manufacturing the same

Abstract

This invention discloses a technology that makes the mounting area and its surroundings flatter than before, thereby improving the reliability of connections with surface-mounted electronic components. [Solution] In this embodiment, the wiring board 10 is constructed by alternately stacking a plurality of conductive layers 30, each containing a first conductive layer with a frame-shaped plane portion 34, and a plurality of insulating layers. Of the outermost surface, the region overlapping with the region inside the plane portion 34 when viewed from the stacking direction is the mounting region on which electronic components are mounted. Furthermore, the plurality of conductive layers 30 of the wiring board 10 are provided with resin receiving portions 35 into which the resin of the insulating layer enters. The inner peripheral portion R21, including the inner edge of the plane portion 34, has a larger proportion of the resin receiving portion 35 compared to the outer peripheral portion R22 outside the inner peripheral portion R21.

Description

Technical Field

[0004] , ,

[0005] , , ,

[0001] The present disclosure relates to a wiring board in which a plurality of conductive layers and a plurality of insulating layers are alternately laminated, and a method for manufacturing the same.

Background Art

[0002] Conventionally, as this type of wiring board, a first conductive layer having a frame-shaped plane portion is included in a plurality of conductive layers, and the inside of the outermost surface of the wiring board that is inside the plane portion is a mounting area where electronic components are surface-mounted. (For example, see Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the conventional wiring board described above, the remaining copper ratio is lower on the inner side surrounded by the plane portion than the plane portion. Therefore, among the insulating layers laminated on the first conductive layer, the insulating layer laminated on the plane portion is thicker than the insulating layer laminated inside the plane portion. As a result, the mounting area may be recessed, and the connection with the surface-mounted electronic components may be insufficient. Therefore, the present application discloses a technology capable of making the mounting area and its periphery flatter than before and improving the connection reliability with surface-mounted electronic components.

Means for Solving the Problems

[0005] A wiring board according to one aspect of the present disclosure is a wiring board in which a plurality of conductive layers and a plurality of insulating layers are alternately laminated, including a first conductive layer having a frame-shaped plain portion, and the outermost surface, when viewed from the lamination direction, overlaps with the region inside the plain portion, and the region on which electronic components are mounted is a mounting region, wherein the plurality of conductive layers are provided with resin receiving portions into which the resin of the insulating layer enters, and the inner peripheral portion including the inner edge of the plain portion has a larger proportion of the resin receiving portion than the outer peripheral portion outside the inner peripheral portion.

[0006] A method for manufacturing a wiring board according to one aspect of the present disclosure includes alternately stacking a plurality of conductive layers, each having a first conductive layer with a frame-shaped plane portion, and a plurality of insulating layers, and forming a mounting area for mounting electronic components in the outermost surface, in a region that overlaps with the region inside the plane portion when viewed from the stacking direction, wherein the plurality of conductive layers have resin receiving portions into which the resin of the insulating layer enters, and the proportion of the resin receiving portion is made larger in the inner peripheral portion, including the inner edge of the plane portion, compared to the outer peripheral portion outside the inner peripheral portion. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is a cross-sectional view of a wiring board. [Figure 2] Figure 2 is a plan view of the first conductive layer. [Figure 3] Figures 3A and 3B are cross-sectional views showing the manufacturing process of a wiring board. [Figure 4] Figures 4A and 4B are cross-sectional views showing the manufacturing process of a wiring board. [Figure 5] Figures 5A and 5B are cross-sectional views showing the manufacturing process of a wiring board. [Figure 6] Figure 6 is an enlarged cross-sectional view showing the manufacturing process of a wiring board. [Figure 7] Figure 7 is an enlarged cross-sectional view showing the manufacturing process of a wiring board. [Figure 8] Figures 8A and 8B are cross-sectional views showing the manufacturing process of a wiring board. [Figure 9] Figure 9 is an enlarged cross-sectional view showing the manufacturing process of a wiring board. [Modes for carrying out the invention]

[0008] An embodiment of the present disclosure will be described with reference to Figures 1 to 9. As shown in Figure 1, the wiring board 10 of this embodiment comprises a core board 11 and build-up layers 20 laminated on both the front and back surfaces of the core board 11.

[0009] The core substrate 11 comprises an insulating layer 12, a conductive layer 13 laminated on both the front and back surfaces of the insulating layer 12, and a plurality of through-hole conductors 14.

[0010] The build-up layer 20 comprises a plurality of alternatingly stacked insulating layers 21 and a plurality of conductive layers 30, and a plurality of via conductors 31. The outermost conductive layer 30 of the build-up layer 20 contains a plurality of pads 32. A solder resist layer 40 having a plurality of openings 40H that expose the plurality of pads 32 is stacked on the outermost surface of the build-up layer 20.

[0011] A mounting area R90 for mounting electronic components 90 is formed on the upper surface of the wiring board 10. The mounting area R90 is located inward from the outer edge of the surface of the wiring board 10 and comprises a plurality of solder bumps 41 arranged in a grid pattern. Multiple upper surfaces 42 are formed on the plurality of solder bumps 41, which are included in a common, hypothetical press surface.

[0012] Here, the area directly below the mounting area R90 of the wiring board 10 is called the direct-below area R1, and the area surrounding the direct-below area R1 is called the outer area R2. As shown in Figure 2, in the direct-below area R1 of the upper build-up layer 20, multiple signal lines (not shown) and multiple lands 33 connected to multiple pads 32 on the upper side of the wiring board 10 are formed, and in the outer area R2, a plane area 34 covering a wide area is often formed. For this reason, in the upper build-up layer 20, the residual copper ratio tends to be higher in the outer area R2 than in the direct-below area R1. Note that in Figure 2, conductors are shown in gray, and areas without conductors are shown in white.

[0013] In this embodiment, the plain portion 34 of the first conductive layer 30A is divided into an inner circumferential portion R21 including the inner edge and an outer circumferential portion R22 outside the inner circumferential portion R21, and a plurality of through holes 35 are formed in the inner circumferential portion R21 and the outer circumferential portion R22. The proportion of the plurality of through holes 35 that occupy the inner circumferential portion R21 and the outer circumferential portion R22 is different.

[0014] Specifically, the inner circumference R21 has a constant width, for example, 5 to 15 mm (preferably 10 mm). The multiple through holes 35 are, for example, all approximately the same diameter, arranged in a grid pattern, and penetrate the plain portion 34. The multiple through holes 35 function as degassing holes and also as resin receiving portions that receive the resin of the first insulating layer 21A (see Figures 1 and 9) laminated on the first conductive layer 30A. The multiple through holes 35 in the inner circumference R21 are arranged more densely than the multiple through holes 35 in the outer circumference R22 so that the proportion of resin receiving portions in the inner circumference R21 is higher than the proportion of resin receiving portions in the outer circumference R22. Furthermore, the proportion of resin receiving portions in the inner circumference R21 is slightly larger than or approximately equal to the proportion of resin receiving portions in the region R1 directly below it.

[0015] As shown in Figure 9, with this configuration, the first insulating layer 21A laminated on the first conductive layer 30A has a thickness T21 in its inner circumference R21 that is thinner than the thickness T22 in its outer circumference R22, and is approximately the same thickness as or slightly thicker than the thickness T1 in the region directly beneath R1. When the conductive layer 30 and the solder resist layer 40 are laminated on such a first insulating layer 21A, the surface of the wiring board 10 slopes gently inward from the outer edge of the peripheral region R91 that is directly above the inner circumference R21 and surrounding the mounting region R90, and the height difference from the inside of the peripheral region R91 to the mounting region R90 is small.

[0016] The thickness T1 of the region directly beneath R1, the thickness T21 of the inner circumference R21, and the thickness T22 of the outer circumference R22 in the first insulating layer 21A correspond, for example, to the average thickness of the region directly beneath R1, the inner circumference R21, or the outer circumference R22.

[0017] The wiring board 10 of the present disclosure is manufactured as follows. (1) A copper-clad laminate in which metal foils are laminated on both sides of an insulating layer is prepared. Then, from the copper-clad laminate, by a known method, as shown in FIG. 3A, a core substrate 11 is obtained in which conductive layers 13 laminated on both the front and back surfaces of the insulating layer 12 are connected to each other by a plurality of through-hole conductors 14.

[0018] (2) Next, for example, by a semi-additive method, a plurality of insulating layers 21 and a plurality of conductive layers 30 are alternately laminated on both surfaces of the core substrate 11, and a plurality of via conductors 31 that connect between adjacent conductive layers 30 in the lamination direction are formed. Then, as shown in FIG. 3B, it is formed up to the insulating layer 21 below the first conductive layer 30A having a plurality of via holes 31H. Note that in FIG. 3B, only the upper side of the wiring board 10 from the core substrate 11 is shown.

[0019] (3) Next, electroless plating treatment is performed to form an electroless plating film (not shown) on the insulating layer 21 and the inner surfaces of the plurality of via holes 31H, and a plating resist 80 having a predetermined pattern is formed on the electroless plating film (see FIG. 4A).

[0020] Here, the plating resist 80 having a predetermined pattern includes a plurality of pillars 81. The plurality of pillars 81 are provided at positions where a plurality of through-holes 35 of the plane portion 34 in the first conductive layer 30A are formed, and the plurality of pillars 81 included in the inner peripheral portion R21 are arranged more densely than the plurality of pillars 81 included in the outer peripheral portion R22.

[0021] (4) As shown in FIG. 4B, electrolytic plating treatment is performed to fill electrolytic plating in the plurality of via holes 31H to form a plurality of via conductors 31, and an electrolytic plating film 30D is formed on a portion of the electroless plating film (not shown) that is exposed from the plating resist 80.

[0022] (5) After the plating resist 80 is peeled off, the electroless plating film on the underside of the plating resist 80 is removed. As a result, a first conductive layer 30A is formed, which includes a plain portion 34 having a plurality of through holes 35, as shown in Figure 5A.

[0023] (6) As shown in Figure 5B, an insulating film for the build-up substrate is laminated on the first conductive layer 30A as the first insulating layer 21A and then heat-pressed. At this time, the molten resin of the insulating film enters the resin receiving portions of the first conductive layer 30A, which include multiple through holes 35. As a result, as shown in Figure 6, the thickness T21 of the inner peripheral portion R21 of the first insulating layer 21A becomes thinner than the thickness T22 of the outer peripheral portion R22, and is approximately equal to or slightly thicker than the thickness T1 of the region directly beneath R1.

[0024] (7) Similar to steps (3) to (5) above, a conductive layer 30 containing a plurality of pads 32 is laminated on the first insulating layer 21A, and then a solder resist layer 40 having a plurality of openings 40H is laminated. As a result, as shown in Figure 7, the surface of the solder resist layer 40 slopes gently inward from the peripheral region R91 and is concave, and the height difference between the inside of the peripheral region R91 and the mounting region R90 is made small, so that the surface of a region slightly larger than the mounting region R90 becomes substantially flat.

[0025] (8) Next, as shown in Figure 8A, multiple solder bumps 41 are formed on the multiple pads 32.

[0026] (9) As shown in Figure 8B, multiple solder bumps 41 are pressed by a pressure plate P having a flat press surface P1, and multiple upper surfaces 42 are formed on top of the multiple solder bumps 41. At this time, as shown in Figure 9, the slope of the peripheral region R91 is gentle, and the surface of a region slightly larger than the mounting region R90 is substantially flat, so the outer edge of the pressure plate P does not interfere with the surface of the wiring board 10, and the multiple solder bumps 41 are pressed by the pressure plate P (see Figure 1). With this, the wiring board 10 is completed.

[0027] Next, the effects of the wiring board 10 will be explained. In the wiring board 10 of this embodiment, the inner circumference R21 of the plain portion 34 of the first conductive layer 30A, which is formed to surround the mounting area R90, has a larger proportion of resin receiving portion compared to the outer circumference R22. As a result, on the inner circumference R21 of the first insulating layer 21A that overlaps the plain portion 34 of the first conductive layer 30A, a large amount of resin flows into the resin receiving portion, and the thickness T21 of the first insulating layer 21A becomes thinner. Then, on the surface of the wiring board 10 formed based on this first insulating layer 21A, the height difference between the mounting area R90 and the surrounding area R91 is suppressed. As a result, the area around the mounting area R90 can be made flatter than before, and the connection reliability with the surface-mounted electronic components 90 can be improved.

[0028] Furthermore, in this embodiment, the ratio of the resin receiving portion between the inner circumference R21 of the plain portion 34 and the directly beneath region R1 is approximately equal, so the difference between the thickness T21 of the first insulating layer 21A that overlaps the inner circumference R21 and the thickness T1 that overlaps the directly beneath region R1 is suppressed. This reduces the height difference between the mounting region R90 and its surrounding region R91 on the surface of the wiring board 10. Also, in this embodiment, the width of the inner circumference R21 directly beneath the surrounding region R91 is 5 to 15 mm (preferably 10 mm), and the pressure plate P fits within the region consisting of the mounting region R90 and the surrounding region R91. As a result, the outer edge of the pressure plate P that presses the multiple solder bumps 41 of the mounting region R90 is less likely to interfere with the surface of the wiring board 10. Furthermore, since the surface depressions of the wiring board 10 are suppressed, the multiple solder bumps 41 are pressed by the pressure plate P to form multiple upper surfaces 42. This suppresses variations in the area of ​​the upper surfaces 42 of the multiple solder bumps 41, improving the reliability of the connection between the surface-mounted electronic components 90 and the multiple solder bumps 41.

[0029] Furthermore, in this embodiment, the resin receiving portion formed in the plain portion 34 can be realized with a simple configuration of multiple through holes 35. Moreover, these multiple through holes 35 can function not only to adjust the proportion of the resin receiving portion, but also as degassing holes. In other words, the proportion of the resin receiving portion can be easily changed by changing the density of the degassing holes.

[0030] [Other embodiments] In Figure 1, the first conductive layer 30A is located second from the outside among the upper build-up layers 20 of the wiring board 10, but it is not limited to this position, and the first conductive layer 30A may be placed in any position. Furthermore, the first conductive layer 30A having a plane portion 34 is not limited to one layer, but may consist of multiple layers, and all conductive layers 30 included in the upper build-up layers 20 may be the first conductive layer 30A including the plane portion 34. Moreover, the first conductive layer 30A may be included in the lower build-up layers 20 of the wiring board 10.

[0031] The mounting area R90 is not limited to being located in the center of the surface of the wiring board 10, but may be located inside the outer edge. Also, the plane portion 34 of the first conductive layer 30A may be frame-shaped, and its width does not have to be constant. Similarly, the inner circumference R21 of the plane portion 34 does not have to be constant in width; for example, a part of it may be wider or narrower than the rest. Furthermore, wiring such as signal lines may be formed on the outside of the plane portion 34.

[0032] In Figure 2, the width of the inner circumference R21 is narrower than the width of the outer circumference R22, but this is not limited to this. For example, the inner circumference R21 and the outer circumference R22 may be approximately the same width, or the inner circumference R21 may be wider than the outer circumference R22.

[0033] In the above embodiment, the multiple through holes 35 in the inner circumference R21 and the multiple through holes 35 in the outer circumference R22 were of the same diameter, but the spacing between the through holes 35 was different. However, the embodiment is not limited to this, and for example, the spacing between the through holes 35 may be the same, but the diameters of the multiple through holes 35 in the inner circumference R21 and the multiple through holes 35 in the outer circumference R22 may be different.

[0034] While this specification and drawings disclose specific examples of the technology included in the claims, the technology described in the claims is not limited to these specific examples, but also includes various modifications and changes to these examples, as well as parts of the examples taken individually. [Explanation of Symbols]

[0035] 10 Wiring board 11 Core board 20 Build-up Layers 21 Insulating layer 21A First insulating layer 30 Conductive layer 30A First conductive layer 34 Plain section 35 Through hole (resin receiving part) 41 Handa Bump 42 Upper plane 90 Electronic Components P Pressure Plate R1 Direct Sub-region R2 outer area R21 Inner circumference R22 outer periphery R90 Implementation Area R91 surrounding area

Claims

1. Multiple conductive layers and multiple insulating layers are alternately laminated, each containing a first conductive layer having a frame-shaped plain portion. In a wiring board where the outermost surface, when viewed from the stacking direction, overlaps with the area inside the aforementioned plane portion, the area on which electronic components are mounted is the mounting area, Each of the aforementioned conductive layers is provided with a resin receiving portion into which the resin of the insulating layer enters. The inner circumference, including the inner edge of the plain portion, has a larger proportion of the resin receiving portion compared to the outer circumference outside the inner circumference.

2. In the wiring board according to claim 1, The resin receiving portion formed in the plain portion is a plurality of through holes that penetrate the plain portion.

3. In the wiring board according to claim 2, The aforementioned multiple through holes are degassing holes.

4. In the wiring board according to claim 1, In the first conductive layer, the region inside the plain portion and the inner circumference of the plain portion have approximately the same proportion of resin receiving portion.

5. In the wiring board according to claim 1, The width of the inner circumference is 5 to 15 mm.

6. In the wiring board according to any one of claims 1 to 5, core substrate and The core substrate comprises a build-up layer formed on both sides, having the plurality of conductive layers and the plurality of insulating layers, All of the plurality of conductive layers in the build-up layer on the side on which the electronic component is mounted are the first conductive layer.

7. In the wiring board according to any one of claims 1 to 5, Multiple solder bumps arranged in a grid pattern in the aforementioned mounting area, Each of the aforementioned plurality of solder bumps comprises a plurality of upper surfaces formed on each of the plurality of solder bumps and included in a common, imaginary press surface.

8. Multiple conductive layers, including a first conductive layer having a frame-shaped plain portion, and multiple insulating layers are alternately laminated. A method for manufacturing a wiring board, comprising the following steps: a mounting area for mounting electronic components is formed on the outermost surface in a region that overlaps with the region inside the plane portion when viewed from the stacking direction; The plurality of conductive layers have resin receiving portions into which the resin of the insulating layer enters. This includes making the proportion of the resin receiving portion larger in the inner circumferential portion, including the inner edge of the plain portion, compared to the outer circumferential portion outside the inner circumferential portion.

9. In the method for manufacturing a wiring board according to claim 8, The resin receiving portion is a plurality of through holes that penetrate the plain portion.

10. In the method for manufacturing a wiring board according to claim 9, The aforementioned multiple through holes are degassing holes.

11. In the method for manufacturing a wiring board according to claim 8, In the first conductive layer, the region inside the plain portion and the inner circumference of the plain portion have approximately the same proportion of resin receiving portion.

12. In the method for manufacturing a wiring board according to claim 8, The width of the inner circumference is 5 to 15 mm.

13. In the method for manufacturing a wiring board according to any one of claims 8 to 12, The core board will be prepared, The core substrate is laminated with a build-up layer having the plurality of conductive layers and the plurality of insulating layers on both the front and back surfaces, All of the plurality of conductive layers in the build-up layer on the side on which the electronic component is mounted are the first conductive layer.

14. In the method for manufacturing a wiring board according to any one of claims 8 to 12, Multiple solder bumps are formed in a grid pattern on the aforementioned mounting area, The above-mentioned plurality of solder bumps are pressed and flattened by a pressure plate, and this is included.

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