Analog-to-digital conversion device and offset correction method

Abstract

To provide an analog-to-digital converting device and a method of off-set calibration.SOLUTION: An analog-to-digital converting device includes: N-stage first analog-to-digital converters (ADCs) having a first sampling frequency and configured to convert, by a time-inter leaves manner, an input signal into multi-stage first quantized outputs; a second ADC having a second sampling frequency, and configured to convert the input signal into a second quantized output, wherein, the first sampling frequency is (N+1) / N times of the second sampling frequency; a calibration circuit configured to calibrate the multi-stage first quantized outputs and the second quantized output, so as to respectively generate multi-stage third quantized outputs and a fourth quantized output; a data recover circuit configured to output, by the second sampling frequency, one of the multi-stage third quantized outputs as a fifth quantized output, subtract the fifth quantized output from the fourth quantized output to generate a plurality of output data; and an output circuit configured to generate an output signal on the basis of the multi-stage third quantized output and the plurality of output data.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to analog-to-digital conversion technology, and more particularly to an analog-to-digital conversion device and an offset correction method that prevent loss of sampling results. [Background technology]

[0002] Analog to digital converters (ADCs) are widely used in communication systems, electronic devices, and various computer systems. Due to process variations, the output signal of the ADC may contain an offset error corresponding to a non-zero voltage, for example, when a 0V signal is input to the ADC. Depending on the ADC, the degree of offset may vary depending on the usage conditions and random changes in components, making it difficult to uniformly correct the offset at the time of factory shipment. Therefore, the ADC usually has an automatic offset correction function. However, the automatic offset correction function of the ADC may erroneously erase the sampling result of the ADC when the input signal of the ADC has a certain frequency. Summary of the Invention [Problem to be solved by the invention]

[0003] In view of this, how to prevent the offset automatic correction function of an analog-to-digital converter (ADC) from erroneously erasing the sampling results of the ADC has become a problem to be solved in the industry. [Means for solving the problem]

[0004] The present disclosure provides an analog-to-digital conversion device, including: a first ADC with N stages (N is a positive integer equal to or greater than 2) having a first sampling frequency for converting an input signal into a multi-stage first quantized output in a time interleaved manner; a second ADC having a second sampling frequency, the first sampling frequency being (N+1) / N times the second sampling frequency, for converting the input signal into a second quantized output; a first correction circuit for correcting offsets of the multi-stage first quantized output and the second quantized output to generate a multi-stage third quantized output and a fourth quantized output, respectively; a data recovery circuit coupled to the first correction circuit, for outputting one of the multi-stage third quantized outputs as a fifth quantized output at the second sampling frequency and subtracting the fifth quantized output from the fourth quantized output to generate a plurality of output data; and an output circuit for generating an output signal based on the multi-stage third quantized output and the plurality of output data.

[0005] The present disclosure relates to an offset correction method applied to an analog-to-digital conversion device including a first ADC and a second ADC of N stages, the method comprising the steps of: converting an input signal into a multi-stage first quantized output based on a first sampling frequency using the first ADC of N stages (N is a positive integer equal to or greater than 2) in a time interleaved manner; and converting the input signal into a second quantized output based on a second sampling frequency using the second ADC, the first sampling frequency being (N+1) times the second sampling frequency. / N times; correcting offsets of the multi-stage first quantized output and the second quantized output to generate a multi-stage third quantized output and a fourth quantized output, respectively; outputting one of the multi-stage third quantized outputs as a fifth quantized output at a second sampling frequency; subtracting the fifth quantized output from the fourth quantized output to generate a plurality of output data; and generating an output signal based on the multi-stage third quantized output and the plurality of output data. Effect of the Invention

[0006] The above analog-to-digital conversion apparatus and offset correction method can generate an accurate output signal without losing any sampling results when the frequency of the input signal is equal to an integer multiple of the sampling frequency of the first ADC. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a simplified functional block diagram of an analog-to-digital conversion device according to an embodiment of the present disclosure. [Diagram 2] 2A to 2C are waveform diagrams of a number of clock signals in FIG. 1 according to some embodiments. [Diagram 3] FIG. 2 is a schematic diagram of signal components of an input signal according to one embodiment of the present disclosure. [Figure 4] FIG. 4 is an operational schematic diagram of a selection circuit according to an embodiment of the present disclosure. [Diagram 5] FIG. 2 is a simplified functional block diagram of a processing circuit according to one embodiment of the present disclosure. [Figure 6] FIG. 2 is a simplified functional block diagram of a first sub-correction circuit according to an embodiment of the present disclosure. [Figure 7] 4 is a flowchart of an offset correction method according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The embodiments of the present disclosure will now be described in conjunction with the associated drawings, in which like element references indicate the same or similar parts or method flows.

[0009] FIG. 1 is a simplified functional block diagram of an analog-to-digital conversion device 100 according to an embodiment of the present disclosure. FIG. 2 is a waveform diagram of several embodiments of a plurality of clock signals in FIG. 1. Referring to FIG. 1 and FIG. 2 at the same time, the analog-to-digital conversion device 100 includes a multi-stage first analog-to-digital conversion device 100 (ADC) 1100-1103, a second ADC 120, a first correction circuit 130, a data recovery circuit 140, and an output circuit 150. The first ADCs 1100-1103 are used to sample an input signal SIN according to a plurality of first clock signals CLKA0-CLKA3, respectively, and generate a multi-stage first quantized output QA0-QA3, respectively. In some embodiments, the analog-to-digital conversion device 100 may further include a time-skew correction circuit and / or a gain correction circuit. For convenience of explanation, these circuits are not illustrated in FIG. 1.

[0010] As shown in FIG. 2, the first clock signals CLKA0-CLKA3 are time-interleaved signals. There is a time interval between adjacent ones of the first clock signals CLKA0-CLKA3, so that the first ADCs 1100-1103 perform sampling and analog-to-digital conversion of the input signal SIN at different times. For example, based on the first clock signal CLKA0, the first ADC 1100 can sample at a sampling time TM1. Based on the first clock signal CLKA1, the first ADC 1101 can sample at a sampling time TM2. The first ADCs 1100-1103 are used to alternately sample the input signal SIN, so that the analog-to-digital conversion device 100 operates as a time-interleaved analog-to-digital converter in one embodiment. In one embodiment, the difference between sampling time TM1 and sampling time TM2 is one system sampling period TS of analog-to-digital conversion device 100, and the reciprocal of the system sampling period TS is the system sampling frequency fs of analog-to-digital conversion device 100, i.e., TS=1 / fs.

[0011] The first ADC 120 is used to sample the input signal SIN according to the second clock signal CLKB to generate a second quantized output QB. The frequencies of the first clock signals CLKA0-CLKA3 are higher than the frequency of the second clock signal CLKB, so that the first sampling frequency of the first ADCs 1100-1103 is higher than the second sampling frequency of the second ADC 120. The second ADC 120 contributes to improving the accuracy of the sampling results of the first ADCs 1100-1103, and the details will be further described below.

[0012] In the following examples, for convenience of explanation, the first sampling frequency (or the frequency of the first clock signals CLKA0 to CLKA3) is assumed to be 500 MHz, and the second sampling frequency (or the frequency of the second clock signal CLKB) is assumed to be 400 MHz. However, the number of the first ADCs 1100 to 1103, the first sampling frequency (or the frequency of the first clock signals CLKA0 to CLKA3), and the second sampling frequency (or the frequency of the second clock signal CLKB) of the present disclosure are not limited to the above and following exemplary embodiments. In some embodiments, when the analog-to-digital conversion device 100 includes N stages of first ADCs, the first sampling frequency (or the frequency of the first clock signals CLKA0 to CLKA3) is (N+1) / N times the second sampling frequency (or the frequency of the second clock signal CLKB), where N is a positive integer equal to or greater than 2. In other words, the first sampling frequency is fs / N and the second sampling frequency is fs / (N+1).

[0013] The first correction circuit 130 is coupled to the first ADCs 1100-1103, the second ADC 120, the data recovery circuit 140 and the output circuit 150. The first correction circuit 130 is used to correct the offset of the first quantized outputs QA0-QA3 to generate multi-stage third quantized outputs QC0-QC3, and is also used to correct the offset of the second quantized output QB to generate a fourth quantized output QD. The third quantized outputs QC0-QC3 are transmitted to the data recovery circuit 140 and the output circuit 150. The fourth quantized output QD is transmitted to the data recovery circuit 140.

[0014] In detail, the first correction circuit 130 includes a plurality of first sub-correction circuits 1320-1323 coupled to the first ADCs 1100-1103, respectively, and a second sub-correction circuit 134 coupled to the second ADC 120. The first sub-correction circuits 1320-1323 operate in the same manner, and for convenience of explanation, only the first sub-correction circuit 1320 will be described below as an example. The first sub-correction circuit 1320 is used to average the first quantized output QA0 to obtain an offset correction amount of the first quantized output QA0. Next, the first sub-correction circuit 1320 subtracts the offset correction amount from the first quantized output QA0 to generate a third quantized output QC0. In addition, the second sub-correction circuit 134 is used to average the second quantized output QB to obtain an offset correction amount of the second quantized output QB. Next, the second sub-correction circuit 134 subtracts the offset correction amount from the second quantized output QB to generate a fourth quantized output QD.

[0015] In some cases, the first correction circuit 130 may erroneously correct the first quantized outputs QA0-QA3. Referring to FIG. 3, FIG. 3 is a schematic diagram of signal components of an input signal SIN according to an embodiment of the present disclosure. The input signal SIN includes a target signal 310 having a frequency of 500 MHz, and the analog-to-digital conversion device 100 is ideally used to generate a digital output signal SOUT based on the target signal 310. In FIG. 3, the interval between adjacent sampling times TP1-TP21 is one system sampling period TS.

[0016] When the frequency of the target signal 310 is the same as the first sampling frequency of the first ADCs 1100-1103 (for example, all are 500 MHz) or the frequency of the target signal 310 is a positive integer multiple of the first sampling frequency (for example, when the first ADC has N stages, the frequency of the target signal 310 is fs×i / N, where i is a positive integer), the first ADCs 1100-1103 continuously sample the same value for the target signal 310. In this case, since the first correction circuit 130 obtains the offset correction amount by averaging, each offset correction amount is not equal to the true offset amount but is equal to the corresponding first quantization output, and as a result, the first correction circuit 130 erroneously corrects the first quantization outputs QA0-QA3.

[0017] 3, when the first ADC 1100 samples the target signals 310, the target signals 310 are all about 0.1 V, so that the first quantized output QA0 maintains a state corresponding to 0.1 V. Based on this, the first correction circuit 130 calculates an offset correction amount for the first quantized output QA0 corresponding to 0.1 V, so that the third quantized output QC0 (i.e., the first quantized output QA0 after correction) corresponds to 0 V.

[0018] Also, for example, when the first ADC 1101 samples, the target signals 310 are all about 0.9 V, and as a result, the first quantized output QA1 maintains a state corresponding to 0.9 V. Based on this, the first correction circuit 130 calculates the offset correction amount of the first quantized output QA1 corresponding to 0.9 V so that the third quantized output QC1 (i.e., the first quantized output QA1 after correction) corresponds to 0 V.

[0019] The data recovery circuit 140 recovers the first quantized outputs QA0-QA3, which are erroneously corrected, using the fourth quantized output QD of the second ADC 120 (or as the first quantized outputs QA0-QA3), to generate output data DO0-DO3. The output circuit 150 is used to generate a digital output signal SOUT based on the third quantized outputs QC0-QC3 and the output data DO0-DO3. In one embodiment, the output circuit 150 is used to add the output data DO0-DO3 to the third quantized outputs QC0-QC3, respectively. For example, the combination of the third quantized output QC0 and the output data DO0 corresponds to the sampling result of the first ADC 1100, the combination of the third quantized output QC1 and the output data DO1 corresponds to the sampling result of the first ADC 1101, and so on. The output circuit 150 may continuously perform a data combination operation to generate an output signal SOUT having a system sampling frequency fs. In some embodiments, the output circuit 150 may be realized by a multiplexer circuit, although the present disclosure is not limited thereto.

[0020] Hereinafter, the principle of using the fourth quantized output QD to recover the first quantized outputs QA0 to QA3 will be described. By setting the first sampling frequency to (N+1) / N times the second sampling frequency of the second ADC 120, the second ADC 120 can sequentially sample at substantially the same time as the first ADCs 1100 to 1103, and the second ADC 120 can obtain the sampling results of the first ADCs 1100 to 1103. For example, as shown in FIG. 3, the first ADC 1100 and the second ADC 120 simultaneously sample the target signal 310 of 0.1V at the sampling time TP1, so that the fourth quantized output QD at the sampling time TP1 may be used to recover the first quantized output QA0 at the sampling time TP1 (or be the first quantized output QA0). Since the first ADC 1101 and the second ADC 120 simultaneously sample the 0.9V target signal 310 at sampling time TP6, the fourth quantized output QD at sampling time TP6 may be used to recover (or be) the first quantized output QA1 at sampling time TP6, and so on. In some embodiments where the first ADC has N stages, in two consecutive samples of the second ADC 120, the second ADC 120 first samples substantially simultaneously with the first ADC of the K-1th stage of the first ADCs of the N stages, and then samples substantially simultaneously with the first ADC of the Kth stage, where K is a positive integer less than or equal to N.

[0021] In some embodiments, the input signal SIN also includes other crosstalk signals (e.g., the crosstalk signal 320) having a different frequency from the target signal 310. In general, these crosstalk signals are AC signals, so the influence of the crosstalk signals on the fourth quantized output QD can be removed by connecting averaging filters in series, such as the first averaging filters 5300-5303 and the second averaging filters 5400-5403 in FIG. 5. For example, the fourth quantized output QD at the sampling time TP1 may be processed by an averaging filter and then used to recover the first quantized output QA0. Also, for example, the fourth quantized output QD at the sampling time TP6 may be processed by another averaging filter and then used to recover the first quantized output QA1. However, when the frequency of the crosstalk signal 320 is 100 MHz (i.e., when the first ADC has N stages and the frequency of the crosstalk signal 320 is fs×j / [N×(N+1)] (j is a positive integer)), the effect of the crosstalk signal 320 on the fourth quantized output QD is somewhat similar to the effect of a DC signal, so the component of the crosstalk signal 320 cannot be removed from the fourth quantized output QD by the averaging filter.

[0022] For example, as shown in Fig. 3, when the second ADC 120 samples at sampling time TP1 and sampling time TP21 to recover the first quantized output QA0, the crosstalk signals 320 are both about 0.3 V. Therefore, even if the two fourth quantized outputs QD are averaged, the components of the crosstalk signal 320 are not removed but still remain completely.

[0023] A data recovery circuit 140 can be used to solve the above problem. The data recovery circuit 140 includes a selection circuit 142 and a processing circuit 144. The data recovery circuit 140 is used to output a corresponding one of the third quantized outputs QQC0-QC3 as a fifth quantized output QE at a second sampling frequency (e.g., by the selection circuit 142). Thus, the fifth quantized output QE can be understood as a quantized output obtained by sampling the input signal SIN at the second sampling frequency, and includes a component related to the crosstalk signal 320 (e.g., 100 MHz) but does not include a component related to the target signal 310 (e.g., 500 MHz) because the component has already been removed by the first correction circuit 130. The data recovery circuit 140 is further used to subtract the fifth quantized output QE from the fourth quantized output QD to remove components related to the crosstalk signal 320 (e.g., 100 MHz) in the fourth quantized output QD and to leave components related to the target signal 310 (e.g., 500 MHz) to generate a plurality of output data DO0-DO3. In some embodiments, the output data DO0-DO3 correspond to sampling results of the target signal 310 (e.g., 500 MHz) by the four channels of the first ADCs 1100-1103, respectively.

[0024] Hereinafter, the operation of the selection circuit 142 and the processing circuit 144 will be further described in conjunction with FIG. 4 and FIG. 5. Referring to FIG. 4, FIG. 4 is an operation schematic diagram of the selection circuit 142 according to an embodiment of the present disclosure. As described above, the interval between adjacent sampling times TP1 to TP21 is one system sampling period TS. The selection circuit 142 is used to receive the third quantized outputs QC0 to QC3, and is used to output one of the third quantized outputs QC0 to QC3 as the fifth quantized output QE every four system sampling periods TS (i.e., every N system sampling periods TS when the first ADC has N stages). As shown in FIG. 4, the selection circuit 142 outputs the third quantized output QC0 at the sampling time TP1, the third quantized output QC1 at the sampling time TP6, the third quantized output QC2 at the sampling time TP11, and the third quantized output QC3 at the sampling time TP16.

[0025] In other words, the sampling time of the third quantized output currently output by the selection circuit 142 and the sampling time of the third quantized output previously output are different from each other by five system sampling periods. TS (i.e., if the first ADC has N stages, then N+1 system sampling periods TS are apart.) For example, as shown in FIG. 4, in the plurality of third quantized outputs forming the fifth quantized output QE, the third quantized output QC1 (sampling time TP6) and the previous third quantized output QC0 (sampling time TP1) are separated by five system sampling periods TS. TS It is just a few meters away.

[0026] In one embodiment, the selection circuit 142 may include a latch circuit or a random access memory to store the four third quantized outputs QC0-QC3 for every four system sampling periods TS, and may further include a multiplexer for outputting a corresponding one of the four third quantized outputs QC0-QC3.

[0027] 1, in some embodiments, the data recovery circuit 140 further includes a second correction circuit 146. The second correction circuit 146 is coupled to the selection circuit 142 and is used to correct the offset of the third quantized output output from the selection circuit 142 to generate a fifth quantized output QE. The correction principle of the second correction circuit 146 is similar to that of the first sub-correction circuits 1320-1323 or the second sub-correction circuit 134 described above, and will not be described again here for convenience.

[0028] In some embodiments, the input signal SIN includes a crosstalk signal having a second sampling frequency (e.g., a 400 MHz crosstalk signal not shown in FIG. 3). As can be seen from FIG. 4, the output of the selection circuit 142 can be understood as a quantized output of the input signal SIN sampled at the second sampling frequency, whereby the crosstalk signal of the second sampling frequency generates a fixed-value DC component at the output of the selection circuit 142. Therefore, the second correction circuit 146 may be used to remove the component of the crosstalk signal related to the second sampling frequency from the output of the selection circuit 142 by averaging. In some embodiments, if the input signal SIN does not include a crosstalk signal of the second sampling frequency, the second correction circuit 146 can be omitted.

[0029] Reference is now made to Figure 5, which is a simplified functional block diagram of processing circuitry 144 according to one embodiment of the present disclosure. Processing circuitry 144 includes a first demultiplexer 510, a second demultiplexer 520, a plurality of first averaging filters 5300-5303, a plurality of second averaging films 5300-5303, and a plurality of first arithmetic circuits 5500-5503.

[0030] The first demultiplexer 510 is used for receiving the fifth quantized output QE, and for sequentially allocating data at the fifth quantized output QE to a plurality of output terminals X0 to X3 of the first demultiplexer 510 according to sampling times. For example, the first demultiplexer 510 may use the output terminals X0 to X3 to respectively output the third quantized output QC0 at sampling time TP1, the third quantized output QC1 at sampling time TP6, the third quantized output QC2 at sampling time TP11, and the third quantized output QC3 at sampling time TP16 in Fig. 4, and the rest are analogized in this way.

[0031] The first averaging filters 5300-5303 are coupled to the output terminals X0-X3, respectively, and are used for averaging the output signals of the output terminals X0-X3 to generate a plurality of first data DA0-DA3. The first averaging filters 5300-5303 are used for removing information of crosstalk signals of other frequencies not mentioned before from the output signals of the output terminals X0-X3.

[0032] The second demultiplexer 520 is used for receiving the fourth quantized output QD, and sequentially assigns data at the fourth quantized output QD to a plurality of output terminals Y0 to Y3 of the second demultiplexer 520 according to sampling times. For example, referring to Fig. 3 and Fig. 5 at the same time, the second demultiplexer 520 may use the output terminals Y0 to Y3 to respectively output the fourth quantized output QD at sampling time TP1, the fourth quantized output QD at sampling time TP6, the fourth quantized output QD at sampling time TP11, and the fourth quantized output QD at sampling time TP16, and the rest are analogized in this way.

[0033] The second averaging filters 5400-5403 are respectively coupled to the output terminals Y0-Y3 and are used for averaging the output signals of the output terminals Y0-Y3 to generate a plurality of second data DB0-DB3. The second averaging filters 5400-5403 are used for removing information of crosstalk signals of other frequencies not mentioned before from the output signals of the output terminals Y0-Y3.

[0034] From the above, the multiple sampling times (for example, sampling times TP1, TP6, TP11, and TP16) corresponding to the first data DA0 to DA3 are substantially the same as the multiple sampling times corresponding to the second data DB0 to DB3, respectively. In some embodiments, the first averaging filters 5300 to 5303 and the second averaging filters 5400 to 5403 may be realized by moving average filters. In some embodiments, when the input signal SIN does not include the crosstalk signal of the other frequency described above, the first averaging filters 5300 to 5303 and the second averaging filters 5400 to 5403 may be omitted, and the output terminals X0 to X3 of the first demultiplexer 510 may directly output the first data DA0 to DA3, and the output terminals Y0 to Y3 of the second demultiplexer 520 may directly output the second data DB0 to DB3.

[0035] Generally speaking, the information included in the first data DA0 to DA3 corresponds to the crosstalk signal 320. The information included in the second data DB0 to DB3 corresponds to the target signal 310 and the crosstalk signal 320. The frequency of the target signal 310 is 500 MHz (or fs×i / N), and the frequency of the crosstalk signal 320 is 100 MHz (or fs×j / [N×(N+1)]).

[0036] The first arithmetic circuits 5500-5503 are used to subtract the first data DA0-DA3 from the second data DB0-DB3, respectively, to generate the output data DO0-DO3. Therefore, the information in the output data DO0-DO3 corresponds to the target signal 310 only.

[0037] FIG. 6 is a simplified functional block diagram of the first sub-correction circuit 1320 according to an embodiment of the present disclosure. The first sub-correction circuit 1320 includes a third averaging filter 610 and a second arithmetic circuit 620. The third averaging filter 610 is used to average the first quantized output QA0. The second arithmetic circuit 620 is used to subtract the output of the third averaging filter 610 (i.e., the first quantized output QA0 after averaging, or the offset correction amount of the first quantized output QA0) from the first quantized output QA0 to generate a third quantized output QC0. In this embodiment, the components, connections, and operations of the other first sub-correction circuits 1321-1323 and the second sub-correction circuit 134 are all applicable to the description of the first sub-correction circuit 1320 in FIG. 6 above, and will not be described again here for convenience of description.

[0038] As described above, the analog-to-digital conversion device 100 can ensure that an accurate output signal SOUT is generated without losing the sampling result when the frequency of the input signal SIN is equal to an integer multiple of the first sampling frequency of the first ADCs 1100-1103 during offset correction. It should be noted that the analog-to-digital conversion device 100 can also be applied when the frequency of the target signal 310 is not an integer multiple of the first sampling frequency. In this case, the first correction circuit 130 does not erroneously correct the first quantized outputs QA0-QA3, so that the fourth quantized output QD and the fifth quantized output QE are substantially random numbers, whose values ​​are removed by the first averaging filters 5300-5303 and the second averaging filters 5400-5403 in FIG. 5. Therefore, the first data DA0-DA3 and the second data DB0-DB3 in Figure 5 can all correspond to 0V, which causes the output data DO0-DO3 to correspond to 0V without affecting the output signal SOUT, and this is equivalent to the output circuit 150 generating an accurate output signal SOUT using only the third quantized outputs QC0-QC3.

[0039] 7 is a flowchart of an offset correction method 700 according to one embodiment of the present disclosure. The analog-to-digital conversion apparatus 100 in the above-described embodiments may be used to perform the offset correction method 700. It should be understood that any of the methods described herein may include more or fewer steps than those shown in the flowchart, and that the steps in the methods may be performed in any suitable order.

[0040] In step S710, the first ADCs 1100 to 1103 convert the input signal SIN into first quantized outputs QA0 to QA3 in a time interleaved manner based on the first sampling frequency.

[0041] In step S720, the second ADC converts the input signal SIN into a second quantized output QB based on the second sampling frequency, where the first sampling frequency is (N+1) / N times the second sampling frequency.

[0042] In step S730, the first correction circuit 130 corrects the offsets of the first quantized outputs QA0 to QA3 to generate third quantized outputs QC0 to QC3, and corrects the offset of the second quantized output QB to generate a fourth quantized output QD.

[0043] In step S740, the data recovery circuit 140 outputs one of the third quantized outputs QC0 to QC3 as a fifth quantized output QE at the second sampling frequency.

[0044] In step S750, the data recovery circuit 140 subtracts the fifth quantized output QE from the fourth quantized output QD to generate output data DO0 to DO3.

[0045] In step S760, the output circuit 150 generates an output signal SOUT based on the third quantized outputs QC0 to QC3 and the output data DO0 to DO3.

[0046] Specific terms are used in the specification and claims to refer to specific components. However, those skilled in the art should understand that the same components may be referred to by different nouns. The specification and claims do not distinguish components based on differences in names, but on functional differences between components. The term "including" in the specification and claims is an open term and should be interpreted as "including, but not limited to." Note that "coupled" includes both direct and indirect connection means. Thus, when the specification states that a first component is coupled to a second component, it means that the first component may be directly connected to the second component by a signal connection method such as electrical connection, wireless transmission, or optical transmission, or may be indirectly connected to the second component by other components or connection means.

[0047] As used herein, the term "and / or" includes any combination of one or more of the listed items, and any singular term also includes the plural references, unless otherwise stated in the specification.

[0048] The above is merely a preferred embodiment of the present disclosure, and various modifications and equivalent changes can be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the above, any modifications and equivalent changes made to the present disclosure within the scope of the following claims are intended to be covered by the present disclosure. [Explanation of symbols]

[0049] 100 Analog-to-Digital Conversion Device 1100 to 1103 first analog-to-digital converter 120 Second Analog-to-Digital Converter 130 First correction circuit 1320 to 1323 First sub-correction circuit 134 Second Sub-Compensation Circuit 140 Data Recovery Circuit 142 Selection circuit 144 Processing Circuit 146 Second compensation circuit 150 Output circuit CLKA0~CLKA3 First clock signal CLKB Second clock signal DO0~DO3 output data QA0~QA3 First quantization output QB Second quantization output QC0~QC3 Third quantization output QD Fourth quantized output QE 5th quantization output SIN input signal SOUT Output signal TS System Sampling Period fs system sampling frequency TM1, TM2, TP1~TP21 Sampling time 310 Target Signal 320 Crosstalk Signal 510 First Demultiplexer 520 Second Demultiplexer 5300~5303 First averaging filter 5400~5403 Second averaging filter 5500 to 5503 First arithmetic circuit DA0~DA3 First data DB0~DB3 Second data X0~X3,Y0~Y3 Output end 610 Third Averaging Filter 620 Second arithmetic circuit 700 Offset correction method S710~S760 Step

Claims

1. a first analog-to-digital converter (ADC) of N stages having a first sampling frequency for converting an input signal to a multi-stage first quantized output in a time interleaved manner; a second ADC having a second sampling frequency for converting the input signal to a second quantized output; a first correction circuit for correcting offsets of the multi-stage first quantized output and the multi-stage second quantized output to generate a multi-stage third quantized output and a multi-stage fourth quantized output, respectively; a data recovery circuit coupled to the first correction circuit, for outputting one quantized output of the multi-stage third quantized outputs at the second sampling frequency as a fifth quantized output, and for subtracting the fifth quantized output from the fourth quantized output to generate a plurality of output data; an output circuit that generates an output signal based on the multi-stage third quantization output and the plurality of output data; Including, N of the N stages is a positive integer equal to or greater than 2, and the first sampling frequency is (N+1) / N times the second sampling frequency. Analog-to-digital conversion device.

2. 2. The analog-to-digital conversion device according to claim 1, wherein in two consecutive samplings of the second ADC, the second ADC samples simultaneously with a first ADC of a K-1th stage among the first ADCs of the N stages, and then samples simultaneously with a first ADC of a Kth stage among the first ADCs of the N stages, where K is a positive integer less than or equal to N.

3. the analog-to-digital conversion apparatus operates as a time-interleaved analog-to-digital converter and has a system sampling period, and the data recovery circuit comprises: a selection circuit for receiving the multi-stage third quantized outputs and for outputting one of the multi-stage third quantized outputs as the fifth quantized output for every N system sampling periods; 2. The analog-to-digital conversion device of claim 1, wherein the sampling times of two successive third quantized outputs output by said selection circuit are spaced apart by (N+1) system sampling periods.

4. The data recovery circuit comprises:

4. The analog-to-digital conversion device of claim 3, further comprising a second correction circuit coupled to the selection circuit for correcting an offset of one of the third quantized outputs of the multiple stages to generate the fifth quantized output.

5. The data recovery circuit comprises:

4. The analog-to-digital conversion device of claim 3, further comprising a second correction circuit coupled to the selection circuit for removing a component associated with a crosstalk signal having a frequency equal to the second sampling frequency from one quantized output of the third quantized outputs of the multiple stages.

6. The data recovery circuit comprises: a first demultiplexer for allocating the fifth quantized output to a plurality of first data; a second demultiplexer for allocating the fourth quantized output to a plurality of second data; a plurality of first arithmetic circuits for subtracting the plurality of first data from the plurality of second data, respectively, to generate the plurality of output data; 2. The analog-to-digital conversion apparatus of claim 1, comprising a processing circuit including:

7. 7. The analog-to-digital conversion device according to claim 6, wherein a plurality of sampling times corresponding to the plurality of first data are the same as a plurality of sampling times corresponding to the plurality of second data.

8. The processing circuitry includes: a plurality of first averaging filters for averaging the plurality of outputs of the first demultiplexer, respectively, to generate the plurality of first data; a plurality of second averaging filters for averaging the plurality of outputs of the second demultiplexer, respectively, to generate the plurality of second data; 7. The analog-to-digital conversion apparatus of claim 6, further comprising:

9. The first correction circuit includes: a plurality of first sub-correction circuits respectively coupled to the N stages of first ADCs; a second sub-correction circuit coupled to the second ADC; Equipped with Each of the plurality of first sub-correction circuits includes: a third averaging filter for averaging a corresponding one of the first quantized outputs of the multi-stage; and a second arithmetic circuit for subtracting an output of the third averaging filter from the corresponding one of the first quantized outputs of the multi-stage to generate a corresponding one of the third quantized outputs of the multi-stage; the second sub-correction circuit includes: a fourth averaging filter for averaging the second quantized output; and a third arithmetic circuit for subtracting an output of the fourth averaging filter from the second quantized output to generate the fourth quantized output.

2. An analog-to-digital conversion device according to claim 1.

10. 1. An offset correction method applied to an analog-to-digital conversion device including a first analog-to-digital converter (ADC) and a second ADC of N stages, comprising: converting an input signal into a multi-stage first quantized output based on a first sampling frequency using the N-stage first ADC in a time interleaved manner; converting the input signal to a second quantized output based on a second sampling frequency using the second ADC; correcting offsets of the multi-stage first quantized output and the second quantized output to generate a multi-stage third quantized output and a multi-stage fourth quantized output, respectively; outputting one quantized output of the multi-stage third quantized outputs as a fifth quantized output at the second sampling frequency; subtracting the fifth quantized output from the fourth quantized output to generate a plurality of output data; generating an output signal based on the multi-stage third quantization output and the plurality of output data; Including, 13. An offset correction method, wherein N of the N stages is a positive integer equal to or greater than 2, and the first sampling frequency is (N+1) / N times the second sampling frequency.

11. 11. The offset correction method according to claim 10, wherein in two consecutive samplings of the second ADC, the second ADC samples simultaneously with a first ADC of a K-1th stage among the first ADCs of the N stages and then samples simultaneously with a first ADC of a Kth stage among the first ADCs of the N stages, where K is a positive integer less than or equal to N.

12. the analog-to-digital conversion apparatus operates as a time-interleaved analog-to-digital converter and has a system sampling period; The step of outputting one quantized output of the multi-stage third quantized outputs as the fifth quantized output at the second sampling frequency includes: a selection circuit for outputting one of the multi-stage third quantized outputs as the fifth quantized output for every N system sampling periods; 11. The offset correction method according to claim 10, wherein the sampling times of two successive third quantized outputs output by the selection circuit are spaced apart by (N+1) of the system sampling periods.

13. outputting one quantized output of the multi-stage third quantized outputs as the fifth quantized output for every N system sampling periods; 13. The offset correction method of claim 12, further comprising correcting an offset of one of the multi-stage third quantized outputs to generate the fifth quantized output.

14. outputting one quantized output of the multi-stage third quantized outputs as the fifth quantized output for every N system sampling periods; 13. The offset correction method of claim 12, further comprising removing a component associated with a crosstalk signal having a frequency the same as the second sampling frequency from one of the third quantized outputs of the multiple stages.

15. The step of subtracting the fifth quantized output from the fourth quantized output to generate the plurality of output data includes: Allocating the fifth quantization output to a plurality of first data; Allocating the fourth quantization output to a plurality of second data; The offset correction method according to claim 10 , further comprising: subtracting the plurality of first data from the plurality of second data, respectively, to generate the plurality of output data.

16. 16. The offset correction method according to claim 15, wherein the plurality of sampling times corresponding to the plurality of first data are the same sampling times as the plurality of sampling times corresponding to the plurality of second data.

17. 16. The offset correction method according to claim 15, further comprising: averaging each of a plurality of signals formed by assigning the fifth quantization output to form the plurality of first data; and averaging each of a plurality of signals formed by assigning the fourth quantization output to form the plurality of second data.

18. The step of correcting offsets of the multi-stage first quantized output and the multi-stage second quantized output to generate a multi-stage third quantized output and a multi-stage fourth quantized output, respectively, includes: averaging each of the multi-stage first quantized outputs to generate an averaged multi-stage first quantized output; subtracting the averaged multi-stage first quantized outputs from the multi-stage first quantized outputs, respectively, to generate the multi-stage third quantized output; averaging the second quantized output to generate an averaged second quantized output; and subtracting the averaged second quantized output from the second quantized output to generate the fourth quantized output.

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