Analog-to-digital converter, conversion method and electronic product

Abstract

The invention provides an analog-to-digital converter, a conversion method and an electronic product. The analog-to-digital converter comprises a differential analog-to-digital conversion module and a compensation module, the differential analog-to-digital conversion module is used for eliminating sampling thermal noise based on a double-sampling mode and realizing analog-to-digital conversion of an input signal; the compensation module receives the compensation signal, the output end of the compensation module is connected to the input end of a pre-amplifier in the differential analog-to-digital conversion module, and the compensation module compensates the change of the input signal coupled to the input end of the pre-amplifier based on a differential mode; wherein the input signal and the compensation signal which are connected to the same input end of the pre-amplifier are differential signals. According to the analog-to-digital converter, the conversion method and the electronic product, the sampling thermal noise elimination technology is adopted, the signal bandwidth limited by the saturation problem of the amplifier is increased by adopting the first-order approximate compensation module based on the differentiating circuit, and the analog-to-digital converter has the advantages of being small in sampling capacitance, low in noise, large in signal bandwidth and the like.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to an analog-to-digital converter, a conversion method and an electronic product. Background Art

[0002] Analog to Digital converter (ADC) plays a vital role in integrated circuits (IC). It is the key bridge between the analog world and the digital world. Common types of ADCs include: Successive Approximation Register (SAR ADC), Σ-Δ ADC, and Pipeline ADC. ADCs are increasingly required to achieve high precision. However, since the sampling thermal noise (kT / C noise) must meet the requirements of the signal-to-noise ratio (SNR), the sampling capacitor needs to be large enough in high-precision design, which also causes it to occupy most of the area and power consumption. At the same time, in the system design stage, an overly large sampling capacitor will also increase the power consumption and design complexity of the input signal driving circuit and the reference voltage driving circuit, which is no less difficult than ADC design.

[0003] In order to overcome the limitation of sampling thermal noise on sampling capacitors, the solution that has attracted much attention at present is to reduce the impact of sampling thermal noise on ADC performance through double sampling. This solution can effectively eliminate noise under low-frequency input signals. However, in the case of high-frequency input signals, the rapidly changing input signal will cause the amplifier output to saturate, which will greatly reduce the sampling thermal noise elimination effect and seriously reduce the linearity of the system.

[0004] Therefore, how to achieve high-quality sampling thermal noise elimination in both low-frequency input signals and high-frequency input signals has become one of the problems that technicians in this field need to solve urgently.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present invention and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the present invention. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide an analog-to-digital converter, a conversion method and an electronic product, which are used to solve the problems of poor sampling thermal noise elimination effect and impact on system linearity in the case of high-frequency input signals in the prior art.

[0007] To achieve the above-mentioned object and other related objects, the present invention provides an analog-to-digital converter, the analog-to-digital converter comprising at least:

[0008] Differential analog-to-digital conversion module and compensation module;

[0009] The differential analog-to-digital conversion module eliminates sampling thermal noise based on a double sampling method and realizes analog-to-digital conversion of the input signal;

[0010] The compensation module receives a compensation signal, and an output end is connected to an input end of a preamplifier in the differential analog-to-digital conversion module, and compensates for a change in coupling of the input signal to the input end of the preamplifier based on a differential method;

[0011] The input signal and the compensation signal connected to the same input terminal of the pre-amplifier are differential signals.

[0012] Optionally, the compensation module includes a first compensation unit and a second compensation unit, and the first compensation unit and the second compensation unit both include a differential circuit, a first switch, a second switch and a compensation capacitor;

[0013] The input end of the differential circuit receives the corresponding compensation signal, and the output end is connected to the lower plate of the compensation capacitor via the first switch; the upper plate of the compensation capacitor is connected to the corresponding input end of the pre-amplifier;

[0014] One end of the second switch is connected to the common mode voltage, and the other end is connected to the lower plate of the compensation capacitor;

[0015] The sampling timing of the first switch is consistent with the sampling timing of the sampling capacitor in the differential analog-to-digital conversion module, and the on-off state of the second switch is opposite to that of the first switch.

[0016] More optionally, the analog-to-digital converter satisfies:

[0017]

[0018] Among them, Δt is the time difference between the two samples, R d is the value of the resistor in the differential circuit, C d is the value of the capacitor in the differential circuit, C R is the value of the compensation capacitor, C S is the value of the sampling capacitor.

[0019] More optionally, the differential analog-to-digital conversion module is a SAR ADC structure.

[0020] More optionally, the differential analog-to-digital conversion module includes a third switch, a first switch capacitor array, a fourth switch, a first noise elimination capacitor, a fifth switch, a sixth switch, a second switch capacitor array, a seventh switch, a second noise elimination capacitor, an eighth switch, a preamplifier, a latch, and a SAR logic unit;

[0021] One end of the third switch is connected to the first input signal, and the other end is connected to the lower plate of each sampling capacitor in the first switch capacitor array; the lower plate of each sampling capacitor in the first switch capacitor array is also connected to the positive reference voltage and the negative reference voltage through corresponding switches, and the upper plate is connected to the first input end of the pre-amplifier; one end of the fourth switch is connected to the common mode voltage, and the other end is connected to the upper plate of each sampling capacitor in the first switch capacitor array;

[0022] One end of the sixth switch is connected to the second input signal, and the other end is connected to the lower plate of each sampling capacitor in the second switch capacitor array; the lower plate of each sampling capacitor in the second switch capacitor array is also connected to the positive reference voltage and the negative reference voltage through corresponding switches, and the upper plate is connected to the second input end of the pre-amplifier; one end of the seventh switch is connected to the common mode voltage, and the other end is connected to the upper plate of each sampling capacitor in the second switch capacitor array;

[0023] The first output terminal and the second output terminal of the preamplifier are connected to the lower plates of the first noise elimination capacitor and the second noise elimination capacitor respectively;

[0024] One end of the fifth switch is connected to the common mode voltage, and the other end is connected to the upper plate of the first noise elimination capacitor; one end of the eighth switch is connected to the common mode voltage, and the other end is connected to the upper plate of the second noise elimination capacitor;

[0025] The first input terminal and the second input terminal of the latch are respectively connected to the upper plates of the first noise elimination capacitor and the second noise elimination capacitor;

[0026] The SAR logic unit is connected to the output end of the latch, and controls the first switch capacitor array and each switch in the first switch capacitor array to switch to a corresponding reference voltage based on an output signal of the latch.

[0027] More optionally, the differential analog-to-digital conversion module is a Pipe-SAR ADC structure.

[0028] More optionally, the differential analog-to-digital conversion module includes a third switch, a first switch capacitor array, a fourth switch, a first noise elimination capacitor, a fifth switch, a sixth switch, a second switch capacitor array, a seventh switch, a second noise elimination capacitor, an eighth switch, a first feedback capacitor, a second feedback capacitor, a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a pre-amplifier, a comparator, a SAR logic unit, a post-amplifier and at least one SAR ADC unit;

[0029] One end of the third switch is connected to the first input signal, and the other end is connected to the lower plate of each sampling capacitor in the first switch capacitor array; the lower plate of each sampling capacitor in the first switch capacitor array is also connected to the positive reference voltage and the negative reference voltage through corresponding switches, and the upper plate is connected to the input end of the pre-amplifier; one end of the fourth switch is connected to the common mode voltage, and the other end is connected to the upper plate of each sampling capacitor in the first switch capacitor array;

[0030] One end of the sixth switch is connected to the second input signal, and the other end is connected to the lower plate of each sampling capacitor in the second switch capacitor array; the lower plate of each sampling capacitor in the second switch capacitor array is also connected to the positive reference voltage and the negative reference voltage through corresponding switches, and the upper plate is connected to the second input end of the pre-amplifier; one end of the seventh switch is connected to the common mode voltage, and the other end is connected to the upper plate of each sampling capacitor in the second switch capacitor array;

[0031] The first output terminal and the second output terminal of the preamplifier are connected to the lower plates of the first noise elimination capacitor and the second noise elimination capacitor respectively;

[0032] One end of the fifth switch is connected to the common mode voltage, and the other end is connected to the upper plate of the first noise elimination capacitor; one end of the eighth switch is connected to the common mode voltage, and the other end is connected to the upper plate of the second noise elimination capacitor;

[0033] The first input terminal and the second input terminal of the comparator are respectively connected to the upper plates of the first noise elimination capacitor and the second noise elimination capacitor;

[0034] The SAR logic unit is connected to the output end of the comparator, and controls each switch in the first switch capacitor array and the second switch capacitor array to switch to a corresponding reference voltage based on an output signal of the SAR logic unit;

[0035] The first input terminal and the second input terminal of the post-stage amplifier are respectively connected to the upper plates of the first noise elimination capacitor and the second noise elimination capacitor, and form a ring amplifier with the pre-amplifier;

[0036] The lower plate of the first feedback capacitor is connected to the common mode voltage via the ninth switch, and is also connected to the first output terminal of the post-stage amplifier via the tenth switch; the upper plate of the first feedback capacitor is connected to the output terminal of the first switch capacitor array; the lower plate of the second feedback capacitor is connected to the common mode voltage via the eleventh switch, and is also connected to the second output terminal of the post-stage amplifier via the twelfth switch; the upper plate of the second feedback capacitor is connected to the output terminal of the second switch capacitor array;

[0037] The SAR ADC units of each stage are cascaded in sequence to the output end of the post-stage amplifier.

[0038] More specifically, the differential analog-to-digital conversion module also includes a thirteenth switch, a fourteenth switch, a first resistor and a second resistor; the first resistor is connected between the fifth switch and the common mode voltage, and the thirteenth switch is connected in parallel to both ends of the first resistor; the second resistor is connected between the eighth switch and the common mode voltage, and the fourteenth switch is connected in parallel to both ends of the second resistor.

[0039] To achieve the above object and other related objects, the present invention further provides an analog-to-digital conversion method, which is implemented based on the above analog-to-digital converter, and the analog-to-digital conversion method at least includes:

[0040] At a first sampling moment, the input signal and the sampled thermal noise are collected to the input end of the preamplifier; at the same time, a compensation voltage is obtained by differentiating the compensation signal, and the compensation voltage is loaded to the input end of the preamplifier to compensate for the voltage change of the input signal coupled to the input end of the preamplifier;

[0041] At the second sampling moment, sampling and storing the signals that have been compensated and pre-amplified in sequence;

[0042] In the quantization stage, the sampling thermal noise stored at the output of the preamplifier and the sampling thermal noise sampled at the input of the preamplifier cancel each other out; the potential of the lower plate of the sampling capacitor is adjusted based on successive approximation logic, thereby achieving analog-to-digital conversion.

[0043] To achieve the above-mentioned object and other related objects, the present invention further provides an electronic product, which at least includes: the above-mentioned analog-to-digital converter.

[0044] As described above, the analog-to-digital converter, conversion method and electronic product of the present invention have the following beneficial effects:

[0045] 1. The analog-to-digital converter, conversion method and electronic product of the present invention offset the voltage change coupled from the input signal through the compensation module, thereby reducing the signal change at the pre-amplifier input node, avoiding saturation of the pre-amplifier output, greatly improving the spurious-free dynamic range of the analog-to-digital converter, and thus improving the stability and reliability of the analog-to-digital converter under high-frequency signals.

[0046] 2. The analog-to-digital converter, conversion method and electronic product of the present invention eliminate the sampling thermal noise based on the double sampling technology, effectively reduce the equivalent input noise, and thus reduce the area of ​​the sampling capacitor; at the same time, the noise of the compensation module can also be eliminated, further reducing the area and power consumption of the compensation module.

[0047] 3. The analog-to-digital converter, conversion method and electronic product of the present invention have significant advantages in improving analog-to-digital conversion performance and widening signal bandwidth. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 Shown is a structural schematic diagram of the analog-to-digital converter of the present invention.

[0049] Figure 2 It is a schematic diagram showing the structure of the compensation unit of the present invention.

[0050] Figure 3 Shown is another structural schematic diagram of the analog-to-digital converter of the present invention.

[0051] Figure 4 Display as Figure 1 and Figure 3 Schematic diagram of the working timing of the analog-to-digital converter.

[0052] Figure 5 Shown is another structural schematic diagram of the analog-to-digital converter of the present invention.

[0053] Figure 6 Display as Figure 5 Schematic diagram of the working timing of the analog-to-digital converter.

[0054] Figure 7 It is a schematic diagram showing the principle of the output saturation of the pre-amplifier of the present invention when a high-frequency signal is applied.

[0055] Figure 8 It is a schematic diagram showing the principle of preventing the pre-amplifier from outputting saturation when a high-frequency signal is generated in the present invention.

[0056] Fig. 9 It is a schematic diagram showing the simulation of the spurious free dynamic range of the analog-to-digital converter of the present invention and the analog-to-digital converter without compensation at different input signal frequencies.

[0057] Fig.10Shown is a schematic diagram of simulation results of each equivalent input noise in the analog-to-digital converter of the present invention.

[0058] Component number description

[0059] 1 Analog-to-digital converter

[0060] 11 Differential analog-to-digital conversion module

[0061] 111a, 111b first and second switch capacitor arrays

[0062] 112 Pre-amplifier

[0063] 113 Latch

[0064] 114 SAR logic unit

[0065] 115 Comparator

[0066] 116 Post-amplifier

[0067] 117 SAR ADC unit

[0068] 12a, 12b The first and second compensation units

[0069] 121 Differential Circuits

[0070] 121a Op amp DETAILED DESCRIPTION

[0071] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0072] See also Figures 1 to 10 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0073] like Figure 1 and Figure 8As shown, the present invention provides an analog-to-digital converter 1, which includes: a differential analog-to-digital conversion module 11 and a compensation module. The differential analog-to-digital conversion module 11 eliminates sampling thermal noise based on a double sampling method and realizes analog-to-digital conversion of the input signal; the compensation module receives the compensation signal, and the output end is connected to the input end of the preamplifier in the differential analog-to-digital conversion module 11, and compensates for the change of the input signal coupled to the preamplifier input end based on a differential method; wherein the input signal and the compensation signal connected to the same input end of the preamplifier are differential signals. In this example, the first input signal is V ip , the corresponding first compensation signal is V in ; The second input signal is V in , and its corresponding second compensation signal is V ip .

[0074] like Figure 2 As shown, the compensation module includes a first compensation unit 12a and a second compensation unit 12b. In this embodiment, the first compensation unit 12a and the second compensation unit 12b both include a differential circuit 121, a first switch K1, a second switch K2 and a compensation capacitor C R .

[0075] Specifically, the input end of the differential circuit 121 receives the corresponding compensation signal, and the output end is connected to the compensation capacitor C via the first switch K1. R The lower plate of the compensation capacitor C R The upper plate of is used as the output end of the corresponding compensation unit (connected to the input end of the pre-amplifier); Figure 4 As shown, the first switch K1 is controlled by the first control signal The sampling timing of the first switch K1 is consistent with the sampling timing of the sampling capacitor in the differential analog-to-digital conversion module 11. Figure 2 As shown, as an example, the differential circuit 121 includes an operational amplifier 121a, a capacitor C d (input capacitor) and resistor R d (feedback resistor), capacitor C d The lower plate of the differential circuit 121 is used as the input terminal, and the capacitor C d The upper plate is connected to the input end of the operational amplifier 121a, and the output end of the operational amplifier 121a is used as the output end of the differential circuit 121. The resistor R d Connected to the input terminal of op amp 121a (capacitor C d In actual use, any circuit structure that can achieve differentiation is applicable to the present invention, and is not limited to this embodiment.

[0076] Specifically, one end of the second switch K2 is connected to the common mode voltage V CM , the other end is connected to the compensation capacitor C R The lower plate. Figure 3 As shown, the second switch K2 is controlled by the first control signal The counter signal That is, the on-off state of the second switch K2 is opposite to that of the first switch K1.

[0077] As an implementation of the present invention, the differential analog-to-digital conversion module 11 is a SAR ADC structure. Figure 1 As shown, as an example, the differential analog-to-digital conversion module 11 includes a third switch K3, a first switch capacitor array 111a, a fourth switch K4, a preamplifier 112, a first noise elimination capacitor C NCa , a fifth switch K5, a sixth switch K6, a second switch capacitor array 111b, a seventh switch K7, a second noise elimination capacitor C NCb , an eighth switch K8 , a latch 113 and a SAR logic unit 114 .

[0078] Specifically, one end of the third switch K3 is connected to the first input signal V ip , and the other end is connected to the lower plate of each sampling capacitor Cs in the first switch capacitor array 111a; the third switch K3 is controlled by the second control signal The lower plates of the sampling capacitors Cs in the first switch capacitor array 111a are also connected to the positive phase reference voltage V RP And the inverting reference voltage V RN The upper plate of each sampling capacitor Cs in the first switch capacitor array 111a is connected to the first input terminal of the preamplifier 112. One end of the fourth switch K4 is connected to the common mode voltage V CM , and the other end is connected to the upper plate of each sampling capacitor Cs in the first switch capacitor array 111a; the fourth switch K4 is controlled by the first control signal The first noise elimination capacitor C NCa The lower plate of the fifth switch K5 is connected to the first output terminal of the preamplifier 112, and the upper plate is connected to the first input terminal of the latch 113. One end of the fifth switch K5 is connected to the common mode voltage V CM , the other end is connected to the first noise elimination capacitor C NCa The fifth switch K5 is controlled by the second control signal The sixth switch K6, the second switch capacitor array 111b, the seventh switch K7, the second noise elimination capacitor C NCbThe eighth switch K8 and the eighth switch K8 constitute another branch in the differential path, and the connection relationship is not described here one by one. The preamplifier 112 and the latch 113 constitute a comparator. In this embodiment, the preamplifier 112 is set as a high-bandwidth low-noise amplifier. The SAR logic unit 114 is connected to the output end of the latch 113, and controls each switch in the first switch capacitor array 111a and the second switch capacitor array 111b to switch to the corresponding reference voltage (positive phase reference voltage V RP Or inverting reference voltage V RN ) to achieve successive approximation analog-to-digital conversion.

[0079] Furthermore, if Figure 3 As shown, the differential analog-to-digital conversion module 11 further includes a thirteenth switch K13, a fourteenth switch K14, a first resistor R1 and a second resistor R2. The first resistor R1 is connected to the fifth switch K5 and the common mode voltage V CM The thirteenth switch K13 is connected in parallel to both ends of the first resistor R1, and the thirteenth switch K13 is controlled by the fourth control signal Used to adjust the first noise elimination capacitor C NCa The potential of the upper plate is the first noise elimination capacitor C after the sampling capacitor sampling is completed and before the noise elimination capacitor sampling NCa The potential of the upper plate changes from the common mode voltage V CM The voltage is adjusted up to the sum of the common mode voltage and the voltage drop on the first resistor; similarly, the connection relationship and function of the second resistor R2 and the fourteenth switch K14 are similar and will not be described in detail here.

[0080] The differential analog-to-digital conversion module 11 ( Figure 1 and Figure 3 ) control sequence is as follows Figure 4 As shown. Any SAR ADC structure that eliminates sampling thermal noise based on a double sampling method is applicable to the present invention, and is not limited to this embodiment. The differential analog-to-digital conversion module 11 based on the SAR ADC structure of the present invention embeds a noise elimination capacitor at the output end of the pre-amplifier 112, and cooperates with the original sampling capacitor to achieve double sampling, collect sampling thermal noise and eliminate the noise in the process of successive approximation quantization; therefore, the analog-to-digital converter can achieve a high signal-to-noise and distortion ratio (SNDR).

[0081] As another implementation of the present invention, in order to improve the quantization speed, the differential analog-to-digital conversion module 11 is set to a Pipe-SAR ADC structure. Figure 5 As shown, as an example, the differential analog-to-digital conversion module 11 includes a third switch K3, a first switch capacitor array 111a, a fourth switch K4, a preamplifier 112, a first noise elimination capacitor CNCa , the fifth switch K5, the comparator 115, the SAR logic unit 114, the post-amplifier 116, the first feedback capacitor C FBa , the sixth switch K6, the second switch capacitor array 111b, the seventh switch K7, the second noise elimination capacitor C NCbb , the eighth switch K8, the second feedback capacitor C FBb , a ninth switch K9, a tenth switch K10, an eleventh switch K11, a twelfth switch K12 and at least one SAR ADC unit 117; wherein the third switch K3, the sixth switch K6, the first switch capacitor array 111a, the second switch capacitor array 111b, the fourth switch K4, the seventh switch K7, the preamplifier 112, the first noise elimination capacitor C NCa , the second noise elimination capacitor C NCb , the fifth switch K5, the eighth switch K8 and Figure 1 The first input terminal and the second input terminal of the post-stage amplifier 116 are respectively connected to the first noise elimination capacitor C NCa And the second noise elimination capacitor C NCb The upper plate of the comparator 115 forms a ring amplifier with the preamplifier 112 (the output is inverted with the input, which can be achieved by adjusting the output phase of the preamplifier 112 and / or the post-amplifier 116). The first input terminal and the second input terminal of the comparator 115 are respectively connected to the first noise elimination capacitor C NCa And the second noise elimination capacitor C NCb The first feedback capacitor C FBa The lower plate of the common mode voltage V CM The ninth switch K9 is controlled by the second control signal The first feedback capacitor C FBa The lower electrode plate is also connected to the first output terminal of the post-stage amplifier 116 via the tenth switch K10, and the tenth switch K10 is controlled by the third control signal The first feedback capacitor C FBa The upper plate of the second feedback capacitor C is connected to the output end of the first switch capacitor array 111a. FBb The eleventh switch K11 and the twelfth switch K12 are connected between the second input terminal of the pre-amplifier 112 and the second output terminal of the post-amplifier 116 in a similar connection relationship, which will not be described in detail here. Each level of SAR ADC unit 117 is cascaded to the output terminal of the post-amplifier 116 in sequence; in this example, only one level of SAR ADC unit 117 is set as the second level SAR ADC.

[0082] Similarly, further, the differential analog-to-digital conversion module 11 of the present implementation may further include a thirteenth switch K13, a fourteenth switch K14, a first resistor R1 and a second resistor R2, the connection relationship and function of which are similar to those of Figure 3 The same, I will not elaborate here one by one.

[0083] The control timing of the differential analog-to-digital conversion module 11 of this implementation is as follows: Figure 6 As shown, the differential analog-to-digital conversion module 11 of this example can achieve a high signal-to-noise-distortion ratio and a high sampling rate.

[0084] like Figure 1 to Figure 6 As shown in the figure, at sampling time t1, the sampling capacitor Cs is controlled to sample based on the lower plate, and an additional sampling time t2 is added on this basis to control the sampling of the noise elimination capacitor; there is a delay Δt between sampling time t1 and sampling time t2. The sampling thermal noise at sampling time t1 is regarded as dynamic offset, and the influence of the sampling thermal noise is offset by self-zeroing through double sampling of the sampling capacitor Cs and the noise elimination capacitor. For simplicity, Figure 5 Take the single side of the differential structure as an example to illustrate, Figure 7 As shown, in the initial state, the third switch K3, the fourth switch K4 and the fifth switch K5 are in the state of the first control signal and the second control signal Under the control of, they are all in a closed state; at the sampling time t1, the first control signal The fourth switch K4 is controlled to be disconnected, and the sampling thermal noise is fixed at this time. For a continuously working analog-to-digital converter, this noise can be regarded as random noise of the system, but for the current sampling quantization process, this noise can also be regarded as dynamic offset. In this example, in order to increase energy efficiency, the amplifier in the multiplexed SAR ADC comparator is used as a pre-amplifier to treat the sampling thermal noise as the offset of the pre-amplifier after Δt (sampling time t2), and the effect of this noise on the performance of the analog-to-digital conversion system is offset by outputting the offset self-zeroing, thereby breaking through the limitation of the signal-to-noise and distortion ratio (SNDR) of a small sampling capacitor.

[0085] During Δt, the first input signal V ip is also changing and is coupled to the input terminal V of the preamplifier 112 through the sampling capacitor Cs. T ; Sampling thermal noise and coupling to V through sampling capacitor Cs T The changing input signals of the nodes are amplified by the preamplifier 112. In simple terms, the output voltage of the preamplifier 112 satisfies at sampling time t2:

[0086] A 1out (t2) = A1 · [Vip (t2)-V ip (t1)+v ns1 ] (1);

[0087] Where A1 is the gain of the preamplifier 112, V ip (t2) is the value of the input signal at sampling time t2, V ip (t1) is the value of the input signal at sampling time t1, v ns1 is the sampling thermal noise on the sampling capacitor Cs at sampling time t1. It is worth noting that formula (1) does not include the influence of other non-ideal factors such as the offset and noise of the pre-amplifier 112; nor does it consider the gain coefficient caused by the parasitic capacitance and feedback capacitance at the input end of the pre-amplifier 112 on the output calculation of the pre-amplifier 112.

[0088] The noise introduced by the preamplifier 112 at the sampling time t2 is equivalent to the input end, satisfying the following relationship:

[0089]

[0090] Where γ is the noise coefficient, k is the Boltzmann constant, T is the temperature, C NC is the capacitance of the noise elimination capacitor.

[0091] Under low frequency input signal, due to the first input signal V ip The change itself is relatively slow. In the Δt time period, the first input signal V ip The change in the amount is relatively small; however, when the first input signal V ip When it is a high frequency signal, due to the rapid change, the first input signal V ip The variation of is relatively large, such as Figure 7 As shown, if the sampling capacitor C S The change in the coupled input signal is amplified (A1·[V ip (t2)-V ip(t1)]) exceeds the output range of the preamplifier 112, the performance of the analog-to-digital converter will be seriously reduced; the above problem can be alleviated by reducing the delay Δt or reducing the gain of the preamplifier 112. Combining formula (1) and formula (2), reducing the delay Δt requires increasing the bandwidth of the preamplifier 112 to better collect the sampling thermal noise on the noise elimination capacitor; if the noise introduced by the preamplifier 112 at the sampling time t2 is to be guaranteed to remain unchanged, the power consumption of the preamplifier 112 needs to be increased, which may seriously reduce the overall energy efficiency of the system. On the other hand, reducing the gain of the preamplifier 112 can also alleviate the problem of amplifier saturation, but this will also cause the preamplifier 112 to introduce greater noise at the sampling time t2, reducing the overall signal-to-noise distortion ratio of the analog-to-digital converter. This limitation limits the ability of sampling thermal noise elimination technology to improve signal bandwidth.

[0092] The compensation module of the present invention compensates the influence of the changing signal on the input node of the preamplifier 112 through a first-order approximate compensation path based on a differential circuit, effectively canceling the input signal (satisfying ) is coupled to the input node of the preamplifier 112, so that the preamplifier 112 can work in a smaller input range, which not only ensures the elimination of sampling thermal noise, but also improves the linearity of the system. The input signal (compensation signal) of the differential circuit 121 satisfies Without considering the limited gain and limited bandwidth of the operational amplifier 121a in the differential circuit 121, the output of the differential circuit 121 satisfies:

[0093] V ind =-R d ·C d ·dV in (3);

[0094] Among them, dV in is the differential of the compensation signal Vin.

[0095] At sampling time t1, the first switch K1 and the fourth switch K4 are turned off, the second switch K2 is turned on, and the compensation capacitor C R and sampling capacitor C S The upper plate of the common mode voltage V CM Disconnect, and the compensation capacitor C R The lower plate of the output from the differential circuit 121 is switched to the common mode voltage V CM , the compensation path passes through the compensation capacitor C R V T The voltage change of the node satisfies:

[0096]

[0097] Among them, C P VT The parasitic capacitance of the node. Combining formula (1) and formula (4), we can get if:

[0098]

[0099] That is Then V T The voltage of the node is compensated in a first-order approximation, which can reduce the sampling thermal noise while avoiding the saturation of the output voltage of the preamplifier 112. In addition, this compensation condition is independent of the input signal frequency.

[0100] It should be noted that the above principle is described based on an analog-to-digital converter with a Pipe-SAR ADC structure. The principle of an analog-to-digital converter based on a SAR ADC structure is similar and will not be described in detail here.

[0101] The present invention also provides an analog-to-digital conversion method, which is implemented based on the analog-to-digital converter of the present invention. The method comprises:

[0102] 1) At the first sampling time t1, the input signal and the sampled thermal noise are collected to the input end of the pre-amplifier 112; at the same time, the compensation voltage is obtained by differentiating the compensation signal, and the compensation voltage is loaded to the input end of the pre-amplifier 112 to compensate for the voltage change of the input signal coupled to the input end of the pre-amplifier 112.

[0103] Specifically, in this embodiment, Figure 5 The Pipe-SAR ADC structure analog-to-digital converter is used as an example. In the initial state, the first control signal and the second control signal is high level, the third control signal is low level, the first switch K1 in each compensation unit is closed, and the second switch K2 is opened; the third switch K3, the fourth switch K4, the fifth switch K5, the sixth switch K6, the seventh switch K7, the eighth switch K8, the ninth switch K9, and the eleventh switch K11 in the differential analog-to-digital conversion module are closed, and the tenth switch K10 and the twelfth switch K12 are opened, and the compensation capacitor C R The upper plate of the sampling capacitor Cs is connected to the common mode voltage V CM At the first sampling time t1, the first control signal jumps to a low level, the first switch K1 in each compensation unit is disconnected, and the second switch K2 is closed; the fourth switch K4 and the seventh switch K7 in the differential analog-to-digital conversion module are disconnected, and the compensation capacitor C R and the upper plate of the sampling capacitor Cs from the common mode voltage V CM Disconnect, compensation capacitor C R The lower plate is switched to the common mode voltage V CM, the sampling capacitor Cs completes sampling. At this time, the sampled thermal noise is collected to the upper plate of the sampling capacitor Cs. Before the second sampling time t2 arrives, the change in the input signal is coupled to the upper plate of the sampling capacitor Cs (Vcs) and is compensated by the voltage (V CR ) cancels out, the input signal (V AIN ) becomes smaller, thereby making the output signal (Vo1) of the preamplifier 112 within the output range, such as Figure 8 shown.

[0104] 2) At the second sampling time t2, the signals that have been compensated and pre-amplified are sampled and stored.

[0105] Specifically, at the second sampling time t2, the second control signal The third switch K3, the fifth switch K5, the sixth switch K6, the eighth switch K8, the ninth switch K9 and the eleventh switch K11 are disconnected, and the upper plate of the noise elimination capacitor is connected from the common mode voltage V CM Disconnect, the input signal and sampled thermal noise are sampled and stored on the noise elimination capacitor. At this time, the noise elimination capacitor completes sampling.

[0106] 3) In the quantization stage, the sampling thermal noise stored at the output of the preamplifier 112 and the sampling thermal noise sampled at the input of the preamplifier 112 are offset by the preamplifier 112; the potential of the lower plate of the sampling capacitor is adjusted based on the successive approximation logic, thereby realizing analog-to-digital conversion.

[0107] Specifically, after the double sampling is completed, the third control signal The signal level jumps to a high level, and the tenth switch K10 and the twelfth switch K12 are turned on to realize inter-stage amplification. In this process, since the sampling thermal noise at the input end of the preamplifier 112 is in antiphase with the sampling thermal noise on the noise elimination capacitor, noise cancellation is realized on the noise elimination capacitor.

[0108] The present invention also provides an electronic product, which includes the analog-to-digital converter 1 of the present invention, thereby achieving high-performance analog-to-digital conversion and meeting requirements such as accuracy, linearity, power consumption, and conversion speed. The electronic product is applicable to the fields of audio processing, video processing, medical equipment, industrial automation, consumer electronics, automotive electronics, and energy management, and will not be described in detail here.

[0109] In order to verify the improvement of system performance by the analog-to-digital converter 1 of the present invention, Figure 5 The analog-to-digital converter 1 with the compensation module is compared with the analog-to-digital converter without the compensation module. For a fair comparison, except for the compensation path, the other circuits are kept the same (that is, the difference between the two is only whether the compensation module is set);S The capacitance value is 2pF, and the post-amplifier 116 adopts a gain-enhanced operational amplifier structure to achieve a high-gain operational amplifier. Such a test design ensures the reliability and comparability of the test results. Fig. 9 As shown, compared with an uncompensated analog-to-digital converter, the analog-to-digital converter of the present invention can improve the spurious-free dynamic range (SFDR) performance by 10dB to 30dB under the condition of an input frequency signal of about 2MHz to 10MHz. This improvement will bring significant improvements to the performance and stability of the system, making the analog-to-digital converter perform better under high-frequency signals.

[0110] The present invention eliminates the sampling thermal noise by using a pre-amplifier to collect and offset the sampling thermal noise as an offset voltage. The sampling thermal noise elimination effect of the present invention is further tested below. Figure 5 For example, the analog-to-digital converter Fig.10 As shown in the figure, after adopting the sampling thermal noise elimination technology of the present invention, the equivalent input sampling thermal noise is reduced from the original 105μV to 9.8μV, and the total noise of the equivalent input sampling thermal noise, pre-amplifier, post-amplifier and differential circuit (calculated by summing the squares of each term and then taking the square root) is reduced from 113μV to 39.8μV. Therefore, the sampling thermal noise elimination technology of the present invention can achieve a signal-to-noise distortion ratio of 92dB when using a 2pF sampling capacitor. In addition, Fig.10 It can also be seen that the noise of the differential circuit can also be eliminated by the structure, so the area and power consumption required to realize the operational amplifier 121a are much lower than those of the pre-amplifier 112 and the post-amplifier 116. It can be seen that the analog-to-digital converter of the present invention has significant advantages in improving system performance and reducing power consumption.

[0111] In summary, the present invention provides an analog-to-digital converter, a conversion method and an electronic product, including: a differential analog-to-digital conversion module and a compensation module; the differential analog-to-digital conversion module eliminates sampling thermal noise based on a double sampling method, and realizes analog-to-digital conversion of the input signal; the compensation module receives the compensation signal, and the output end is connected to the input end of the preamplifier in the differential analog-to-digital conversion module, and compensates for the change of the input signal coupled to the input end of the preamplifier based on a differential method; wherein the input signal and the compensation signal connected to the same input end of the preamplifier are differential signals. The analog-to-digital converter, the conversion method and the electronic product of the present invention adopt sampling thermal noise elimination technology, and increase the signal bandwidth limited by the amplifier saturation problem by adopting a first-order approximate compensation module based on a differential circuit, and have the advantages of small sampling capacitance, low noise, and large signal bandwidth. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0112] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. An analog-to-digital converter, characterized in that: The analog-to-digital converter comprises at least: Differential analog-to-digital conversion module and compensation module; The differential analog-to-digital conversion module eliminates sampling thermal noise based on a double sampling method and realizes analog-to-digital conversion of the input signal; The compensation module receives a compensation signal, and an output end is connected to an input end of a preamplifier in the differential analog-to-digital conversion module, and compensates for a change in coupling of the input signal to the input end of the preamplifier based on a differential method; The input signal and the compensation signal connected to the same input terminal of the pre-amplifier are differential signals.

2. The analog-to-digital converter according to claim 1, characterized in that: The compensation module includes a first compensation unit and a second compensation unit, and the first compensation unit and the second compensation unit each include a differential circuit, a first switch, a second switch and a compensation capacitor; The input end of the differential circuit receives the corresponding compensation signal, and the output end is connected to the lower plate of the compensation capacitor via the first switch; The upper plate of the compensation capacitor is connected to the corresponding input terminal of the pre-amplifier; One end of the second switch is connected to the common mode voltage, and the other end is connected to the lower plate of the compensation capacitor; The sampling timing of the first switch is consistent with the sampling timing of the sampling capacitor in the differential analog-to-digital conversion module, and the on-off state of the second switch is opposite to that of the first switch.

3. The analog-to-digital converter according to claim 2, characterized in that: The analog-to-digital converter satisfies: Among them, Δt is the time difference between the two samples, R d is the value of the resistor in the differential circuit, C d is the value of the capacitor in the differential circuit, C R is the value of the compensation capacitor, C S is the value of the sampling capacitor.

4. The analog-to-digital converter according to any one of claims 1 to 3, characterized in that: The differential analog-to-digital conversion module is a SARADC structure.

5. The analog-to-digital converter according to claim 4, characterized in that: The differential analog-to-digital conversion module includes a third switch, a first switch capacitor array, a fourth switch, a first noise elimination capacitor, a fifth switch, a sixth switch, a second switch capacitor array, a seventh switch, a second noise elimination capacitor, an eighth switch, a preamplifier, a latch, and a SAR logic unit; One end of the third switch is connected to the first input signal, and the other end is connected to the lower plate of each sampling capacitor in the first switch capacitor array; the lower plate of each sampling capacitor in the first switch capacitor array is also connected to the positive reference voltage and the negative reference voltage through corresponding switches, and the upper plate is connected to the first input end of the pre-amplifier; one end of the fourth switch is connected to the common mode voltage, and the other end is connected to the upper plate of each sampling capacitor in the first switch capacitor array; One end of the sixth switch is connected to the second input signal, and the other end is connected to the lower plate of each sampling capacitor in the second switch capacitor array; the lower plate of each sampling capacitor in the second switch capacitor array is also connected to the positive reference voltage and the negative reference voltage through corresponding switches, and the upper plate is connected to the second input end of the pre-amplifier; one end of the seventh switch is connected to the common mode voltage, and the other end is connected to the upper plate of each sampling capacitor in the second switch capacitor array; The first output terminal and the second output terminal of the preamplifier are connected to the lower plates of the first noise elimination capacitor and the second noise elimination capacitor respectively; One end of the fifth switch is connected to the common mode voltage, and the other end is connected to the upper plate of the first noise elimination capacitor; One end of the eighth switch is connected to the common mode voltage, and the other end is connected to the upper plate of the second noise elimination capacitor; The first input terminal and the second input terminal of the latch are respectively connected to the upper plates of the first noise elimination capacitor and the second noise elimination capacitor; The SAR logic unit is connected to the output end of the latch, and controls the first switch capacitor array and each switch in the first switch capacitor array to switch to a corresponding reference voltage based on an output signal of the latch.

6. The analog-to-digital converter according to any one of claims 1 to 3, characterized in that: The differential analog-to-digital conversion module is a Pipe-SAR ADC structure.

7. The analog-to-digital converter according to claim 6, characterized in that: The differential analog-to-digital conversion module includes a third switch, a first switch capacitor array, a fourth switch, a first noise elimination capacitor, a fifth switch, a sixth switch, a second switch capacitor array, a seventh switch, a second noise elimination capacitor, an eighth switch, a first feedback capacitor, a second feedback capacitor, a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a pre-amplifier, a comparator, a SAR logic unit, a post-amplifier and at least one SAR ADC unit; One end of the third switch is connected to the first input signal, and the other end is connected to the lower plate of each sampling capacitor in the first switch capacitor array; the lower plate of each sampling capacitor in the first switch capacitor array is also connected to the positive reference voltage and the negative reference voltage through corresponding switches, and the upper plate is connected to the first input end of the pre-amplifier; one end of the fourth switch is connected to the common mode voltage, and the other end is connected to the upper plate of each sampling capacitor in the first switch capacitor array; One end of the sixth switch is connected to the second input signal, and the other end is connected to the lower plate of each sampling capacitor in the second switch capacitor array; the lower plate of each sampling capacitor in the second switch capacitor array is also connected to the positive reference voltage and the negative reference voltage through corresponding switches, and the upper plate is connected to the second input end of the pre-amplifier; one end of the seventh switch is connected to the common mode voltage, and the other end is connected to the upper plate of each sampling capacitor in the second switch capacitor array; The first output terminal and the second output terminal of the preamplifier are connected to the lower plates of the first noise elimination capacitor and the second noise elimination capacitor respectively; One end of the fifth switch is connected to the common mode voltage, and the other end is connected to the upper plate of the first noise elimination capacitor; One end of the eighth switch is connected to the common mode voltage, and the other end is connected to the upper plate of the second noise elimination capacitor; The first input terminal and the second input terminal of the comparator are respectively connected to the upper plates of the first noise elimination capacitor and the second noise elimination capacitor; The SAR logic unit is connected to the output end of the comparator, and controls each switch in the first switch capacitor array and the second switch capacitor array to switch to a corresponding reference voltage based on an output signal of the SAR logic unit; The first input terminal and the second input terminal of the post-stage amplifier are respectively connected to the upper plates of the first noise elimination capacitor and the second noise elimination capacitor, and form a ring amplifier with the pre-amplifier; The lower plate of the first feedback capacitor is connected to the common mode voltage via the ninth switch, and is also connected to the first output terminal of the post-stage amplifier via the tenth switch; the upper plate of the first feedback capacitor is connected to the output terminal of the first switch capacitor array; the lower plate of the second feedback capacitor is connected to the common mode voltage via the eleventh switch, and is also connected to the second output terminal of the post-stage amplifier via the twelfth switch; the upper plate of the second feedback capacitor is connected to the output terminal of the second switch capacitor array; The SAR ADC units of each stage are cascaded in sequence to the output end of the post-stage amplifier.

8. The analog-to-digital converter according to claim 5 or 7, characterized in that: The differential analog-to-digital conversion module also includes a thirteenth switch, a fourteenth switch, a first resistor and a second resistor; the first resistor is connected between the fifth switch and the common mode voltage, and the thirteenth switch is connected in parallel to both ends of the first resistor; the second resistor is connected between the eighth switch and the common mode voltage, and the fourteenth switch is connected in parallel to both ends of the second resistor.

9. An analog-to-digital conversion method, implemented based on the analog-to-digital converter according to any one of claims 1 to 8, characterized in that: The analog-to-digital conversion method at least comprises: At a first sampling moment, the input signal and the sampled thermal noise are collected to the input end of the preamplifier; at the same time, a compensation voltage is obtained by differentiating the compensation signal, and the compensation voltage is loaded to the input end of the preamplifier to compensate for the voltage change of the input signal coupled to the input end of the preamplifier; At the second sampling moment, sampling and storing the signals that have been compensated and pre-amplified in sequence; In the quantization stage, the sampling thermal noise stored at the output of the preamplifier and the sampling thermal noise sampled at the input of the preamplifier cancel each other out; the potential of the lower plate of the sampling capacitor is adjusted based on successive approximation logic, thereby achieving analog-to-digital conversion.

10. An electronic product, characterized in that: The electronic product at least comprises: an analog-to-digital converter as described in any one of claims 1-8.

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