Signal generation device and signal generation method executed by the signal generation device

Abstract

Define the timing of the start of SSC modulation in a shorter time than before. 【Solution means】 The signal generator 1 includes a clock source 2 that generates a clock of a reference frequency, a jitter modulation source 3 that generates a jitter clock obtained by modulating the clock of the reference frequency, a signal generation source 4 that generates a signal of a frequency transition pattern defined by a desired standard for input to the object under measurement W at the timing of the jitter clock, and an operation unit 5 that sets the type of the signal of the frequency transition pattern, the start time of modulation applied to the clock of the reference frequency, and the frequency offset amount when applying modulation to the clock of the reference frequency. The signal generation source 4 notifies the jitter modulation source 3 of the timing of switching of the signal of the frequency transition pattern for which modulation is applied to the clock of the reference frequency. When receiving the notification from the signal generation source 4, the jitter modulation source 3 outputs a jitter clock obtained by applying modulation of the frequency offset amount to the clock of the reference frequency to the signal generation source 4.

Description

Technical Field

[0001] The present invention relates to a signal generation device that generates a signal using SSC (spread spectrum clocking). and executed by the signal generation device It relates to a signal generation method.

Background Art

[0002] The standard speed of USB used for communication between a computer and a device has been steadily increasing. Along with the increase in speed, the methods for ensuring signal quality have become more complex. As one of these methods, for example, as disclosed in Patent Document 1 below, spread spectrum clocking (SSC) is known. Naturally, the method of applying SSC and its frequency are also defined by standards. The standards define not only the regulations for the product itself but also the test methods for the product. All manufacturers producing products using USB standards and the like need to comply with these.

[0003] Here, as an example of testing whether a device under test operates normally with SSC applied to a 3-bit signal, a part of the Trit Error Rate test on the RX side of USB4 v2 Gen4 will be described as an example. FIG. 4 shows the order of the frequency transition patterns defined in USB4 v2 Gen4 in a diagram. When performing the Trit Error Rate test on the RX side of USB4 v2 Gen4, for the device under test (DUT), as shown in FIG. 4, it is necessary to give data patterns in the order of (1) PRBS11 (without SSC) → (2) PRTS7 (without SSC) → (3) PRTS19 (without SSC) → (4) PRTS19 (with SSC) (the measurement of the error rate itself is performed thereafter). Also, in FIG. 4, the switching from (3) to (4) needs to be performed within 500 μs.

Prior Art Documents

Patent Documents

[0004] [Patent Document 1] Japanese Patent Publication No. 7376521 [Summary of the Invention] [Problems to be Solved by the Invention]

[0005] By the way, when performing the above-described test, what the device manufacturer needs is a signal generator. The role of the signal generator is to generate a signal, but it cannot operate alone and often requires a separate clock source. And when frequency transition is required as described above, a device for modulating the clock in addition to the clock source is also required. As an example of such a device, a jitter modulation source can be cited. Jitter is the fluctuation of phase, and the jitter modulation source can give jitter with a specified pattern and fluctuation amount to the input clock and output it. That is, if it is an error rate measurement device (BERTS: Bit Error Rate Test Set) equipped with all of a clock source, a jitter modulation source, and a signal generation source, the demand can be satisfied by the device alone.

[0006] In this type of error rate measurement device, a clock source, a jitter modulation source, and a signal generation source are each incorporated as modules into the same device. Therefore, as a matter of course, each module can perform a certain degree of cooperative operation. Moreover, since the control device of the error rate measurement device controls each module, there is no technical problem here.

[0007] However, this is on the order of several hundred ms to several seconds, and as shown in FIG. 4, it is not possible to perform the cooperative operation of each module on the order of μs. The control device of the conventional error rate measurement device is not much different from a general computer, provides a GUI to the user, and controls each module based on the input from the user. That is, since it is based on application software, it is not suitable for timing control in the first place. From the above, a new mechanism is required to enable the output as shown in FIG. 4.

[0008] Therefore, the present invention has been made in view of the above problems, and a signal generation device and a executed by the signal generation device signal generation method capable of defining the timing of the start of modulation of SSC in a shorter time than before are provided.

Means for Solving the Problems

[0009] To achieve the above object, the signal generation device according to claim 1 of the present invention includes a clock source 2 that generates a clock of a reference frequency, a jitter modulation source 3 that generates a jitter clock obtained by modulating the clock of the reference frequency generated by the clock source, a signal generation source 4 that generates a signal of a frequency transition pattern defined by a desired standard for input to a measurement object W at the timing of the jitter clock, and an operation unit 5 that sets the type of the signal of the frequency transition pattern, the start time of modulation with respect to the clock of the reference frequency, and the frequency offset amount when modulating the clock of the reference frequency. The signal generation device 1 is characterized in that It includes a device control unit 8 that controls the switching timing of the signal of the frequency transition pattern that modulates the clock of the reference frequency, the signal generation source notifies the jitter modulation source of the switching timing of the signal of the frequency transition pattern that is modulated with respect to the clock of the reference frequency, and the jitter modulation source outputs, to the signal generation source, a jitter clock obtained by modulating the clock of the reference frequency by the frequency offset amount when receiving the notification from the signal generation source.

[0010] The signal generation device according to claim 2 of the present invention is the signal generation device according to claim 1, wherein the clock source 2, the jitter modulation source 3, and the signal generation source 4 are configured by modules that can be selectively attached to and detached from a plurality of slots 1c provided in the device main body 1a.

[0011] The signal generation device according to claim 3 of the present invention is the signal generation device according to claim 2, wherein a selector unit 7 for connecting between the modules is arranged. The device control unit 8, The selector unit is controlled to connect between the module of the jitter modulation source 3 and the module of the signal generation source 4 at the switching timing of the signal of the frequency transition pattern that modulates the clock of the reference frequency. ruko It is characterized by the above.

[0012] According to claim 4 of the present invention executed by the signal generation device The signal generation method includes a clock source 2 that generates a clock of a reference frequency, a jitter modulation source 3 that generates a jitter clock obtained by modulating the clock of the reference frequency generated by the clock source, and a frequency transition pattern signal defined by a desired standard for input to the object under measurement W is generated at the timing of the jitter clock by a signal generation source 4. A signal generation method executed by a signal generation device 1 provided with: The clock source, the jitter modulation source, the signal generation source For the FPGAs 2a, 3a, and 4a included in each, a step of loading circuit data when measuring the object under measurement, A step of controlling, by the device control unit 8, the switching timing of the signal of the frequency transition pattern that modulates the clock of the reference frequency, The type of the signal of the frequency transition pattern, the start time of modulating the clock of the reference frequency, and the frequency offset amount when modulating the clock of the reference frequency by the operation unit 5 of the signal generation device Setting step, A step of notifying the switching timing of the signal of the frequency transition pattern that modulates the clock of the reference frequency from the signal generation source to the jitter modulation source, When the jitter modulation source receives the notification from the signal generation source, a step of outputting, from the jitter modulation source to the signal generation source, a jitter clock obtained by modulating the clock of the reference frequency by the frequency offset amount. It is characterized by including.

[0013] According to claim 5 of the present invention executed by the signal generation device The signal generation method is as described in claim 4 executed by the signal generation device In the signal generation method, In the signal generation device 1, there is a detachable moduleThe clock source 2, the jitter modulation source 3, and the signal generation source 4 is installed with respect to a plurality of slots 1c provided in the device body 1a each is mounted is characterized in that.

[0014] According to claim 6 of the present invention executed by the signal generation device The signal generation method is that of claim 5 executed by the signal generation device In the signal generation method, The signal generation device 1, The selector unit 7 for connecting between the modules further has The device control unit 8 controls the selector unit so as to connect between the module of the jitter modulation source 3 and the module of the signal generation source 4 at the timing of switching of the signal of the frequency transition pattern that modulates the clock of the reference frequency pu is characterized by including.

Effect of the Invention

[0015] According to the present invention, the timing of starting the modulation of SSC can be defined in a shorter time (on the order of μs) than before.

Brief Description of the Drawings

[0016]

Figure 1

Figure 2

Figure 3

Figure 4

Embodiments for Carrying Out the Invention

[0017] Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings.

[0018] As shown in FIG. 1, the signal generator 1 of the present embodiment is schematically configured to include a clock source 2, a jitter modulation source 3, a signal generation source 4, an operation unit 5, a display unit 6, a selector unit 7, and a device control unit 8. Using SSC (spread spectrum clocking), it has a function of generating a signal with a frequency transition pattern defined by a desired standard, such as the one shown in FIG. 4, as a signal to be input to the object under measurement W before measuring the error rate.

[0019] Note that the object under measurement W incorporates an error detection unit W1 that detects the presence or absence of an error in the signal input from the signal generation source 4 of the signal generator 1.

[0020] As shown in FIG. 2, the signal generator 1 has a device main body 1a formed of a rectangular housing, and an opening 1b is formed in a side surface portion of the device main body 1a. A plurality of slots (eight slots in the example of FIG. 2) 1c are provided in the opening 1b of the device main body 1a.

[0021] The clock source 2, the jitter modulation source 3, and the signal generation source 4 are configured as modules that can be selectively attached to and detached from the slots 1c of the device main body 1a. The example of FIG. 2 shows a state where modules are mounted in all the slots 1c of the device main body 1a. In actuality, by selectively mounting the modules of the clock source 2, the jitter modulation source 3, and the signal generation source 4 (three modules) in the slots 1c of the device main body 1a, it functions as the signal generator 1. In the slots 1c of the device main body 1a, necessary modules for generating a signal with a frequency transition pattern defined by a desired standard are appropriately combined and selected for mounting, and it is possible to add, remove, and recombine the modules.

[0022] Note that by mounting a module of an error detector in the slot 1c of the device main body 1a, it can also function as an error rate measuring device that receives the signal folded back when a test signal is input to the object under measurement W and measures the error rate.

[0023] The clock source 2 generates a reference clock (clock with a reference frequency) under the control of the device control unit 8 connected to Ethernet (registered trademark), and is composed of the FPGA 2a and the clock generation unit 2b.

[0024] The FPGA 2a includes a module control unit 2aa and a control circuit 2ab. The module control unit 2aa also serves as an interface connecting the device control unit 8 and the control circuit 2ab. In addition to outputting instructions (commands) from the device control unit 8 to the control circuit 2ab, it executes some processing and control within the clock source 2.

[0025] The control circuit 2ab controls the clock generation unit 2b to generate a clock with a reference frequency according to an instruction (command) from the device control unit 8.

[0026] The clock generation unit 2b generates a clock with a reference frequency under the control of the control circuit 2ab based on an instruction (command) from the device control unit 8.

[0027] The jitter modulation source 3 generates a jitter clock with a desired modulation applied to the clock with a reference frequency generated by the clock source 2 under the control of the device control unit 8 connected to Ethernet (registered trademark), and is composed of the FPGA 3a and the jitter modulation unit 3b.

[0028] The FPGA 3a includes a module control unit 3aa and a control circuit 3ab. The module control unit 3aa also serves as an interface connecting the device control unit 8 and the control circuit 3ab. In addition to outputting instructions (commands) from the device control unit 8 to the control circuit 3ab, it executes some processing and control within the jitter modulation source 3.

[0029] The control circuit 3ab controls the jitter modulation unit 3b to generate a jitter clock with a desired modulation applied to the clock with a reference frequency generated by the clock source 2 according to an instruction (command) from the device control unit 8.

[0030] The jitter modulation unit 3b generates a jitter clock obtained by applying a desired modulation to the clock of the reference frequency generated by the clock source 2 under the control of the control circuit 3ab based on an instruction (command) from the device control unit 8.

[0031] The signal generation source 4 generates a signal of a frequency transition pattern defined by a desired standard (a pulse pattern signal with a desired repetition pattern) for input to the object under measurement W under the control of the device control unit 8 connected to Ethernet (registered trademark), using the jitter clock generated by the jitter modulation source 3, and is composed of an FPGA 4a and a data multiplexing unit 4b.

[0032] The FPGA 4a includes a module control unit 4aa and a control circuit 4ab. The module control unit 4aa also serves as an interface connecting between the device control unit 8 and the control circuit 4ab, outputs an instruction (command) from the device control unit 8 to the control circuit 4ab, and executes a part of the processing and control within the signal generation source 4.

[0033] The control circuit 4ab outputs a parallel signal that serves as the basis for a desired signal (for example, a signal of a frequency transition pattern defined by a desired standard as shown in FIG. 4: a serial signal) to the data multiplexing unit 4b according to an instruction (command) from the device control unit 8.

[0034] The data multiplexing unit 4b multiplexes the parallel signal input from the control circuit 4ab according to the timing of the jitter clock generated by the jitter modulation source 3 to generate a desired serial signal (for example, a signal of a frequency transition pattern defined by a desired standard as shown in FIG. 4: "PRBS11 (without SSC)" → "PRTS7 (without SSC)" → "PRTS19 (without SSC)" → "PRTS19 (with SSC)").

[0035] The signal source 4 notifies the jitter modulation source 3 of the timing of switching of the pattern for starting SSC through the path R (the path indicated by the thick arrow in FIG. 1) that connects from the signal source 4 to the jitter modulation source 3 via the selector unit 7, that is, the timing of switching of the signal of the frequency transition pattern for modulating the clock of the reference frequency generated by the clock source 2.

[0036] The operation unit 5 is composed of, for example, various keys, switches, buttons equipped on the main body of the signal generator 1, soft keys on the display screen of the display unit 6, etc., and the user inputs various information necessary for the signal generator 1 to generate a desired signal by operation.

[0037] The display unit 6 is composed of a display device such as a liquid crystal display, an EL (electroluminescence: electroluminescence) display, a CRT, etc., and under the control of the device control unit 8, it displays a setting item screen related to the generation of a desired signal, buttons, soft keys, pull-down menus, input boxes, etc. for setting various conditions on the setting item screen for operation target display.

[0038] Here, FIG. 3 shows an example of the setting screen 11 of the signal source 4. At the upper part of the setting screen 11 of the signal source 4 in FIG. 3, an item “Test Pattern” for setting the type of the signal of the pattern (frequency transition pattern) is displayed. In this “Test Pattern”, the type of the signal of the pattern is selected and set from the pull-down menus 12 and 13. The setting screen 11 of the signal source 4 in FIG. 3 shows a state where “All List” is selected from the pull-down menu 12 of “Test Pattern” and “USB4 Clock Switch” is selected from the pull-down menu 13.

[0039] In the center of the setting screen 11 of the signal source 4 in FIG. 3, the block order 14 of the signals of the frequency transition pattern defined by the desired standard is displayed. In the block order 14 of the signals of this frequency transition pattern, by inputting a desired numerical value into the input box 15, the time from when the block of the signal of the frequency transition pattern is switched until SSC starts (the start time of applying modulation to the clock of the reference frequency generated by the clock source 2) is set. The setting screen 11 of the signal source 4 in FIG. 3 shows a state where "300" is input into the input box 15 and the time from when the block of the signal of the frequency transition pattern is switched to block #3 until SSC starts is set to "300" μs.

[0040] At the lower part of the setting screen 11 of the signal source 4 in FIG. 3, a pattern setting list 16 for each block of the signals of the frequency transition pattern defined by the standard is displayed. In this pattern setting list 16 for each block, the order of the patterns to be generated is indicated by Block No. (block number), and the pattern for each block of Block No. is selected and set from the pull-down menus 17 (17a, 17b, 17c). The setting screen 11 of the signal source 4 in FIG. 3 shows a state where "PRBS11" is selected and set from the pull-down menu 17a as the pattern for block #1, "PRTS7" is selected and set from the pull-down menu 17b as the pattern for block #2, and "PRTS19" is selected and set from the pull-down menu 17c as the patterns for blocks #3 and #4.

[0041] Note that in the pull-down menus 17 (17a, 17b, 17c), in addition to a predetermined number of stages of PRBS and PRTS according to the desired standard, patterns selected from the pseudo-random patterns arbitrarily set and registered by the user in advance can be set.

[0042] The selector unit 7 has the input / output wiring connected in pairs to all the modules of the clock source 2, the jitter modulation source 3, and the signal source 4. The selector unit 7 includes a multiplexer for selecting an output and a demultiplexer for selecting an input under the control of the device control unit 8.

[0043] In this embodiment, the device control unit 8 controls the selector unit 7 such that the multiplexer of the selector unit 7 selects the signal source 4 and the demultiplexer of the selector unit 7 selects the jitter modulation source 3. Thereby, only the path (the path indicated by the thick arrow in FIG. 1) R that connects from the signal source 4 to the jitter modulation source 3 via the selector unit 7 is connected, and the path R is activated.

[0044] Note that the control of the selector unit 7 is automatically performed by the device control unit 8 according to the modules (such as the clock source 2, the jitter modulation source 3, and the signal source 4) to which the device control unit 8 is connected, or is performed by the device control unit 8 according to the user's settings.

[0045] Also, in this embodiment, a plurality of modules including the clock source 2, the jitter modulation source 3, and the signal source 4 are configured to be freely connectable to a plurality of slots 1c. For this reason, although the device control unit 8 controls the selector unit 7 and only the path (the path indicated by the thick arrow in FIG. 1) R that connects from the signal source 4 to the jitter modulation source 3 via the selector unit 7 is connected and the path R is activated, it is not limited thereto. For example, when the slots 1c to which the modules of the clock source 2, the jitter modulation source 3, and the signal source 4 are connected are fixed, or when the configuration includes only the modules of the clock source 2, the jitter modulation source 3, and the signal source 4, it is also possible to connect between the signal source 4 and the jitter modulation source 3 with a dedicated path R and delete the selector unit 7.

[0046] The device control unit 8 comprehensively controls each of the clock source 2, jitter modulation source 3, signal generation source 4, operation unit 5, display unit 6, and selector unit 7. That is, the device control unit 8 controls the display unit 6 to display various setting screens including the setting screen of the signal generation source 4 shown in FIG. 3, generates a clock of a reference frequency, generates a jitter clock, and generates a desired signal (for example, a signal having a frequency transition pattern defined by a desired standard as shown in FIG. 4) based on the operation input of the operation unit 5. It controls the clock source 2, jitter modulation source 3, and signal generation source 4, and controls the selector unit 7 to connect and activate only the path R connecting from the signal generation source 4 to the jitter modulation source 3, and so on.

[0047] Next, the operation of the signal generation device 1 configured as described above will be described. Here, the operation in the case of generating a signal having a frequency transition pattern defined by USB4 v2 Gen4 shown in FIG. 4 (「PRBS11 (without SSC)」→「PRTS7 (without SSC)」→「PRTS19 (without SSC)」→「PRTS19 (with SSC)」) will be described as an example.

[0048] First, various settings necessary for generating the signal of the frequency transition pattern in FIG. 4 are performed. Specifically, in the setting screen 11 of the signal generation source 4 in FIG. 3, select 「All List」 from the pull-down menu 12 of 「Test Pattern」 and select 「USB4 Clock Switch」 from the pull-down menu 13.

[0049] Then, in the setting screen 11 of the signal generation source 4 in FIG. 3, select and set 「PRBS11」 as the pattern of block #1 from the pull-down menu 17a, select and set 「PRTS7」 as the pattern of block #2 from the pull-down menu 17b, select and set 「PRTS19」 as the patterns of blocks #3 and #4 from the pull-down menu 17c, and set the type of the pattern signal.

[0050] Also, on the setting screen 11 of the signal generation source 4 in FIG. 3, as the time until the start of SSC (the start time for applying modulation to the clock of the reference frequency generated by the clock source 2: less than 500 μs), enter "300" in the input box 15 and set it.

[0051] Also, on the setting screen (not shown) of the jitter modulation source 3, by operating the operation unit 5, enter and set the frequency offset: "-3400" in FIG. 4 as a numerical value. In addition, perform on / off settings for pre-coding, on / off settings for polarity inversion, etc. as necessary.

[0052] After finishing the above settings, start the generation and switching of the signals of the frequency transition pattern in FIG. 4 by operating the "Manual": manual transmission button 18 and the "Transmit": automatic transmission button 19 on the setting screen 11 of the signal generation source 4 in FIG. 3. Specifically, as the signals of the frequency transition pattern in FIG. 4, by operating the "Manual": manual transmission button 18, manually generate the patterns in the order of the pattern "PRBS11 (without SSC)" of block #1 and the pattern "PRTS7 (without SSC)" of block #2. Then, by operating the "Transmit": automatic transmission button 19, automatically generate the patterns in the order of the pattern "PRTS19 (without SSC)" of block #3 and the pattern "PRTS19 (with SSC)" of block #4.

[0053] And when generating the signals of the frequency transition pattern in FIG. 4 described above, at the timing of switching of the signals of the frequency transition pattern to which modulation is applied to the clock of the reference frequency, that is, when switching from the pattern "PRTS19 (without SSC)" of block #3 to the pattern "PRTS19 (with SSC)" of block #4, the device control unit 8 controls the selector unit 7 so as to connect only the path R connecting from the signal generation source 4 to the jitter modulation source 3 via the selector unit 7, and the signal generation source 4 notifies the timing of switching to the pattern for starting SSC to the jitter modulation source 3.

[0054] Then, when the jitter modulation source 3 receives a notification of the timing of switching of the pattern for starting SSC from the signal generation source 4, the jitter modulation unit 3b outputs, under the control of the FPGA 3a, a jitter clock modulated with a frequency offset of -3400 PPM with respect to the clock to the data multiplexing unit 4b of the signal generation source 4. As a result, when 300 μs has elapsed since the timing at which the data multiplexing unit 4b of the signal generation source 4 switched to the pattern "PRTS19 (without SSC)" of block #3, the data multiplexing unit 4b of the signal generation source 4 starts generating the pattern "PRTS19 (with SSC)" of block #4 at the timing of the jitter clock modulated with a frequency offset of -3400 PPM with respect to the clock from the jitter modulation unit 3b.

[0055] Incidentally, in the above-described embodiment, when the object under measurement W does not incorporate the error detection unit W1, it may be configured to separately provide an error detector as a module detachable from the slot 1c of the apparatus main body 1a. In this case, the signal generation device 1 functions as an error rate measurement device that inputs a test signal from the signal generation source 4 to the object under measurement W, receives the signal reflected from the object under measurement W in association with the input of this test signal, and the error detector detects the presence or absence of an error and measures the error rate.

[0056] In the above-described embodiment, when generating the signal of the frequency transition pattern in FIG. 4, the settings of the pattern "PRBS11 (without SSC)" in block #1 and the pattern "PRTS7 (without SSC)" in block #2 are set to "Manual", and the "Manual" on the setting screen 11 of the signal source 4 in FIG. 3: By operating the manual start button 18, the generation and switching of the pattern "PRBS11 (without SSC)" in block #1 and the pattern "PRTS7 (without SSC)" in block #2 are manually performed, but it is not limited thereto. For example, on the setting screen 11 of the signal source 4 in FIG. 3, input boxes (input boxes of the same format as the input box 15 of block #3) for inputting and setting the generation time of the pattern are provided corresponding to block #1 and block #2 in the block order 14 of the signal of the frequency transition pattern, respectively. By operating the "Transmit": automatic start button 19, the device control unit 8 may automatically perform the generation and switching of the pattern based on the generation time input and set in each input box.

[0057] Thus, according to this embodiment, since the delay due to the additional path R is several tens to several hundreds of nanoseconds even including the selector unit 7, it is possible to output data and a frequency transition pattern defined by a desired standard while satisfying a regulation on the order of several microseconds as shown in FIG. 4. Thereby, the timing of starting the modulation of SSC can be defined in a shorter time (on the order of microseconds) than before, and a manufacturer of a product using a USB standard or the like, which is a user, can obtain a test input signal to a device with one product. In addition, it is expected that it can be used without the user being conscious of the internal operation by the provided GUI, leading to an improvement in user convenience.

[0058] As described above, the best mode of the signal generation device and executed by the signal generation device the signal generation method according to the present invention has been described, but the present invention is not limited by the description and drawings according to this mode. That is, of course, all other modes, examples, operation techniques, etc. made by those skilled in the art based on this mode are included in the scope of the present invention.

Description of Reference Numerals

[0059] 1 Signal generator 1a Apparatus main body 1b Opening 1c Slot 2 Clock source 2a FPGA 2aa Module control unit 2ab Control circuit 2b Clock generation unit 3 Jitter modulation source 3a FPGA 3aa Module control unit 3ab Control circuit 3b Jitter modulation unit 4 Signal generation source 4a FPGA 4aa Module control unit 4ab Control circuit 4b Data multiplexing unit 5 Operation unit 6 Display unit 7 Selector unit 8 Apparatus control unit 11 Setting screen 12, 13 Pull-down menu 14 Block sequence of frequency transition pattern 15 Input box 16 List of pattern settings for each block 17(17a, 17b, 17c) Pull-down menu 18 Manual transmission button 19 Automatic transmission button Path connecting from signal generation source 4 to jitter modulation source 3 via selector unit 7 W Object under test W1 Error detection unit

Claims

1. A signal generation device (1) comprising: a clock source (2) that generates a clock of a reference frequency; a jitter modulation source (3) that generates a jitter clock obtained by modulating the clock of the reference frequency generated by the clock source; a signal generation source (4) that generates a signal having a frequency transition pattern defined by a desired standard for input to a device under test (W) at the timing of the jitter clock; and an operation unit (5) that sets the type of the signal having the frequency transition pattern, the start time of modulation applied to the clock of the reference frequency, and the frequency offset amount when modulating the clock of the reference frequency. The signal generation device is characterized in that: it includes a device control unit (8) that controls the switching timing of the signal having the frequency transition pattern that is modulated with respect to the clock of the reference frequency; the signal generation source notifies the jitter modulation source of the switching timing of the signal having the frequency transition pattern that is modulated with respect to the clock of the reference frequency; when receiving the notification from the signal generation source, the jitter modulation source outputs a jitter clock obtained by modulating the clock of the reference frequency by the frequency offset amount to the signal generation source. A signal generation device characterized by the above.

2. The signal generation device according to claim 1, wherein the clock source (2), the jitter modulation source (3), and the signal generation source (4) are configured as modules that are selectively detachable from a plurality of slots (1c) provided in the device main body (1a).

3. A selector unit (7) for connecting between the modules is arranged; The signal generation device according to claim 2, wherein the device control unit (8) controls the selector unit so as to connect between the module of the jitter modulation source (3) and the module of the signal generation source (4) at the switching timing of the signal having the frequency transition pattern that is modulated with respect to the clock of the reference frequency.

4. A signal generation method executed by a signal generation device (1) comprising: a clock source (2) that generates a clock of a reference frequency; a jitter modulation source (3) that generates a jitter clock obtained by modulating the clock of the reference frequency generated by the clock source; and a signal generation source (4) that generates a signal having a frequency transition pattern defined by a desired standard for input to a device under test (W) at the timing of the jitter clock. For each of the FPGAs (2a, 3a, 4a) included in the clock source, the jitter modulation source, and the signal generation source, a step of loading circuit data when measuring the object to be measured; A step of controlling, by the device control unit (8), the switching timing of the signal of the frequency transition pattern that modulates the clock of the reference frequency; A step of setting, by the operation unit (5) of the signal generation device, the type of the signal of the frequency transition pattern, the start time of modulating the clock of the reference frequency, and the frequency offset amount when modulating the clock of the reference frequency; A step of notifying the jitter modulation source from the signal generation source of the switching timing of the signal of the frequency transition pattern that modulates the clock of the reference frequency; A signal generation method executed by a signal generation device, comprising: a step of outputting, from the jitter modulation source to the signal generation source, a jitter clock obtained by modulating the clock of the reference frequency by the frequency offset amount when the jitter modulation source receives the notification from the signal generation source.

5. In the signal generation device (1), the clock source (2), the jitter modulation source (3), and the signal generation source (4), which are detachable modules, are respectively mounted on a plurality of slots (1c) provided in the device body (1a). The signal generation method executed by the signal generation device according to claim 4, characterized in that.

6. The signal generation device (1) further includes a selector unit (7) for connecting between the modules; A signal generation method executed by the signal generation device according to claim 5, comprising a step of controlling the selector unit by the device control unit (8) so as to connect between the module of the jitter modulation source (3) and the module of the signal generation source (4) at the switching timing of the signal of the frequency transition pattern that modulates the clock of the reference frequency.

Images