Method and device for determining negative turn-off voltage of switching transistor, and switching transistor drive control circuit

Abstract

The present disclosure discloses a method, an apparatus, and a switching transistor drive control circuit for determining a turn-off negative voltage of a switching transistor, in which the turn-off negative voltage determination method includes a step (S11) of determining a first turn-off negative voltage model and a second turn-off negative voltage model, a step (S13) of inputting the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage into the first turn-off negative voltage model to obtain an upper limit absolute value of the turn-off negative voltage of the switching transistor, a step (S15) of inputting the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and maximum tolerable negative voltage absolute value into the second turn-off negative voltage model to obtain a lower limit absolute value of the turn-off negative voltage of the switching transistor, and a step (S17) of determining a turn-off negative voltage section of the switching transistor based on the upper limit absolute value of the turn-off negative voltage and the lower limit absolute value of the turn-off negative voltage.

Description

[Technical Field]

[0001] This disclosure claims priority to a Chinese patent application filed on April 6, 2022, bearing application number "202210360280.1" and entitled "Method and apparatus for determining the turn-off negative voltage of a switching transistor and a switching transistor drive control circuit," the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to the technical field of inverters, and more particularly to a method and apparatus for determining a negative turn-off voltage of a switching transistor and a switching transistor drive control circuit. [Background technology]

[0003] As people's living standards gradually improve, more and more vehicles are entering many homes, providing convenience for people's travel. In related technology, silicon carbide MOS transistors are used in high-input voltage vehicle compressor inverter systems to reduce losses and improve inverter efficiency, but silicon carbide MOS transistors have the problem of being prone to false turn-on. Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure aims to solve at least one of the technical problems existing in the related art to some extent, and therefore, a first object of the present disclosure is to propose a method for determining a negative turn-off voltage of a switching transistor, which can accurately determine a negative turn-off voltage interval of a switching transistor, thereby effectively preventing erroneous turn-on of the switching transistor when performing negative turn-off voltage control on the switching transistor using the negative turn-off voltage interval, thereby protecting the switching transistor and extending its service life.

[0005] A second object of the present disclosure is to propose an apparatus for determining a negative turn-off voltage of a switching transistor.

[0006] A third object of the present disclosure is to propose an inverter.

[0007] A fourth object of the present disclosure is to propose a computer-readable storage medium.

[0008] A fifth object of the present disclosure is to propose a switching transistor drive control circuit.

[0009] A sixth object of the present disclosure is to propose a motor control system.

[0010] A seventh object of the present disclosure is to propose a compressor.

[0011] An eighth object of the present disclosure is to propose a vehicle.

[0012] In order to achieve the above object, an embodiment of a first aspect of the present disclosure proposes a method for determining a negative turn-off voltage of a switching transistor, including the steps of determining a first turn-off negative voltage model and a second turn-off negative voltage model; obtaining a turn-off gate resistance and a turn-on gate resistance of a switching transistor, obtaining a bus voltage, and obtaining a minimum turn-on voltage and a tolerable maximum negative voltage absolute value of the switching transistor; inputting the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the minimum turn-on voltage into the first turn-off negative voltage model to obtain an upper limit absolute value of the negative turn-off voltage of the switching transistor, and inputting the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the tolerable maximum negative voltage absolute value into the second turn-off negative voltage model to obtain a lower limit absolute value of the negative turn-off voltage of the switching transistor; and determining a negative turn-off voltage range of the switching transistor based on the upper limit absolute value of the negative turn-off voltage and the lower limit absolute value of the negative turn-off voltage.

[0013] According to the method for determining the negative turn-off voltage of a switching transistor of an embodiment of the present disclosure, the first turn-off negative voltage model is input with the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor to obtain an upper limit absolute value of the negative turn-off voltage of the switching transistor, and the second turn-off negative voltage model is input with the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and absolute value of the maximum negative voltage that the switching transistor can withstand to obtain a lower limit absolute value of the negative turn-off voltage of the switching transistor, and the negative turn-off voltage interval of the switching transistor is accurately determined based on the upper limit absolute value of the negative turn-off voltage of the switching transistor. When negative voltage turn-off control is performed on the switching transistor using this negative turn-off voltage interval, erroneous turn-on of the switching transistor can be effectively prevented, and the switching transistor can be protected and its service life can be extended.

[0014] In some embodiments of the present disclosure, the first turn-off negative voltage model is V SS_min =λ1*f1(R G_on ,R G_off ,V DC )-V th where V SS_min is the absolute upper limit of the turn-off negative voltage, λ1 is the first derating parameter, and f1(R G_on ,R G_off ,V DC ) is a function corresponding to the first turn-off negative voltage model, and R G_on is the turn-on gate resistance, and R G_off is the turn-off gate resistance, and V DC is the bus voltage, and V th is the minimum turn-on voltage.

[0015] In some embodiments of the present disclosure, the second turn-off negative voltage model is V SS_max =VGS_max -λ2*f2(R G_on ,R G_off ,V DC ) where V SS_max is the absolute value of the lower limit of the turn-off negative voltage, λ2 is the second derating parameter, and f2(R G_on ,R G_off ,V DC ) is a function corresponding to the second turn-off negative voltage model, and R G_on is the turn-on gate resistance, and R G_off is the turn-off gate resistance, and V DC is the bus voltage, and V GS_max is the absolute value of the maximum negative voltage that can be tolerated.

[0016] In some embodiments of the present disclosure, the step of determining the negative turn-off voltage section of the switching transistor based on the absolute upper limit value of the negative turn-off voltage and the absolute lower limit value of the negative turn-off voltage includes the steps of setting a negative value of the absolute upper limit value of the negative turn-off voltage as a negative turn-off voltage upper limit voltage and a negative value of the absolute lower limit value of the negative turn-off voltage as a negative turn-off voltage lower limit voltage, and determining the negative turn-off voltage section from the negative turn-off voltage lower limit voltage and the negative turn-off voltage upper limit voltage.

[0017] In some embodiments of the present disclosure, the switching transistor is a silicon carbide MOS transistor.

[0018] In order to achieve the above object, an embodiment of a second aspect of the present disclosure proposes an apparatus for determining a turn-off negative voltage of a switching transistor, including: a first determination module for determining a first turn-off negative voltage model and a second turn-off negative voltage model; an acquisition module for acquiring a turn-off gate resistance and a turn-on gate resistance of a switching transistor, acquiring a bus voltage, and acquiring a minimum turn-on voltage and a tolerable maximum negative voltage absolute value of the switching transistor; and a second determination module for inputting the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the minimum turn-on voltage into the first turn-off negative voltage model to acquire an upper limit absolute value of the turn-off negative voltage of the switching transistor, inputting the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the tolerable maximum negative voltage absolute value into the second turn-off negative voltage model to acquire a lower limit absolute value of the turn-off negative voltage of the switching transistor, and determining a turn-off negative voltage range of the switching transistor based on the upper limit absolute value of the turn-off negative voltage and the lower limit absolute value of the turn-off negative voltage.

[0019] According to the device for determining a negative turn-off voltage of a switching transistor of an embodiment of the present disclosure, the first turn-off negative voltage model is input with the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor to obtain an upper limit absolute value of the negative turn-off voltage of the switching transistor, and the second turn-off negative voltage model is input with the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and absolute value of the maximum negative voltage that the switching transistor can withstand to obtain a lower limit absolute value of the negative turn-off voltage of the switching transistor, and the negative turn-off voltage range of the switching transistor is accurately determined based on the upper limit absolute value of the negative turn-off voltage of the switching transistor, so that when negative voltage turn-off control is performed on the switching transistor using this negative turn-off voltage range, erroneous turn-on of the switching transistor can be effectively prevented, and the switching transistor can be protected and its service life can be extended.

[0020] In order to achieve the above object, an embodiment of a third aspect of the present disclosure proposes an inverter including a memory, a processor, and a switching transistor turn-off negative voltage determination program stored in the memory and executable by the processor, wherein when the processor executes the switching transistor turn-off negative voltage determination program, the switching transistor turn-off negative voltage determination method described in any one of the above embodiments is realized.

[0021] According to the inverter of the embodiment of the present disclosure, the first turn-off negative voltage model is input with the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor to obtain the absolute value of the upper limit of the negative turn-off voltage of the switching transistor, and the second turn-off negative voltage model is input with the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and absolute value of the maximum negative voltage that the switching transistor can withstand to obtain the absolute value of the lower limit of the negative turn-off voltage of the switching transistor. Furthermore, the negative turn-off voltage range of the switching transistor is accurately determined based on the absolute value of the upper limit of the negative turn-off voltage of the switching transistor, so that when the negative voltage turn-off control is performed on the switching transistor using this negative turn-off voltage range, erroneous turn-on of the switching transistor can be effectively prevented, and the switching transistor can be protected and its service life can be extended.

[0022] To achieve the above object, an embodiment of a fourth aspect of the present disclosure proposes a computer-readable storage medium that stores a method for determining a negative turn-off voltage of a switching transistor, and that, when executed by a processor, realizes the method for determining a negative turn-off voltage of a switching transistor described in any one of the above embodiments.

[0023] According to the computer-readable storage medium of the embodiment of the present disclosure, the first turn-off negative voltage model is input with the obtained turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor to obtain an upper limit absolute value of the negative turn-off voltage of the switching transistor; the second turn-off negative voltage model is input with the obtained turn-off gate resistance, turn-on gate resistance, bus voltage, and absolute value of the maximum negative voltage that the switching transistor can withstand to obtain a lower limit absolute value of the negative turn-off voltage of the switching transistor; and the negative turn-off voltage interval of the switching transistor is accurately determined based on the upper limit absolute value of the negative turn-off voltage of the switching transistor. When the negative turn-off voltage interval is used to perform negative voltage turn-off control on the switching transistor, erroneous turn-on of the switching transistor can be effectively prevented, and the service life of the switching transistor can be extended.

[0024] To achieve the above object, an embodiment of a fifth aspect of the present disclosure proposes a switching transistor drive control circuit including a drive power supply, a drive unit, and a control unit, wherein the control unit executes the method for determining a negative turn-off voltage of a switching transistor described in any one of the above embodiments to obtain a negative turn-off voltage section of the switching transistor, and controls the drive power supply according to the negative turn-off voltage section to supply a negative turn-off voltage to the drive unit, and the drive unit is used to turn off the switching transistor according to the negative turn-off voltage when it receives a turn-off control signal.

[0025] According to the switching transistor drive control circuit of the embodiment of the present disclosure, the turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor obtained are input to a first turn-off negative voltage model to obtain an upper limit absolute value of the negative turn-off voltage of the switching transistor, and the turn-off gate resistance, turn-on gate resistance, bus voltage, and absolute value of the maximum negative voltage that the switching transistor can withstand are input to a second turn-off negative voltage model to obtain a lower limit absolute value of the negative turn-off voltage of the switching transistor. Furthermore, the turn-off negative voltage interval of the switching transistor is accurately determined based on the upper limit absolute value of the negative turn-off voltage of the switching transistor, so that when negative voltage turn-off control is performed on the switching transistor using this turn-off negative voltage interval, erroneous turn-on of the switching transistor can be effectively prevented, and the switching transistor can be protected and its service life can be extended.

[0026] In some embodiments of the present disclosure, the driving unit includes: a driving chip, a positive power supply pin of the driving chip connected to the positive turn-on voltage supply terminal of the driving power supply, a negative power supply pin of the driving chip connected to the negative turn-off voltage supply terminal of the driving power supply, an input pin of the driving chip connected to the control unit, and a first gate resistor, one end of which is connected to the output pin of the driving chip and the other end of which is connected to the gate of the switching transistor.

[0027] In some embodiments of the present disclosure, the driving unit further includes a first diode having a cathode connected to one end of the first gate resistor, and a second gate resistor having one end connected to the anode of the first diode and the other end connected to the other end of the first gate resistor.

[0028] In some embodiments of the present disclosure, the driving unit further includes a second diode having a cathode connected to one end of the first gate resistor and an anode connected to the cathode of the first diode.

[0029] In some embodiments of the present disclosure, the driving unit further includes a first diode having a cathode connected to one end of the first gate resistor and an anode connected to the other end of the first gate resistor, and a second gate resistor having one end connected to the anode of the first diode and the other end connected to the gate of the switching transistor.

[0030] In some embodiments of the present disclosure, the driving unit further includes a first coupling capacitance having one end connected to the positive turn-on voltage supply terminal of the driving power supply, and a second coupling capacitance having one end connected to the other end of the first coupling capacitance and the other end connected to the negative turn-off voltage supply terminal of the driving power supply.

[0031] In some embodiments of the present disclosure, when the switching transistor is an upper arm switching transistor, the node between the first coupling capacitance and the second coupling capacitance is connected to the midpoint of the leg in which the upper arm switching transistor is located, and when the switching transistor is a lower arm switching transistor, the node between the first coupling capacitance and the second coupling capacitance is grounded.

[0032] To achieve the above object, an embodiment of a sixth aspect of the present disclosure proposes a motor control system including the switching transistor drive control circuit according to any one of the above embodiments.

[0033] According to the motor control system of the embodiment of the present disclosure, the first turn-off negative voltage model is input with the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor to obtain the absolute value of the upper limit of the negative turn-off voltage of the switching transistor, and the second turn-off negative voltage model is input with the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and absolute value of the maximum negative voltage that the switching transistor can withstand to obtain the absolute value of the lower limit of the negative turn-off voltage of the switching transistor. Furthermore, the negative turn-off voltage range of the switching transistor is accurately determined based on the absolute value of the upper limit of the negative turn-off voltage of the switching transistor, and when negative voltage turn-off control is performed on the switching transistor using this negative turn-off voltage range, it is possible to effectively prevent erroneous turn-on of the switching transistor, protect the switching transistor, and extend its service life.

[0034] To achieve the above object, an embodiment of the seventh aspect of the present disclosure proposes a compressor including the motor control system according to the above embodiment.

[0035] According to the compressor of the embodiment of the present disclosure, the first turn-off negative voltage model is input with the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor to obtain the absolute value of the upper limit of the negative turn-off voltage of the switching transistor, and the second turn-off negative voltage model is input with the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and absolute value of the maximum negative voltage that the switching transistor can withstand to obtain the absolute value of the lower limit of the negative turn-off voltage of the switching transistor. Furthermore, the negative turn-off voltage range of the switching transistor is accurately determined based on the absolute value of the upper limit of the negative turn-off voltage of the switching transistor. When the negative turn-off voltage range is used to perform negative voltage turn-off control on the switching transistor, erroneous turn-on of the switching transistor can be effectively prevented, and the switching transistor can be protected and its service life can be extended.

[0036] To achieve the above object, an embodiment of an eighth aspect of the present disclosure proposes a vehicle including the compressor according to the above embodiment.

[0037] According to the vehicle of the embodiment of the present disclosure, the turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor obtained are input to the first turn-off negative voltage model to obtain the absolute value of the upper limit of the negative turn-off voltage of the switching transistor, and the turn-off gate resistance, turn-on gate resistance, bus voltage, and the absolute value of the maximum negative voltage that the switching transistor can withstand are input to the second turn-off negative voltage model to obtain the absolute value of the lower limit of the negative turn-off voltage of the switching transistor. Furthermore, the turn-off negative voltage range of the switching transistor is accurately determined based on the absolute value of the upper limit of the negative turn-off voltage of the switching transistor, so that when negative voltage turn-off control is performed on the switching transistor using this turn-off negative voltage range, erroneous turn-on of the switching transistor can be effectively prevented, and the switching transistor can be protected and its service life can be extended.

[0038] Additional aspects and advantages of the present disclosure will be set forth in part in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. [Brief explanation of the drawings]

[0039] The above and / or additional aspects and advantages of the present application will become apparent and easier to understand from the following description of the embodiments in conjunction with the accompanying drawings. [Figure 1] FIG. 1 is a schematic flow diagram of a method for determining a negative turn-off voltage of a switching transistor according to one embodiment of the present disclosure. [Figure 2] FIG. 2 is a schematic diagram of a scene of a method for determining a negative turn-off voltage of a switching transistor according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is a schematic diagram of a scene of a method for determining a negative turn-off voltage of a switching transistor according to another embodiment of the present disclosure. [Figure 4]FIG. 4 is a schematic flow diagram of a method for determining a negative turn-off voltage of a switching transistor according to another embodiment of the present disclosure. [Figure 5] FIG. 5 is a block diagram showing a configuration of a device for determining a negative turn-off voltage of a switching transistor according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is a block diagram illustrating the structure of an inverter according to one embodiment of the present disclosure. [Figure 7] FIG. 7 is a block diagram showing a configuration of a switching transistor drive control circuit according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a circuit schematic diagram of a switching transistor drive control circuit according to one embodiment of the present disclosure. [Figure 9] FIG. 9 is a circuit schematic diagram of a switching transistor drive control circuit according to another embodiment of the present disclosure. [Figure 10] FIG. 10 is a circuit schematic diagram of a switching transistor drive control circuit according to another embodiment of the present disclosure. [Figure 11] FIG. 11 is a circuit schematic diagram of a switching transistor drive control circuit according to another embodiment of the present disclosure. [Figure 12] FIG. 12 is a block diagram illustrating the structure of a motor control system according to one embodiment of the present disclosure. [Figure 13] FIG. 13 is a block diagram illustrating the structure of a compressor according to one embodiment of the present disclosure. [Figure 14] FIG. 14 is a block diagram illustrating the structure of a vehicle according to one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0040]

[0033] The following detailed description will be given of the embodiments of the present disclosure shown in the accompanying drawings, in which the same or similar reference numerals throughout indicate the same or similar elements, or elements having the same or similar functions. The embodiments described below with reference to the drawings are exemplary intended to explain the present disclosure, and are not to be construed as limiting the present disclosure.

[0041] In order to clearly describe the method, device, and switching transistor drive control circuit for determining a negative turn-off voltage of a switching transistor according to the embodiments of the present disclosure, the following description will be given with reference to the schematic flow chart of the method for determining a negative turn-off voltage of a switching transistor shown in Fig. 1. As shown in Fig. 1, the method for determining a negative turn-off voltage of a switching transistor according to the embodiments of the present disclosure includes the following steps:

[0042] Step S11 is a step of determining a first turn-off negative voltage model and a second turn-off negative voltage model.

[0043] Step S13 is a step of obtaining the turn-off gate resistance and turn-on gate resistance of the switching transistor, obtaining the bus voltage, and obtaining the minimum turn-on voltage and the absolute value of the maximum negative voltage that can be tolerated of the switching transistor.

[0044] Step S15 is a step of inputting the turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage into the first turn-off negative voltage model to obtain the absolute value of the upper limit of the turn-off negative voltage of the switching transistor, and inputting the turn-off gate resistance, turn-on gate resistance, bus voltage, and the absolute value of the maximum tolerable negative voltage into the second turn-off negative voltage model to obtain the absolute value of the lower limit of the turn-off negative voltage of the switching transistor.

[0045] Step S17 is a step of determining the turn-off negative voltage section of the switching transistor based on the turn-off negative voltage upper limit absolute value and the turn-off negative voltage lower limit absolute value.

[0046] According to the method for determining the negative turn-off voltage of a switching transistor of an embodiment of the present disclosure, the first turn-off negative voltage model is input with the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor to obtain an upper limit absolute value of the negative turn-off voltage of the switching transistor, and the second turn-off negative voltage model is input with the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and absolute value of the maximum negative voltage that the switching transistor can withstand to obtain a lower limit absolute value of the negative turn-off voltage of the switching transistor, and the negative turn-off voltage interval of the switching transistor is accurately determined based on the upper limit absolute value of the negative turn-off voltage of the switching transistor. When negative voltage turn-off control is performed on the switching transistor using this negative turn-off voltage interval, erroneous turn-on of the switching transistor can be effectively prevented, and the switching transistor can be protected and its service life can be extended.

[0047] Although applying a negative turn-off voltage to the gate can be used to prevent erroneous turn-on of the switching transistor, if the absolute value of the upper limit of the negative turn-off voltage is set too small, the switching transistor may still erroneously turn on in some cases. If the absolute value of the lower limit of the negative turn-off voltage is set too large, a negative voltage spike will exceed the absolute value of the lower limit of the negative driving voltage that the switching transistor can tolerate, which may shorten the life of the switching transistor or even cause damage to the switch. Therefore, it is necessary to accurately determine the negative turn-off voltage range of the switching transistor.

[0048] Specifically, the first turn-off negative voltage model can be used to determine the absolute value of the upper limit of the turn-off negative voltage of the switching transistor, and the representation format of the first turn-off negative voltage model includes, but is not limited to, a neural network model, a data mapping diagram / table, a mathematical relational expression, etc. When the first turn-off negative voltage model is a neural network model, the input of the neural network model can include the turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor, and the output of the neural network model can include the absolute value of the upper limit of the turn-off negative voltage of the switching transistor. Thus, after obtaining the turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor, the turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage can be input into the neural network model to quickly obtain a corresponding, more accurate, absolute value of the upper limit of the turn-off negative voltage of the switching transistor. If the first turn-off negative voltage model is a data mapping chart / table, the data mapping chart / table may include absolute values ​​of the turn-off negative voltage upper limit of the switching transistor corresponding to the predetermined turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of different switching transistors. Thus, after obtaining the turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor, the corresponding more accurate absolute values ​​of the turn-off negative voltage upper limit of the switching transistor can be quickly obtained by consulting the data mapping chart / table.If the first turn-off negative voltage model is a mathematical relational expression, this mathematical relational expression can represent the relationship between the turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor and the absolute value of the upper limit of the turn-off negative voltage of the switching transistor. Therefore, after obtaining the turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor, the absolute value of the upper limit of the turn-off negative voltage of the corresponding switching transistor can be obtained from this mathematical relational expression.

[0049] The second turn-off negative voltage model can be used to determine the absolute value of the turn-off negative voltage lower limit of the switching transistor, and the representation format of the second turn-off negative voltage model includes, but is not limited to, a neural network model, a data mapping diagram / table, a mathematical relational expression, etc. When the second turn-off negative voltage model is a neural network model, the input of the neural network model can include the turn-off gate resistance, turn-on gate resistance, bus voltage, and absolute value of the maximum tolerable negative voltage of the switching transistor, and the output of the neural network model can include the absolute value of the turn-off negative voltage lower limit of the switching transistor. Thus, after obtaining the turn-off gate resistance, turn-on gate resistance, bus voltage, and absolute value of the maximum tolerable negative voltage of the switching transistor, the turn-off gate resistance, turn-on gate resistance, bus voltage, and absolute value of the maximum tolerable negative voltage can be input into the neural network model, thereby quickly obtaining a corresponding, more accurate absolute value of the turn-off negative voltage lower limit of the switching transistor. If the second turn-off negative voltage model is a data mapping chart / table, the data mapping chart / table may include absolute values ​​of the turn-off negative voltage lower limits of the switching transistors corresponding to the predetermined turn-off gate resistances, turn-on gate resistances, bus voltages, and absolute values ​​of the maximum negative voltages that can be tolerated of different switching transistors. In this way, after obtaining the turn-off gate resistances, turn-on gate resistances, bus voltages, and absolute values ​​of the maximum negative voltages that can be tolerated of the switching transistors, the corresponding, more accurate absolute values ​​of the turn-off negative voltage lower limits of the switching transistors can be quickly obtained by consulting the data mapping chart / table.If the second turn-off negative voltage model is a mathematical relational expression, this mathematical relational expression can represent the relationship between the turn-off gate resistance, turn-on gate resistance, bus voltage, and absolute value of the maximum negative voltage that can be tolerated of the switching transistor and the lower limit absolute value of the turn-off negative voltage of the switching transistor. Therefore, after obtaining the turn-off gate resistance, turn-on gate resistance, bus voltage, and absolute value of the maximum negative voltage that can be tolerated of the switching transistor, the lower limit absolute value of the turn-off negative voltage of the corresponding switching transistor can be obtained from this mathematical relational expression.

[0050] In some embodiments, the corresponding first turn-off negative voltage model and second turn-off negative voltage model may be determined according to the model number of the switching transistor. The expression formats of the first turn-off negative voltage models of switching transistors of different model numbers may be the same or different, and the expression formats of the second turn-off negative voltage models of switching transistors of different model numbers may be the same or different, but are not limited thereto. In some embodiments, the first turn-off negative voltage model and the second turn-off negative voltage model of switching transistors of the same model number are expressed in the same format.

[0051] It can be understood that the turn-off negative voltage is a negative number, and the turn-off negative voltage section is a section that takes on the value of the turn-off negative voltage, that is, all the numbers in the turn-off negative voltage section are negative numbers.

[0052] In some embodiments of the present disclosure, the first turn-off negative voltage model is expressed by the following equation (1):

[0053] (Number 1) V SS_min =λ1*f1(R G_on ,R G_off ,V DC )-V th ···(1)

[0054] where V SS_minis the absolute upper limit of the turn-off negative voltage, λ1 is the first derating parameter, and f1(R G_on ,R G_off ,V DC ) is the function corresponding to the first turn-off negative voltage model, and R G_on is the turn-on gate resistance and R G_off is the turn-off gate resistance and V DC is the bus voltage, and V th is the minimum turn-on voltage.

[0055] In this way, the relationship between the turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor and the absolute value of the upper limit of the turn-off negative voltage of the switching transistor can be clearly expressed by the above formula (1).

[0056] Specifically, the turn-off gate resistance can be understood to be the total resistance of the turn-off circuit when the switching transistor is turned off, and the turn-on gate resistance can be understood to be the total resistance of the turn-on circuit when the switching transistor is turned on. In some embodiments, the minimum turn-on voltage can be obtained by querying corresponding data based on a specific model number of the switching transistor. In some embodiments, the first derating parameter can be obtained by querying corresponding derating standards based on a specific model number of the resistor. In some embodiments, the bus voltage can be obtained via a bus voltage measurement device.

[0057] In some embodiments, the relationship between the absolute value of the upper limit of the negative turn-off voltage and the turn-on gate resistance, the turn-off gate resistance, and the bus voltage is shown in Figure 2. It can be understood that when the input turn-on gate resistance, the turn-off gate resistance, and the bus voltage of the first negative turn-off voltage model change, the absolute value of the upper limit of the negative turn-off voltage of the output of the first negative turn-off voltage model also changes accordingly. Furthermore, by substituting different turn-on gate resistances, different turn-off gate resistances, different bus voltages, and corresponding absolute values ​​of the upper limit of the negative turn-off voltage obtained through a large number of simulation experiments into the above-mentioned Equation (1), multiple different polynomials can be obtained. After polynomial fitting, the following specific Equation (2) of the first negative turn-off voltage model can be obtained.

[0058] (Number 2) V SS_min =b2*R G_on +b3*R G_off +b4*V DC +b5*R G_on 2 +b6*R G_off 2 +b7*V DC 2 +b8*R G_on *R G_off +b9*R G_off *V DC +b 10 *R G_off *V DC -V th ···(2)

[0059] Here, b2=-24.41, b3=63.47, b4=222.4, b5=0.555, b6=1.033, b7=-8.683, b8=-1.096, b9=6.276, b 10 =-2.759.

[0060] In one example, the minimum turn-on voltage of the switching transistor is 1.5V, the bus voltage is 900V, the selected turn-on gate resistance is 40Ω, and the selected turn-off gate resistance is 20Ω, and using equation (2), we can obtain the upper absolute value of the turn-off negative voltage, which is 2.44V, that is, the turn-off negative voltage of the switching transistor should be less than −2.44V.

[0061] In some embodiments of the present disclosure, the second turn-off negative voltage model is expressed by the following equation (3):

[0062] (Number 3) V SS_max =V GS_max -λ2*f2(R G_on ,R G_off ,V DC ) ···(3)

[0063] where V SS_max is the absolute value of the lower limit of the turn-off negative voltage, λ2 is the second derating parameter, and f2(R G_on ,R G_off ,V DC ) is the function corresponding to the second turn-off negative voltage model, and R G_on is the turn-on gate resistance and R G_off is the turn-off gate resistance and V DC is the bus voltage, and V GS_max is the maximum absolute value of the negative voltage that can be tolerated.

[0064] In this way, the relationship between the turn-off gate resistance, turn-on gate resistance, bus voltage, and the absolute value of the maximum negative voltage that can be tolerated of the switching transistor and the absolute value of the upper limit of the turn-off negative voltage of the switching transistor can be clearly expressed by the above equation (3).

[0065] Specifically, the turn-off gate resistance can be understood to be the total resistance of the turn-off circuit when the switching transistor is turned off, and the turn-on gate resistance can be understood to be the total resistance of the turn-on circuit when the switching transistor is turned on. In some embodiments, the tolerable maximum negative voltage absolute value can be obtained by querying corresponding data based on a specific model number of the switching transistor. In some embodiments, the second derating parameter can be obtained by querying corresponding derating standards based on a specific model number of the resistor. In some embodiments, the bus voltage can be obtained via a bus voltage measuring device.

[0066] In some embodiments, the relationship between the absolute value of the negative turn-off voltage lower limit and the turn-on gate resistance, the turn-off gate resistance, and the bus voltage is shown in Figure 3. It can be understood that when the turn-on gate resistance, the turn-off gate resistance, and the bus voltage at the input of the second negative turn-off voltage model change, the absolute value of the negative turn-off voltage lower limit at the output of the second negative turn-off voltage model also changes accordingly. Furthermore, by substituting different turn-on gate resistances, different turn-off gate resistances, different bus voltages, and corresponding absolute values ​​of the negative turn-off voltage lower limit into the above equation (3), multiple different polynomials can be obtained. After polynomial fitting, the following specific equation (4) of the second negative turn-off voltage model can be obtained:

[0067] (Number 4) V SS_max =V GS_max +d2*R G_on +d3*R G_off +d4*V DC +d5*R G_on 2 +d6*R G_off 2 +d7*V DC 2 +d8*R G_on *R G_off +d9*R G_off *V DC +d 10 *R G_off *V DC···(4)

[0068] Here, d2=-122.9, d3=1454.0, d4=-488.3, ​​d5=2.069, d6=-47.87, d7=15.43, d8=-0.805, d9=3.800, d 10 =-5.223.

[0069] In one example, the maximum negative voltage that the switching transistor can withstand is −9V, i.e., the absolute value of the maximum negative voltage that the switching transistor can withstand is 9V, the bus voltage is 900V, the selected turn-on gate resistance is 40Ω, and the selected turn-off gate resistance is 20Ω, and using equation (4), the absolute value of the turn-off negative voltage lower limit can be obtained as 4.96V, i.e., the turn-off negative voltage of the switching transistor should be greater than −4.96V.

[0070] With reference to FIG. 4, in some embodiments of the present disclosure, step S17 further includes the following steps:

[0071] Step S171 is a step of setting the negative value of the upper limit absolute value of the turn-off negative voltage as the upper limit voltage of the turn-off negative voltage, and setting the negative value of the lower limit absolute value of the turn-off negative voltage as the lower limit voltage of the turn-off negative voltage.

[0072] Step S173 is a step of determining the negative turn-off voltage section from the lower limit negative turn-off voltage and the upper limit negative turn-off voltage.

[0073] This allows the turn-off negative voltage section of the switching transistor to be obtained more accurately, and the switching transistor can be turned off when the gate voltage of the switching transistor is within the turn-off negative voltage section, thereby effectively preventing erroneous turn-on of the switching transistor.

[0074] Specifically, the absolute value of the upper limit of the negative turn-off voltage can be understood as the absolute value of the upper limit of the negative turn-off voltage, and the absolute value of the lower limit of the negative turn-off voltage can be understood as the absolute value of the lower limit of the negative turn-off voltage. In other words, since the absolute value of the upper limit of the negative turn-off voltage and the absolute value of the lower limit of the negative turn-off voltage are both positive values ​​and the negative turn-off voltage of the switching transistor is a negative value, the negative value of the upper limit of the negative turn-off voltage is the upper limit of the negative turn-off voltage, and the negative value of the lower limit of the negative turn-off voltage is the lower limit of the negative turn-off voltage. Therefore, the negative turn-off voltage section is determined from the lower limit of the negative turn-off voltage and the upper limit of the negative turn-off voltage, and it is ensured that the negative turn-off voltage of the selected switching transistor is equal to or greater than the lower limit of the negative turn-off voltage and is equal to or less than the upper limit of the negative turn-off voltage.

[0075] In one example, the minimum turn-on voltage of the switching transistor is 1.5V, the maximum negative voltage that the switching transistor can withstand is −9V, i.e., the absolute value of the maximum negative voltage that the switching transistor can withstand is 9V, the bus voltage is 900V, the selected turn-on gate resistance is 40Ω, and the selected turn-off gate resistance is 20Ω. Using equation (2), the absolute value of the upper limit of the turn-off negative voltage can be obtained as 2.44V, i.e., the upper limit voltage of the turn-off negative voltage of the switching transistor is −2.44V. Using equation (4), the absolute value of the lower limit of the turn-off negative voltage of the switching transistor can be obtained as 4.96V, i.e., the lower limit voltage of the turn-off negative voltage of the switching transistor is −4.96V. Therefore, the turn-off negative voltage range of the switching transistor is determined as [−4.96V, −2.44V].

[0076] In some embodiments of the present disclosure, the switching transistor is a silicon carbide MOS transistor.

[0077] As described above, the above method can more accurately determine the turn-off negative voltage interval, thereby effectively preventing erroneous turn-on of the silicon carbide MOS transistor, protecting the silicon carbide MOS transistor, and extending the service life of the silicon carbide MOS transistor. It can be understood that silicon carbide MOS transistors are prone to erroneous turn-on due to their fast switching speed and low minimum turn-on voltage.

[0078] It should be noted that the specific numerical values ​​mentioned above are merely for illustrative purposes of explaining the implementation of the present disclosure in detail, and should not be understood as limiting the present disclosure. In other examples, embodiments, or examples, other numerical values ​​can be selected according to the present disclosure, and are not particularly limited herein.

[0079] To realize the above embodiments, the embodiments of the present disclosure further propose a device for determining a negative turn-off voltage of a switching transistor, which can realize the method for determining a negative turn-off voltage of a switching transistor described in any one of the above embodiments. Figure 5 is a block diagram showing the configuration of a device for determining a negative turn-off voltage of a switching transistor according to one embodiment of the present disclosure. As shown in Figure 5, the device 10 for determining a negative turn-off voltage of a switching transistor proposed in the present disclosure includes a first determination module 12, an acquisition module 14, and a second determination module 16. The first determination module 12 is used to determine a first turn-off negative voltage model and a second turn-off negative voltage model, the acquisition module 14 is used to acquire the turn-off gate resistance and turn-on gate resistance of the switching transistor, acquire the bus voltage, and acquire the minimum turn-on voltage and the tolerable maximum negative voltage absolute value of the switching transistor, the second determination module 16 inputs the turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage into the first turn-off negative voltage model to acquire the turn-off negative voltage upper limit absolute value of the switching transistor, and inputs the turn-off gate resistance, turn-on gate resistance, bus voltage, and the tolerable maximum negative voltage absolute value into the second turn-off negative voltage model to acquire the turn-off negative voltage lower limit absolute value of the switching transistor, and determines the turn-off negative voltage section of the switching transistor based on the turn-off negative voltage upper limit absolute value and the turn-off negative voltage lower limit absolute value.

[0080] According to the device 10 for determining a negative turn-off voltage of a switching transistor of an embodiment of the present disclosure, the first turn-off negative voltage model is input with the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor to obtain an upper limit absolute value of the negative turn-off voltage of the switching transistor, and the second turn-off negative voltage model is input with the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and absolute value of the maximum negative voltage that the switching transistor can withstand to obtain a lower limit absolute value of the negative turn-off voltage of the switching transistor. Furthermore, the device 10 accurately determines a negative turn-off voltage range of the switching transistor based on the upper limit absolute value of the negative turn-off voltage of the switching transistor, so that when negative voltage turn-off control is performed on the switching transistor using this negative turn-off voltage range, erroneous turn-on of the switching transistor can be effectively prevented, and the switching transistor can be protected and its service life can be extended.

[0081] In some embodiments of the present disclosure, the first turn-off negative voltage model is V SS_min =λ1*f1(R G_on ,R G_off ,V DC )-V th where V SS_min is the absolute upper limit of the turn-off negative voltage, λ1 is the first derating parameter, and f1(R G_on ,R G_off ,V DC ) is the function corresponding to the first turn-off negative voltage model, and R G_on is the turn-on gate resistance and R G_off is the turn-off gate resistance and V DC is the bus voltage, and V th is the minimum turn-on voltage.

[0082] In some embodiments of the present disclosure, the second turn-off negative voltage model is V SS_max =V GS_max -λ2*f2(RG_on ,R G_off ,V DC ) is expressed by the mathematical formula (3), where V SS_max is the absolute value of the lower limit of the turn-off negative voltage, λ2 is the second derating parameter, and f2(R G_on ,R G_off ,V DC ) is the function corresponding to the second turn-off negative voltage model, and R G_on is the turn-on gate resistance and R G_off is the turn-off gate resistance and V DC is the bus voltage, and V GS_max is the maximum absolute value of the negative voltage that can be tolerated.

[0083] In some embodiments of the present disclosure, the second determination module 16 includes a first determination unit and a second determination unit, where the first determination unit is used to determine the negative value of the turn-off negative voltage upper limit absolute value as the turn-off negative voltage upper limit voltage and the negative value of the turn-off negative voltage lower limit absolute value as the turn-off negative voltage lower limit voltage, and the second determination unit is used to determine the turn-off negative voltage section from the turn-off negative voltage lower limit voltage and the turn-off negative voltage upper limit voltage.

[0084] In some embodiments of the present disclosure, the switching transistor is a silicon carbide MOS transistor.

[0085] It should be noted that the above-described embodiments and explanations of the beneficial effects of the method for determining the negative turn-off voltage of a switching transistor also apply to the device 10 for determining the negative turn-off voltage of a switching transistor of the present disclosure, and detailed descriptions thereof will be omitted here to avoid redundancy.

[0086] To realize the above embodiments, the embodiments of the present disclosure further propose an inverter capable of implementing the method for determining a negative turn-off voltage of a switching transistor described in any one of the above embodiments. FIG. 6 is a block diagram showing the structure of an inverter according to one embodiment of the present disclosure. As shown in FIG. 6, the inverter 30 includes a memory 32, a processor 34, and a program 36 for determining a negative turn-off voltage of a switching transistor stored in the memory 32 and executable by the processor 34. When the processor 34 executes the program 36 for determining a negative turn-off voltage of a switching transistor, the method for determining a negative turn-off voltage of a switching transistor described in any one of the above embodiments is implemented.

[0087] According to the inverter 30 of the embodiment of the present disclosure, the first turn-off negative voltage model is input with the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor to obtain the absolute value of the upper limit of the negative turn-off voltage of the switching transistor, and the second turn-off negative voltage model is input with the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and absolute value of the maximum negative voltage that the switching transistor can withstand to obtain the absolute value of the lower limit of the negative turn-off voltage of the switching transistor. Furthermore, the negative turn-off voltage range of the switching transistor is accurately determined based on the absolute value of the upper limit of the negative turn-off voltage of the switching transistor, so that when the negative voltage turn-off control is performed on the switching transistor using this negative turn-off voltage range, erroneous turn-on of the switching transistor can be effectively prevented, and the switching transistor can be protected and its service life can be extended.

[0088] For example, when the switching transistor turn-off negative voltage determination program 36 is executed by the processor 34, the following steps of the switching transistor turn-off negative voltage determination method are realized.

[0089] Step S11 is a step of determining a first turn-off negative voltage model and a second turn-off negative voltage model.

[0090] Step S13 is a step of obtaining the turn-off gate resistance and turn-on gate resistance of the switching transistor, obtaining the bus voltage, and obtaining the minimum turn-on voltage and the absolute value of the maximum negative voltage that can be tolerated of the switching transistor.

[0091] Step S15 is a step of inputting the turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage into the first turn-off negative voltage model to obtain the absolute value of the upper limit of the turn-off negative voltage of the switching transistor, and inputting the turn-off gate resistance, turn-on gate resistance, bus voltage, and the absolute value of the maximum tolerable negative voltage into the second turn-off negative voltage model to obtain the absolute value of the lower limit of the turn-off negative voltage of the switching transistor.

[0092] Step S17 is a step of determining the turn-off negative voltage section of the switching transistor based on the turn-off negative voltage upper limit absolute value and the turn-off negative voltage lower limit absolute value.

[0093] It should be noted that the above-described embodiments and explanations of the beneficial effects of the method for determining the negative turn-off voltage of the switching transistor also apply to the inverter 30 of the present disclosure, and detailed descriptions thereof will be omitted here to avoid redundancy.

[0094] To achieve the above embodiment, an embodiment of the present disclosure further proposes a computer-readable storage medium that, when a method for determining a turn-off negative voltage of a switching transistor stored therein is executed by a processor, realizes the method for determining a turn-off negative voltage of a switching transistor described in any one of the above embodiments.

[0095] According to the computer-readable storage medium of the embodiment of the present disclosure, the first turn-off negative voltage model is input with the obtained turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor to obtain an upper limit absolute value of the negative turn-off voltage of the switching transistor; the second turn-off negative voltage model is input with the obtained turn-off gate resistance, turn-on gate resistance, bus voltage, and absolute value of the maximum negative voltage that the switching transistor can withstand to obtain a lower limit absolute value of the negative turn-off voltage of the switching transistor; and the negative turn-off voltage interval of the switching transistor is accurately determined based on the upper limit absolute value of the negative turn-off voltage of the switching transistor. When the negative turn-off voltage interval is used to perform negative voltage turn-off control on the switching transistor, erroneous turn-on of the switching transistor can be effectively prevented, and the service life of the switching transistor can be extended.

[0096] To achieve the above embodiments, the present disclosure further proposes a switching transistor drive control circuit. FIG. 7 is a circuit schematic diagram of a switching transistor drive control circuit according to an embodiment of the present disclosure. As shown in FIG. 7, the switching transistor drive control circuit 50 of the embodiment of the present disclosure includes a drive power supply 52, a drive unit 54, and a control unit 56. The control unit 56 executes the method for determining the negative turn-off voltage of the switching transistor 70 described in any one of the above embodiments to obtain the negative turn-off voltage period of the switching transistor 70, and controls the drive power supply 52 to supply a negative turn-off voltage to the drive unit 54 according to the negative turn-off voltage period. The drive unit 54 is used to turn off the switching transistor 70 according to the negative turn-off voltage upon receiving the turn-off control signal.

[0097] According to the switching transistor drive control circuit 50 of the embodiment of the present disclosure, the turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor 70 obtained are input to the first turn-off negative voltage model to obtain the absolute value of the upper limit of the negative turn-off voltage of the switching transistor 70, and the turn-off gate resistance, turn-on gate resistance, bus voltage, and the absolute value of the maximum negative voltage that the switching transistor 70 can withstand are input to the second turn-off negative voltage model to obtain the absolute value of the lower limit of the negative turn-off voltage of the switching transistor 70. Furthermore, a turn-off negative voltage range of the switching transistor 70 is accurately determined based on the upper limit absolute value of the negative turn-off voltage of the switching transistor 70 and the lower limit absolute value of the negative turn-off voltage of the switching transistor 70. When negative voltage turn-off control is performed on the switching transistor 70 using this turn-off negative voltage range, erroneous turn-on of the switching transistor 70 can be effectively prevented, and the service life of the switching transistor 70 can be extended.

[0098] In some embodiments, the control unit 56 may be a Micro Control Unit (MCU).

[0099] In some embodiments of the present disclosure, the driving unit 54 includes a first coupling capacitance and a second coupling capacitance. One end of the first coupling capacitance is connected to the positive turn-on voltage supply terminal of the driving power supply. One end of the second coupling capacitance is connected to the other end of the first coupling capacitance and the other end is connected to the negative turn-off voltage supply terminal of the driving power supply.

[0100] In this way, the positive turn-on voltage supply terminal and the negative turn-off voltage supply terminal of the driving power supply are separated by the first coupling capacitance and the second coupling capacitance.

[0101] In one example, with reference to FIG. 8, the first coupling capacitance is capacitance C 1P and capacity C 2P and the second coupling capacitance is capacitance C 1N and capacity C 2NThe driving power supply 52 includes a first driving power supply 522 and a second driving power supply 524, and has a capacitance C 1P One end of the capacitor C is connected to the positive turn-on voltage supply terminal VDD1 of the first driving power supply 522, and the other end of the capacitor C 1N a first node P1 connected to one end of a capacitance C 1N The other end of the capacitor C is connected to the negative turn-off voltage supply terminal VSS1 of the first driving power supply 522. 2P One end of the capacitor C is connected to the positive turn-on voltage supply terminal VDD2 of the second driving power supply 524, and the other end of the capacitor C 2N and a second node P2 connected to one end of the capacitance C 2N The other end of the second driving power supply 524 is connected to the negative turn-off voltage supply terminal VSS2 of the second driving power supply 524.

[0102] In some embodiments of the present disclosure, when the switching transistor 70 is an upper arm switching transistor, the node between the first coupling capacitance and the second coupling capacitance is connected to the midpoint of the leg in which the upper arm switching transistor is located, and when the switching transistor 70 is a lower arm switching transistor, the node between the first coupling capacitance and the second coupling capacitance is grounded.

[0103] In this way, by employing the switching transistor drive control circuit 50 in the bridge inverter circuit, the switching transistor 70 can be accurately turned off, and erroneous turn-on of the switching transistor 70 can be effectively prevented, thereby protecting the switching transistor 70 and extending its service life. It should be understood that the bridge inverter circuit can include a single-phase full-bridge inverter circuit, a three-phase bridge inverter circuit, or a bridge inverter circuit of another topology.

[0104] In one example, with reference to FIG. 8 , the switching transistor 70 includes an upper arm switching transistor Q1 and a lower arm switching transistor Q2, the upper arm switching transistor Q1 having a source connected to the drain of the lower arm switching transistor Q2 and having a third node P3, and when the switching transistor 70 is the upper arm switching transistor Q1, a first coupling capacitance C 1P and the second coupling capacitance C 1N A first node P1 between the upper arm switching transistor Q1 and the lower arm switching transistor Q2 is connected to the midpoint of the leg where the upper arm switching transistor Q1 is located (i.e., the third node P3). When the switching transistor 70 is the lower arm switching transistor Q2, a first coupling capacitance C 2P and the second coupling capacitance C 2N A second node P2 between them is grounded.

[0105] In some embodiments of the present disclosure, the driving unit 54 includes a driving chip and a first gate resistor. The positive power supply pin of the driving chip is connected to the positive turn-on voltage supply terminal of the driving power supply, the negative power supply pin of the driving chip is connected to the negative turn-off voltage supply terminal of the driving power supply, the input pin of the driving chip is connected to the control unit and receives the turn-off control signal issued by the control unit. One end of the first gate resistor is connected to the output pin of the driving chip and the other end is connected to the gate of the switching transistor.

[0106] In this way, the driver chip can drive the switching transistor to turn on or turn off through the first gate resistor.

[0107] In one example, referring to FIG. 8, the driver chips include chip U1 and chip U2, and the first gate resistor is resistor R on 1 and resistor R on 2, the driving power supply 52 includes a first driving power supply 522 and a second driving power supply 524, the switching transistor 70 includes an upper arm switching transistor Q1 and a lower arm switching transistor Q2, and the first coupling capacitance is a capacitance C 1P and capacity C 2Pand the second coupling capacitance is capacitance C 1N and capacity C 2N Includes:

[0108] The positive power supply pin VDD of the driver chip U1 is connected to the positive turn-on voltage supply terminal VDD1 of the first driver power supply 522, the negative power supply pin VSS of the driver chip U1 is connected to the negative turn-off voltage supply terminal VSS1 of the first driver power supply 522, the input pin IN of the driver chip U1 is connected to the first end of the control unit 56 to receive the turn-off control signal issued by the control unit 56, and the output pin OUT of the driver chip U1 is connected to the resistor R on It is connected to one end of resistor R on The other end of the capacitance C1 is connected to the gate of the upper arm switching transistor Q1, the source of the upper arm switching transistor Q1 is connected to the drain of the lower arm switching transistor Q2, and a third node P3 is formed. 1P One end of the capacitor C is connected to the positive turn-on voltage supply terminal VDD1 of the first driving power supply 522. 1P The other end of the capacitor C 1N , and has a first node P1 connected to a third node P3, and a capacitance C 1N The other end is connected to the negative turn-off voltage supply terminal VSS1 of the first driving power supply 522.

[0109] The positive power supply pin VDD of the driver chip U2 is connected to the positive turn-on voltage supply terminal VDD2 of the second driver power supply 524, the negative power supply pin VSS of the driver chip U2 is connected to the negative turn-off voltage supply terminal VSS2 of the second driver power supply 524, the input pin IN of the driver chip U2 is connected to the second end of the control unit 56 to receive the turn-off control signal issued by the control unit 56, and the output pin OUT of the driver chip U2 is connected to the resistor R on 2 is connected to one end of resistor R on The other end of the capacitance C2 is connected to the gate of the lower-arm switching transistor Q2. The drain of the lower-arm switching transistor Q2 is connected to the source of the upper-arm switching transistor Q1, and the source of the lower-arm switching transistor Q2 is grounded. 2POne end of the capacitor C is connected to the positive turn-on voltage supply terminal VDD2 of the second driving power supply 524. 2P The other end of the capacitor C 2N The second node P2 is connected to one end of the capacitor C 2N The other end is connected to the negative turn-off voltage supply terminal VSS2 of the second driving power supply 524.

[0110] When the control unit 56 sends a turn-on control signal through the first terminal, the positive power supply pin VDD of the driver chip U1 communicates with the output pin OUT, the first driver power supply 522 supplies a positive voltage to the positive power supply pin VDD of the driver chip U1, the OUT pin of the driver chip U1 outputs a positive voltage, and the resistor R on After dividing the voltage through 1, a positive turn-on voltage is supplied to the gate of the upper arm switching transistor Q1, and the upper arm switching transistor Q1 is turned on. At this time, the turn-on gate resistance is resistor R on 1. When the control unit 56 sends a turn-off control signal through the first terminal, the negative power supply pin VSS of the driver chip U1 communicates with the output pin OUT, the first driver power supply 522 supplies a negative voltage to the negative power supply pin VSS of the driver chip U1, the OUT pin of the driver chip U1 outputs a negative voltage, and the resistor R on After dividing the voltage through 1, a negative turn-off voltage is supplied to the gate of the upper arm switching transistor Q1, and the upper arm switching transistor Q1 is turned off. At this time, the turn-off gate resistance is resistor R on It can be seen that the resistance value is 1.

[0111] When the control unit 56 sends a turn-on control signal through the second terminal, the positive power supply pin VDD of the driver chip U2 communicates with the output pin OUT, the second driver power supply 524 supplies a positive voltage to the positive power supply pin VDD of the driver chip U2, the OUT pin of the driver chip U2 outputs a positive voltage, and the resistor R on After dividing the voltage through 2, a positive turn-on voltage is supplied to the gate of the lower arm switching transistor Q2, and the lower arm switching transistor Q2 is turned on. At this time, the turn-on gate resistance is resistor R on2. When the control unit 56 sends a turn-off control signal through the second terminal, the negative power supply pin VSS of the driver chip U2 communicates with the output pin OUT, the second driver power supply 524 supplies a negative voltage to the driver chip U2, the OUT pin of the driver chip U2 outputs a negative voltage, and the resistor R on After dividing the voltage through 1, a negative turn-off voltage is supplied to the gate of the lower arm switching transistor Q2, and the lower arm switching transistor Q2 is turned off. At this time, the turn-off gate resistance is resistor R on It can be seen that the resistance value is 2.

[0112] In some embodiments of the present disclosure, the driving unit 54 includes a first diode and a second gate resistor, the cathode of the first diode is connected to one end of the first gate resistor, and the second gate resistor has one end connected to the anode of the first diode and the other end connected to the other end of the first gate resistor.

[0113] In one example, referring to FIG. 9, the driver chips include chip U1 and chip U2, and the first gate resistor is resistor R on 1 and resistor R on 2, and the second gate resistor is resistor R off 1 and resistor R off 2, the driving power supply 52 includes a first driving power supply 522 and a second driving power supply 524, the switching transistor 70 includes an upper arm switching transistor Q1 and a lower arm switching transistor Q2, and the first coupling capacitance is a capacitance C 1P and capacity C 2P and the second coupling capacitance is capacitance C 1N and capacity C 2N and the first diode includes a diode D1 and a diode D2.

[0114] The positive power supply pin VDD of the driver chip U1 is connected to the positive turn-on voltage supply terminal VDD1 of the first driver power supply 522, the negative power supply pin VSS of the driver chip U1 is connected to the negative turn-off voltage supply terminal VSS1 of the first driver power supply 522, the input pin IN of the driver chip U1 is connected to the first end of the control unit 56 to receive the turn-off control signal issued by the control unit 56, and the output pin OUT of the driver chip U1 is connected to the resistor R on It is connected to one end of resistor R on The other end of the diode D1 is connected to the gate of the upper arm switching transistor Q1, the source of the upper arm switching transistor Q1 is connected to the drain of the lower arm switching transistor Q2, and a third node P3 is formed. The cathode of the diode D1 is connected to the resistor R on One end of diode D1 is connected to the other end of resistor R off 1 and resistor R off The other end of 1 is resistor R on The other end of 1 is connected to the capacitance C 1P One end of the capacitor C is connected to the positive turn-on voltage supply terminal VDD1 of the first driving power supply 522. 1P The other end of the capacitor C 1N , and has a first node P1 connected to a third node P3, and a capacitance C 1N The other end is connected to the negative turn-off voltage supply terminal VSS1 of the first driving power supply 522.

[0115] The positive power supply pin VDD of the driver chip U2 is connected to the positive turn-on voltage supply terminal VDD2 of the second driver power supply 524, the negative power supply pin VSS of the driver chip U2 is connected to the negative turn-off voltage supply terminal VSS2 of the second driver power supply 524, the input pin IN of the driver chip U2 is connected to the second end of the control unit 56 to receive the turn-off control signal issued by the control unit 56, and the output pin OUT of the driver chip U2 is connected to the resistor R on 2 is connected to one end of resistor R onThe other end of diode D2 is connected to the gate of the lower-arm switching transistor Q2. The drain of the lower-arm switching transistor Q2 is connected to the source of the upper-arm switching transistor Q1, and the source of the lower-arm switching transistor Q2 is grounded. The cathode of diode D2 is connected to resistor R on 2, and the anode of diode D2 is connected to resistor R off 2 and resistor R off The other end of 2 is resistor R on The other end of 2 is connected to the capacitance C 2P One end of the capacitor C is connected to the positive turn-on voltage supply terminal VDD2 of the second driving power supply 524. 2P The other end of the capacitor C 2N The second node P2 is connected to one end of the capacitor C 2N The other end is connected to the negative turn-off voltage supply terminal VSS2 of the second driving power supply 524.

[0116] When the control unit 56 sends a turn-on control signal through the first terminal, the positive power supply pin VDD of the driver chip U1 communicates with the output pin OUT, the first driver power supply 522 supplies a positive voltage to the positive power supply pin VDD of the driver chip U1, the OUT pin of the driver chip U1 outputs a positive voltage, the diode D1 is cut off, and the resistor R on After dividing the voltage through 1, a positive turn-on voltage is supplied to the gate of the upper arm switching transistor Q1, and the upper arm switching transistor Q1 is turned on. At this time, the turn-on gate resistance is resistor R on 1. When the control unit 56 sends a turn-off control signal through the first terminal, the negative power supply pin VSS of the driver chip U1 communicates with the output pin OUT, the first driver power supply 522 supplies a negative voltage to the negative power supply pin VSS of the driver chip U1, the OUT pin of the driver chip U1 outputs a negative voltage, the diode D1 is turned on, and the resistor R on 1 and Resistance off 1 are connected in parallel, a negative turn-off voltage is supplied to the gate of the upper arm switching transistor Q1, and the upper arm switching transistor Q1 is turned off. At this time, the turn-off gate resistance is resistor Ron 1 and Resistance off It can be seen that 1 and 2 are the resistance values ​​after connecting them in parallel.

[0117] When the control unit 56 sends a turn-on control signal through the second terminal, the positive power supply pin VDD of the driver chip U2 communicates with the output pin OUT, the second driver power supply 524 supplies a positive voltage to the positive power supply pin VDD of the driver chip U2, the OUT pin of the driver chip U2 outputs a positive voltage, the diode D2 is cut off, and the resistor R on After dividing the voltage through 2, a positive turn-on voltage is supplied to the gate of the lower arm switching transistor Q2, and the lower arm switching transistor Q2 is turned on. At this time, the turn-on gate resistance is resistor R on 2. When the control unit 56 sends a turn-off control signal through the second terminal, the negative power supply pin VSS of the driver chip U2 is connected to the output pin OUT, the second driver power supply 524 supplies a negative voltage to the driver chip U2, the OUT pin of the driver chip U2 outputs a negative voltage, the diode D2 is turned on, and the resistor R on 2 and Resistance off 2 are connected in parallel, a negative turn-off voltage is applied to the gate of the lower arm switching transistor Q2, and the lower arm switching transistor Q2 is turned off. At this time, the turn-off gate resistance is the resistance R on 1 and Resistance off It can be seen that 1 and 2 are the resistance values ​​after connecting them in parallel.

[0118] It should be noted that when a diode is turned on, there is a turn-on resistance, which in some embodiments may be taken into account when calculating the turn-on gate resistance and the turn-off gate resistance.

[0119] In some embodiments of the present disclosure, the driving unit 54 further includes a second diode having a cathode connected to one end of the first gate resistor and an anode connected to the cathode of the first diode.

[0120] In one example, referring to FIG. 10, the driver chips include chip U1 and chip U2, and the first gate resistor is resistor R on 1 and resistor R on 2, and the second gate resistor is resistor R off 1 and resistor R off 2, the driving power supply 52 includes a first driving power supply 522 and a second driving power supply 524, the switching transistor 70 includes an upper arm switching transistor Q1 and a lower arm switching transistor Q2, and the first coupling capacitance is a capacitance C 1P and capacity C 2P and the second coupling capacitance is capacitance C 1N and capacity C 2N The first diodes include diode D1 and diode D3, and the second diodes include diode D2 and diode D4.

[0121] The positive power supply pin VDD of the driver chip U1 is connected to the positive turn-on voltage supply terminal VDD1 of the first driver power supply 522, the negative power supply pin VSS of the driver chip U1 is connected to the negative turn-off voltage supply terminal VSS1 of the first driver power supply 522, the input pin IN of the driver chip U1 is connected to the first end of the control unit 56 to receive the turn-off control signal issued by the control unit 56, the output pin OUT of the driver chip U1 is connected to the anode of the diode D2, and the cathode of the diode D2 is connected to the resistor R on It is connected to one end of resistor R on The other end of diode D1 is connected to the gate of upper-arm switching transistor Q1, the source of upper-arm switching transistor Q1 is connected to the drain of lower-arm switching transistor Q2, and a third node P3 is formed. The cathode of diode D1 is connected to the anode of diode D2, and the anode of diode D1 is connected to resistor R off 1 and resistor R off The other end of 1 is resistor R on The other end of 1 is connected to the capacitance C 1P One end of the capacitor C is connected to the positive turn-on voltage supply terminal VDD1 of the first driving power supply 522. 1P The other end of the capacitor C 1N, and has a first node P1 connected to a third node P3, and a capacitance C 1N The other end is connected to the negative turn-off voltage supply terminal VSS1 of the first driving power supply 522.

[0122] The positive power supply pin VDD of the driver chip U2 is connected to the positive turn-on voltage supply terminal VDD2 of the second driver power supply 524, the negative power supply pin VSS of the driver chip U2 is connected to the negative turn-off voltage supply terminal VSS2 of the second driver power supply 524, the input pin IN of the driver chip U2 is connected to the second terminal of the control unit 56 to receive the turn-off control signal issued by the control unit 56, the output pin OUT of the driver chip U2 is connected to the anode of the diode D4, and the cathode of the diode D4 is connected to the resistor R on 2 and resistor R on The other end of diode D2 is connected to the gate of the lower arm switching transistor Q2. The cathode of diode D3 is connected to the anode of diode D4, and the anode of diode D3 is connected to resistor R off 2 and resistor R off The other end of 2 is resistor R on The drain of the lower-arm switching transistor Q2 is connected to the source of the upper-arm switching transistor Q1, and the source of the lower-arm switching transistor Q2 is grounded. 2P One end of the capacitor C is connected to the positive turn-on voltage supply terminal VDD2 of the second driving power supply 524. 2P The other end of the capacitor C 2N The second node P2 is connected to one end of the capacitor C 2N The other end is connected to the negative turn-off voltage supply terminal VSS2 of the second driving power supply 524.

[0123] When the control unit 56 sends a turn-on control signal through the first terminal, the positive power supply pin VDD of the driver chip U1 communicates with the output pin OUT, the first driver power supply 522 supplies a positive voltage to the positive power supply pin VDD of the driver chip U1, the OUT pin of the driver chip U1 outputs a positive voltage, the diode D2 is turned on, the diode D1 is cut off, and the resistor R on After dividing the voltage through 1, a positive turn-on voltage is supplied to the gate of the upper arm switching transistor Q1, and the upper arm switching transistor Q1 is turned on. At this time, the turn-on gate resistance is resistor R on 1. When the control unit 56 sends a turn-off control signal through the first terminal, the negative power supply pin VSS of the driver chip U1 communicates with the output pin OUT, the first driver power supply 522 supplies a negative voltage to the negative power supply pin VSS of the driver chip U1, the OUT pin of the driver chip U1 outputs a negative voltage, the diode D1 is turned on, the diode D2 is cut off, and the resistor R off After dividing the voltage through 1, a negative turn-off voltage is supplied to the gate of the upper arm switching transistor Q1, and the upper arm switching transistor Q1 is turned off. At this time, the turn-off gate resistance is resistor R off It can be seen that the resistance value is 1.

[0124] When the control unit 56 sends a turn-on control signal through the second terminal, the positive power supply pin VDD of the driver chip U2 communicates with the output pin OUT, the second driver power supply 524 supplies a positive voltage to the positive power supply pin VDD of the driver chip U2, the OUT pin of the driver chip U2 outputs a positive voltage, the diode D4 is turned on, the diode D3 is cut off, and the resistor R on After dividing the voltage through 2, a positive turn-on voltage is supplied to the gate of the lower arm switching transistor Q2, and the lower arm switching transistor Q2 is turned on. At this time, the turn-on gate resistance is resistor R on2. When the control unit 56 sends a turn-off control signal through the second terminal, the negative power supply pin VSS of the driver chip U2 is connected to the output pin OUT, the second driver power supply 524 supplies a negative voltage to the negative power supply pin VSS of the driver chip U2, the OUT pin of the driver chip U2 outputs a negative voltage, the diode D3 is turned on, the diode D4 is cut off, and the resistor R off After dividing the voltage through 2, a negative turn-off voltage is supplied to the gate of the lower arm switching transistor Q2, and the lower arm switching transistor Q2 is turned off. At this time, the turn-off gate resistance is resistor R off It can be seen that the resistance value is 2.

[0125] It should be noted that when a diode is turned on, there is a turn-on resistance, which in some embodiments may be taken into account when calculating the turn-on gate resistance and the turn-off gate resistance.

[0126] In some embodiments of the present disclosure, the driving unit 54 includes a first diode and a second gate resistor, the cathode of the first diode is connected to one end of the first gate resistor and the anode is connected to the other end of the first gate resistor, and the second gate resistor is connected to the anode of the first diode and the other end of the second gate resistor is connected to the gate of the switching transistor.

[0127] In one example, referring to FIG. 11, the driver chips include chip U1 and chip U2, and the first gate resistor is resistor R on 1 and resistor R on 2, and the second gate resistor is resistor R off 1 and resistor R off 2, the driving power supply 52 includes a first driving power supply 522 and a second driving power supply 524, the switching transistor 70 includes an upper arm switching transistor Q1 and a lower arm switching transistor Q2, and the first coupling capacitance is a capacitance C 1P and capacity C 2P and the second coupling capacitance is capacitance C 1N and capacity C 2N and the first diode includes a diode D1 and a diode D2.

[0128] The positive power supply pin VDD of the driver chip U1 is connected to the positive turn-on voltage supply terminal VDD1 of the second driver power supply 524, the negative power supply pin VSS of the driver chip U1 is connected to the negative turn-off voltage supply terminal VSS1 of the first driver power supply 522, the input pin IN of the driver chip U1 is connected to the first terminal of the control unit 56 to receive the turn-off control signal issued by the control unit 56, and the output pin OUT of the driver chip U1 is connected to the resistor R on 1 and resistor R on The other end of 1 is resistor R off 1 and resistor R off The other end of the diode D1 is connected to the gate of the upper arm switching transistor Q1, the source of the upper arm switching transistor Q1 is connected to the drain of the lower arm switching transistor Q2, and a third node P3 is formed. The cathode of the diode D1 is connected to the resistor R on One end of diode D1 is connected to the other end of resistor R on 1 connected to the other end. Capacitance C 1P One end of the capacitor C is connected to the positive turn-on voltage supply terminal VDD1 of the first driving power supply 522. 1P The other end of the capacitor C 1N , and has a first node P1 connected to a third node P3, and a capacitance C 1N The other end is connected to the negative turn-off voltage supply terminal VSS1 of the first driving power supply 522.

[0129] The positive power supply pin VDD of the driver chip U2 is connected to the positive turn-on voltage supply terminal VDD2 of the second driver power supply 524, the negative power supply pin VSS of the driver chip U2 is connected to the negative turn-off voltage supply terminal VSS2 of the second driver power supply 524, the input pin IN of the driver chip U2 is connected to the second terminal of the control unit 56 to receive the turn-off control signal issued by the control unit 56, and the output pin OUT of the driver chip U2 is connected to the resistor R on 2 and one end of resistor R on The other end of 2 is resistor R off 2 and resistor R offThe other end of diode D2 is connected to the gate of the lower-arm switching transistor Q2. The drain of the lower-arm switching transistor Q2 is connected to the source of the upper-arm switching transistor Q1, and the source of the lower-arm switching transistor Q2 is grounded. The cathode of diode D2 is connected to resistor R on 2, and the anode of diode D2 is connected to resistor R on The other end of 2 is connected to the capacitance C 2P One end of the capacitor C is connected to the positive turn-on voltage supply terminal VDD2 of the second driving power supply 524. 2P The other end of the capacitor C 2N The second node P2 is connected to one end of the capacitor C 2N The other end is connected to the negative turn-off voltage supply terminal VSS2 of the second driving power supply 524.

[0130] When the control unit 56 sends a turn-on control signal through the first terminal, the positive power supply pin VDD of the driver chip U1 communicates with the output pin OUT, the first driver power supply 522 supplies a positive voltage to the positive power supply pin VDD of the driver chip U1, the OUT pin of the driver chip U1 outputs a positive voltage, the diode D1 is cut off, and the resistor R on 1 and resistor R off After series voltage division with 1, a positive turn-on voltage is supplied to the gate of the upper arm switching transistor Q1, turning on the upper arm switching transistor Q1. At this time, the turn-on gate resistance is resistor R on 1 and resistor R off When the control unit 56 sends a turn-off control signal through the first terminal, the negative power supply pin VSS of the driver chip U1 communicates with the output pin OUT, the first driver power supply 522 supplies a negative voltage to the negative power supply pin VSS of the driver chip U1, the OUT pin of the driver chip U1 outputs a negative voltage, the diode D1 is turned on, and the resistor R on 1 is shorted and resistor R offAfter dividing the voltage through 1, a negative turn-off voltage is supplied to the gate of the upper arm switching transistor Q1, and the upper arm switching transistor Q1 is turned off. At this time, the turn-off gate resistance is resistor R off It can be seen that the resistance value is 1.

[0131] When the control unit 56 sends a turn-on control signal through the second terminal, the positive power supply pin VDD of the driver chip U2 communicates with the output pin OUT, the second driver power supply 524 supplies a positive voltage to the positive power supply pin VDD of the driver chip U2, the OUT pin of the driver chip U2 outputs a positive voltage, the diode D2 is cut off, and the resistor R on 1 and resistor R off After series voltage division with 1, a positive turn-on voltage is supplied to the gate of the lower arm switching transistor Q2, turning on the lower arm switching transistor Q2. At this time, the turn-on gate resistance is resistor R on 2 and resistor R off When the control unit 56 sends a turn-off control signal through the second terminal, the negative power supply pin VSS of the driver chip U2 is connected to the output pin OUT, the second driver power supply 524 supplies a negative voltage to the negative power supply pin VSS of the driver chip U2, and the OUT pin of the driver chip U2 outputs a negative voltage, the diode D2 is turned on, and the resistor R on 2 is shorted, and resistor R off After dividing the voltage through 2, a negative turn-off voltage is supplied to the gate of the lower arm switching transistor Q2, and the lower arm switching transistor Q2 is turned off. At this time, the turn-off gate resistance is resistor R off It can be seen that the resistance value is 2.

[0132] It should be noted that when a diode is turned on, there is a turn-on resistance, which in some embodiments may be taken into account when calculating the turn-on gate resistance and the turn-off gate resistance.

[0133] In order to realize the above-described embodiments, a motor control system is also proposed in the embodiments of the present disclosure. FIG. 12 is a block diagram showing the structure of a motor control system according to one embodiment of the present disclosure. As shown in FIG. 12, the motor control system 100 includes a switching transistor drive control circuit 50 described in any one of the above-described embodiments.

[0134] In order to realize the above-described embodiments, a compressor is also proposed in the embodiments of the present disclosure. FIG. 13 is a block diagram showing the structure of a compressor according to the embodiments of the present disclosure. As shown in FIG. 13, a compressor 200 includes the motor control system 100 according to the above-described embodiments.

[0135] In order to realize the above-described embodiment, a vehicle is also proposed in an embodiment of the present disclosure. FIG. 14 is a block diagram showing the structure of a vehicle according to one embodiment of the present disclosure. As shown in FIG. 14, vehicle 300 is equipped with compressor 200 according to the above-described embodiment.

[0136] The vehicle 300 may be a new energy vehicle. In some embodiments, the new energy vehicle may be a pure electric vehicle using a motor as the main driving force. In other embodiments, the new energy vehicle may be a hybrid vehicle using both an internal combustion engine and a motor as the main driving force. Regarding the internal combustion engine and motor that provide driving force to the new energy vehicle described in the above embodiments, the internal combustion engine may use gasoline, diesel, hydrogen, etc. as fuel, and the method of supplying electrical energy to the motor may employ a power battery, a hydrogen fuel cell, etc., and is not particularly limited here. Note that this is merely an exemplary description of the structure of a new energy vehicle and does not limit the scope of protection of the present disclosure.

[0137] In some embodiments, the compressor applicable to the new energy vehicle according to the embodiments of the present disclosure may be an electric compressor including a drive unit and a compression unit, and the drive unit of the electric compressor drives the compression unit to perform compression work, for example, the drive unit may be a drive motor including a rotor and a stator. In some embodiments, the electric compressor may be a low back pressure compressor, and the drive unit may be disposed in a low pressure chamber communicating with the suction port of the compressor, and the compression unit may be disposed in a high pressure chamber communicating with the discharge port of the compressor. In some embodiments, the electric compressor may be a horizontal compressor, and the drive unit and the compression unit may be arranged horizontally.

[0138] According to the motor control system 100, the compressor 200, and the vehicle 300 of the embodiment of the present disclosure, the first turn-off negative voltage model is input with the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and minimum turn-on voltage of the switching transistor to obtain the absolute value of the upper limit of the negative turn-off voltage of the switching transistor, and the second turn-off negative voltage model is input with the acquired turn-off gate resistance, turn-on gate resistance, bus voltage, and absolute value of the maximum negative voltage that the switching transistor can withstand to obtain the absolute value of the lower limit of the negative turn-off voltage of the switching transistor. Furthermore, a negative turn-off voltage interval of the switching transistor is accurately determined based on the absolute value of the upper limit of the negative turn-off voltage of the switching transistor, and when negative voltage turn-off control is performed on the switching transistor using this negative turn-off voltage interval, erroneous turn-on of the switching transistor can be effectively prevented, and the switching transistor can be protected and its service life can be extended.

[0139] It should be noted that the above-described embodiments of the switching transistor drive control circuit and the description of the beneficial effects also apply to the motor control system 100, compressor 200, and vehicle 300 of the present disclosure, but will not be expanded upon in detail here to avoid redundancy.

[0140] Those skilled in the art will appreciate that embodiments of the present disclosure may be provided as a method, a system, or a computer program product. Thus, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware embodiments. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk memory, CD-ROM, optical memory, etc.) containing computer-usable program code.

[0141] The present disclosure will be described with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and combinations of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine such that the instructions, when executed by the processor of the computer or other programmable data processing device, generate means for implementing the functions specified in one or more of the flowcharts and / or one or more blocks in the block diagrams.

[0142] These computer program instructions may also be stored in a computer-readable memory that can be used to cause a computer or other programmable data processing apparatus to operate in a particular manner, and the instructions stored in the computer-readable memory may produce an article of manufacture including an instruction device that implements the functions specified in one or more flows of the flowcharts and / or one or more blocks of the block diagrams.

[0143] These computer program instructions are loaded into a computer or other programmable data processing apparatus and cause the computer or other programmable data processing apparatus to execute a series of operational steps to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable data processing apparatus perform the functions / acts set out in one or more flows of the flowcharts and / or one or more blocks of the block diagrams.

[0144] In the description herein, references to "one embodiment," "some embodiments," "example," "particular example," or "some examples" mean that a particular feature, structure, material, or characteristic described in connection with at least one embodiment or example of the present disclosure is included in at least one embodiment or example of the present disclosure. In the present specification, general references to the above terms do not necessarily refer to the same embodiment or example. Furthermore, the described particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

[0145] Additionally, terms such as "first," "second," etc., used in the embodiments of the present disclosure are used for descriptive purposes only and cannot be understood as indicating or implying the relative importance thereof or as implicitly designating the number of technical features. Thus, features qualified by the terms "first" and "second" in the embodiments of the present disclosure explicitly or implicitly indicate that the embodiment includes at least one of the feature. In the description of the present disclosure, the term "plurality" means at least two, e.g., two, three, or four, unless otherwise clearly and specifically limited.

[0146] In this disclosure, unless otherwise expressly specified or limited, the terms "attached," "connected," "connected," and "fixed" should be generally understood, and may refer to, for example, a fixed connection, a detachable connection, or an integral connection, a mechanical connection, an electrical connection, a direct connection or an indirect connection via an intermediate medium, or an internal communication between two elements or an interaction between two elements, but are not particularly limited thereto. Those skilled in the art can understand the specific meanings of the above terms in this disclosure depending on the specific circumstances.

[0147] It should be noted that the constituent elements of the above-described embodiments can be combined in any manner, and for the sake of brevity, not all possible combinations of the constituent elements in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these constituent elements, all should be considered to be within the scope described in this specification.

[0148] Although embodiments of the present disclosure have been shown and described above, it will be understood that the above embodiments are illustrative and not limiting of the present disclosure, and that those skilled in the art may change, modify, substitute, and vary the above embodiments within the scope of the present disclosure.

Claims

1. determining a first turn-off negative voltage model and a second turn-off negative voltage model; obtaining a turn-off gate resistance and a turn-on gate resistance of a switching transistor, obtaining a bus voltage, and obtaining a minimum turn-on voltage and a maximum negative voltage absolute value that can be tolerated by the switching transistor; obtaining an absolute value of an upper limit of a negative turn-off voltage of the switching transistor by inputting the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the minimum turn-on voltage into the first turn-off negative voltage model, and obtaining an absolute value of a lower limit of a negative turn-off voltage of the switching transistor by inputting the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the absolute value of the maximum negative voltage that can be tolerated into the second turn-off negative voltage model; determining a negative turn-off voltage interval of the switching transistor based on the upper limit absolute value of the negative turn-off voltage and the lower limit absolute value of the negative turn-off voltage.

2. The first turn-off negative voltage model is V ＳＳ_ｍｉｎ = λ １ *f １ (R Ｇ_ｏｎ , R Ｇ_ｏｆｆ , V ＤＣ )-V ｔｈ where V ＳＳ_ｍｉｎ is the upper absolute value of the turn-off negative voltage, and λ １ is the first derating parameter, and f １ (R Ｇ_ｏｎ , R Ｇ_ｏｆｆ , V ＤＣ ) is a function corresponding to the first turn-off negative voltage model, and R Ｇ_ｏｎ is the turn-on gate resistance, and R Ｇ_ｏｆｆ is the turn-off gate resistance, and V ＤＣ is the bus voltage, and V ｔｈ 2. The method of claim 1, wherein: is the minimum turn-on voltage.

3. The second turn-off negative voltage model is V ＳＳ_ｍａｘ =V ＧＳ_ｍａｘ -λ ２ *f ２ (R Ｇ_ｏｎ , R Ｇ_ｏｆｆ , V ＤＣ ) where V ＳＳ_ｍａｘ is the absolute value of the lower limit of the turn-off negative voltage, and λ ２ is the second derating parameter, and f ２ (R Ｇ_ｏｎ , R Ｇ_ｏｆｆ , V ＤＣ ) is a function corresponding to the second turn-off negative voltage model, and R Ｇ_ｏｎ is the turn-on gate resistance, and R Ｇ_ｏｆｆ is the turn-off gate resistance, and V ＤＣ is the bus voltage, and V ＧＳ_ｍａｘ 2. The method for determining a negative turn-off voltage of a switching transistor according to claim 1, wherein: is the absolute value of the maximum negative voltage that can be tolerated.

4. determining a negative turn-off voltage section of the switching transistor based on the upper limit absolute value of the negative turn-off voltage and the lower limit absolute value of the negative turn-off voltage, a negative value of the upper limit absolute value of the turn-off negative voltage is set as a turn-off negative voltage upper limit voltage, and a negative value of the lower limit absolute value of the turn-off negative voltage is set as a turn-off negative voltage lower limit voltage; 2. The method of claim 1, further comprising: determining the negative turn-off voltage section from the lower limit negative turn-off voltage and the upper limit negative turn-off voltage.

5. 5. The method for determining a turn-off negative voltage of a switching transistor according to claim 1, wherein the switching transistor is a silicon carbide MOS transistor.

6. a first determining module for determining a first turn-off negative voltage model and a second turn-off negative voltage model; an acquisition module for acquiring a turn-off gate resistance and a turn-on gate resistance of a switching transistor, acquiring a bus voltage, and acquiring a minimum turn-on voltage and a maximum withstandable negative voltage absolute value of the switching transistor; and a second determination module for inputting the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the minimum turn-on voltage into the first turn-off negative voltage model to obtain an absolute value of an upper limit of the negative turn-off voltage of the switching transistor, inputting the turn-off gate resistance, the turn-on gate resistance, the bus voltage, and the absolute value of the maximum tolerable negative voltage into the second turn-off negative voltage model to obtain an absolute value of a lower limit of the negative turn-off voltage of the switching transistor, and determining a negative turn-off voltage range of the switching transistor based on the absolute value of the upper limit of the negative turn-off voltage and the absolute value of the lower limit of the negative turn-off voltage.

7. An inverter including a memory, a processor, and a switching transistor turn-off negative voltage determination program stored in the memory and executable by the processor, wherein the method for determining a switching transistor turn-off negative voltage according to any one of claims 1 to 4 is realized when the processor executes the switching transistor turn-off negative voltage determination program.

8. A computer-readable storage medium storing a program for determining a turn-off negative voltage of a switching transistor, the program realizing the method for determining a turn-off negative voltage of a switching transistor according to any one of claims 1 to 4 when the program is executed by a processor.

9. a driving power source, a driving unit, and a control unit; The control unit executes the method for determining a turn-off negative voltage of a switching transistor according to any one of claims 1 to 4 to obtain a turn-off negative voltage section of the switching transistor, and controls the driving power supply according to the turn-off negative voltage section to supply a negative turn-off voltage to the driving unit; a switching transistor drive control circuit, wherein the drive unit is used to drive the switching transistor to turn off in response to the negative turn-off voltage when receiving a turn-off control signal;

10. The drive unit is a driver chip, the positive power supply pin of which is connected to the positive turn-on voltage supply terminal of the driver power supply, the negative power supply pin of which is connected to the negative turn-off voltage supply terminal of the driver power supply, and the input pin of which is connected to the control unit and receives the turn-off control signal issued by the control unit; 10. The switching transistor drive control circuit according to claim 9, further comprising: a first gate resistor having one end connected to an output pin of the driver chip and the other end connected to the gate of the switching transistor.

11. The drive unit is a first diode having a cathode connected to one end of the first gate resistor; 11. The switching transistor drive control circuit according to claim 10, further comprising: a second gate resistor having one end connected to the anode of the first diode and the other end connected to the other end of the first gate resistor.

12. The drive unit is The switching transistor drive control circuit according to claim 11 , further comprising a second diode having a cathode connected to one end of the first gate resistor and an anode connected to the cathode of the first diode.

13. The drive unit is a first diode having a cathode connected to one end of the first gate resistor and an anode connected to the other end of the first gate resistor; 11. The switching transistor drive control circuit according to claim 10, further comprising: a second gate resistor having one end connected to the anode of the first diode and the other end connected to the gate of the switching transistor.

14. The drive unit is a first coupling capacitor having one end connected to the positive turn-on voltage supply terminal of the driving power supply; 10. The switching transistor drive control circuit according to claim 9, further comprising: a second coupling capacitance having one end connected to the other end of the first coupling capacitance and the other end connected to the negative turn-off voltage supply terminal of the drive power supply.

15. when the switching transistor is an upper-arm switching transistor, a node between the first coupling capacitance and the second coupling capacitance is connected to a midpoint of a leg in which the upper-arm switching transistor is located; The switching transistor drive control circuit according to claim 14 , wherein when the switching transistor is a lower-arm switching transistor, a node between the first coupling capacitance and the second coupling capacitance is grounded.

16. A motor control system including the switching transistor drive control circuit according to claim 9.

17. A compressor including the motor control system of claim 16.

18. A vehicle including the compressor of claim 17.

Images