Phase-change material-based XOR logic gates

Abstract

The device includes a phase change material, a first electrode at a first end of the phase change material, a second electrode at a second end of the phase change material, and a heating element coupled to at least a portion of the phase change material between the first and second ends. The device also includes a first input terminal coupled to the heating element, a second input terminal coupled to the heating element, and an output terminal coupled to the second electrode.

Description

[Background technology]

[0001] The present invention relates to semiconductors, and more particularly to techniques for forming semiconductor structures. Semiconductors and integrated circuit chips have become ubiquitous in many products, especially as cost and size continue to decrease. There is a continuing desire to reduce the size of structural features and / or provide a greater number of structural features for a given chip size. Miniaturization generally allows for improved performance at lower power levels and lower cost. Current technology is at or approaching atomic-level scaling of certain microdevices, such as logic gates, field-effect transistors (FETs), and capacitors. Summary of the Invention

[0002] Embodiments of the present invention provide techniques for implementing XOR logic gates using phase change materials.

[0003] In one embodiment, an apparatus includes a phase change material, a first electrode at a first end of the phase change material, a second electrode at a second end of the phase change material, and a heating element coupled to at least a portion of the phase change material between the first and second ends. The apparatus also includes a first input terminal coupled to the heating element, a second input terminal coupled to the heating element, and an output terminal coupled to the second electrode.

[0004] In another embodiment, a method includes supplying a first voltage to a first input terminal coupled to a heating element, the heating element being coupled to at least a given portion of the phase change material between a first end of the phase change material and a second end of the phase change material, the first end of the phase change material being coupled to a first electrode and the second end of the phase change material being coupled to a second electrode. The method also includes supplying a second voltage to a second input terminal coupled to the heating element and measuring a magnitude of the voltage at an output terminal coupled to the second electrode.

[0005] In another embodiment, a method of operating a logic gate includes setting at least a given portion of a phase change material to a first phase having a first resistivity in response to one of two or more inputs to the logic gate being exclusively true; setting the given portion of the phase change material to a second phase having a second resistivity higher than the first resistivity in response to two of the two or more inputs to the logic gate being true; and determining an output logic state of the logic gate based on a measured resistance between an input electrode coupled to a first end of the phase change material and an output electrode coupled to a second end of the phase change material.

[0006] In another embodiment, a system includes two or more logic stages, each of the two or more logic stages including one or more logic devices. At least one of the one or more logic devices of a given logic stage of the two or more logic stages includes a phase change material-based logic gate including a phase change material and a heating element interconnected such that an output terminal is in a true logic state when one of first and second input terminals coupled to the heating element is exclusively in a true logic state. The phase change material-based logic gate of the given logic stage includes an enable output terminal coupling the heating element to a logic device of another logic stage of the two or more logic stages.

[0007] In another embodiment, a method includes measuring a current at an enable output terminal of a first logic device of a first logic stage of two or more logic stages, determining whether the measured current at the enable output terminal of the first logic device of the first logic stage exceeds a specified threshold enable current, and triggering an enable input terminal of a second logic device of a second logic stage of the two or more logic stages in response to determining that the measured current at the enable output terminal of the first logic device of the first logic stage exceeds the specified threshold enable current. The second logic device comprises a phase change material-based logic gate including a phase change material and a heating element interconnected such that an output terminal is in a true logic state when one of first and second input terminals coupled to the heating element is exclusively in a true logic state. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 2 is a circuit diagram of an XOR logic gate according to one embodiment of the present invention. [Figure 2] 1 is a plot illustrating set and reset pulses for a phase change memory device according to one embodiment of the present invention. [Figure 3] 1 is a plot showing the programmed resistance and programming current of a phase change memory device according to one embodiment of the present invention. [Figure 4] FIG. 1 illustrates an XOR logic gate implemented using phase change memory devices, according to one embodiment of the present invention. [Figure 5] FIG. 1 illustrates a multi-level logic system using XOR logic gates implemented using phase change memory devices, according to one embodiment of the present invention. [Figure 6] FIG. 1 illustrates an XOR logic gate implemented using phase change memory devices that is part of a multi-level logic system, according to one embodiment of the present invention. [Figure 7] FIG. 1 illustrates an enable control circuit for a multi-level logic system using XOR logic gates implemented using phase change memory devices, according to one embodiment of the present invention. [Figure 8] 8 is a timing control diagram for the XOR logic gate of FIG. 6 in the multi-level logic system of FIG. 7, according to one embodiment of the present invention. [Figure 9] FIG. 1 illustrates an integrated circuit comprising one or more logic gates, according to one embodiment of the present invention. [Figure 10] 1 illustrates an integrated circuit comprising a multi-level logic system, according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] Exemplary embodiments of the present invention may be described herein in the context of exemplary methods for forming logic gates using phase change materials, and exemplary apparatus, systems, and devices formed using such methods. However, it should be understood that embodiments of the present invention are not limited to the exemplary methods, apparatus, systems, and devices, but are instead more broadly applicable to other suitable methods, apparatus, systems, and devices.

[0010] XOR ("exclusive OR") is a logical operation that outputs "true" when one of two or more inputs is exclusively true (e.g., in the case of a two-input XOR, when the inputs are different). An XOR gate is a digital logic gate that provides a true output (e.g., 1 or high) when only one of its inputs is true. XOR gates may be constructed using multiple other logic gates, such as combinations of AND, OR, and NOT gates. FIG. 1 shows a circuit diagram 100 of an XOR gate constructed using a NOT gate 101, an OR gate 103, and an AND gate 105. FIG. 1 also shows a table 150 of XOR logic operations, showing the value of the output Q for given input values ​​for A and B. There is no single device currently available to represent XOR logic. Instead, multiple devices are used to represent XOR logic, as shown in the circuit diagram 100 of FIG. 1.

[0011] Exemplary embodiments provide a structure for implementing XOR logic that requires only a single phase change memory (PCM) device. Thus, embodiments can significantly improve density because a single PCM device is used to replace conventional transistors used to implement XOR logic. Some embodiments further utilize a heater design for the PCM device and a set of enable terminals for the multi-level logic structure.

[0012] PCM is a type of nonvolatile computer memory. PCM devices utilize the behavior of certain materials, such as chalcogenide glass, which can be "switched" between two states (e.g., crystalline and amorphous) by the application of heat. Chalcogenide glass is an example of a phase-change material, characterized by existing in two primary states (e.g., crystalline and amorphous). In the amorphous state, chalcogenide glass or other phase-change material has a first resistance (e.g., high resistance), while in the crystalline state, chalcogenide glass or other phase-change material has a second resistance (e.g., low resistance) that is different from the first resistance. Thus, phase-change materials can be used to represent one of two binary states.

[0013] To convert a phase-change material between a crystalline and amorphous state, an electric current can be applied to change the temperature of the phase-change material. For example, to "reset" a phase-change material (e.g., a chalcogenide glass) from a crystalline state to an amorphous state, a high electric current can be applied to raise the temperature of the phase-change material above approximately 600 degrees Celsius (°C). This may require applying a pulse of electric current lasting several nanoseconds to the phase-change material. To "set" a phase-change material (e.g., convert it from its amorphous state to its crystalline state), the phase-change material (e.g., a chalcogenide glass) can be heated to a temperature below approximately 400°C but above approximately 200°C, held at that temperature for a duration, and then cooled according to the decay profile of the applied current pulse. In some cases, the total time required to set a phase-change material can be up to 100 nanoseconds or more. The "set" time of a phase-change material is typically substantially longer than its "reset" time. However, it should be noted that the specific examples of set and reset times, and the specific temperature ranges provided for the set and reset operations, are presented by way of example only, and embodiments are not limited to only these specific values, which may vary based on the type of phase change material utilized.

[0014] As mentioned above, the phase change material may be an amorphous-crystalline phase change material, such as a chalcogenide phase change material. The phase transition of a chalcogenide phase change material is thermally driven and is bistable at room temperature. Chalcogenide phase change materials include germanium antimonide telluride (Ge x Sb y Te z ), germanium telluride (Ge x Te y ), antimony telluride (Sb x Te y ), silver antimony telluride (Ag x Sb y Te z ), silver indium antimony telluride (Ag w In x Sb y Te z ), and the like. In some embodiments, Ge2Sb2Te5 is used as the phase change material. In other embodiments, Ge3Sb2Te2, GeTe, SbTe, or AgInSbTe may be used as the phase change material. In these chalcogenide phase change materials, the chalcogenide can be thermally switched between a crystalline phase and an amorphous phase. For example, a first current pulse (e.g., a short, strong current pulse) can be used to thermally switch the amorphous phase chalcogenide phase change material (e.g., Ge x Sb y Te z ) can be Joule heated to a temperature of about 300°C, which crystallizes the amorphous phase chalcogenide phase change material. Using a second current pulse (e.g., longer, lower intensity) with a higher power but slower pulse, the crystalline phase chalcogenide phase change material can be Joule heated to a temperature of about 600°C, which melt-quenches the crystalline phase chalcogenide phase change material to the amorphous phase.

[0015] FIG. 2 shows a plot 200 of applied voltage over time for a PCM device. Plot 200 shows how voltage, and therefore temperature, varies with read, set, and reset pulses for the PCM device. Plot 200 also shows how the crystallization temperature (T CRYST ) and melting temperature (T MELT ) is also shown. As shown, the read operation is performed at T CRYST The reset pulse is performed for a relatively short duration, typically shorter than the length of the reset pulse, at a voltage less than T MELT Use a voltage corresponding to a temperature higher than T. CRYST Higher than T MELT A voltage corresponding to a lower temperature is used. Plot 200 further shows that the set pulse has a longer duration than the reset pulse. The reset pulse for the PCM device has a higher pulse amplitude (e.g., approximately twice the amplitude) than the set pulse.

[0016] 3 shows a plot 300 illustrating the programmed resistance and programming current of a PCM device. Plot 300 also shows the set and reset curves of the PCM device. The programming current for the reset operation is approximately twice the programming current for the set operation.

[0017] FIG. 4 illustrates an XOR gate 400 implemented using a PCM device, also referred to herein as a PCM-based XOR gate 400. The PCM device includes a phase change material 402, which is shown to include both a crystalline (c-PCM) region 402-1 and an amorphous (a-PCM) region 402-2. In operation, the amorphous region 402-2 can be switched from a-PCM to c-PCM by applying heat using a heater 408. The heater 408 is coupled to the phase change material 402 via an insulator layer 406. The insulator layer 406 comprises a material that is an electrical insulator but provides good thermal conductivity. The insulator layer 406 is positioned between the PCM 402 and the heater 408 so that the path of the heater current does not directly intersect with the PCM current flow. The PCM device includes an input node 404-1 and an output node 404-2. The input node 404-1 is coupled to VDD 401, which represents a high voltage. Input node 404-1 is sometimes referred to as the power supply node. Output node 404-2 is coupled to output (Y) 407. Resistive element (R) 418 is also coupled to output node 404-2 and to ground 419, which represents a low voltage.

[0018] The heater 408 is controlled by inputs X1 403 and X2 405. Figure 4 shows a table 450 illustrating the logic of the PCM-based XOR gate 400. The inputs X1 403 and X2 405 are coupled to a resistor (R p ) 412, 416. Heater 408 is also coupled to ground or low voltage 411. In other embodiments, node 411 may represent an enable output node in a multi-level logic system. The combination of diodes 410, 414 and resistive elements 412, 416 may provide at least a portion of the controller for PCM-based XOR logic gate 400.

[0019] Before logic is applied to inputs X1 403 and X2 405, the PCM device is reset to a-PCM (e.g., region 402-2 is reset as a-PCM). This can be achieved using an enable signal and an additional heater, as described in more detail below. Once reset, the logic of inputs X1 403 and X2 405 is applied. Figure 4 shows a logic table 450 for PCM-based XOR gate 400, where a value of "1" for inputs X1 403, X2 405 means to apply a voltage pulse, and a value of "0" for inputs X1 403, X2 405 means not to apply a voltage pulse (e.g., ground). For output (Y) 407, a value of "0" means low current (e.g., high resistance), and a value of "1" means high current (e.g., low resistance). Diodes 410, 414 are used to allow "on" current to flow through the associated resistive element 412, 416 when X1 403 or X2 405 is 0, and "programming" current to flow through resistive element 412, 416, and therefore heater 408, only when X1 403 or X2 405 is 1. When X1 403 and X2 405 are both 1, the current is high and region 402-2 of the PCM device is reset to a-PCM. When X1 403 and X2 405 are both 0, region 402-2 of the PCM device is unchanged. When one of X1 403 and X2 405 is 1 and the other is 0, the current is in an intermediate range such that region 402-2 of the PCM device is set (e.g., from a-PCM to c-PCM).

[0020] 5 shows a multi-stage logic system including a first stage having a PCM-based XOR gate 500-1 and a second stage having an additional device 500-2. The additional device 500-2 may be another XOR gate (which may, but need not be, implemented using a PCM device as described herein), a different type of logic gate (e.g., AND, NAND, OR, NOR, NOT, etc.), or another device that uses at least some information from the first-stage device as input. The multi-stage logic is provided using various enable terminals, including a first enable input terminal (EN_i1) 509-1 of the PCM-based XOR gate 500-1, a first enable output terminal (EN_o1) 511-1, a second enable input terminal (EN_i2) 509-2, and a second enable output terminal (EN_o2) 511-2 of the PCM-based XOR gate 500-1. As shown, the enable output terminal EN_o1 511-1 of the first stage provides an input to the enable input terminal EN_i2 509-2 of the second stage. The first stage also has inputs X1 503 and X2 505 similar to X1 403 and X2 405 described above. The PCM-based XOR gate 500-1 and the additional device 500-2 are both coupled to VDD 501, which represents a high voltage similar to VDD 401. The PCM-based XOR gate 500-1 of the first stage has a first output OUT1(Y1) 507-1, and the additional device 500-2 of the second stage has a second output OUT2(Y2) 507-2. Figure 5 shows a logic table 550 illustrating the value of OUT1(Y1) 507-1 given different input values ​​for X1 503 and X2 505.

[0021] Threshold enable current level I for the first or second stage EN , the enable output terminal of that stage is triggered. For example, if the current flowing through the PCM device in PCM-based XOR gate 500-1 is I EN, the enable output terminal EN_o1 511-1 is triggered, which controls the enable input terminal EN_i2 509-2 of the second stage. If the additional device 500-2 is also a PCM-based XOR gate, the enable input terminal EN_i2 509-2 can be used to provide a pre-reset current to an independent heater of the additional device 500-2 to create a pre-reset state (e.g., setting at least a portion of the phase change material of the PCM device to a-PCM before applying an input thereto).

[0022] In the multi-stage logic system of FIG. 5, when either or both of X1 503 and X2 505 are 1, the enable output terminal EN_o1 511-1 of the first stage has a current (e.g., I>I th ). If X1 503 and X2 505 are both 0, OUT1(Y1) 507-1 is 0, the PCM device is unchanged, and there is no need to trigger the next level. For the second stage, the enable input terminal EN_i2 509-2 is triggered when the enable output terminal EN_o1 511-1 of the previous stage (e.g., the first stage) is triggered. Triggering the enable input terminal EN_i2 509-2 of the second stage is assumed to be by providing sufficient current to apply some action to the additional device 500-2 of the second stage. If the additional device 500-2 is another PCM-based XOR gate, the triggering action is to apply sufficient programming current to an independent heater (e.g., a heater different from the one used by the input of the additional device 500-2) so that enough heat is generated to reset the phase change material (e.g., pre-reset before applying the input of the additional device 500-2).

[0023] While Figure 5 shows a multi-level logic system including only two stages for clarity of explanation, it should be understood that a multi-level logic system may include three or more stages. Each stage is assumed to have an enable input terminal that is coupled to or triggered by the enable output terminal of the previous stage. Each stage is assumed to have an enable input terminal that is coupled to or triggered by the enable output terminal of the previous stage, and an enable output terminal that is coupled to and triggers the enable input terminal of the next stage. For the final stage of a multi-level logic system, an enable output terminal may not be necessary.

[0024] FIG. 6 illustrates an XOR gate 600 implemented using a PCM device, also referred to as a PCM-based XOR gate 600, configured for use as part of a multi-level logic system such as that shown in FIG. 5. The PCM device includes a phase change material 602, which is shown to include both crystalline (c-PCM) regions 602-1 and amorphous (a-PCM) regions 602-2. In operation, the amorphous region 602-2 can be switched from a-PCM to c-PCM by applying heat using a heater 608. The heater 608 is coupled to the phase change material 602 through an insulator layer 606-1. The PCM device includes an input node 604-1 and an output node 604-2. The input node 604-1 is coupled to VDD 601, which represents a high voltage. The output node 604-2 is coupled to an output (Y) 607. A resistive element (R) 618 is also coupled to the output node 604-2 and to ground 619, which represents a low voltage.

[0025] The heater 608 is controlled by inputs X1 603 and X2 605. Figure 6 shows a table 650 illustrating the logic of the PCM-based XOR gate 600. The inputs X1 603 and X2 605 are coupled to a resistor (R p) 612, 616. Heater 608 is also coupled to enable output terminal EN_o 611. Enable output terminal EN_o 611 of PCM-based XOR gate 600 may be coupled to an enable input terminal of another device in a multi-level logic system, as described above with respect to FIG.

[0026] Before logic is applied to inputs X1 603 and X2 605, the PCM device is reset to a-PCM (e.g., region 602-2 is reset as a-PCM). This may be achieved using an enable input signal EN_i 609, which is assumed to be received from a previous stage in the multi-stage logic system. The enable input signal EN_i 609 is coupled to a pre-reset resistor element (R PRE ) 622, which outputs to an additional heater 620 that is independent of heater 608. Like heater 608, heater 620 may be coupled to PCM 602 via an electrically insulating but thermally conductive insulating layer 606-2. Heater 620 also has a terminal coupled to ground 619. When current exceeds a threshold enable current level in a previous stage of the multi-level logic system, the enable output terminal of that previous stage is triggered and controls enable input terminal EN_i 609, which supplies a pre-reset current to the independent heater 620. This creates a pre-reset state (e.g., setting the second region 602-2 of the PCM device to a-PCM before applying inputs X1 603 and X2 605). Similarly, enable output terminal EN_o 611 of the current stage controls the pre-reset state of the next stage.

[0027] When reset, the logic of inputs X1 603 and X2 605 is applied. Figure 6 shows a logic table 650 for PCM-based XOR gate 600, where a value of "1" for inputs X1, X2 means to apply a voltage pulse, and a value of "0" for inputs X1 603, X2 605 means not to apply a voltage pulse (e.g., ground). For output (Y) 607, a value of "0" means low current (e.g., high resistance), and a value of "1" means high current (e.g., low resistance). Diodes 610, 614 are used to allow "on" current to flow through the associated resistive element 612, 616 when X1 603 or X2 605 is 0, and "programming" current to flow through resistive element 612, 616, and therefore heater 608, only when X1 603 or X2 605 is 1. When X1 603 and X2 605 are both 1, the current is high and PCM device region 602-2 is reset to a-PCM. When X1 603 and X2 605 are both 0, PCM device region 602-2 is unchanged. When one of X1 603 and X2 605 is 1 and the other is 0, the current is in an intermediate range such that PCM device region 602-2 is set (e.g., from a-PCM to c-PCM).

[0028] 7 shows a multi-stage logic system including first and second stages having respective PCM-based XOR gates 700-1 and 700-2. However, it should be understood that the first stage or second stage may use a different type of logic gate (e.g., AND, NAND, OR, NOR, NOT, etc.) or another device that uses as input at least some information from a previous stage in the multi-stage system and / or provides some information as an output used by another stage in the multi-stage system or as an overall output of the multi-stage system.

[0029] 7 is provided using various enable terminals, including a first enable input terminal (EN_i1) 709-1 of PCM-based XOR gate 700-1, a first enable output terminal (EN_o1) 711-1 of PCM-based XOR gate 700-1, a second enable input terminal (EN_i2) 709-2 of PCM-based XOR gate 700-2, and a second enable output terminal (EN_o2) 711-2 of PCM-based XOR gate 700-2. First stage enable output terminal EN_o1 711-1 provides one input to the XOR logic of PCM-based XOR gate 700-2, and X3 713 provides the other input, as shown (in other words, EN_o1 711-1 and X3 713 are used as “X1” and “X2” for PCM-based XOR gate 700-2). The first stage also has inputs X1 703 and X2 705, similar to X1 603 and X2 605 described above. Both PCM-based XOR gates 700-1 and 700-2 are coupled to VDD 701, which represents a high voltage similar to VDD 601. PCM-based XOR gate 700-1 of the first stage has a first output OUT1 (Y1) 707-1, and PCM-based XOR gate 700-2 of the second stage has a second output OUT2 (Y2) 707-2. The logic tables for evaluating PCM-based XOR gates 700-1 and 700-2 are similar to the other logic tables 450, 550, and 650 shown in Figures 4-6.

[0030] Threshold enable current level I for the first or second stage EN , the enable output terminal of that stage is triggered. For example, if the current flowing through the PCM device in PCM-based XOR gate 700-1 is I EN , the enable output terminal EN_o1 711-1 is triggered. As shown in Figure 7, the enable control circuit 730 is coupled between the enable output terminal 711-1 of the first stage and the enable input terminal EN_i2 709-2 of the second stage. The enable control circuit 730 controls the threshold enable current level I for the enable output terminal EN_o1 711-1 of the previous stage. ENWhen the enable control circuit 730 triggers the enable input terminal EN_i2709-2 of the next stage, the enable input terminal EN_i2709-2 may be used to provide a pre-reset current to a separate heater of the PCM-based XOR gate 700-2 to create a pre-reset state (e.g., to set at least a portion of the phase change material of the PCM-based XOR gate 700-2 to a-PCM prior to application of an input thereto).

[0031] In the multi-stage logic system of FIG. 7, when either or both of X1 703 and X2 705 are 1, the enable output terminal EN_o1 711-1 of the first stage has a current (e.g., I>I th ). If X1 703 and X2 705 are both 0, the PCM device is unchanged, there is no need to trigger the next level, and the enable output terminal EN_o1 711-1 will not output a current below the threshold enable current (for example, I EN ). For the second stage, the enable control circuit 730 triggers the enable input terminal EN_i2 709-2 when the enable output terminal EN_o1 711-1 of the previous stage (e.g., the first stage) has a current that exceeds the threshold enable current. Triggering the enable input terminal EN_i2 709-2 of the second stage is assumed to provide sufficient programming current to a separate heater (e.g., different from the ones used by the inputs, OUT1(Y1) 707-1 and X3 713, of PCM-based XOR gate 700-2) so that enough heat is generated to reset the phase change material (e.g., to pre-reset the inputs, OUT1(Y1) 707-1 and X3 713, before applying them to PCM-based XOR gate 700-2).

[0032] ​7 shows a multi-level logic system including only two stages for clarity of explanation, it should be understood that a multi-level logic system may include three or more stages. Each stage is assumed to have an enable input terminal that is coupled to or triggered by the enable output terminal of the previous stage, and an enable output terminal that is coupled to and triggers the enable input terminal of the next stage. For the final stage of a multi-level logic system, an enable output terminal may not be necessary.

[0033] FIG. 8 shows a circuit timing diagram illustrating the control of the enable input and enable output terminals of a PCM-based XOR gate (e.g., as shown in FIG. 6) of a multi-level logic system (e.g., as shown in FIG. 7). FIG. 8 shows a pre-reset state 801, in which the enable input terminal EN_i is high, triggering a reset of the PCM device so that at least a portion of the phase change material (e.g., region 602-2 in FIG. 6) is reset to a-PCM. FIG. 8 also shows the application of different input states 803, 805, 807, and 809. In input state 803, X1=0, X2=0, and enable output terminals EN_o and Y1 are both low. For input state 805, X1=1, X2=0, and enable output terminals EN_o and Y1 are both high. Similarly, for input state 807, X1=0, X2=1, and enable output terminals EN_o and Y1 are both high. For input state 809, X1=1, X2=1, enable output terminal EN_o is high, and Y1 is low.

[0034] The semiconductor devices and methods for forming the same according to the above-described techniques can be used in a variety of applications, hardware, or electronic systems, or combinations thereof. Suitable hardware and systems for implementing embodiments of the present invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communication devices (e.g., cellular phones and smart phones), solid-state media storage devices, functional circuits, and the like. Systems and hardware incorporating semiconductor devices are contemplated embodiments of the present invention. Given the teachings provided herein, those skilled in the art will be able to contemplate other implementations and applications of the present invention.

[0035] In some embodiments, the techniques described above are used in connection with semiconductor devices that may require or otherwise utilize, for example, complementary metal-oxide-semiconductor (CMOS), metal-oxide-semiconductor field-effect transistors (MOSFETs), or fin field-effect transistors (FinFETs), or combinations thereof. By way of non-limiting example, the semiconductor devices may include, but are not limited to, CMOS, MOSFET, or FinFET devices, or semiconductor devices that use CMOS, MOSFET, or FinFET technologies, or combinations thereof, or both.

[0036] The various structures described above may be implemented into integrated circuits. The resulting integrated circuit chips may be distributed by manufacturers in raw wafer form (i.e., as a single wafer containing multiple unpackaged chips), as bare die, or in packaged form. In the latter case, the chips are packaged in single-chip packages (such as plastic carriers with leads attached to a motherboard or other higher-level carrier) or multi-chip packages (such as ceramic carriers with surface or buried wiring, or both). In either case, the chips are integrated with other chips, discrete circuit elements, or other signal processing devices, or a combination thereof, as part of either (a) an intermediate product such as a motherboard or (b) a final product. The final product can be any product containing integrated circuit chips, ranging from toys and other low-end applications to sophisticated computer products with displays, keyboards or other input devices, and central processing units.

[0037] 9 illustrates an exemplary integrated circuit 900 including one or more logic gates 910, at least one of which is assumed to comprise a PCM-based XOR gate as described above with respect to FIGS. 4 and 6. FIG. 10 illustrates another exemplary integrated circuit 1000 including a multi-level logic system 1010 comprising a set of logic stages 1012-1, 1012-2, ..., 1012-N (collectively, logic stages 1012), each implementing one or more logic gates 1020-1, 1020-2, ..., 1020-N (collectively, logic gates 1020). Again, at least one of the logic gates 1020 is assumed to comprise a PCM-based XOR gate as described above with respect to FIGS. 4 and 6. At least two of the logic stages 1012 are assumed to be connected via enable input and enable output terminals as described above with respect to FIGS. 5 and 7.

[0038] In some embodiments, an apparatus comprises a phase change material, a first electrode at a first end of the phase change material, a second electrode at a second end of the phase change material, a heating element coupled to at least a given portion of the phase change material between the first end and the second end, a first input terminal coupled to the heating element, a second input terminal coupled to the heating element, and an output terminal coupled to the second electrode.

[0039] The first input terminal may include a first diode having a first terminal and a second terminal and a first resistive element. The second terminal of the first diode is coupled to the first resistive element, and the first resistive element is coupled to the heating element. The second input terminal may include a second diode having a first terminal and a second terminal and a second resistive element. The second terminal of the second diode is coupled to the second resistive element, and the second resistive element is coupled to the heating element. The first terminal of the first diode may be connected to a first voltage pulse source, and the first terminal of the second diode may be connected to a second voltage pulse source. When the first voltage pulse source does not supply one or more first voltage pulses to the first terminal of the first diode, a first current is supplied to the first resistive element through the first diode, the first current being less than a threshold current required to supply a programming current to the heating element through the first resistive element. When the first voltage pulse source supplies one or more first voltage pulses to the first terminal of the first diode, a second current is supplied to the first resistive element through the first diode, the second current being equal to or greater than a threshold current required to supply a programming current to the heating element through the first resistive element. Similarly, when the second voltage pulse source does not supply one or more second voltage pulses to the first terminal of the second diode, a first current is supplied to the second resistive element through the second diode, the first current being less than a threshold current required to supply a programming current to the heating element through the second resistive element. When the second voltage pulse source supplies one or more second voltage pulses to the first terminal of the second diode, a second current is supplied to the second resistive element through the second diode, the second current being equal to or greater than a threshold current required to supply a programming current to the heating element through the second resistive element.

[0040] The device may further comprise an electrically insulating and thermally conductive layer disposed between the heating element and the portion of the phase change material.

[0041] The device can further include an additional heating element coupled to another portion of the phase change material between the first end and the second end, the additional heating element coupled to the enable input terminal. The device can also include an electrically insulating and thermally conductive layer disposed between the additional heating element and the other portion of the phase change material.

[0042] The apparatus may further comprise an enable output terminal coupled to the heating element, the enable output terminal being coupled to an enable input terminal of the additional device.

[0043] The first input terminal may include a first input to the logic gate (an XOR logic gate), the second input terminal may include a second input to the logic gate, and the output terminal may include an output of the logic gate.

[0044] The heating element is configured to apply heat to a given portion of the phase change memory material, and the amount of heat applied to the given portion of the phase change memory material is based at least in part on the amount of current supplied to the heating element. The phase change material in the first phase has a first resistivity, and the phase change material in the second phase has a second resistivity higher than the first resistivity. The first input terminal is configured to supply a first current to the heating element in response to one or more first voltage pulses applied to the first input terminal. The second input terminal is configured to supply a second current to the heating element in response to one or more second voltage pulses applied to the second input terminal. In response to both the first current and the second current being supplied to the heating element, the heating element is configured to apply a first level of heat to the given portion of the phase change memory material sufficient to reset the given portion of the phase change memory material to the second phase. In response to a single current of the first current and the second current being supplied to the heating element, the heating element is configured to apply a second level of heat to a given portion of the phase change memory material sufficient to set the given portion of the phase change memory material to the first phase.

[0045] In some embodiments, the method includes supplying a first voltage to a first input terminal coupled to a heating element, the heating element being coupled to at least a given portion of the phase change material between a first end of the phase change material and a second end of the phase change material, the first end of the phase change material being coupled to a first electrode and the second end of the phase change material being coupled to a second electrode, the method also includes supplying a second voltage to a second input terminal coupled to the heating element and measuring a magnitude of the voltage at an output terminal coupled to the second electrode.

[0046] The method may further include determining an output value of a logic gate (an XOR logic gate) based on the measured magnitude of a voltage at an output terminal coupled to the second electrode, wherein the first input terminal comprises a first input to the logic gate, the second input terminal comprises a second input to the logic gate, and the output terminal comprises an output of the logic gate that generates a true output value when one of the first and second inputs is exclusively true.

[0047] The phase change material in the first phase has a first resistivity and the phase change material in the second phase has a second resistivity higher than the first resistivity, and the method may further include resetting a given portion of the phase change material to the first phase before applying the first voltage to the first input terminal and before applying the second voltage to the second input terminal.

[0048] Supplying a first voltage to the first input terminal can include applying one or more positive voltage pulses to the first input terminal when the value of the first input is true. Supplying a second voltage to the second input terminal can include applying one or more positive voltage pulses to the second input terminal when the value of the second input is true. The one or more positive voltage pulses, when applied to the first input terminal, result in a first current being applied to the heating element. The one or more positive voltage pulses, when applied to the second input terminal, result in a first current being applied to the heating element. In response to both the first current and the second current being supplied to the heating element, the heating element is configured to apply a first level of heat to a given portion of the phase change memory material sufficient to reset the given portion of the phase change memory material to a second phase. In response to a single current of the first current and the second current being supplied to the heating element, the heating element is configured to apply a second level of heat to a given portion of the phase change memory material sufficient to set the given portion of the phase change memory material to the first phase.

[0049] In some embodiments, a method of operating a logic gate (e.g., an XOR logic gate) includes setting at least a given portion of a phase change material to a first phase having a first resistivity in response to one of two or more inputs to the logic gate being exclusively true; setting the given portion of the phase change material to a second phase having a second resistivity higher than the first resistivity in response to two of the two or more inputs to the logic gate being true; and determining an output logic state of the logic gate based on a measured resistance between an input electrode coupled to a first end of the phase change material and an output electrode coupled to a second end of the phase change material.

[0050] A heating element may be coupled to a given portion of the phase change material between the first end and the second end, and setting the given portion of the phase change material to a first phase may include applying one or more positive voltage pulses to one of a first input terminal coupled to the heating element and a second input terminal coupled to the heating element, and setting the given portion of the phase change material to a second phase may include applying one or more positive voltage pulses to both the first input terminal coupled to the heating element and the second input terminal coupled to the heating element.

[0051] In some embodiments, the system comprises two or more logic stages, each of the two or more logic stages comprising one or more logic devices. At least one of the one or more logic devices of a given logic stage of the two or more logic stages comprises a phase change material-based logic gate (XOR logic gate) including a phase change material and a heating element interconnected such that an output terminal is in a true logic state when one of first and second input terminals coupled to the heating element is exclusively in a true logic state. The phase change material-based logic gate of the given logic stage comprises an enable output terminal coupling the heating element to a logic device of another logic stage of the two or more logic stages.

[0052] The phase change material-based logic gate of a given logic stage may include an enable input terminal coupled to an additional heating element coupled to at least another portion of the phase change material. The enable input terminal of the phase change material-based logic gate of a given logic stage may be coupled to an enable output terminal of a logic device of a previous logic stage of the two or more logic stages.

[0053] The enable output terminal of a phase change material-based logic gate in a given logic stage may be coupled to the enable input terminal of a logic device in a subsequent logic stage of the two or more logic stages. The logic device in the subsequent logic stage may comprise another phase change material-based logic gate. The output terminal of the phase change material-based logic gate in a given logic stage may be coupled to an input to another heating element coupled to the phase change material of another phase change material-based logic gate in the subsequent logic stage.

[0054] In some embodiments, a method includes measuring a current at an enable output terminal of a first logic device of a first logic stage of the two or more logic stages, determining whether the measured current at the enable output terminal of the first logic device of the first logic stage exceeds a specified threshold enable current, and triggering an enable input terminal of a second logic device of a second logic stage of the two or more logic stages in response to determining that the measured current at the enable output terminal of the first logic device of the first logic stage exceeds the specified threshold enable current. The second logic device comprises a phase change material-based logic gate including a phase change material and a heating element interconnected such that an output terminal is in a true logic state when one of first and second input terminals coupled to the heating element is exclusively in a true logic state.

[0055] Triggering the enable input terminal of the second logic device can include controlling the application of heat to the given portion of the phase change material from an additional heating element coupled to the given portion of the phase change material.

[0056] The phase change material in the first phase can have a first resistivity and the phase change material in the second phase can have a second resistivity higher than the first resistivity, and triggering the enable input terminal of the second logic device can include resetting a given portion of the phase change material to the second phase.

[0057] It should be understood that the various layers, structures, and regions illustrated in the figures are schematic and not drawn to scale. Additionally, for ease of illustration, one or more layers, structures, and regions of a type commonly used in forming semiconductor devices or structures may not be explicitly shown in a given figure. This does not imply that any layers, structures, and regions not explicitly shown are omitted from the actual semiconductor structure. Furthermore, it should be understood that the embodiments discussed herein are not limited to the specific materials, features, and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it should be emphasized that the descriptions provided herein are not intended to encompass all of the processing steps that may be required to form a functional semiconductor integrated circuit device. Rather, certain processing steps commonly used in forming semiconductor devices, such as, for example, wet cleaning and annealing steps, have purposely not been described herein for economy of illustration.

[0058] Additionally, the same or similar reference numbers are used throughout the figures to indicate the same or similar features, elements, or structures, and therefore, detailed descriptions of the same or similar features, elements, or structures are not repeated for each figure. It should be understood that the terms "approximately" or "substantially," as used herein with respect to thickness, width, percentage, range, temperature, time, and other process parameters, are intended to indicate close or approximation, but not exactness. For example, the terms "approximately" or "substantially," as used herein, mean that a small margin of error exists, such as ±5%, preferably less than 2% or 1%, or less than the stated amount.

[0059] In the above description, various materials, dimensions, and processing parameters are provided for different elements. Unless otherwise noted, such materials are given by way of example only, and embodiments are not limited to the specific examples given. Similarly, unless otherwise noted, all dimensions and processing parameters are given by way of example only, and embodiments are not limited to the specific dimensions or ranges given.

[0060] The description of various embodiments of the present invention has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications or technical improvements to technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. An apparatus comprising: a phase change material; a first electrode at a first end of the phase change material; a second electrode at a second end of the phase change material; a heating element coupled to at least a portion of the phase change material between the first end and the second end; a first input terminal coupled to the heating element; a second input terminal coupled to the heating element; an output terminal coupled to the second electrode; Equipped with the first input terminal and the second input terminal are configured to simultaneously apply a voltage pulse to the heating element; Device.

2. 2. The apparatus of claim 1, wherein the first input terminal comprises a first diode having a first terminal and a second terminal, and a first resistive element, the second terminal of the first diode coupled to the first resistive element, and the first resistive element coupled to the heating element.

3. 3. The apparatus of claim 2, wherein the second input terminal comprises a second diode having a first terminal and a second terminal, and a second resistive element, the second terminal of the second diode coupled to the second resistive element, and the second resistive element coupled to the heating element.

4. The device of claim 1 , further comprising an electrically insulating and thermally conductive layer disposed between the heating element and the given portion of the phase change material.

5. 1. An apparatus comprising: a phase change material; a first electrode at a first end of the phase change material; a second electrode at a second end of the phase change material; a heating element coupled to at least a portion of the phase change material between the first end and the second end; a first input terminal coupled to the heating element; a second input terminal coupled to the heating element; an output terminal coupled to the second electrode; an additional heating element coupled to another portion of the phase change material between the first end and the second end; wherein the additional heating element is coupled to an enable input terminal.

6. The apparatus of claim 5 , further comprising an electrically insulating and thermally conductive layer disposed between the additional heating element and the further portion of the phase change material.

7. 1. An apparatus comprising: a phase change material; a first electrode at a first end of the phase change material; a second electrode at a second end of the phase change material; a heating element coupled to at least a portion of the phase change material between the first end and the second end; a first input terminal coupled to the heating element; a second input terminal coupled to the heating element; an output terminal coupled to the second electrode; an enable output terminal coupled to the heating element; the enable output terminal is coupled to an enable input terminal of an additional device; The apparatus, wherein the enable output terminal controls the enable input terminal based on voltage pulses applied to the first input terminal and the second input terminal.

8. 1. An apparatus comprising: a phase change material; a first electrode at a first end of the phase change material; a second electrode at a second end of the phase change material; a heating element coupled to at least a portion of the phase change material between the first end and the second end; a first input terminal coupled to the heating element; a second input terminal coupled to the heating element; an output terminal coupled to the second electrode; Equipped with the phase change material and the heating element form at least part of a logic gate interconnected such that when one of the first input terminal and the second input terminal is exclusively in a true logic state, the output terminal is in a true logic state.

9. 9. A system comprising two or more logic stages, each of the two or more logic stages comprising one or more logic devices, wherein at least one of the one or more logic devices of a given logic stage of the two or more logic stages comprises a phase change material-based logic gate having the device of any one of claims 1 to 8 interconnected such that an output terminal is in a true logic state when one of the first input terminal and the second input terminal is in a true logic state, and wherein the phase change material-based logic gate of the given logic stage comprises an enable output terminal that couples the heating element to a logic device of another logic stage of the two or more logic stages.

10. 10. The system of claim 9, wherein the phase change material based logic gate of the given logic stage comprises an enable input terminal coupled to an additional heating element coupled to at least another portion of the phase change material.

11. 11. The system of claim 10, wherein the enable input terminal of the phase change material-based logic gate of the given logic stage is coupled to an enable output terminal of a logic device of a previous logic stage of the two or more logic stages.

12. 10. The system of claim 9, wherein the enable output terminal of the phase change material-based logic gate of the given logic stage is coupled to an enable input terminal of a logic device of a subsequent logic stage of the two or more logic stages.

13. 13. The system of claim 12, wherein the logic device of the subsequent logic stage comprises another phase change material based logic gate.

14. 14. The system of claim 13, wherein the output terminal of the phase change material based logic gate in the given logic stage is coupled to an input to another heating element coupled to the phase change material of the other phase change material based logic gate in the subsequent logic stage.

15. 1. A method comprising: supplying a first voltage to a first input terminal coupled to a heating element, the heating element being coupled to at least a given portion of the phase change material between a first end of the phase change material and a second end of the phase change material, the first end of the phase change material being coupled to a first electrode and the second end of the phase change material being coupled to a second electrode; providing a second voltage to a second input terminal coupled to the heating element; measuring the magnitude of a voltage at an output terminal coupled to the second electrode; A method comprising:

16. 16. The method of claim 15, further comprising determining an output value of a logic gate based on the measured magnitude of the voltage at the output terminal coupled to the second electrode, wherein the first input terminal comprises a first input to the logic gate, the second input terminal comprises a second input to the logic gate, and the output terminal comprises an output of the logic gate.

17. 17. The method of claim 16, wherein providing the first voltage to the first input terminal comprises applying one or more positive voltage pulses to the first input terminal when the value of the first input is true.

18. 17. The method of claim 16, wherein providing the second voltage to the second input terminal comprises applying one or more positive voltage pulses to the second input terminal when the value of the second input is true.

19. 16. The method of claim 15, wherein the phase change material in a first phase has a first resistivity and the phase change material in a second phase has a second resistivity higher than the first resistivity, and further comprising resetting the given portion of the phase change material to the second phase before applying the first voltage to the first input terminal and before applying the second voltage to the second input terminal.

20. 1. A method of operating a logic gate, comprising: setting at least a given portion of a phase change material to a first phase having a first resistivity in response to one of two or more inputs to the logic gate being exclusively true; setting the given portion of the phase change material to a second phase having a second resistivity higher than the first resistivity in response to two of the two or more inputs to the logic gate being true; determining an output logic state of the logic gate based on a measured resistance between an input electrode coupled to a first end of the phase change material and an output electrode coupled to a second end of the phase change material; A method comprising:

21. 21. The method of claim 20, wherein a heating element is coupled to the given portion of the phase change material between the first end and the second end, and setting the given portion of the phase change material to the first phase comprises applying one or more positive voltage pulses to one of a first input terminal coupled to the heating element and a second input terminal coupled to the heating element.

22. 22. The method of claim 21 , wherein setting the given portion of the phase change material to the second phase comprises applying one or more positive voltage pulses to both the first input terminal coupled to the heating element and the second input terminal coupled to the heating element.

23. 1. A method comprising: measuring a current at an enable output terminal of a first logic device of a first logic stage of the two or more logic stages; determining whether the measured current at the enable output terminal of the first logic device of the first logic stage exceeds a specified threshold enable current; triggering an enable input terminal of a second logic device of a second logic stage of the two or more logic stages in response to determining that the measured current at the enable output terminal of the first logic device of the first logic stage exceeds the specified threshold enable current; Including, the second logic device comprises a phase change material based logic gate including a phase change material and a heating element interconnected such that an output terminal is in a true logic state when one of a first input terminal and a second input terminal coupled to the heating element is exclusively in a true logic state; method.

24. 24. The method of claim 23, wherein triggering the enable input terminal of the second logic device comprises controlling the application of heat to the given portion of the phase change material from an additional heating element coupled to the given portion of the phase change material.

25. 24. The method of claim 23, wherein the phase change material in a first phase has a first resistivity and the phase change material in a second phase has a second resistivity higher than the first resistivity, and wherein triggering the enable input terminal of the second logic device comprises resetting the given portion of the phase change material to the second phase.

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