Method for manufacturing a semiconductor device and method for inspecting a semiconductor device.

Abstract

To provide a technique capable of identifying the type of lamination defects.SOLUTION: A method of manufacturing a semiconductor device 1 that includes a pn diode structure in an epitaxial layer 104 laminated on a semiconductor substrate 102 includes an identification step of identifying the type of lamination defects formed in the epitaxial layer. The identification step includes: a first step S1 of energizing through the pn diode structure; a second step S2 of, after the first step, measuring electrical characteristic values depending on the lamination defects; a third step S3 of, after the second step, energizing through the pn diode structure; and a fourth step S4 of, after the third step, measuring electrical characteristic values depending on the lamination defects.SELECTED DRAWING: Figure 13

Description

Technical Field

[0001] The technology disclosed in this specification relates to a method for manufacturing a semiconductor device and a method for inspecting a semiconductor device.

Background Art

[0002] Certain types of semiconductor devices may include a pn diode structure in an epitaxial layer stacked on a semiconductor substrate. For example, a type of semiconductor device called a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) includes a pn diode structure composed of an n-type drift layer and a p-type body layer in an epitaxial layer stacked on a semiconductor substrate. When current flows through such a pn diode structure, it is known that stacking defects are formed in the epitaxial layer due to the recombination energy of electrons and holes. The formation of stacking defects increases the on-resistance of the semiconductor device.

[0003] Patent Document 1 discloses a method of energizing through a pn diode structure until the forward resistance value saturates and detecting the presence or absence of stacking defects from the degree of change in the forward resistance value before and after energization.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] There are several types of stacking faults, including triangular faults, band faults, and U-shaped faults. Triangular faults form over a relatively small area within the epitaxial layer, so their impact on increasing the on-resistance of semiconductor devices is small. On the other hand, band faults and U-shaped faults form over a relatively large area within the epitaxial layer, so their impact on increasing the on-resistance of semiconductor devices is large. In particular, band faults and U-shaped faults can become large in area depending on their location within the epitaxial layer, potentially significantly increasing the on-resistance of semiconductor devices. Therefore, manufacturing processes that may result in the formation of band faults and U-shaped faults need to be improved.

[0006] While the technology described in Patent Document 1 can detect the presence or absence of stacking faults, it cannot identify the type of stacking fault. This specification provides a technology that can identify the type of stacking fault. [Means for solving the problem]

[0007] This specification can provide a method for manufacturing a semiconductor device including a pn diode structure within an epitaxial layer stacked on a semiconductor substrate. This manufacturing method may include a identification step for identifying the type of stacking fault formed in the epitaxial layer. The identification step may include a first step of energizing the pn diode structure, a second step of measuring an electrical characteristic value dependent on the stacking fault after the first step, a third step of energizing the pn diode structure after the second step, and a fourth step of measuring an electrical characteristic value dependent on the stacking fault after the third step. The energizing in the first and third steps may be performed consecutively. That is, the measurement in the second step may be performed during continuous energizing, with the period before the measurement in the second step being the first step and the period after the measurement in the second step being the third step.

[0008] This specification can also provide a method for inspecting a semiconductor device which includes a pn diode structure in an epitaxial layer stacked on a semiconductor substrate. This inspection method may include a identification step for identifying the type of stacking fault formed in the epitaxial layer. The identification step may include a first step of applying current through the pn diode structure; a second step, after the first step, of measuring an electrical characteristic value dependent on the stacking fault; a third step, after the second step, of applying current through the pn diode structure; and a fourth step, after the third step, of measuring an electrical characteristic value dependent on the stacking fault. The application of current in the first and third steps may be performed consecutively. That is, the measurement in the second step may be performed during continuous application of current, with the period before the measurement in the second step being the first step and the period after the measurement in the second step being the third step.

[0009] In the above-described method for manufacturing and inspecting a semiconductor device, when current is applied in the first step, the stacking fault begins to form within the epitaxial layer. The time from the start of the stacking fault formation until its expansion stops varies depending on the type of stacking fault. According to the above manufacturing method and inspection method, if there is a significant difference between the electrical characteristic value measured in the second step and the electrical characteristic value measured in the fourth step, it is possible to identify the existence of a type of stacking fault that does not stop expanding when current is applied in the first step and continues to expand when current is applied in the third step. In this way, the above-described method for manufacturing and inspecting a semiconductor device makes it possible to identify at least some of the types of stacking faults. [Brief explanation of the drawing]

[0010] [Figure 1] This is a plan view of a semiconductor layer schematically showing the planar layout of the active region and the termination region of the semiconductor device disclosed herein. [Figure 2] This section schematically shows a cross-sectional view of a key part of the semiconductor layer of the semiconductor device disclosed herein, and corresponds to the line II-II in Figure 1. [Figure 3]This figure schematically illustrates stacking faults formed in the semiconductor layer of a semiconductor device disclosed herein. [Figure 4] This figure schematically shows the state immediately after the expansion of a triangular defect in the drift layer begins when current is applied through the pn diode structure incorporated in the semiconductor device disclosed herein. [Figure 5] This figure schematically shows the expansion of a triangular defect in the drift layer when current is applied through a pn diode structure incorporated in the semiconductor device disclosed herein. [Figure 6] This figure schematically shows the state after the expansion of triangular defects in the drift layer has stopped when current is applied through the pn diode structure incorporated in the semiconductor device disclosed herein. [Figure 7] This figure schematically shows the shape of a triangular defect formed in the drift layer of a semiconductor device disclosed herein, when viewed from a plan view. [Figure 8] This figure shows the relationship between the expansion rate of stacking faults and the temperature of the semiconductor layer at different current densities when current is passed through a pn diode structure incorporated in the semiconductor device disclosed herein. [Figure 9] This figure shows the relationship between the energizing time and the on-resistance fluctuation when current is passed through a pn diode structure embedded in the semiconductor device disclosed herein. [Figure 10] Figure 9 schematically shows the stacking faults formed in the semiconductor layer during the energizing time t1. [Figure 11] Figure 9 schematically shows the stacking faults formed in the semiconductor layer during the energizing time t2. [Figure 12] Figure 9 schematically shows the stacking faults formed in the semiconductor layer during the energizing time t3. [Figure 13] This figure shows a flow diagram of a part of the method for manufacturing a semiconductor device disclosed herein. [Modes for carrying out the invention]

[0011] (Configuration of semiconductor device 1) As shown in Figure 1, the semiconductor device 1 is a semiconductor chip composed of a semiconductor layer 10. When viewed from a direction perpendicular to its upper surface (hereinafter referred to as "when viewed from above"), the semiconductor layer 10 includes an active region 10A and a termination region 10B that encircles the active region 10A. The active region 10A is a region in the semiconductor layer 10 through which current flows, as will be described later, and is a region in which a specific device structure is formed. The termination region 10B is a region for ensuring the breakdown voltage of the semiconductor device 1, and is, for example, a region in which a guard ring structure or a resurf structure is formed. Hereinafter, the thickness direction of the semiconductor layer 10 will be referred to as the z direction, the direction parallel to the upper surface of the semiconductor layer 10 will be referred to as the x direction, and the direction perpendicular to the x and z directions will be referred to as the y direction.

[0012] As shown in Figure 2, the semiconductor device 1 is a power semiconductor element called a MOSFET, and comprises a semiconductor layer 10, a drain electrode 22 covering the lower surface 10b of the semiconductor layer 10, a source electrode 24 covering the upper surface 10a of the semiconductor layer 10, and a plurality of trench gates 30 provided in trenches extending from the upper surface 10a of the semiconductor layer 10 toward the interior. Each of the plurality of trench gates 30 extends along the y-direction when the semiconductor layer 10 is viewed from above. The plurality of trench gates 30 are also spaced apart from each other along the x-direction, forming a striped layout. Note that the striped layout of the plurality of trench gates 30 is just one example, and other layouts may be adopted.

[0013] The semiconductor layer 10 comprises a semiconductor substrate 102 and an epitaxial layer 104 laminated on the semiconductor substrate 102. These semiconductor substrate 102 and epitaxial layer 104 are not particularly limited, but may be, for example, 4H silicon carbide (4H-SiC). The crystal plane of the upper surface 10a of the semiconductor layer 10, i.e., the upper surface 10a of the epitaxial layer 104, is tilted by an off-angle in the (11-20) direction with respect to the (0001) Si plane. The off-angle is not particularly limited, but may be, for example, 4°. The semiconductor layer 10 is n + A drain layer 11 of type n -The drift layer 12 of the type, the p-type body layer 13, and p + type body contact region 14, and n + type source region 15, and has.

[0014] The drain layer 11 is provided in the lower layer portion of the semiconductor layer 10 and is disposed at a position exposed to the lower surface 10b of the semiconductor layer 10. The drain layer 11 is the semiconductor substrate 102 and is also the underlying substrate for epitaxial growth of the epitaxial layer 104. The drain layer 11 makes ohmic contact with the drain electrode 22 that coats the lower surface 10b of the semiconductor layer 10.

[0015] The drift layer 12 is provided between the drain layer 11 and the body layer 13. The drift layer 12 is formed by crystal growth from the surface of the drain layer 11 using epitaxial growth technology.

[0016] The body layer 13 is provided on the drift layer 12 and is disposed in the upper layer portion of the semiconductor layer 10. The body layer 13 is not particularly limited, but for example, it may be formed by introducing p-type impurity ions into the upper layer portion of the semiconductor layer 10 using ion implantation technology. Thus, in the semiconductor device 1, a pn diode structure composed of a p-type body layer 13 and an n-type drift layer 12 is built in the epitaxial layer 104.

[0017] The body contact region 14 is provided on the body layer 13, is disposed in the upper layer portion of the semiconductor layer 10, and is disposed at a position exposed to the upper surface 10a of the semiconductor layer 10. The body contact region 14 is not particularly limited, but for example, it may be formed by introducing p-type impurity ions into the upper layer portion of the semiconductor layer 10 using ion implantation technology. The body contact region 14 makes ohmic contact with the source electrode 24 that coats the upper surface 10a of the semiconductor layer 10.

[0018] The source region 15 is provided on the body layer 13, positioned in the upper part of the semiconductor layer 10, and exposed to the upper surface 10a of the semiconductor layer 10. The source region 15 is separated from the drift layer 12 by the body layer 13. The source region 15 is in contact with the side surface of the trench gate 30. The source region 15 is formed by introducing nitrogen or phosphorus into the surface of the semiconductor layer 10 using ion implantation technology. The source region 15 is in ohmic contact with the source electrode 24 that covers the upper surface 10a of the semiconductor layer 10.

[0019] The trench gate 30 is filled in a trench formed in the upper part of the semiconductor layer 10, and penetrates the source region 15 and the body layer 13 to reach the drift layer 12. The trench gate 30 has a gate insulating film 32 and a gate electrode 34 that faces the semiconductor layer 10 via the gate insulating film 32.

[0020] Thus, the semiconductor device 1 is configured as a vertical MOSFET and can perform transistor operation, controlling the current flowing from the drain electrode 22 to the source electrode 24 by the voltage applied to the gate electrode 34. Furthermore, the semiconductor device 1 has a pn diode structure composed of a body layer 13 and a drift layer 12, and this pn diode structure can be operated as a freewheeling diode. In the mode in which the pn diode structure operates, a voltage is applied between the drain electrode 22 and the source electrode 24 such that the source electrode 24 is more positive than the drain electrode 22. At this time, holes are injected from the body layer 13 into the drift layer 12, electrons are injected from the drain layer 11 into the drift layer 12, and current flows from the source electrode 24 to the drain electrode 22.

[0021] (Formation and expansion of stacking faults) When current is applied through the pn diode structure built into the semiconductor device 1, stacking faults are formed within the drift layer 12 by the recombination energy of holes and electrons injected into the drift layer 12. Figure 3 shows three types of stacking faults 2, 4, and 6 that are formed when current is applied through the pn diode structure. Since stacking faults 2, 4, and 6 are formed by the recombination energy of holes and electrons, they are formed within the active region 10A of the semiconductor layer 10 where the pn diode structure exists. Figure 3 shows three types of stacking faults: triangular fault 2, band fault 4, and U-shaped fault 6.

[0022] Triangular defects 2 are formed by extending from a basal plane dislocation (BPD) present in the semiconductor substrate 102 or a basal plane dislocation (BPD) present in the epitaxial layer 104 to a size corresponding to the thickness of the drift layer 12. Band defects 4 are formed by extending from a basal plane dislocation (BPD) present in the semiconductor substrate 102 along a direction perpendicular to the step flow direction (in this example, the (11-20) direction, which is the x-direction) (i.e., the y-direction) to the edge of the active region 10A. The direction in which band defects 4 extend is one of the directions in the y-direction, and in the example in Figure 3, an example extending downward in the y-direction is shown. U-shaped defects 6 are formed by extending from a half-loop dislocation present in the epitaxial layer 104 within the half-loop.

[0023] Triangular defects 2 are relatively small because their expansion stops at a size corresponding to the thickness of the drift layer 12. On the other hand, band defects 4 can be large because, depending on the position of the basal plane dislocation (BPD), they may traverse a large portion of the active region 10A. U-shaped defects 6 can also be formed in large sizes depending on the size of the half-loop dislocation. For this reason, the manufacturing process in which band defects 4 and U-shaped defects 6 are formed needs to be improved.

[0024] (Estimated expansion time for triangular defects) Figures 4 to 6 show the changes in the state of triangular defect 2 from the start of expansion to its cessation. Figure 4 shows the state of triangular defect 2 immediately after the start of expansion. Figure 5 shows the state of triangular defect 2 during the expansion of the triangular defect 2. Figure 6 shows the state of triangular defect 2 after the expansion of the triangular defect 2 has stopped. In Figures 4 to 6, the base plane (0001) is exposed and shown. The base plane (0001) is tilted with respect to the surface of the semiconductor substrate 102 by an off-angle θ.

[0025] As shown in Figure 4, a basal plane dislocation (BPD) is present within the semiconductor substrate 102. When current is applied through the pn diode structure built into the semiconductor device 1, the recombination energy of the injected holes and electrons causes the basal plane dislocation (BPD) to extend within the basal plane of the epitaxial layer 104, and the triangular defect 2 expands within the basal plane from the basal plane dislocation (BPD) of the epitaxial layer 104. The basal plane dislocation (BPD) extending within the basal plane of the epitaxial layer 104 is parallel to the step flow direction (in this example, the (11-20) direction, which is the x-direction) when the epitaxial layer 104 is viewed from above. In the epitaxial layer 104 made of 4H-SiC, the triangular defect 2 expands within a 60° range from the basal plane dislocation (BPD) of the epitaxial layer 104. As shown in Figure 5, the expansion of the triangular defect 2 continues with increasing current application time. As shown in Figure 6, the triangular defect 2 expands within the base plane to a size corresponding to the thickness Dt of the drift layer 12 and then stops.

[0026] Figure 7 shows the shape of the triangular defect 2 when the semiconductor layer 10 is viewed from above. The triangular defect 2 takes the shape of a right triangle when the semiconductor layer 10 is viewed from above. The triangular defect 2 is formed by extending from the position of a basal plane dislocation (BPD), which is the 60° vertex, to the 30° vertex. In this specification, the length between the start and end points when the semiconductor layer 10 is viewed from above, that is, the length of the hypotenuse of the right triangle, is called the extension length of the triangular defect 2. The extension length of the triangular defect 2 can be expressed as (Dt / tanθ) × 2, where Dt is the length of the drift layer 12 and θ is the off-angle.

[0027] In this specification, the rate at which triangular defects 2 expand along the direction connecting the starting and ending points when the semiconductor layer 10 is viewed in plan view is referred to as the expansion rate of triangular defects 2. As shown in Figure 8, the expansion rate of triangular defects 2 depends on the current density when current is passed through the pn diode structure and the temperature of the semiconductor layer 10. The higher the current density, the greater the expansion rate, and the higher the temperature of the semiconductor layer 10, the greater the expansion rate. Such expansion rates can be determined from test samples of the same type of semiconductor device, for example, by using observation by photoluminescence.

[0028] The estimated expansion time of triangular defect 2, from the start of expansion to its cessation, can be calculated by dividing the expansion length of triangular defect 2 by the expansion velocity of triangular defect 2.

[0029] (Variation in power-on time and on-resistance) Figure 9 shows the change in the on-resistance of semiconductor device 1 when current is passed through the pn diode structure of semiconductor device 1. When current is passed through the pn diode structure, stacking faults are formed in the drift layer 12, and the on-resistance of semiconductor device 1 increases. Here, the on-resistance of semiconductor device 1 is substituted with the on-voltage Vd when semiconductor device 1 is operating as a transistor. Instead of the on-voltage of semiconductor device 1, the forward voltage when semiconductor device 1 is operating as a diode may be used. Both of these electrical characteristic values ​​increase as the electrical resistance of the drift layer 12 increases, depending on the area of ​​the stacking faults. Alternatively, other electrical characteristic values ​​that depend on the area of ​​the stacking faults formed in the drift layer 12 may be used.

[0030] The broken line L1 in Figure 9 shows the variation in on-resistance when only triangular defects 2 are formed. The broken line L2 in Figure 9 shows the variation in on-resistance when triangular defects 2 and band defects 4 are formed. The same applies when a U-shaped defect 6 (see Figure 3) is formed instead of band defects 4. Furthermore, broken lines L1 and L2 illustrate the case when the same number of triangular defects 2 are formed. Figures 10 to 12 show the stacking fault state at each time t1 to t3 for broken line L2 when triangular defects 2 and band defects 4 are formed.

[0031] The energizing time t1 is the time from when the expansion of the triangular defect 2 begins until it stops. As shown by the broken line L1, if only triangular defects 2 are formed, the increase in the on-resistance of the semiconductor device 1 saturates at energizing time t1. Note that the amount of fluctuation in on-resistance varies depending on the number of triangular defects 2 formed, but if only triangular defects 2 are formed, the increase in the on-resistance of the semiconductor device 1 saturates at energizing time t1. This energizing time t1 is a time that can be estimated using the expansion estimation time described above.

[0032] When triangular defects 2 and band-shaped defects 4 are formed, the band-shaped defect 4 is in the process of expanding at energizing time t1 (see Figure 10). As shown by the broken line L2, the expansion of the band-shaped defect 4 continues at energizing time t2 (see Figure 11), and the increase in the on-resistance of the semiconductor device 1 also continues. As shown by the broken line L2, at energizing time t3, the expansion of the band-shaped defect 4 stops as it reaches the edge of the active region 10A (see Figure 12), and the increase in the on-resistance of the semiconductor device 1 saturates. Depending on the position and direction of expansion of the band-shaped defect 4, the energizing time at which the increase in on-resistance saturates may be shorter or longer than the energizing time t2. Also, the energizing time at which the increase in on-resistance saturates varies depending on the number of band-shaped defects 4 that are formed.

[0033] As described above, when only triangular defects 2 are formed, the increase in the on-resistance of the semiconductor device 1 saturates at energizing time t1, which is an energizing time that can be estimated by the extended estimation time. When stacking faults of other types besides triangular defects 2, such as band defects 4 and U-shaped defects 6, are formed in addition to triangular defects 2, the increase in the on-resistance of the semiconductor device 1 saturates at energizing time longer than energizing time t1.

[0034] (Method of manufacturing semiconductor devices) As explained above, the energization time at which the increase in the on-resistance of semiconductor device 1 saturates when current is passed through the pn diode structure of semiconductor device 1 depends on the type of stacking fault. In particular, triangular fault 2 is estimated to cause the increase in on-resistance to saturate at the extended estimation time described above. By utilizing this knowledge, the type of stacking fault that is formed can be identified.

[0035] Figure 13 shows a partial flow of the manufacturing method for the semiconductor device 1. This manufacturing flow is an identification step that identifies the type of stacking fault in the drift layer 12, and may be performed in the final stage of manufacturing the semiconductor device 1, for example, at the pre-shipment inspection stage.

[0036] First, in step S1, current is applied through the pn diode structure of the semiconductor device 1. The current application time in step S1 is set to the extended estimated time (corresponding to time t1 in Figure 9).

[0037] Next, in step S2, the on-resistance of semiconductor device 1 is measured. As described above, the on-resistance of semiconductor device 1 is substituted by the on-voltage of semiconductor device 1. Let Vd(t1) be the on-voltage measured in step S2.

[0038] Next, in step S3, current is applied through the pn diode structure of the semiconductor device 1. The current application time in step S3 is set to a time when the stripe defects and U-shaped defects have sufficiently expanded, assuming that they are formed (for example, corresponding to time t2 onwards in Figure 9).

[0039] Next, in step S4, the on-resistance of semiconductor device 1 is measured. The on-voltage measured in step S4 is denoted as Vd(t2).

[0040] Next, in step S5, it is determined whether the on-voltage Vd(t2) measured in step S4 is greater than the on-voltage Vd(t1) measured in step S2. If Vd(t2) is not greater than Vd(t1), it is determined that only triangular defects have been formed, since the on-resistance of the semiconductor device 1 has saturated at time t1 (step S6). On the other hand, if Vd(t2) is greater than Vd(t1), it is determined that the on-resistance of the semiconductor device 1 has continued to increase after time t1, and the expansion of stacking faults of a type other than triangular defects, such as band defects and U-shaped defects, has continued, so it is determined that at least one of band defects and U-shaped defects has been formed. Note that, considering the case where the expansion of triangular defects has not completely stopped at time t1, the determination in step S5 may be changed to whether the difference between Vd(t2) and Vd(t1) is greater than the margin voltage. In this way, according to the manufacturing method in Figure 13, it is possible to identify the presence or absence of stacking faults of a type other than triangular defects, and this can be fed back into improving the manufacturing process. In the above, while band defects and U-shaped defects were given as examples of stacking faults other than triangular defects, the term "stacking faults other than triangular defects" here includes various types of stacking faults in which defect expansion does not saturate at time t1.

[0041] The features of the technology disclosed herein are summarized below. Note that the technical elements described below are independent elements that exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing.

[0042] (Feature 1) A method for manufacturing a semiconductor device (1) which includes a pn diode structure within an epitaxial layer (104) stacked on a semiconductor substrate (102), The system includes a process for identifying the type of stacking fault formed within the epitaxial layer, The aforementioned specific step is, The first step (S1) involves energizing through the aforementioned pn diode structure, Following the first step, a second step (S2) is performed in which the electrical characteristic values ​​dependent on the stacking faults are measured, Following the second step, a third step (S3) is performed in which current is passed through the pn diode structure, A method for manufacturing a semiconductor device, comprising: a fourth step (S4) of measuring the stacking fault-dependent electrical characteristic value after the third step.

[0043] (Feature 2) The method for manufacturing a semiconductor device according to Feature 1, wherein the energizing time in the first step is set to the estimated expansion time from when the expansion of the triangular defect (2) among the stacking faults formed in the epitaxial layer begins until it is estimated to have stopped.

[0044] (Feature 3) The epitaxial layer has an n-type drift layer (12) and a p-type body layer (13). The method for manufacturing a semiconductor device according to feature 2, wherein the expansion estimation time is calculated by dividing the expansion length of the triangular defect, which is calculated from the off-angle (θ) of the epitaxial layer and the thickness (Dt) of the drift layer, by the expansion rate of the stacking fault.

[0045] (Feature 4) The method for manufacturing a semiconductor device according to feature 3, wherein the expansion rate of the stacking fault is set based on the current density during energization and the temperature of the epitaxial layer.

[0046] (Feature 5) A method for manufacturing a semiconductor device according to any one of features 1 to 4, wherein the semiconductor substrate is silicon carbide.

[0047] (Feature 6) A method for inspecting a semiconductor device (1) which includes a pn diode structure within an epitaxial layer (104) stacked on a semiconductor substrate (102), The system includes a process for identifying the type of stacking fault formed within the epitaxial layer, The aforementioned specific step is, The first step (S1) involves energizing through the aforementioned pn diode structure, Following the first step, a second step (S2) is performed in which the electrical characteristic values ​​dependent on the stacking faults are measured, Following the second step, a third step (S3) is performed in which current is passed through the pn diode structure, A method for inspecting a semiconductor device, comprising: a fourth step (S4) of measuring an electrical characteristic value dependent on the stacking fault, after the third step.

[0048] Although specific examples of the present invention have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. Furthermore, the technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technologies illustrated in this specification or drawings can achieve multiple objectives simultaneously, and achieving even one of these objectives itself constitutes technical usefulness. [Explanation of Symbols]

[0049] 1: Semiconductor device, 2: Triangular defect, 4: Band defect, 6: U-shaped defect, 10: Semiconductor layer, 11: Drain layer, 12: Drift layer, 13: Body layer, 14: Body contact region, 15: Source region, 22: Drain electrode, 24: Source electrode, 30: Trench gate, 102: Semiconductor substrate, 104: Epitaxial layer

Claims

1. A method for manufacturing a semiconductor device (1) which includes a pn diode structure in an epitaxial layer (104) stacked on a semiconductor substrate (102), The system includes a process for identifying the type of stacking fault formed within the epitaxial layer, The aforementioned specific step is, The first step (S1) involves energizing through the aforementioned pn diode structure, Following the first step, a second step (S2) is performed in which the electrical characteristic values ​​dependent on the stacking faults are measured, Following the second step, a third step (S3) is performed, in which current is passed through the pn diode structure. The process includes, after the third step, a fourth step (S4) of measuring the electrical characteristic values ​​that depend on the stacking faults, A method for manufacturing a semiconductor device, wherein the energizing time in the first step is set to the estimated expansion time from when the expansion of the triangular defect (2) among the stacking faults formed in the epitaxial layer begins until it is estimated to have stopped.

2. The epitaxial layer has an n-type drift layer (12) and a p-type body layer (13). The method for manufacturing a semiconductor device according to claim 1, wherein the expansion estimation time is calculated by dividing the expansion length of the triangular defect, which is calculated from the off-angle (θ) of the epitaxial layer and the thickness (Dt) of the drift layer, by the expansion rate of the stacking fault.

3. The method for manufacturing a semiconductor device according to claim 2, wherein the expansion rate of the stacking fault is set based on the current density during energization and the temperature of the epitaxial layer.

4. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the semiconductor substrate is silicon carbide.

5. A method for inspecting a semiconductor device (1) which includes a pn diode structure in an epitaxial layer (104) stacked on a semiconductor substrate (102), The system includes a process for identifying the type of stacking fault formed within the epitaxial layer, The aforementioned specific step is, The first step (S1) involves energizing through the aforementioned pn diode structure, Following the first step, a second step (S2) is performed in which the electrical characteristic values ​​dependent on the stacking faults are measured, Following the second step, a third step (S3) is performed, in which current is passed through the pn diode structure. The process includes, after the third step, a fourth step (S4) of measuring the electrical characteristic values ​​that depend on the stacking faults, A method for inspecting a semiconductor device, wherein the energizing time in the first step is set to the estimated expansion time from when the expansion of the triangular defect (2) among the stacking faults formed in the epitaxial layer begins until it is estimated to have stopped.

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