Methods for manufacturing semiconductor substrates and semiconductor devices

Abstract

To provide a semiconductor substrate, and a method for manufacturing a semiconductor device that reduces cracks and defects occurring in a main body.SOLUTION: A semiconductor substrate 10 comprises a main substrate 1, a seed section SD positioned above the main substrate 1, and a first conductor section 8F and a second semiconductor section 8S arranged in the first direction (Y-direction), the first semiconductor section and the second semiconductor section are in contact with the seed section SD, and the seed section SD has the first direction (Y-direction) as its longitudinal direction. A hollow space VD is positioned between the main substrate 1, the first semiconductor section 8F, and the second semiconductor section.SELECTED DRAWING: Figure 2A

Description

Technical Field

[0001] The present disclosure relates to a semiconductor substrate and the like.

Background Art

[0002] Patent Document 1 discloses a method of forming a floating semiconductor device layer (including an active layer) above a main substrate such as a silicon substrate using the ELO (Epitaxial Lateral Overgrowth) method.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] The semiconductor substrate according to the present disclosure includes a main substrate, a seed portion located above the main substrate, and first and second semiconductor portions arranged in a first direction. The first and second semiconductor portions are in contact with the seed portion. The seed portion has the first direction as its longitudinal direction, and a hollow portion is located between the main substrate and the first and second semiconductor portions.

Brief Description of the Drawings

[0005] [Figure 1] It is a plan view showing the configuration of the semiconductor substrate according to the present embodiment. [Figure 2A] It is a cross-sectional view showing the configuration of the semiconductor substrate according to the present embodiment. [Figure 2B] It is a cross-sectional view showing the configuration of the semiconductor substrate according to the present embodiment. [Figure 3] It is a plan view showing an example of the manufacturing method of the semiconductor substrate according to the present embodiment. [Figure 4] It is a flowchart showing an example of the manufacturing method of the semiconductor substrate according to the present embodiment [Figure 5]This is a block diagram showing an example of a semiconductor substrate manufacturing apparatus according to this embodiment. [Figure 6] This is a flowchart showing an example of a method for manufacturing a semiconductor device according to this embodiment. [Figure 7] This is a block diagram showing an example of a semiconductor device manufacturing apparatus according to this embodiment. [Figure 8] This is a schematic diagram showing the configuration of the electronic device according to this embodiment. [Figure 9] This is a plan view showing the configuration of a semiconductor substrate according to Example 1. [Figure 10] This is a cross-sectional view taken along the arrow cc in Figure 9. [Figure 11] This is a cross-sectional view taken along the arrow dd in Figure 9. [Figure 12] This is a plan view showing the semiconductor device framing process in Example 1. [Figure 13] This is a cross-sectional view showing the semiconductor device framing process in Example 1. [Figure 14A] This is a cross-sectional view showing an alternative configuration of the semiconductor substrate according to Example 1. [Figure 14B] This is a cross-sectional view showing an alternative configuration of the semiconductor substrate according to Example 1. [Figure 15] This is a plan view showing an alternative configuration of the semiconductor substrate according to Example 1. [Figure 16] This is a flowchart showing the method for manufacturing the template substrate in Example 1. [Figure 17] Figure 16 is a cross-sectional view showing the manufacturing method. [Figure 18] This is a flowchart showing an alternative method for manufacturing the template substrate in Example 1. [Figure 19] Figure 18 is a cross-sectional view showing the manufacturing method. [Figure 20] This is a flowchart showing the method for manufacturing a semiconductor substrate in Example 1. [Figure 21] This is a cross-sectional view showing the manufacturing method of Figure 20. [Figure 22] This is a plan view showing an alternative configuration of the semiconductor substrate according to Example 1. [Figure 23] It is a plan view showing another configuration of the semiconductor substrate according to Example 1. [Figure 24] It is a cross-sectional view showing another manufacturing method of the semiconductor substrate in Example 1. [Figure 25] It is a plan view showing the configuration of the semiconductor substrate according to Example 2. [Figure 26] It is a cross-sectional view showing the configuration of the semiconductor substrate according to Example 2. [Figure 27] It is a cross-sectional view showing the configuration of the semiconductor substrate according to Example 2. [Figure 28] It is a schematic cross-sectional view showing the configuration of Example 4. [Figure 29] It is a cross-sectional view showing an application example of Example 4 to an electronic device. [Figure 30] It is a schematic cross-sectional view showing the configuration of Example 5. [Figure 31] It is a plan view showing the semiconductor substrate of Example 6. [Figure 32] It is a cross-section showing the semiconductor substrate of Example 6.

MODE FOR CARRYING OUT THE INVENTION

[0006] 〔Semiconductor substrate〕 FIG. 1 is a plan view showing the configurations of the first and second semiconductor portions of the semiconductor substrate according to the present embodiment. FIGS. 2A and 2B are cross-sectional views showing the configuration of the semiconductor substrate according to the present embodiment. As shown in FIGS. 1, 2A, and 2B, the semiconductor substrate 10 (semiconductor wafer) according to the present embodiment includes a main substrate 1, a seed portion SD located above the main substrate 1, and first and second semiconductor portions 8F and 8S arranged in the first direction (Y direction), and the first semiconductor portion 8F and the second semiconductor portion 8S are in contact with the seed portion SD. The seed portion SD has the Y direction as its longitudinal direction. A hollow portion (void portion) VD is located between the main substrate 1 and the first semiconductor portion 8F and the second semiconductor portion 8S. In the present disclosure, the first semiconductor portion 8F and the second semiconductor portion 8S may be first and second semiconductor layers 8F and 8S formed in a layer shape.

[0007] The upper surface 1f of the main substrate is provided with a protruding portion 1Q, and the seed portion SD is located on the protruding portion 1Q. Above the main substrate 1, a mask pattern 6 having an opening K and a mask portion 5 is provided. In a plan view, the opening K and the seed portion SD overlap, and a hollow portion VD is located between the first and second semiconductor portions 8F and 8S and the mask portion 5.

[0008] The first semiconductor section 8F includes a first floating section P1 facing the main substrate 1 via a hollow section VD, and the second semiconductor section 8S includes a second floating section P2 facing the main substrate 1 via a hollow section VD, with the first floating section P1 and the second floating section P2 being separated. The first semiconductor section 8F includes a third floating section P3 that is paired with the first floating section P1, and the first floating section P1 and the third floating section P3 are aligned in a second direction (X direction) perpendicular to the first direction (Y direction) in a floating state (without a support member on the lower side, in contact with the hollow section). The second semiconductor section 8S includes a fourth floating section P4 that is paired with the second floating section P2, and the second floating section P2 and the fourth floating section P4 are aligned in the X direction in a floating state.

[0009] The first semiconductor section 8F includes a first base section BF located on the seed section SD, and the first base section BF is located between the first and third floating sections P1 and P3 and connected to the first and third floating sections P1 and P3. The second semiconductor section 8S includes a second base section BS located on the seed section SD, and the second base section BS is located between the second and fourth floating sections P2 and P4 and connected to the second and fourth floating sections P2 and P4.

[0010] The first floating section P1 includes a tether section T1 connected to the first base section BF and a main body section H1 connected to the tether section T1, wherein the length of the tether section T1 in the Y direction is smaller than that of the main body section H1. The third floating section P3 includes a tether section T3 connected to the first base section BF and a main body section H3 connected to the tether section T3, wherein the length of the tether section T3 in the Y direction is smaller than that of the main body section H3. However, the configuration of the tether section T1 is not limited to this. The tether section T1 may have the same length in the Y direction as the main body section H1 and a thickness (size in the Z direction) smaller than that of the main body section H1. Furthermore, the tether section T1 may have a length in the Y direction smaller than that of the main body section H1 and a thickness smaller than that of the main body section H1.

[0011] The semiconductor substrate 10 includes a third conductor portion 8T located on the seed portion SD, and the first base portion BF and the second base portion BS are connected via the third semiconductor portion 8T. In this disclosure, the third conductor portion 8T is formed in layers and may hereafter be referred to as the third conductor layer 8T.

[0012] In the semiconductor substrate 10, multiple layered components are stacked on the main substrate 1, and the stacking direction can be "upward." Viewing the semiconductor substrate 10 from a line of sight parallel to the normal direction of the semiconductor substrate 10 can be referred to as a "planar view." A semiconductor substrate refers to a substrate containing a semiconductor portion, and the main substrate 1 may be semiconductor or non-semiconductor. The main substrate 1, mask pattern 6, and layered first seed portion S1 are sometimes collectively referred to as the template substrate 7.

[0013] The first and second semiconductor sections 8F and 8S include a nitride semiconductor. Nitride semiconductors can be represented, for example, as AlxGayInzN (0≦x≦1;0≦y≦1;0≦z≦1;x+y+z=1), and specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). GaN-based semiconductors are semiconductors containing gallium atoms (Ga) and nitrogen atoms (N), and examples include GaN, AlGaN, AlGaInN, InGaN, etc. The first and second semiconductor sections 8F and 8S may be doped (e.g., n-type including a donor) or undoped.

[0014] The first and second semiconductor sections 8F and 8S can be formed using the ELO (Epitaxial Lateral Overgrowth) method. In the ELO method, for example, as shown in Figures 2A and 2B, a GaN-based semiconductor and a different substrate with a different lattice constant are used as the main substrate 1, a nitride semiconductor is used for the seed section SD, and an inorganic compound film is used for the mask section 5. The first semiconductor section 8F containing the GaN-based semiconductor can be grown laterally (X direction) from the first base section BF above (in the air) the mask section 5. In this case, the thickness direction (Z direction) of the first semiconductor section 8F is the GaN-based crystal <0001> The orientation (c-axis direction) and longitudinal shape of the seed portion SD and opening K can be such that the longitudinal direction (first direction, Y direction) of the seed portion SD and opening K is the <1-100> direction (m-axis direction) of the GaN-based crystal, and the width direction (second direction, X direction) of the seed portion SD and opening K is the <11-20> direction (a-axis direction) of the GaN-based crystal. The layer formed by the ELO method (including the first and second semiconductor portions 8F and 8S, etc.) is sometimes referred to as the ELO semiconductor portion 8.

[0015] The first semiconductor portion 8F formed by the ELO method includes a low-dislocation portion (first floating portion P1) which overlaps with the mask portion 5 in a plan view and has relatively few through-dislocations, and a first base portion BF which overlaps with the seed SD of the aperture K in a plan view and has relatively more through-dislocations than the low-dislocation portion. The low-dislocation portion may have a configuration in which the non-through-dislocation density is greater than the through-dislocation density. If a layered active portion (hereinafter simply referred to as the active layer) is included above the first semiconductor portion 8F, for example, the light-emitting region of the active layer can be provided so as to overlap with the low-dislocation portion in a plan view.

[0016] A penetrating dislocation is a dislocation (defect) that extends from the bottom surface or interior of the first semiconductor portion 8F to its surface or surface layer along the thickness direction (Z direction) of the first semiconductor portion 8F. Penetrating dislocations can be observed by performing a CL (Cathode luminescence) measurement on the surface layer (parallel to the c-plane) of the first semiconductor portion 8F. Non-penetrating dislocations are dislocations that are measured by CL in a cross-section along a plane parallel to the thickness direction (e.g., the m-plane), and are mainly basal plane (c-plane) dislocations.

[0017] At least the first and second semiconductor sections 8F and 8S are provided with layered functional sections 9. The functional layer 9 (hereinafter also simply referred to as the functional layer) may be a single layer or a laminate. The functional layer 9 may have at least one of the following functions: function as a component of a semiconductor device, protection from external forces, protection from static electricity, protection from the intrusion of foreign substances such as water and oxygen, protection from etchants, optical function, and sensing function. The functional layer 9 may also be formed on the side surfaces (end faces) of the first and second semiconductor sections 8F and 8S.

[0018] In the semiconductor substrate 10 shown in Figures 1, 2A, and 2B, the first floating portion P1 of the first semiconductor portion 8F that is in contact with the hollow portion VD (but not with the seed portion SD) and the second floating portion P2 of the second semiconductor portion 8S that is in contact with the hollow portion VD (but not with the seed portion SD) are separated. Therefore, the process of separating the semiconductor device, including the main body portions H1 and H3, from the semiconductor substrate 10 is simplified. For example, to separate the main body portion H1 of the first floating portion P1 from the semiconductor substrate 10, the tether portion T1 can be broken. In addition, because the main body portion H1 is floating above the main substrate 1, the stress from the main substrate 1 is relieved, reducing the occurrence of cracks and defects in the main body portion H1. Furthermore, by lifting the main body H1 from the main substrate 1 and placing a mask portion 5 that functions as a selective growth mask (deposition suppression mask) beneath the main body H1, the main body H1 becomes a low-dislocation region, and an active region (e.g., a light-emitting region) can be formed so as to overlap with the low-dislocation region in a plan view. The through-dislocation density of the low-dislocation region is, for example, 5 × 10⁻⁶. 6 [pcs / cm 2 The dimensions are as follows, and the size of the main body H1 in the X direction can be 10 μm or more. Furthermore, the main body H1 and the tether T1 can be formed by simple processes such as etching after the formation of the ELO semiconductor part.

[0019] [Manufacturing of semiconductor substrates] Figure 3 is a plan view showing an example of a semiconductor substrate manufacturing method according to this embodiment. Figure 4 is a flowchart showing an example of a semiconductor substrate manufacturing method according to this embodiment. In the semiconductor substrate manufacturing method shown in Figures 3 and 4, after the step of preparing a template substrate 7, an ELO semiconductor portion (air bridge structure) 8 that does not contact the mask pattern 6 is formed on the template substrate 7, and then the ELO semiconductor portion 8 is patterned (e.g., etched) using photolithography to form first and second semiconductor portions 8F and 8S. This process makes it possible to form a first floating portion P1 including the main body portion H1 and tether portion T1, etc., and a second floating portion P2 separated from the first floating portion P1. Note that the step of forming a functional layer 9 can be performed before or after the step of patterning the ELO semiconductor portion 8.

[0020] Figure 5 is a block diagram showing an example of a semiconductor substrate manufacturing apparatus according to this embodiment. The semiconductor substrate manufacturing apparatus 70 in Figure 5 includes a semiconductor part forming unit 72 that performs the process of forming first and second semiconductor parts 8F and 8S on a template substrate 7, and a control unit 74 that controls the semiconductor part forming unit 72. The semiconductor part forming unit 72 forms an ELO semiconductor part 8 that does not contact the mask pattern 6, and then performs the process of patterning the ELO semiconductor part 8 using, for example, a photolithography method to form the first and second semiconductor parts 8F and 8S. The semiconductor substrate manufacturing apparatus 70 may also be configured to form a functional layer 9.

[0021] The semiconductor forming unit 72 may include an MOCVD apparatus and a patterning apparatus, and the control unit 74 may include a processor and memory. The control unit 74 may be configured to control the semiconductor forming unit 72 by executing a program stored in, for example, an internal memory, a communication device, or an accessible network, and this program and the recording medium on which this program is stored are also included in this embodiment.

[0022] [Manufacturing of semiconductor devices] Figure 6 is a flowchart showing an example of a semiconductor device manufacturing method according to this embodiment. In the semiconductor device manufacturing method shown in Figure 6, after the step of preparing the semiconductor substrate 10, the tether portion T1 etc. is broken to separate the main body portion H1 etc. from the semiconductor substrate 10, and a semiconductor device is obtained.

[0023] Figure 7 is a block diagram showing an example of a semiconductor device manufacturing apparatus according to this embodiment. The semiconductor device manufacturing apparatus 80 in Figure 7 comprises a semiconductor device generation unit 82 and a control unit 84 that controls the semiconductor device generation unit 82. The semiconductor device generation unit 82 performs a process of obtaining a semiconductor device by breaking the tether unit T1 to separate the main body unit HT from the semiconductor substrate 10. The semiconductor device manufacturing apparatus 80 may also be configured to form a functional layer 9.

[0024] [Semiconductor devices] The main body H1, separated from the semiconductor substrate 10, can function as a semiconductor device. Specific examples of semiconductor devices include light-emitting diodes (LEDs), semiconductor lasers, Schottky diodes, photodiodes, and transistors (including power transistors and high-electron-mobility transistors).

[0025] [Electronic equipment] Figure 8 is a schematic diagram showing the configuration of the electronic device according to this embodiment. The electronic device 30 in Figure 8 includes a semiconductor device 20 including a main body H1, a drive board 23 on which the semiconductor device 20 is mounted, and a control circuit 25 that controls the drive board 23.

[0026] Examples of electronic devices 30 include display devices, laser emission devices (including Fabry-Perot type and surface-emitting type), lighting devices, communication devices, information processing devices, sensing devices, power control devices, and the like.

[0027] [Example 1] (Overall structure) Figure 9 is a plan view showing the configuration of a semiconductor substrate according to Embodiment 1. Figure 10 is a cross-sectional view taken along the arrow cc in Figure 9. Figure 11 is a cross-sectional view taken along the arrow dd in Figure 9. As shown in Figures 9 to 11, the semiconductor substrate 10 according to Embodiment 1 comprises a main substrate 1, a seed portion SD located above the main substrate 1, and a first semiconductor portion 8F and a second semiconductor portion 8S arranged in the Y direction. The first semiconductor portion 8F and the second semiconductor portion 8S are in contact with the seed portion SD, and a hollow portion (void portion) VD is located between the main substrate 1 and the first semiconductor portion 8F and the second semiconductor portion 8S.

[0028] The first semiconductor section 8F includes a first floating section P1 in contact with the hollow section VD, and the second semiconductor section 8S includes a second floating section P2 in contact with the hollow section VD, with the first floating section P1 and the second floating section P2 being separated. The first semiconductor section 8F includes a third floating section P3 paired with the first floating section P1, and the first floating section P1 and the third floating section P3 are aligned in the X direction while floating. The first semiconductor section 8F includes a first base section BF located on the seed section SD, and the first base section BF is located between the first and third floating sections P1 and P3 and is connected to the first and third floating sections P1 and P3.

[0029] In Embodiment 1, the length of the first floating portion P1 in the X direction is greater than the thickness of the first floating portion P1. A protrusion 1Q projecting upward is provided on the upper surface 1F of the main substrate, and the seed portion SD is located on the protrusion 1Q, with the length of the first floating portion P1 in the X direction being greater than the height of the protrusion 1Q. The first floating portion P1 includes a tether portion T1 connected to the first base portion BF and a main body portion H1 connected to the tether portion T1, and the length of the tether portion T1 in the Y direction is smaller than that of the main body portion H1.

[0030] The semiconductor substrate 10 includes a functional layer 9 that overlaps with the first floating portion P1 in a plan view. The functional layer 9 overlaps with the main body portion H1 and the tether portion T1 in a plan view. The length of the tether portion T1 in the Y direction is greater than the thickness of the tether portion T1. The length of the tether portion T1 in the Y direction is less than or equal to half the length of the main body portion H1 in the Y direction.

[0031] The configuration is not limited to one in which the functional layer 9 overlaps the main body H1 and the tether T1 in a plan view. In a plan view, the functional layer 9 may not overlap the tether T1; that is, the functional layer 9 may be laminated on the main body H1 but not on the tether T1. This makes it easier for the tether T1 to break when the product is separated into individual pieces.

[0032] The semiconductor substrate 10 has a mask pattern 6 above the main substrate 1, which has an opening K and a mask portion 5 (selective growth mask), and in a plan view, the opening K and the seed portion SD overlap. A hollow portion VD is located between the first semiconductor portion 8F and the mask portion 5. The mask portion 5 covers the end face of the seed portion SD. That is, the upper surface of the seed portion SD is in contact with the first base portion BF, the lower surface of the seed portion SD is in contact with the upper surface (convex portion 1Q) of the main substrate 1, and the end face (side surface) is covered by the mask portion 5. For this reason, the semiconductor portion 8F does not come into contact with the end face of the seed portion SD.

[0033] Figure 12 is a plan view showing the semiconductor device piecemaking process in Example 1. Figure 13 is a cross-sectional view showing the semiconductor device piecemaking process in Example 1. As shown in Figures 12 and 13, for example, by breaking the tether portions T1 and T3, the main body portion H1 of the first floating portion P1 and the main body portion H3 of the third floating portion P3 can be separated from the semiconductor substrate 10, and the semiconductor device 20 can be obtained. A portion Tf of the tether portion T1 may remain on one side of the semiconductor device 20, and the anchor film 9a (described later) may remain on the other side.

[0034] Regarding the method for fracturing the tether portions T1 and T3, pressure may be applied from above (downward) to the functional layer 9 (by pressing), or they may be fractured with a laser. Alternatively, they may be fractured by temperature control of the semiconductor substrate 10. For example, a Peltier element may be used to lower the temperature of the semiconductor substrate 10 with the adhesive tape attached. In this case, the adhesive tape, which generally has a larger coefficient of thermal expansion than the semiconductor, will contract significantly, applying stress to the tether portions T1 and T3. As a further method, a support substrate may be bonded to the semiconductor substrate 10, and a mechanical upward force may be applied to the tether portions T1 and T3 to fracture them.

[0035] (Main board) The main substrate 1 can be a heterogeneous substrate having a different lattice constant from the GaN-based semiconductor. Examples of heterogeneous substrates include single-crystal silicon (Si) substrates, sapphire (Al2O3) substrates, and silicon carbide (SiC) substrates. The surface orientation of the main substrate 1 is, for example, the (111) plane for a silicon substrate, the (0001) plane for a sapphire substrate, and the 6H-SiC(0001) plane for a SiC substrate. These are examples, and any main substrate and surface orientation that can grow the ELO semiconductor portion is acceptable.

[0036] (Seed section) The seed portion SD is the growth starting point for the ELO semiconductor portion, and nitride semiconductors (GaN-based semiconductors, AlN, InAlN, InN, etc.), silicon carbide (SiC), etc. can be used. For example, aluminum nitride (AlN) locally formed on the protrusions of the main substrate 1, which is a silicon substrate or a silicon carbide substrate, can be used as the seed portion SD. Alternatively, a GaN-based semiconductor locally formed on the protrusions of the main substrate 1, which is a silicon carbide substrate, can be used as the seed portion SD.

[0037] Figure 14A is a cross-sectional view showing an alternative configuration of the semiconductor substrate according to Example 1. As shown in Figure 14A, seed portions SD of GaN-based semiconductors may be locally formed on the protrusions of the main substrate 1, which is a silicon substrate, via buffer portions 2B (e.g., AlN). When a silicon substrate is used for the main substrate 1 and a GaN-based semiconductor is used for the seed portions SD, the two (silicon substrate and GaN-based semiconductor) may melt together. By providing a buffer portion 2B such as AlN, melting can be suppressed. Furthermore, by providing a buffer portion 2B with a lattice constant close to that of the GaN-based semiconductor, improvement in the crystallinity of the seed portions SD can also be expected. Low-temperature (800°C or below) formed AlN may be used as the buffer portion 2B. This improves the crystallinity of the seed portions SD (e.g., GaN-based semiconductor). The seed portions SD and buffer portions 2B may be formed by methods other than MOCVD, such as sputtering. This reduces consumable costs and depreciation costs, and increases productivity. Figure 14B is a cross-sectional view showing an alternative configuration of the semiconductor substrate according to Example 1. As shown in Figure 14B, a seed portion SD may be provided on a part of the upper surface of the protrusion 1Q.

[0038] (Mask pattern) The mask pattern 6 has a mask portion 5 and an opening K, where the seed portion SD is exposed. The opening K may be a plurality of slits extending in the Y direction, with the mask portion 5 positioned between adjacent openings K. Figure 15 is a plan view showing an alternative configuration of the semiconductor substrate according to Embodiment 1. As shown in Figure 15, the opening K and seed portion SD may be separated in the Y direction. That is, a plurality of seed portions SD with the Y direction as the longitudinal direction are arranged in the Y direction. In this way, a plurality of ELO semiconductor portions arranged in the Y direction are formed, and the stress generated between the main substrate 1 and mainly the first semiconductor portion 8F can be relieved. This reduces the occurrence of defects and cracks in the first semiconductor portion 8F. In addition, the warping of the main substrate 1 is reduced, making it easier to increase the diameter of the main substrate 1. The mask portion 5 and the opening K refer to the parts with and without a mask body, and it is not necessary to consider whether the mask portion 5 is layered or not. The mask pattern 6 may be a mask layer. Also, the entire opening K does not have to be surrounded by the mask portion 5.

[0039] As the mask portion 5, for example, a single layer film containing one of the following: silicon oxide film (SiOx), titanium nitride film (TiN, etc.), silicon nitride film (SiNx), silicon oxynitride film (SiON), and a metal film having a high melting point (e.g., 1000 degrees or higher), or a multilayer film containing at least two of these, can be used. Although silicon oxide films may decompose and evaporate in small amounts during the deposition of the ELO semiconductor portion and be incorporated into the ELO semiconductor portion, silicon nitride films and silicon oxynitride films have the advantage of being less likely to decompose and evaporate at high temperatures. Therefore, the mask portion 5 may be a single layer film of silicon nitride film or silicon oxynitride film, a multilayer film formed by forming silicon oxide film and silicon nitride film in that order, a multilayer film formed by forming silicon nitride film and silicon oxide film in that order, or a multilayer film formed by forming silicon nitride film, silicon oxide film and silicon nitride film in that order.

[0040] (Template board) Figure 16 is a flowchart showing the manufacturing method of a template substrate in Example 1. Figure 17 is a cross-sectional view showing the manufacturing method in Figure 16. In Figures 16 and 17, the manufacturing process involves the steps of: depositing a seed layer SL and a sacrificial film ZF (e.g., photoresist) on a main substrate 1 in that order; patterning the seed layer SL using the patterned sacrificial film ZF as a mask pattern; etching the surface of the main substrate 1 using the sacrificial film ZF as a mask pattern to form a protrusion 1Q; forming a mask pattern 6 that covers the main substrate 1 and the sacrificial film ZF (e.g., using a sputtering method or a PECVD method); and removing the photoresist with a remover to form an opening K that exposes the seed portion SD and a mask portion 5. In this case, the mask portion 5 covers the end face (side surface) of the seed portion SD.

[0041] Figure 18 is a flowchart showing an alternative method for manufacturing the template substrate in Example 1. Figure 19 is a cross-sectional view showing the manufacturing method in Figure 18. In Figures 18 and 19, the process involves: depositing a seed layer SL and a sacrificial film ZF (silicon oxide film or resist film) in that order on a main substrate 1, which is a silicon substrate or silicon carbide substrate; patterning the seed layer SL and the sacrificial film ZF; etching the surface of the main substrate 1 using the sacrificial film ZF as a mask pattern to form a protrusion 1Q; etching (removing) the sacrificial film ZF; and performing a substrate processing treatment (thermal oxidation treatment or nitriding treatment) on the surface of the main substrate 1 to form a substrate processed film (silicon thermal oxide film, silicon nitride film, or silicon oxynitride film) which is a mask portion 5 and an opening K. The substrate processed film has excellent film quality and is suitable for selective growth masks placed at high temperatures.

[0042] The thickness of the mask pattern 6 is, for example, about 100 nm to about 4 μm (preferably about 150 nm to about 2 μm), and the width of the aperture K is about 0.1 μm to about 20 μm. The smaller the width of the aperture K, the fewer the number of through-dislocations propagating from each aperture K to the ELO semiconductor portion 8. In addition, the area of ​​the main body portion (H1, etc.), which is a low-dislocation portion, can be increased.

[0043] (Filming of the ELO semiconductor portion) In Example 1, the ELO semiconductor portion (including 8F, 8S, and 8T) was made of a GaN layer, and ELO film deposition was performed on the aforementioned template substrate 7 using a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus. As an example of ELO film deposition conditions, the following can be used: substrate temperature: 1120°C, growth pressure: 50kPa, TMG (trimethylgallium): 22sccm, NH3: 15slm, V / III = 6000 (ratio of the amount of Group V raw material supplied to the amount of Group III raw material supplied).

[0044] In this case, the ELO semiconductor portion is selectively grown on the seed portion SD, and then grows laterally above (in the air) the mask portion 5. Lateral growth is stopped before the ELO semiconductor portions growing laterally from both sides above the mask portion 5 meet.

[0045] The method for increasing the lateral film deposition rate is as follows: First, a longitudinal growth layer is formed on the seed portion SD in the Z direction (c-axis direction), and then a lateral growth layer is formed in the X direction (a-axis direction). To promote longitudinal growth, the growth temperature is lowered to, for example, 1050°C. In this case, by setting the thickness of the longitudinal growth layer to 10 μm or less, preferably 5 μm or less, and more preferably 3 μm or less, the thickness of the lateral growth layer can be kept low, thereby increasing the lateral film deposition rate.

[0046] Regarding the film deposition temperature for the ELO semiconductor portion 8, a temperature of 1150°C or lower is preferable to a high temperature exceeding 1200°C. Formation of the ELO semiconductor portion 8 is possible even at low temperatures below 1000°C, which is even more preferable from the viewpoint of suppressing the decomposition of the mask portion 5.

[0047] Furthermore, for low-temperature film deposition below 1000°C, it is preferable to use triethylgallium (TEG) as the gallium raw material gas. Compared to TMG, TEG allows for more efficient decomposition of organic raw materials at low temperatures, thus increasing the lateral film deposition rate.

[0048] In addition to the metal-organic vapor deposition (MOCVD) method mentioned above, other methods such as hydride vapor deposition (HVPE) and molecular beam vapor deposition (MBE) can be used for crystal growth in the ELO method.

[0049] (Functional layer) The functional layer 9 located on the first and second semiconductor sections 8F and 8S includes a layered device section 9d (hereinafter also simply referred to as the device layer), an insulating film 9p (passivation film) located above the device layer 9d, and first and second electrodes E1 and E2 located above the insulating film 9p. The main body section H1 and the functional layer 9 may also function as semiconductor devices such as light-emitting diodes and semiconductor lasers.

[0050] The device layer 9d, the insulating film 9p, and the first and second electrodes E1 and E2 do not overlap with the tether portion T1. The device layer 9d is, for example, a laminate of an n-type semiconductor portion (e.g., GaN-based), an undoped semiconductor portion (e.g., GaN-based), and a p-type semiconductor portion (e.g., GaN-based), and the undoped semiconductor portion can be the active layer (a layer where electrons and holes bond). The device layer 9d can be formed by any method. An inorganic film such as silicon oxide or silicon nitride can be used for the insulating film 9p. One of the first and second electrodes E1 and E2 can be the anode and the other the cathode. The area of ​​the first electrode E1 can be made larger than the area of ​​the second electrode E2. In Example 1, the first and second electrodes E1 and E2 are provided on the device layer 9d, but the invention is not limited to this. For example, only the first electrode E1 may be provided on the device layer 9d.

[0051] Figure 20 is a flowchart showing the method for manufacturing a semiconductor substrate in Example 1. Figure 21 is a cross-sectional view showing the manufacturing method in Figure 20. As shown in Figures 9, 20, and 21, the process includes the steps of forming an ELO semiconductor portion 8 on a template substrate 7, forming a device layer 9d on the ELO semiconductor portion 8, depositing an insulating film 9p on the device layer 9d, for example by PECVD, patterning the insulating film 9p, forming first and second electrodes E1 and E2, and dry etching the ELO semiconductor portion 8 (for example, reactive ion etching: RIE) to form a first semiconductor portion 8F including main body portions H1 and H3 and tether portions T1 and T3, and a second semiconductor portion 8S. For etching the ELO semiconductor portion 8, dry methods such as ECR (electron cyclotron resonance) etching and CAIB (chemically assisted ion beam) etching may be used, as well as wet methods such as PEC (photoelectrochemical) etching.

[0052] The insulating film 9p is a passivation film (e.g., silicon oxide film, silicon nitride film) formed above the device layer 9d, and in a plan view it overlaps with the main body H1 but does not overlap with the tether T1. This avoids the problem of the insulating film 9p preventing the tether T1 from breaking. Furthermore, as shown in Figure 13, a portion of the insulating film 9p (for example, the portion that covers the center of the end face of the main body H1 and extends to the mask portion 5 on the main substrate) functions as an anchor film 9a. This ensures that the main body H1 is stable and that the anchor film 9a is broken simultaneously with the tether T1.

[0053] Furthermore, when forming the ELO semiconductor portion 8, the ELO semiconductor portions growing laterally from both sides above the mask portion 5 may be brought together, and the joined portions (high dislocation portions) may be removed when etching the ELO semiconductor portion 8.

[0054] Figure 22 is a plan view showing an alternative configuration of the semiconductor substrate according to Embodiment 1. As shown in Figure 22, the first floating portion P1 may include a plurality of tether portions T1-T5, and the main body portion H1 may be connected to the first base portion BF via the plurality of tether portions T1-T5. Providing a plurality of tether portions T1-T5 has the advantage of stabilizing the main body portion H1.

[0055] Figure 23 is a plan view showing an alternative configuration of the semiconductor substrate according to Example 1. As shown in Figure 23, the tether portion T1 of the first floating portion P1 may have a notch NC. In this case, the side surface of the notch NC can be configured to be at a 60° angle with respect to the X direction. Such a notch NC can be formed, for example, by creating a semicircular notch when forming the tether portion, and then immersing it in TMAH (tetramethylammonium hydroxide) to expose the m-plane of the GaN-based semiconductor. By forming a sharp fracture initiation point such as a notch NC, the fracture of the tether portion T1 becomes easier.

[0056] Figure 24 is a cross-sectional view showing another method for manufacturing a semiconductor substrate in Example 1. In Figure 10, a protrusion 1Q is provided on the main substrate 1, but the method is not limited to this. As shown in Figure 24, a template substrate 7 is used which includes, in this order, a main substrate 1 (e.g., a silicon substrate), a planar buffer layer 2 (e.g., AlN), and a local seed portion SD (e.g., a GaN-based semiconductor) with the Y direction as the longitudinal direction, and the seed portion SD is exposed at the opening K of the mask pattern 6. An ELO semiconductor portion (including the first semiconductor portion 8F) in contact with the seed portion SD and the mask portion 5 is formed, and then the mask portion 5 may be removed by etching (e.g., wet etching). This makes it possible to float the first semiconductor portion 8F (so that its lower surface is in contact with the hollow portion VD). The mask portion 5 may also be removed before forming the functional layer 9.

[0057] [Example 2] Figure 25 is a plan view showing the configuration of a semiconductor substrate according to Embodiment 2. Figures 26 and 27 are cross-sectional views showing the configuration of a semiconductor substrate according to Embodiment 2. In Embodiment 1, the ELO semiconductor portions growing laterally from both sides above the mask portion 5 are stopped growing laterally before they meet, and the first and second semiconductor portions 8F and 8S have end faces (edges) that overlap with the mask portion 5 in a plan view, but the embodiment is not limited to this. As shown in Figures 25 to 27, the ELO semiconductor portions growing laterally from both sides above the mask portion 5 may meet.

[0058] As shown in Figures 25 to 27, the first semiconductor section 8F includes a first floating section P1 facing the main substrate 1 via a hollow section VD, and the second semiconductor section 8S includes a second floating section P2 facing the main substrate 1 via a hollow section VD, with the first floating section P1 and the second floating section P2 being separated. The first semiconductor section 8F includes a third floating section P3 that is paired with the first floating section P1, and the first floating section P1 and the third floating section P3 are aligned in the X direction while floating. The first semiconductor section 8F includes a first base section BF located on the seed section SD, and the first base section BF is located between the first and third floating sections P1 and P3 and is connected to the first and third floating sections P1 and P3. The first floating section P1 includes a tether section T1 connected to the first base section BF and a main body section H1 connected to the tether section T1, wherein the length of the tether section T1 in the Y direction is shorter than that of the main body section H1.

[0059] The semiconductor substrate 10 has a mask pattern 6 above the main substrate 1, which has an opening K and a mask portion 5 (selective growth mask), and in a plan view, the opening K and the seed portion SD overlap. A hollow portion VD is located between the first semiconductor portion 8F and the mask portion 5. The mask portion 5 covers the end face of the seed portion SD. That is, the upper surface of the seed portion SD is in contact with the first base portion BF, the lower surface of the seed portion SD is in contact with the upper surface (convex portion 1Q) of the main substrate 1, and the end face (side surface) is covered by the mask portion 5. For this reason, the semiconductor portion 8F does not come into contact with the end face of the seed portion SD.

[0060] The functional layer 9 formed on the semiconductor portion 8 includes a device layer 9d, an insulating film 9p (passivation film) located above the device layer 9d, and first and second electrodes E1 and E2 located above the insulating film 9p.

[0061] [Example 3] In Examples 1 and 2, the ELO semiconductor portion is a GaN layer, but the invention is not limited to this. In Example 3, an InGaN layer, which is a GaN-based semiconductor portion, can also be formed as the first and second semiconductor portions 8F and 8S (ELO semiconductor portion). Lateral deposition of the InGaN layer is carried out at a low temperature, for example, below 1000°C. This is because at high temperatures, the vapor pressure of indium increases, and it is not effectively incorporated into the film. Lowering the deposition temperature has the effect of reducing the interaction between the mask portion 5 and the InGaN layer. In addition, the InGaN layer has the effect of being less reactive with the mask portion 5 than the GaN layer. It is desirable that the indium is incorporated into the InGaN layer at an In composition level of 1% or more, as this further reduces the reactivity with the mask portion 5. Triethylgallium (TEG) is preferably used as the gallium source gas.

[0062] [Example 4] Figure 28 is a schematic cross-sectional view showing the configuration of Embodiment 4. In Embodiment 4, a semiconductor device 20 that functions as an LED (light-emitting diode) is composed of a main body H1 and a device layer 9d. The main body H1 (e.g., GaN-based semiconductor) is an n-type semiconductor doped with, for example, silicon. The device layer 9d includes, in order from the bottom layer, an active layer 34, an electron blocking layer 35, and a GaN-based p-type semiconductor portion 36. The active layer 34 is MQW (Multi-Quantum Well) and includes an InGaN layer and a GaN layer. The electron blocking layer 35 is, for example, an AlGaN layer. The GaN-based p-type semiconductor portion 36 is, for example, a GaN layer. The anode 38 (e.g., first electrode E1) is arranged to be in contact with the GaN-based p-type semiconductor portion 36, and the cathode 39 (e.g., second electrode E2) is arranged to be in contact with the main body H1.

[0063] Figure 29 is a cross-sectional view showing an example of the application of Embodiment 4 to an electronic device. Embodiment 4 allows for the creation of a red micro-LED 20R, a green micro-LED 20G, and a blue micro-LED 20B. By mounting these on a drive board (TFT board) 23, a micro-LED display 30D (electronic device) can be constructed. As an example, the red micro-LED 20R, green micro-LED 20G, and blue micro-LED 20B are mounted on multiple pixel circuits 27 of the drive board 23 via a conductive resin 24 (for example, an anisotropic conductive resin), and then a control circuit 25 and a driver circuit 29 are mounted on the drive board 23. A portion of the driver circuit 29 may be included in the drive board 23.

[0064] [Example 5] Figure 30 is a schematic cross-sectional view showing the configuration of Example 5. In Example 5, the main body H1 and the device layer 9d constitute a semiconductor device 20 that functions as a semiconductor laser. The device layer 9d includes, in order from the bottom layer, an n-type cladding layer 41, an n-type optical guide layer 42, an active layer 43, an electron blocking layer 44, a p-type optical guide layer 45, a p-type cladding layer 46, and a GaN-based p-type semiconductor portion 47. InGaN layers can be used for each optical guide layer 42-45. GaN layers or AlGaN layers can be used for each cladding layer 41-46. The anode 48 is arranged to be in contact with the GaN-based p-type semiconductor portion 47, and the main body H1 is mounted on the n-pad 49 of the mounting substrate 53.

[0065] [Example 6] Figure 31 is a plan view showing the semiconductor substrate of Example 6. Figure 32 is a cross-sectional view showing the semiconductor substrate of Example 6. The semiconductor substrate 10 of Example 6 includes a template substrate 7 with first and second seed regions J1 and J2 and a growth suppression region (deposition suppression region) SP on its upper surface, a first semiconductor portion 8F extending from the first seed region J1 to above the growth suppression region SP, with a hollow portion VD formed between it and the growth suppression region SP, and a second semiconductor portion 8S extending from the second seed region J2 to above the growth suppression region SP, with a hollow portion VD formed between it and the growth suppression region SP. The first and second semiconductor portions 8F and 8S are adjacent to each other in the first direction (Y direction) with a gap G1 between them. The Y direction may be the m-axis direction of the first and second semiconductor portions 8F and 8S containing nitride semiconductors. The first and second seed regions J1 and J2 may be located above the growth suppression region SP.

[0066] The first and second seed regions J1 and J2 may have a shape with the Y direction as its longitudinal side. The ends of the first and second semiconductor sections 8F and 8S may each taper in the Y-axis direction. A fourth semiconductor section 8U may be arranged adjacent to the first semiconductor section 8F in the X direction with a gap G2 in between. The X direction may be the a-axis direction of the first and second semiconductor sections 8F and 8U containing nitride semiconductors. The semiconductor substrate 10 has the advantage of being less prone to warping. The first and second seed regions J1 and J2 may be the region on the upper surface of the seed section that overlaps with the opening of the mask pattern, and the growth suppression region SP may be the upper surface of the mask section. [Explanation of Symbols]

[0067] 1 Main board SD Seed Section 5 Mask section 6 Mask Patterns 7 Template board 8F, Semiconductor Division 1 8S Semiconductor Division 2 9 Functional Layers 9d Device Layer 10 Semiconductor substrates 20 Semiconductor Devices 30 Electronic equipment 70 Semiconductor substrate manufacturing equipment K opening VD hollow part P1 First floating section P2 Second floating section P3 Third Floating Section H1 Main Unit T1 Tether section

Claims

1. A template substrate having a mask pattern with a mask portion and an opening on its upper surface, The semiconductor portion comprises a first portion extending upward from the opening and a second portion extending upward from the first portion above the mask portion, The opening has a shape with the first direction as the longitudinal direction, A hollow portion is located between the second portion and the mask portion. The second portion includes a main body and a tether portion located closer to the first portion than the main body and having a shorter length in the first direction than the main body.

2. When the direction perpendicular to the first direction is taken as the second direction, The semiconductor substrate according to claim 1, wherein the main body portion has a length in the first direction greater than the length in the second direction.

3. The semiconductor substrate according to claim 1, wherein the length of the tether portion in the first direction is half or less the length of the main body portion in the first direction.

4. The semiconductor substrate according to claim 1, wherein the length of the tether portion in the first direction is greater than the thickness of the tether portion.

5. The semiconductor portion includes a nitride semiconductor. The semiconductor substrate according to claim 1, wherein the first direction is the <1-100> direction of the nitride semiconductor.

6. The semiconductor substrate according to any one of claims 1 to 5, wherein the through-dislocation density of the second portion is smaller than the through-dislocation density of the first portion.

7. The penetration dislocation density in the second portion is 5 × 10 ６ [pcs / cm ２ The semiconductor substrate according to any one of claims 1 to 5, wherein the semiconductor substrate is as follows:

8. When the direction perpendicular to the first direction is taken as the second direction, The semiconductor substrate according to any one of claims 1 to 5, wherein the length of the main body in the second direction is 10 μm or more.

9. The semiconductor substrate according to any one of claims 1 to 5, wherein the tether portion has a notch whose length in the first direction is smaller than that of the other parts of the tether portion.

10. A semiconductor substrate preparation step comprising: a template substrate having a mask pattern with a mask portion and an opening on its upper surface; a semiconductor portion having a first portion extending upward from the opening and a second portion extending upward from the first portion above the mask portion, wherein the opening has a shape with a first direction as its longitudinal direction, a hollow portion is located between the second portion and the mask portion, and the second portion includes a main body portion and a tether portion located closer to the first portion than the main body portion and having a shorter length in the first direction than the main body portion; A method for manufacturing a semiconductor device, comprising the step of breaking the tether portion.

11. A method for manufacturing a semiconductor device according to claim 10, wherein a portion of the tether portion remains on the side surface of the main body portion after the fracture.

12. A method for manufacturing a semiconductor device according to claim 10, comprising the step of forming a functional layer on the main body before the step of breaking the tether portion.

13. The method for manufacturing a semiconductor device according to claim 12, wherein the functional layer includes an electrode and an active layer.

14. A method for manufacturing a semiconductor device according to claim 12, wherein in the step of rupturing the tether portion, the tether portion is ruptured by applying pressure to the functional layer.

15. The process of preparing the semiconductor substrate is as follows: A step of preparing a substrate comprising the template substrate and a semiconductor portion having a first portion extending upward from the opening and a second portion extending upward from the first portion above the mask portion, A method for manufacturing a semiconductor device according to any one of claims 10 to 12, comprising the step of forming the tether portion and the main body portion by etching the second portion.

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