Semiconductor device and method for manufacturing a semiconductor device

Abstract

To improve the performance of a semiconductor device that includes an oscillation circuit.SOLUTION: A semiconductor device that includes an oscillation circuit includes a MISFET formed on a semiconductor substrate SB and having a halo region, and MISFET 2, 3 formed on the semiconductor substrate and having no halo region. Gate electrode G2, G3 of the respective MISFET 2, 3 having no halo region are electrically connected to each other. The MISFET 2, 3 having no halo region are used as a pair transistor included in the oscillation circuit.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and can be suitably used, for example, for a semiconductor device including an oscillation circuit and a method for manufacturing the same.

Background Art

[0002] Japanese Patent Application Laid-Open No. 9-45906 (Patent Document 1) describes a technique for forming a pocket region after forming a source-drain region.

[0003] In addition, Japanese Patent Application Laid-Open No. 2019-9345 (Patent Document 2) describes a technique related to a semiconductor device including an oscillation circuit.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] In a semiconductor device including an oscillation circuit, it is desired to improve performance.

[0006] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0007] According to one embodiment, a semiconductor device equipped with an oscillation circuit includes a semiconductor substrate, a plurality of first MISFETs formed on the semiconductor substrate, and a plurality of second MISFETs formed on the semiconductor substrate. Each of the plurality of first MISFETs is a MISFET having a halo region, and each of the plurality of second MISFETs is a MISFET without a halo region. The plurality of second MISFETs are used as pair transistors included in the oscillation circuit. [Effects of the Invention]

[0008] According to one embodiment, the performance of a semiconductor device equipped with an oscillation circuit can be improved. [Brief explanation of the drawing]

[0009] [Figure 1] This is a plan view of the main part of a semiconductor device according to one embodiment. [Figure 2] This is a plan view of the main part of a semiconductor device according to one embodiment. [Figure 3] This is a cross-sectional view of a main part of a semiconductor device according to one embodiment. [Figure 4] This is a plan view of the main part of a semiconductor device according to one embodiment. [Figure 5] This is a cross-sectional view of a main part of a semiconductor device according to one embodiment. [Figure 6] This is a cross-sectional view of a main part of a semiconductor device according to one embodiment. [Figure 7] This is a plan view of the main part of a modified semiconductor device. [Figure 8] This is a cross-sectional view of a key part during the manufacturing process of a semiconductor device according to one embodiment. [Figure 9] This is a cross-sectional view of a key part during the manufacturing process of the same semiconductor device as in Figure 8. [Figure 10] Figure 8 shows a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 11] This is a cross-sectional view of a key part during the manufacturing process of the same semiconductor device as in Figure 10. [Figure 12] Figure 10 shows a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 13] It is a cross-sectional view of the main part during the manufacturing process of the same semiconductor device as shown in FIG. 12. [Figure 14] It is a cross-sectional view of the main part during the manufacturing process of the semiconductor device following FIG. 12. [Figure 15] It is a cross-sectional view of the main part during the manufacturing process of the same semiconductor device as shown in FIG. 14. [Figure 16] It is a cross-sectional view of the main part during the manufacturing process of the semiconductor device following FIG. 14. [Figure 17] It is a cross-sectional view of the main part during the manufacturing process of the same semiconductor device as shown in FIG. 16. [Figure 18] It is a cross-sectional view of the main part during the manufacturing process of the semiconductor device following FIG. 16. [Figure 19] It is a cross-sectional view of the main part during the manufacturing process of the same semiconductor device as shown in FIG. 18. [Figure 20] It is a cross-sectional view of the main part during the manufacturing process of the semiconductor device following FIG. 18. [Figure 21] It is a cross-sectional view of the main part during the manufacturing process of the same semiconductor device as shown in FIG. 20. [Figure 22] It is a cross-sectional view of the main part during the manufacturing process of the semiconductor device of the first modified example. <{ [Figure 23] It is a cross-sectional view of the main part during the manufacturing process of the semiconductor device following FIG. 22. [Figure 24] It is a cross-sectional view of the main part during the manufacturing process of the same semiconductor device as shown in FIG. 23. [Figure 25] It is a cross-sectional view of the main part during the manufacturing process of the same semiconductor device as shown in FIG. 23. ` [Figure 26] It is a cross-sectional view of the main part during the manufacturing process of the semiconductor device following FIG. 23. [Figure 27] It is a cross-sectional view of the main part during the manufacturing process of the same semiconductor device as shown in FIG. 26. [Figure 28] [[ID=!46]]It is a cross-sectional view of the main part during the manufacturing process of the same semiconductor device as shown in FIG. 26. [Figure 29] It is a cross-sectional view of the main part during the manufacturing process of the semiconductor device of the second modified example. [Figure 30] It is a cross-sectional view of the main part during the manufacturing process of the same semiconductor device as shown in FIG. 29. <{ [Figure 31] It is a cross-sectional view of the main part during the manufacturing process of the semiconductor device following FIG. 29. [Figure 32] This is a cross-sectional view of a key part during the manufacturing process of the same semiconductor device as in Figure 31. [Figure 33] Figure 31 is a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 34] This is a cross-sectional view of a key part during the manufacturing process of the same semiconductor device as Figure 33. [Figure 35] Figure 33 is a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 36] This is a cross-sectional view of a key part during the manufacturing process of the same semiconductor device as in Figure 35. [Figure 37] This is a circuit diagram showing a part of the oscillator circuit. [Figure 38] This is a circuit block diagram of a semiconductor device according to one embodiment. [Figure 39] This is a cross-sectional view of a main part of a semiconductor device according to one embodiment. [Figure 40] This is a cross-sectional view of a main part of a semiconductor device according to one embodiment. [Figure 41] This is a process flow chart showing the manufacturing process for semiconductor devices. [Figure 42] A circuit diagram of a pair of transistors. [Figure 43] A circuit diagram of a pair of transistors. [Figure 44] A circuit diagram of a pair of transistors. [Figure 45] A circuit diagram of a pair of transistors. [Figure 46] This is a plan view showing an example layout of paired transistors. [Figure 47] This is a plan view showing an example layout of paired transistors. [Figure 48] This is a plan view showing an example layout of paired transistors. [Figure 49] This is a cross-sectional view of the main part of a semiconductor device when the layout shown in Figure 47 is applied. [Figure 50] This is a cross-sectional view of the main part of a semiconductor device when the layout shown in Figure 47 is applied. [Figure 51] This is a plan view of the main part of a semiconductor device according to one embodiment. [Figure 52] This is a cross-sectional view of a main part of a semiconductor device according to one embodiment. [Figure 53] This is a plan view of the main part of a semiconductor device according to one embodiment. [Figure 54] This is a cross-sectional view of a main part of a semiconductor device according to one embodiment. [Modes for carrying out the invention]

[0010] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments. Unless otherwise specified, these are not unrelated, and one may be a modification, detail, or supplementary explanation of part or all of the other. Furthermore, when referring to the number of elements, etc. (including number, numerical value, quantity, range, etc.) in the following embodiments, unless otherwise specified or clearly limited to a specific number in principle, it is not limited to that specific number, and may be greater than or less than that number. Moreover, in the following embodiments, it goes without saying that the constituent elements (including element steps, etc.) are not necessarily essential unless otherwise specified or clearly considered essential in principle. Similarly, when referring to the shape, positional relationship, etc. of constituent elements, etc. in the following embodiments, unless otherwise specified or clearly considered not to be so in principle, it shall include those that substantially approximate or resemble that shape, etc. The same applies to the numerical values ​​and ranges mentioned above.

[0011] The embodiments will be described in detail below with reference to the drawings. In all the drawings used to describe the embodiments, the same reference numerals are used for members having the same function, and repeated descriptions of them will be omitted. In addition, in the following embodiments, descriptions of the same or similar parts will not be repeated unless it is particularly necessary.

[0012] Furthermore, in the drawings used in the embodiments, hatching may be omitted even in cross-sectional views to improve readability. Conversely, hatching may be added to plan views to improve readability.

[0013] <About the structure of semiconductor devices> Figures 1 and 2 are plan views of the main parts of the semiconductor device of this embodiment, and Figure 3 is a cross-sectional view of the main parts of the semiconductor device of this embodiment, with the cross-sectional view at the position of line A1-A1 in Figures 1 and 2 corresponding to Figure 3. Furthermore, Figure 4 is a plan view of the main parts of the semiconductor device of this embodiment, and Figures 5 and 6 are cross-sectional views of the main parts of the semiconductor device of this embodiment, with the cross-sectional view at the position of line A2-A2 in Figure 4 corresponding to Figure 5, and the cross-sectional view at the position of line A3-A3 in Figure 4 corresponding to Figure 6.

[0014] Note that the X, Y, and Z directions shown in Figures 1, 2, and 4 are mutually orthogonal directions. The X and Y directions are parallel to the main surface or back surface of the semiconductor substrate SB, i.e., horizontal directions. The Z direction is the thickness direction of the semiconductor substrate SB. Furthermore, the X direction corresponds to the gate length direction of the gate electrodes G1, G2, and G3, and the Y direction corresponds to the gate width direction of the gate electrodes G1, G2, and G3.

[0015] Figures 1 and 2 show the same planar region. Figures 1 and 4 show different planar regions. For ease of understanding, in Figure 1, the formation position of gate electrode G1 is shown by a dotted line, and hatching is applied to the device isolation region ST, n-type semiconductor regions D1a, S1a, and n-type semiconductor regions D1b, S1b. In Figure 2, the formation position of gate electrode G1 is shown by a dotted line, and hatching is applied to the device isolation region ST and p-type halo regions HA1, HA2. In Figure 4, the formation positions of gate electrode G2 and G3 are shown by dotted lines, and hatching is applied to the device isolation region ST, n-type semiconductor regions D2a, S2a, D3a, S3a, and n-type semiconductor regions D2b, S2b, D3b, S3b.

[0016] The semiconductor device of this embodiment includes multiple MISFETs (Metal Insulator Semiconductor Field Effect Transistors) having a halo region (pocket region) and multiple MISFETs without a halo region (pocket region). Figures 1 to 3 show plan views (Figures 1 and 2) or cross-sectional views (Figure 3) of the MISFET formation region 1A, which is the active region where MISFET 1 having a halo region (pocket region) is formed. Figures 4 and 5 show plan views (Figure 4) or cross-sectional views (Figure 5) of the MISFET formation regions 2A and 3A, which are the active regions where MISFETs 2 and 3 without a halo region (pocket region) are formed.

[0017] As will be described in more detail later, the semiconductor device of this embodiment is a semiconductor device having an oscillator circuit (oscillating circuit). MISFETs 2 and 3, which do not have a halo region, are used as MISFETs that constitute a pair of transistors included in the oscillator circuit.

[0018] In the following explanation, MISFET1,2, and3 are described as n-channel transistors, but they can also be made into p-channel transistors by reversing their conductivity.

[0019] As shown in Figures 1 to 6, a semiconductor substrate (semiconductor wafer) SB made of p-type single crystal silicon having a resistivity of approximately 1 to 10 Ωcm has an element isolation region ST formed therein to separate the elements. This element isolation region ST defines the MISFET formation region 1A, which is the region where MISFET1 is formed (active region), the MISFET formation region 2A, which is the region where MISFET2 is formed (active region), and the MISFET formation region 3A, which is the region where MISFET3 is formed (active region).

[0020] The element isolation region ST is embedded in a groove on the main surface of the semiconductor substrate SB. Each of the MISFET formation regions 1A, 2A, and 3A is surrounded by the element isolation region ST in a plan view. FIGS. 1, 2, and 4 show a case where the planar shape of each of the MISFET formation regions 1A, 2A, and 3A is a rectangular shape having sides substantially parallel to the X direction and sides substantially parallel to the Y direction. Note that the plan view corresponds to the case of viewing in a plane substantially parallel to the main surface of the semiconductor substrate SB.

[0021] The element isolation region ST is formed by the STI (Shallow Trench Isolation) method. Therefore, the element isolation region ST is composed of an insulator (insulating film) embedded in a groove formed in the semiconductor substrate SB. The element isolation region ST is mainly composed of silicon oxide.

[0022] A p-type well (p-type well region) PW1 is formed in the semiconductor substrate SB of the MISFET formation region 1A, and a p-type well (p-type well region) PW2 is formed in the semiconductor substrates SB of the MISFET formation regions 2A and 3A. The p-type wells PW1 and PW2 are p-type semiconductor regions into which p-type impurities are introduced. The depth position of the bottom surfaces of the p-type wells PW1 and PW2 is deeper than the depth position of the bottom surface of the element isolation region ST. The MISFET formation region 2A and the MISFET formation region 3A are adjacent to each other via the element isolation region ST in a plan view, and the p-type well PW2 is formed across the MISFET formation region 2A and the MISFET formation region 3A. Therefore, in a plan view, the MISFET formation regions 2A and 3A are included in the p-type well PW2.

[0023] Hereinafter, the configurations of the MISFETs 1, 2, and 3 will be described.

[0024] <<Regarding the configuration of MISFET1>> First, the configuration of MISFET1 will be specifically described with reference to FIGS. 1 to 3.

[0025] MISFET1 has a gate electrode G1 formed on the semiconductor substrate SB (p-type well PW1) of the MISFET formation region 1A via a gate insulating film GF1, and n-type semiconductor regions S1 and D1 for source and drain (source or drain) formed on both sides of the gate electrode G1 in a plan view.

[0026] The gate electrode G1 extends in the Y direction so as to cross the MISFET formation region 1A in a plan view. Therefore, the gate electrode G1 is continuously formed on the semiconductor substrate SB of the MISFET formation region 1A and on the device isolation region ST surrounding the MISFET formation region 1A. The gate insulating film GF1 is interposed between the semiconductor substrate SB (p-type well PW1) and the gate electrode G1. The gate insulating film GF1 may also be interposed between the device isolation region ST and the gate electrode G1, but the device isolation region ST and the gate electrode G1 may be in contact with each other.

[0027] In the semiconductor substrate SB (p-type well PW1) of the MISFET formation region 1A, the region below the gate electrode G1 is the region where the channel is formed, i.e., the channel formation region. The channel formation region of MISFET 1 is formed in the surface layer of the semiconductor substrate SB and is adjacent to the gate insulating film GF1 located below the gate electrode G1.

[0028] A sidewall spacer SW is formed on the sidewall of the gate electrode G1 as a sidewall insulating film. The sidewall spacer SW is formed of an insulating film, and may be composed of a single film or a multilayer film.

[0029] In a plan view, a pair of n-type semiconductor regions D1 and S1 are formed so as to sandwich the gate electrode G1 in the X direction. One of these regions (in this case, n-type semiconductor region S1) functions as the source region of MISFET1, and the other (in this case, n-type semiconductor region D1) functions as the drain region of MISFET1. The n-type semiconductor regions D1 and S1 are formed within the semiconductor substrate SB (p-type well PW1) of the MISFET formation region 1A. The pair of n-type semiconductor regions D1 and S1 have an LDD (Lightly doped Drain) structure.

[0030] Therefore, the n-type semiconductor region S1 is composed of an n-type semiconductor region (extension region, low-concentration region) S1a with a low impurity concentration and an n-type semiconductor region (high-concentration region) S1b with a higher impurity concentration than the n-type semiconductor region S1a. Similarly, the n-type semiconductor region D1 is composed of an n-type semiconductor region (extension region, low-concentration region) D1a with a low impurity concentration and an n-type semiconductor region (high-concentration region) D1b with a higher impurity concentration than the n-type semiconductor region D1a. The impurity concentration (n-type impurity concentration) of the n-type semiconductor region D1b is higher than the impurity concentration (n-type impurity concentration) of the n-type semiconductor region D1a, and the impurity concentration (n-type impurity concentration) of the n-type semiconductor region S1b is higher than the impurity concentration (n-type impurity concentration) of the n-type semiconductor region S1a.

[0031] The n-type semiconductor regions D1a and S1a are self-alignedly formed on the gate electrode G1, and the n-type semiconductor regions D1b and S1b are self-alignedly formed on sidewall spacers SW provided on the sidewalls of the gate electrode G1. Therefore, the n-type semiconductor region D1a is located under the sidewall spacer SW on one sidewall of the gate electrode G1, and the n-type semiconductor region S1a is located under the sidewall spacer SW on the other sidewall of the gate electrode G1. The n-type semiconductor region D1a and the n-type semiconductor region S1a are separated from each other with the channel formation region interposed therebetween (separated in the X direction). And the high-concentration n-type semiconductor regions D1b and S1b are formed outside the low-concentration n-type semiconductor regions D1a and S1a (on the side away from the channel formation region). The n-type semiconductor region D1b is separated from the channel formation region by the amount of the n-type semiconductor region D1a (separated in the X direction) and is formed at a position adjacent to the n-type semiconductor region D1a. The n-type semiconductor region S1b is separated from the channel formation region by the amount of the n-type semiconductor region S1a (separated in the X direction) and is formed at a position adjacent to the n-type semiconductor region S1a. The n-type semiconductor region D1a is interposed between the channel formation region and the n-type semiconductor region D1b, and the n-type semiconductor region S1a is interposed between the channel formation region and the n-type semiconductor region S1b.

[0032] Each of the n-type semiconductor regions D1 and S1 is formed in the semiconductor substrate SB (p-type well PW1) of the MISFET formation region 1A and extends in the Y direction along the gate electrode G1. Therefore, the n-type semiconductor region D1a and the n-type semiconductor region D1b that constitute the n-type semiconductor region D1 each extend in the Y direction along the gate electrode G1, and the n-type semiconductor region S1a and the n-type semiconductor region S1b that constitute the n-type semiconductor region S1 each extend in the Y direction along the gate electrode G1.

[0033] <<Configuration of MISFET2>> Next, the configuration of MISFET2 will be described with reference to FIGS. 4 to 6.

[0034] MISFET2 has a gate electrode G2 formed on the semiconductor substrate SB (on the p-type well PW2) of the MISFET formation region 2A via a gate insulating film GF2, and n-type semiconductor regions D2 and S2 for source and drain formed on both sides of the gate electrode G2 in a plan view.

[0035] The n-type semiconductor regions D2 and S2 are formed within the semiconductor substrate SB (p-type well PW2) of the MISFET formation region 2A. The n-type semiconductor region D2 is composed of an n-type semiconductor region (extension region, low-concentration region) D2a with a low impurity concentration and an n-type semiconductor region (high-concentration region) D2b with a higher impurity concentration than the n-type semiconductor region D2a. Similarly, the n-type semiconductor region S2 is composed of an n-type semiconductor region (extension region, low-concentration region) S2a with a low impurity concentration and an n-type semiconductor region (high-concentration region) S2b with a higher impurity concentration than the n-type semiconductor region S2a.

[0036] Regarding the gate electrode G2, gate insulating film GF2, n-type semiconductor regions D2, D2a, D2b, S2, S2a, S2b, and sidewall spacer SW, the descriptions in the above "Configuration of MISFET1" are applicable, and thus the repetitive descriptions are omitted here. However, when diverting the descriptions in the above "Configuration of MISFET1" as the descriptions in this "Configuration of MISFET1" section, the following replacements need to be made. That is, "MISFET1" is replaced with "MISFET2", "MISFET formation region 1A" is replaced with "MISFET formation region 2A", "p-type well PW1" is replaced with "p-type well PW2", "gate electrode G1" is replaced with "gate electrode G2", "gate insulating film GF1" is replaced with "gate insulating film GF2". Also, "n-type semiconductor region D1" is replaced with "n-type semiconductor region D2", "n-type semiconductor region D1a" is replaced with "n-type semiconductor region D2a", "n-type semiconductor region D1b" is replaced with "n-type semiconductor region D2b". Also, "n-type semiconductor region S1" is replaced with "n-type semiconductor region S2", "n-type semiconductor region S1a" is replaced with "n-type semiconductor region S2a", "n-type semiconductor region S1b" is replaced with "n-type semiconductor region S2b".

[0037] <<Configuration of MISFET3>> Next, the configuration of MISFET3 will be described with reference to FIGS. 4 to 6.

[0038] The configuration of MISFET2 and the configuration of MISFET3 are basically the same. MISFET3 has a gate electrode G3 formed on a semiconductor substrate SB (on a p-type well PW2) in a MISFET formation region 3A via a gate insulating film GF3, and n-type semiconductor regions D3, S3 for source and drain formed on both sides of the gate electrode G3 in a plan view.

[0039] The n-type semiconductor regions D3 and S3 are formed in the semiconductor substrate SB (p-type well PW2) of the MISFET formation region 3A. The n-type semiconductor region D3 is composed of an n-type semiconductor region with a low impurity concentration (extension region, low-concentration region) D3a and an n-type semiconductor region with a higher impurity concentration than the n-type semiconductor region D3a (high-concentration region) D3b. The n-type semiconductor region S3 is composed of an n-type semiconductor region with a low impurity concentration (extension region, low-concentration region) S3a and an n-type semiconductor region with a higher impurity concentration than the n-type semiconductor region S3a (high-concentration region) S3b.

[0040] Regarding the gate electrode G3, the gate insulating film GF3, the n-type semiconductor region D3, the n-type semiconductor region D3a, the n-type semiconductor region D3b, the n-type semiconductor region S3, the n-type semiconductor region S3a, the n-type semiconductor region S3b, and the sidewall spacer SW, the description in the above "Configuration of MISFET1" can be applied, so the repetitive description is omitted here. However, when diverting the description in the above "Configuration of MISFET1" as the description in this "Configuration of MISFET3" column, the following replacements need to be made. That is, "MISFET1" is replaced with "MISFET3", "MISFET formation region 1A" is replaced with "MISFET formation region 3A", "p-type well PW1" is replaced with "p-type well PW2", "gate electrode G1" is replaced with "gate electrode G3", and "gate insulating film GF1" is replaced with "gate insulating film GF3". Also, "n-type semiconductor region D1" is replaced with "n-type semiconductor region D3", "n-type semiconductor region D1a" is replaced with "n-type semiconductor region D3a", and "n-type semiconductor region D1b" is replaced with "n-type semiconductor region D3b". Also, "n-type semiconductor region S1" is replaced with "n-type semiconductor region S3", "n-type semiconductor region S1a" is replaced with "n-type semiconductor region S3a", and "n-type semiconductor region S1b" is replaced with "n-type semiconductor region S3b".

[0041] <<Regarding the p-type halo region>> MISFET1 further has p-type halo regions (p-type semiconductor regions, p-type pocket regions) HA1 and HA2 formed on the semiconductor substrate SB (p-type well PW1) of MISFET formation region 1A. In contrast, MISFET2 and MISFET3 do not have p-type halo regions (p-type pocket regions). Therefore, the semiconductor substrate SB (p-type well PW2) of MISFET formation region 2A and the semiconductor substrate SB (p-type well PW2) of MISFET formation region 3A do not have anything equivalent to p-type halo regions HA1 and HA2. The p-type halo regions HA1 and HA2 of MISFET1 are described below.

[0042] As shown in Figure 3, the p-type halo region HA1 is formed to cover (enclose) the n-type semiconductor region D1a in a cross-sectional view (a cross-sectional view approximately perpendicular to the Y direction), and the p-type halo region HA2 is formed to cover (enclose) the n-type semiconductor region S1a in a cross-sectional view (a cross-sectional view approximately perpendicular to the Y direction).

[0043] Therefore, the p-type halo region HA1 is adjacent to the side (the side facing the n-type semiconductor region S1a) and bottom surface of the n-type semiconductor region D1a, and the p-type halo region HA2 is adjacent to the side (the side facing the n-type semiconductor region D1a) and bottom surface of the n-type semiconductor region S1a. Parts of each of the p-type halo regions HA1 and HA2 overlap with the gate electrode G1 in a plan view. The p-type halo regions HA1 and HA2 have the opposite conductivity type to the n-type semiconductor regions D1a, S1a, D1b, and S1b, and the same conductivity type as the p-type well PW1, and have a higher impurity concentration (p-type impurity concentration) than the p-type well PW1. The p-type impurity concentration of the p-type halo regions HA1 and HA2 is, for example, 2 × 10⁻⁶. 17 ~1 × 10 19 cm 3 It can be set to a certain extent. Also, the p-type impurity concentration in the p-type well PW1 can be, for example, 1 × 10⁻⁶. 17 ~5×10 18 cm 3 It can be considered to be of a certain degree.

[0044] As described later, the ion implantation used to form the p-type halo regions HA1 and HA2 is oblique ion implantation (gradient ion implantation), which allows the p-type halo regions HA1 and HA2 to be formed so as to cover (enclose) the n-type semiconductor regions D1a and S1a. In general ion implantation (vertical ion implantation), impurity ions are accelerated and implanted in a direction perpendicular to the main surface of the semiconductor substrate SB, but in oblique ion implantation, impurity ions are accelerated and implanted in a direction that is tilted at a predetermined angle from the direction perpendicular to the main surface of the semiconductor substrate SB.

[0045] In the X direction, the n-type semiconductor region D1a and the p-type halo region HA1 are adjacent, and the n-type semiconductor region S1a and the p-type halo region HA2 are adjacent. Of the p-type halo region HA1, the portion adjacent to the n-type semiconductor region D1a in the X direction is located below the gate electrode G1, and of the p-type halo region HA2, the portion adjacent to the n-type semiconductor region S1a in the X direction is located below the gate electrode G1. Alternatively, of the p-type halo region HA1, the portion adjacent to the n-type semiconductor region D1a in the X direction overlaps with the gate electrode G1 in a plan view, and of the p-type halo region HA2, the portion adjacent to the n-type semiconductor region S1a in the X direction overlaps with the gate electrode G1 in a plan view. The p-type halo regions HA1 and HA2 located below the gate electrode G1 (i.e., the portions of the p-type halo regions HA1 and HA2 that overlap with the gate electrode G1 in a plan view) can function as part of the channel formation region.

[0046] <<MISFET1,2,3について> > The gate insulating films GF1 of MISFET1, GF2 of MISFET2, and GF3 of MISFET3 are formed in the same process. Therefore, gate insulating films GF1, GF2, and GF3 are made of the same insulating material (e.g., silicon oxide), and the thicknesses of gate insulating films GF1, GF2, and GF3 are the same.

[0047] The gate electrodes G1 of MISFET1, G2 of MISFET2, and G3 of MISFET3 are formed in the same process. That is, gate electrodes G1, G2, and G3 are formed by patterning a common conductive film (e.g., a polysilicon film). Therefore, gate electrodes G1, G2, and G3 are made of the same conductive material (e.g., polysilicon), and the thickness of gate electrode G1, G2, and G3 are the same.

[0048] The n-type semiconductor regions D1a, S1a and the p-type halo regions HA1, HA2 of MISFET1 are formed after the formation of the gate electrode G1 and before the formation of the sidewall spacer SW on the sidewall of the gate electrode G1. The n-type semiconductor regions D1a, S1a are formed by vertical ion implantation of n-type impurities, and the p-type halo regions HA1, HA2 are formed by oblique ion implantation of p-type impurities.

[0049] The n-type semiconductor regions D2a and S2a of MISFET2 are formed by vertical ion implantation of n-type impurities after the formation of the gate electrode G2 and before the formation of the sidewall spacer SW on the sidewall of the gate electrode G2. The n-type semiconductor regions D3a and S3a of MISFET3 are formed by vertical ion implantation of n-type impurities after the formation of the gate electrode G3 and before the formation of the sidewall spacer SW on the sidewall of the gate electrode G3.

[0050] Since MISFET2 does not have a p-type halo region, oblique ion implantation of p-type impurities is not performed on the semiconductor substrate SB (p-type well PW2) of MISFET formation region 2A after the formation of the gate electrode G2 and before the formation of the sidewall spacer SW on the sidewall of the gate electrode G2. Similarly, since MISFET3 does not have a p-type halo region, oblique ion implantation of p-type impurities is not performed on the semiconductor substrate SB (p-type well PW2) of MISFET formation region 3A after the formation of the gate electrode G3 and before the formation of the sidewall spacer SW on the sidewall of the gate electrode G3. This can be achieved by performing oblique ion implantation to form p-type halo regions HA1 and HA2 while a photoresist pattern is formed that covers the semiconductor substrate SB and gate electrodes G2 and G3 of MISFET formation regions 2A and 3A, and exposes the semiconductor substrate SB and gate electrode G1 of MISFET formation region 1A.

[0051] Since the n-type semiconductor regions D2b, S2b and D3b, S3b are formed by the same ion implantation process, the impurity concentrations (n-type impurity concentrations) of the n-type semiconductor regions D2b, S2b and the impurity concentrations (n-type impurity concentrations) of the n-type semiconductor regions D3b, S3b are the same.

[0052] <<Regarding the structure on the semiconductor substrate SB>> Next, we will describe the structure on the semiconductor substrate SB.

[0053] As shown in Figures 3, 5, and 6, an interlayer insulating film IL is formed on the semiconductor substrate SB as an insulating film, covering the gate electrodes G1, G2, G3 and the sidewall spacer SW. The interlayer insulating film IL is made of, for example, a silicon oxide film. The interlayer insulating film IL can also be formed by a laminate of a relatively thin silicon nitride film and a relatively thick silicon oxide film on the silicon nitride. The upper surface of the interlayer insulating film IL is flattened.

[0054] Contact holes are formed in the interlayer insulating film IL, and conductive plugs (contact plugs) PG, mainly made of tungsten (W) film, are formed (embedded) within the contact holes. Multiple plugs PG are provided, and each plug PG penetrates the interlayer insulating film IL. The plugs PG are formed on the n-type semiconductor regions D1b, S1b, D2b, S2b, D3b, S3b and the gate electrodes G1, G2, G3, respectively. Each of the n-type semiconductor regions D1b, S1b, D2b, S2b, D3b, S3b and the gate electrodes G1, G2, G3 are electrically connected to the plugs PG placed on top of them.

[0055] Furthermore, if a metal silicide layer (not shown) is formed on the upper part (surface layer) of each of the n-type semiconductor regions D1b, S1b, D2b, S2b, D3b, S3b and gate electrodes G1, G2, G3, each plug PG will be in contact with the metal silicide layer and electrically connected to the regions below the metal silicide layer via that layer.

[0056] On the interlayer insulating film IL into which the plug PG is embedded, wiring (first layer wiring) M1 is formed, consisting mainly of a conductive film made of aluminum (Al) or an aluminum alloy. The wiring M1 is not limited to aluminum wiring, but can also be wiring made of other metal materials, such as tungsten wiring or copper wiring. Each plug PG is electrically connected to the wiring M1.

[0057] The structure of the layers above the interlayer insulating film IL and wiring M1 is not shown or described here. In reality, even higher layers of wiring and insulating films are formed.

[0058] Here, the gate electrode G2 of MISFET2 and the gate electrode G3 of MISFET3 are electrically connected. In the cases of Figures 4 and 6, the gate electrode G2 of MISFET2 and the gate electrode G3 of MISFET3 are electrically connected through a plug PG placed on the gate electrode G2, a plug PG placed on the gate electrode G3, and a wiring M1 (gate wiring M1G shown in Figure 6) connecting them. As a method of electrically connecting the gate electrode G2 of MISFET2 and the gate electrode G3 of MISFET3, the gate electrode G2 and the gate electrode G3 can also be formed to be connected integrally, as shown in Figure 7. Figure 7 is a plan view of the main part of a modified example of the semiconductor device of this embodiment, and corresponds to Figure 4. In the case of Figure 7, one end of the gate electrode G2 extending in the Y direction and one end of the gate electrode G3 extending in the Y direction are integrally connected to a gate connection portion GC extending in the X direction. The gate connection portion GC is integrally formed with the gate electrodes G2 and G3 and is located on the element isolation region ST. As a result, the gate electrode G2 of MISFET2 and the gate electrode G3 of MISFET3 are electrically connected through the gate connector GC. In this case, it is not necessary to connect the gate electrode G2 of MISFET2 and the gate electrode G3 of MISFET3 with gate wiring M1G. Since the gate connector GC is formed integrally with the gate electrodes G2 and G3, it is formed in the same process as the gate electrodes G2 and G3 and is made of the same material (e.g., polysilicon) as the gate electrodes G2 and G3. In addition, the sidewall spacer SW is also formed on the side wall of the gate connector GC.

[0059] <Regarding the manufacturing process of semiconductor devices> Next, the method for manufacturing the semiconductor device of this embodiment will be described with reference to the drawings.

[0060] Figures 8 to 21 are cross-sectional views of key parts during the manufacturing process of the semiconductor device of this embodiment. Of these, Figures 8, 10, 12, 14, 16, 18, and 20 show cross-sections that are approximately equivalent to those in Figure 3 (cross-sections at the position of line A1-A1 in Figure 1), while Figures 9, 11, 13, 15, 17, 19, and 21 show cross-sections that are approximately equivalent to those in Figure 5 (cross-sections at the position of line A2-A2 in Figure 4).

[0061] To manufacture a semiconductor device, as shown in Figures 8 and 9, first, a semiconductor substrate (semiconductor wafer) SB made of, for example, p-type single-crystal silicon having a resistivity of about 1 to 10 Ωcm is prepared. Then, an element isolation region ST is formed on the main surface of the semiconductor substrate SB. The element isolation region ST is made of an insulator such as silicon oxide and can be formed by the STI method.

[0062] Next, as shown in Figures 10 and 11, p-type wells PW1 and PW2 are formed in the semiconductor substrate SB using ion implantation. P-type wells PW1 and PW2 can be formed in the same ion implantation process, in which case the impurity concentration (p-type impurity concentration) of p-type well PW1 and the impurity concentration (p-type impurity concentration) of p-type well PW2 are substantially the same. P-type wells PW1 and PW2 are formed to a predetermined depth from the main surface of the semiconductor substrate SB, and in a plan view, the MISFET formation region 1A is contained within p-type well PW1, and the MISFET formation regions 2A and 3A are contained within p-type well PW2.

[0063] Next, as shown in Figures 10 and 11, a gate electrode G1 is formed on the semiconductor substrate SB (p-type well PW1) of the MISFET formation region 1A via a gate insulating film GF1, a gate electrode G2 is formed on the semiconductor substrate SB (p-type well PW2) of the MISFET formation region 2A via a gate insulating film GF2, and a gate electrode G3 is formed on the semiconductor substrate SB (p-type well PW2) of the MISFET formation region 3A via a gate insulating film GF3. This process can be carried out, for example, as follows.

[0064] Specifically, an insulating film for the gate insulating film is formed on the main surface of the semiconductor substrate SB, then a conductive film (e.g., a polysilicon film) for forming gate electrodes G1, G2, and G3 is formed on top of it, and then the conductive film is patterned using photolithography and dry etching to form gate electrodes G1, G2, and G3. The insulating film remaining beneath each of the gate electrodes G1, G2, and G3 (the insulating film for the gate insulating film) becomes the gate insulating film (GF1, GF2, GF3). Therefore, the thicknesses of the gate insulating films GF1, GF2, and GF3 are all the same, and the thicknesses of the gate electrodes G1, G2, and G3 are all the same.

[0065] Next, as shown in Figures 12 and 13, n-type semiconductor regions D1a, S1a, D2a, S2a, D3a, and S3a are formed by vertical ion implantation of n-type impurities.

[0066] In this ion implantation, the gate electrodes G1, G2, and G3 can function as masks (ion implantation blocking masks). Therefore, in the semiconductor substrate SB (p-type well PW1) of the MISFET formation region 1A, n-type semiconductor regions D1a and S1a are formed on both sides of the gate electrode G1. Similarly, in the semiconductor substrate SB (p-type well PW2) of the MISFET formation region 2A, n-type semiconductor regions D2a and S2a are formed on both sides of the gate electrode G2. Furthermore, in the semiconductor substrate SB (p-type well PW2) of the MISFET formation region 3A, n-type semiconductor regions D3a and S3a are formed on both sides of the gate electrode G3. No impurities are implanted in the region directly beneath the gate electrodes G1, G2, and G3 in the semiconductor substrate SB. The n-type semiconductor regions D1a, S1a, D2a, S2a, and D3a, S3a can be formed in the same ion implantation process, in which case their impurity concentrations (n-type impurity concentrations) will be the same.

[0067] Alternatively, after forming the gate electrodes G1, G2, and G3, a photoresist pattern (not shown) can be formed on the semiconductor substrate SB using photolithography technology, and ion implantation can be performed to form n-type semiconductor regions D1a, S1a, D2a, S2a, D3a, and S3a while the photoresist pattern is formed. In this case, the MISFET formation regions 1A, 2A, and 3A should not be covered by the photoresist pattern. The photoresist pattern is removed after the n-type semiconductor regions D1a, S1a, D2a, S2a, D3a, and S3a are formed.

[0068] Next, as shown in Figures 14 and 15, a photoresist pattern (resist pattern) PR1 is formed on the semiconductor substrate SB using photolithography technology. The photoresist pattern PR1 is formed so as to cover the MISFET formation regions 2A and 3A, and expose the MISFET formation region 1A. The MISFET formation region 1A can be considered as the region on the semiconductor substrate SB where MISFET 1 should be formed. The MISFET formation region 2A can be considered as the region on the semiconductor substrate SB where MISFET 2 should be formed. The MISFET formation region 3A can be considered as the region on the semiconductor substrate SB where MISFET 3 should be formed.

[0069] Next, as shown in Figures 14 and 15, p-type halo regions HA1 and HA2 are formed in the semiconductor substrate SB (p-type well PW1) of the MISFET formation region 1A by oblique ion implantation of p-type impurities.

[0070] In this ion implantation, the gate electrode G1 can function as a mask (ion implantation blocking mask). However, because oblique ion implantation is performed, the p-type halo region HA1 is formed to enclose (cover) the n-type semiconductor region D1a, and the p-type halo region HA2 is formed to enclose (cover) the n-type semiconductor region S1a. Parts of each of the p-type halo regions HA1 and HA2 are located directly below the gate electrode G1 (i.e., overlapping the gate electrode G1 in a plan view). The p-type halo regions HA1 and HA2 are spaced apart in the Y direction. The p-type halo regions HA1 and HA2 have the same conductivity type as the p-type well PW, but have a higher p-type impurity concentration than the p-type well PW.

[0071] In ion implantation to form p-type halo regions HA1 and HA2, the photoresist pattern PR1 can also function as a mask (ion implantation blocking mask). Therefore, in this ion implantation, p-type impurities are not implanted into the semiconductor substrate SB (p-type well PW2) of the MISFET formation regions 2A and 3A. After forming the gate electrodes G1, G2, and G3, and before forming the sidewall spacer SW, no impurities of the same conductivity type as the p-type well PW2 (p-type impurities) are ion-implanted into the semiconductor substrate SB (p-type well PW2) of the MISFET formation regions 2A and 3A. For this reason, no p-type halo regions (corresponding to p-type halo regions HA1 and HA2) are formed in the semiconductor substrate SB (p-type well PW2) of the MISFET formation regions 2A and 3A.

[0072] After forming the p-type halo regions HA1 and HA2, the photoresist pattern PR1 is removed by ashing or other methods.

[0073] Next, as shown in Figures 16 and 17, sidewall spacers SW made of, for example, silicon oxide, silicon nitride, or a multilayer film thereof are formed on the sidewalls of the gate electrodes G1, G2, and G3. The sidewall spacers SW can be formed, for example, by depositing a silicon oxide film, a silicon nitride film, or a multilayer film thereof on the entire main surface of the semiconductor substrate SB, and then etching it back using an anisotropic etching technique.

[0074] Next, as shown in Figures 18 and 19, n-type semiconductor regions D1b, S1b, D2b, S2b, D3b, and S3b are formed by ion implantation of n-type impurities (preferably vertical ion implantation).

[0075] In this ion implantation, the gate electrodes G1, G2, G3 and the sidewall spacer SW can function as masks (ion implantation blocking masks). Therefore, in the semiconductor substrate SB (p-type well PW1) of the MISFET formation region 1A, the n-type semiconductor regions D1b and S1b are formed on both sides of the structure consisting of the gate electrode G1 and the sidewall spacer SW on its sidewall. Similarly, in the semiconductor substrate SB (p-type well PW2) of the MISFET formation region 2A, the n-type semiconductor regions D2b and S2b are formed on both sides of the structure consisting of the gate electrode G2 and the sidewall spacer SW on its sidewall. Furthermore, in the semiconductor substrate SB (p-type well PW2) of the MISFET formation region 3A, the n-type semiconductor regions D3b and S3b are formed on both sides of the structure consisting of the gate electrode G3 and the sidewall spacer SW on its sidewall. In the semiconductor substrate SB, no impurities are implanted in the regions directly beneath the gate electrodes G1, G2, G3 and directly beneath the sidewall spacer SW.

[0076] The n-type impurity concentration in n-type semiconductor regions D1b and S1b is higher than that in n-type semiconductor regions D1a and S1a; the n-type impurity concentration in n-type semiconductor regions D2b and S2b is higher than that in n-type semiconductor regions D2a and S2a; and the n-type impurity concentration in n-type semiconductor regions D3b and S3b is higher than that in n-type semiconductor regions D3a and S3a. The n-type semiconductor regions D1b and S1b, D2b and S2b, and D3b and S3b can be formed by the same ion implantation process, in which case their impurity concentrations (n-type impurity concentrations) will be the same.

[0077] Next, if necessary, activation annealing is performed, which is a heat treatment to activate the impurities introduced by the ion implantation process.

[0078] In this way, MISFET1,2,3 are formed.

[0079] Next, if necessary, a metal silicide layer (not shown) is formed on the upper part (upper layer) of each of the n-type semiconductor regions D1b, S1b, D2b, S2b, D3b, S3b and gate electrodes G1, G2, G3 using salicide (self-aligned silicide) technology.

[0080] Next, as shown in Figures 20 and 21 above, an interlayer insulating film IL is formed on the main surface of the semiconductor substrate SB so as to cover the gate electrodes G1, G2, G3 and the sidewall spacer SW. After the formation of the interlayer insulating film IL, the flatness of the interlayer insulating film IL can be improved by polishing the upper surface of the interlayer insulating film IL using the CMP method.

[0081] Next, contact holes are formed in the interlayer insulating film IL, and then plugs PG are formed inside the contact holes.

[0082] Next, wiring M1 is formed on the interlayer insulating film IL. Subsequently, upper layers of interlayer insulating film and wiring are formed, but their illustration and explanation are omitted here.

[0083] As described above, the semiconductor device of this embodiment is manufactured.

[0084] <Examples of variations in the semiconductor device manufacturing process> Next, a first modified example of the semiconductor device manufacturing process of this embodiment will be described with reference to Figures 22 to 28. Here, we will describe the case of manufacturing a semiconductor device having MISFETs 1, 2, and 3 and a resistive element (polysilicon resistive element) PS. Of Figures 22 to 28, Figures 22, 25, and 28 show cross-sectional views of the resistive element formation region 5A, which is the region (planar region) where the resistive element PS is formed. Also, of Figures 22 to 28, Figures 23 and 26 show cross-sections that are approximately equivalent to Figure 3 (cross-sections at the position of line A1-A1 in Figure 1), and Figures 24 and 27 show cross-sections that are approximately equivalent to Figure 5 (cross-sections at the position of line A2-A2 in Figure 4).

[0085] Figure 22 is a cross-sectional view of the resistive element formation region 5A, showing the same process steps as in Figures 10 and 11, and illustrates the state in which the resistive element PS is formed on the element isolation region ST. The resistive element PS is made of polysilicon and is formed in the same process as the gate electrodes G1, G2, and G3. Specifically, after forming an insulating film for the gate insulating film on the main surface of the semiconductor substrate SB, a polysilicon film is formed that serves both for gate electrode formation and resistive element formation. Subsequently, the polysilicon film is patterned using photolithography and dry etching to form the gate electrodes G1, G2, G3 and the resistive element PS together.

[0086] After forming the gate electrodes G1, G2, G3 and the resistive element PS, a photoresist pattern (resist pattern) PR2 is formed on the semiconductor substrate SB using photolithography, as shown in Figures 23 to 25. The photoresist pattern PR2 is formed so as to cover the MISFET formation regions 2A, 3A and the resistive element formation region 5A, while exposing the MISFET formation region 1A. The resistive element formation region 5A can be considered as the region on the semiconductor substrate SB where the resistive element PS should be formed. The resistive element PS is covered with the photoresist pattern PR2.

[0087] Next, as shown in Figures 23 to 25, n-type semiconductor regions D1a and S1a are formed in the semiconductor substrate SB (p-type well PW1) of the MISFET formation region 1A by vertical ion implantation of n-type impurities. In the ion implantation for forming the n-type semiconductor regions D1a and S1a, the photoresist pattern PR2 can also function as a mask (ion implantation blocking mask), so n-type impurities are not implanted in the semiconductor substrate SB (p-type well PW2) of the MISFET formation regions 2A and 3A and in the resistive element PS of the resistive element formation region 5A.

[0088] Next, as shown in Figures 23 to 25, p-type halo regions HA1 and HA2 are formed in the semiconductor substrate SB (p-type well PW1) of the MISFET formation region 1A by oblique ion implantation of p-type impurities. In the ion implantation for forming the p-type halo regions HA1 and HA2, the photoresist pattern PR2 can also function as a mask (ion implantation blocking mask), so p-type impurities are not implanted in the semiconductor substrate SB (p-type well PW2) of the MISFET formation regions 2A and 3A and in the resistive element PS of the resistive element formation region 5A.

[0089] Note that the order of vertical ion implantation for forming n-type semiconductor regions D1a and S1a and oblique ion implantation for forming p-type halo regions HA1 and HA2 does not matter.

[0090] Next, after removing the photoresist pattern PR2 by ashing or other means, a photoresist pattern (resist pattern) PR3 is formed on the semiconductor substrate SB using photolithography technology, as shown in Figures 26 to 28. The photoresist pattern PR3 is formed so as to cover the MISFET formation region 1A and expose the MISFET formation regions 2A, 3A and the resistor element formation region 5A. The resistor element PS is exposed and not covered by the photoresist pattern PR3.

[0091] Next, as shown in Figures 26 to 28, n-type semiconductor regions D2a, S2a, D3a, and S3a are formed in the semiconductor substrate SB (p-type well PW2) of the MISFET formation regions 2A and 3A by vertical ion implantation of n-type impurities. At this time, the resistive element PS is exposed and not covered by the photoresist pattern PR3, so n-type impurities are also implanted into the resistive element PS. As a result, the resistive element PS is adjusted to an impurity concentration suitable for a resistive element. Since the n-type semiconductor regions D2b, S2b, D3b, and S3b can be formed in the same ion implantation process, their impurity concentrations (n-type impurity concentrations) will be the same. The impurity concentrations (n-type impurity concentrations) of the n-type semiconductor regions D1a and S1a may differ from the impurity concentrations (n-type impurity concentrations) of the n-type semiconductor regions D2a, S2a, D3a, and S3a. Furthermore, in ion implantation to form n-type semiconductor regions D2a, S2a, D3a, and S3a, the photoresist pattern PR3 can also function as a mask (ion implantation blocking mask), so n-type impurities are not implanted into the semiconductor substrate SB (p-type well PW1) of the MISFET formation region 1A. Subsequently, the photoresist pattern PR3 is removed by ashing or other methods.

[0092] Next, as shown in Figures 16 and 17 above, sidewall spacers SW are formed on the sidewalls of the gate electrodes G1, G2, and G3. Although not shown here, sidewall spacers SW are also formed on the sidewalls of the resistive elements PS. The subsequent steps are almost the same as those described with reference to Figures 18 to 21 above, so a repeated explanation is omitted here. However, it is preferable to perform the ion implantation for forming the n-type semiconductor regions D1b, S1b, D2b, S2b, D3b, and S3b with a photoresist pattern formed that covers the resistive elements PS in the resistive element formation region 5A and exposes the MISFET formation regions 1A, 2A, and 3A. This prevents n-type impurities from being implanted into the resistive elements PS during the ion implantation step for forming the n-type semiconductor regions D1b, S1b, D2b, S2b, D3b, and S3b.

[0093] In the manufacturing process of the first modified example, ion implantation to form the n-type semiconductor regions D2a, S2a, D3a, and S3a of MISFETs 2 and 3 that do not have halo regions, and ion implantation to introduce impurities into the resistive element PS are performed by a common ion implantation. Also, in the manufacturing process of the first modified example, in the ion implantation process to form p-type halo regions HA1 and HA2 in the MISFET formation region 1A, the photoresist pattern PR2 for preventing ion implantation into the semiconductor substrate SB of the MISFET formation regions 2A and 3A, and the photoresist pattern PR2 for preventing ion implantation into the resistive element PS are common. Therefore, in the manufacturing process of the first modified example, even if MISFETs 2 and 3 that do not have halo regions are not formed, the number of required ion implantation processes and the number of photoresist pattern formations remain unchanged. In other words, when manufacturing a semiconductor device having a MISFET 1 with a halo region and a resistive element PS, applying the manufacturing process of the first modified example allows for the formation of MISFETs 2 and 3 that do not have halo regions without increasing the number of manufacturing processes. Therefore, in the case of the manufacturing process of the first modified example, a semiconductor device having a MISFET1 with a halo region, MISFETs2 and3 without a halo region, and a resistive element PS can be manufactured while suppressing the number of manufacturing steps (and thus suppressing the manufacturing cost of the semiconductor device).

[0094] Next, a second modification of the semiconductor device manufacturing process of this embodiment will be described with reference to Figures 29 to 36. Here, we will describe the case of manufacturing a semiconductor device having MISFETs 1, 2, 3 and a high-voltage MISFET 4. Of Figures 29 to 36, Figures 29, 31, 33, and 35 show a cross-sectional view of the MISFET formation region 1A (a cross-section at the position of line A1-A1 in Figure 1) on the left side of the figure, and a cross-sectional view of the high-voltage MISFET formation region 4A, which is the region (active region) where the high-voltage MISFET 4 is formed, on the right side of the figure. In addition, of Figures 29 to 36, Figures 30, 32, 34, and 36 show cross-sectional views that are approximately equivalent to Figure 5 (a cross-section at the position of line A2-A2 in Figure 4).

[0095] Figures 29 and 30 show the process steps corresponding to Figures 10 and 11, and show the stage in which gate electrodes G1, G2, G3, and G4 are formed. In the high-voltage MISFET formation region 4A, a p-type well PW4 is formed on the semiconductor substrate SB, and the gate electrode G4 is formed on the semiconductor substrate SB (on the p-type well PW4) via a gate insulating film GF4. The thickness of the gate insulating film GF4 of the high-voltage MISFET 4 is greater than the thickness of the gate electrodes GF1, GF2, and GF3 of MISFETs 1, 2, and 3, respectively. This makes it possible to raise the breakdown voltage of MISFET 4 to be higher than that of MISFETs 1, 2, and 3, respectively.

[0096] The gate electrode G4 of the high-voltage MISFET4 can be formed in the same process as the gate electrodes G1, G2, and G3. Specifically, insulating films for gate insulating films GF1, GF2, and GF3 are formed on the semiconductor substrate SB of the MISFET formation regions 1A, 2A, and 3A, and an insulating film for gate insulating film GF4 (a thicker insulating film than those for gate insulating films GF1, GF2, and GF3) is formed on the semiconductor substrate SB of the high-voltage MISFET formation region 4A. Then, a conductive film (e.g., a polysilicon film) for forming gate electrodes G1, G2, G3, and G4 is formed. Subsequently, the gate electrodes G1, G2, G3, and G4 can be formed by patterning the conductive film using photolithography and dry etching. As a result, the thicknesses of the gate insulating films GF1, GF2, and GF3 are the same, but the gate insulating film GF4 is thicker than the gate electrodes GF1, GF2, and GF3 of MISFETs 1, 2, and 3. Also, the thicknesses of the gate electrodes G1, G2, G3, and G4 are the same.

[0097] Next, as shown in Figures 31 and 32, a photoresist pattern (resist pattern) PR4 is formed on the semiconductor substrate SB using photolithography technology. The photoresist pattern PR4 is formed so as to cover the MISFET formation regions 2A, 3A, and 4A, and expose the MISFET formation region 1A. The high-voltage MISFET formation region 4A can be considered as the region on the semiconductor substrate SB where the high-voltage MISFET 4 should be formed.

[0098] Next, as shown in Figures 31 and 32, n-type semiconductor regions D1a and S1a are formed in the semiconductor substrate SB (p-type well PW1) of the MISFET formation region 1A by vertical ion implantation of n-type impurities. In the ion implantation for forming the n-type semiconductor regions D1a and S1a, the photoresist pattern PR4 can also function as a mask (ion implantation blocking mask), so n-type impurities are not implanted in the semiconductor substrate SB (p-type wells PW2 and PW4) of the MISFET formation regions 2A, 3A, and 4A.

[0099] Next, as shown in Figures 31 and 32, p-type halo regions HA1 and HA2 are formed in the semiconductor substrate SB (p-type well PW1) of the MISFET formation region 1A by oblique ion implantation of p-type impurities. In the ion implantation for forming the p-type halo regions HA1 and HA2, the photoresist pattern PR4 can also function as a mask (ion implantation blocking mask), so p-type impurities are not implanted in the semiconductor substrate SB (p-type wells PW2 and PW4) of the MISFET formation regions 2A, 3A, and 4A.

[0100] Note that the order of vertical ion implantation for forming n-type semiconductor regions D1a and S1a and oblique ion implantation for forming p-type halo regions HA1 and HA2 does not matter.

[0101] Next, after removing the photoresist pattern PR4 by ashing or the like, a photoresist pattern (resist pattern) PR5 is formed on the semiconductor substrate SB using photolithography technology, as shown in Figures 33 and 34. The photoresist pattern PR5 is formed so as to cover the MISFET formation region 1A and expose the MISFET formation regions 2A, 3A, and 4A.

[0102] Next, as shown in Figures 33 and 34, n-type semiconductor regions D2a, S2a, D3a, S3a, D4a, and S4a are formed in the semiconductor substrate SB (p-type wells PW2 and PW4) of the MISFET formation regions 2A, 3A, and 4A by vertical ion implantation of n-type impurities. In the semiconductor substrate SB (p-type well PW4) of the high-voltage MISFET formation region 4A, n-type semiconductor regions D4a and S4a are formed on both sides of the gate electrode G4. Since the n-type semiconductor regions D2a, S2a, D3a, S3a, D4a, and S4a can be formed in the same ion implantation process, their impurity concentrations (n-type impurity concentrations) are the same. The impurity concentrations (n-type impurity concentrations) of n-type semiconductor regions D1a and S1a may differ from the impurity concentrations (n-type impurity concentrations) of n-type semiconductor regions D2a, S2a, D3a, S3a, D4a, and S4a. Furthermore, in ion implantation to form n-type semiconductor regions D2a, S2a, D3a, S3a, D4a, and S4a, the photoresist pattern PR5 can also function as a mask (ion implantation blocking mask), so n-type impurities are not implanted into the semiconductor substrate SB (p-type well PW1) of the MISFET formation region 1A. Subsequently, the photoresist pattern PR5 is removed by ashing or other methods.

[0103] Next, as shown in Figures 35 and 36, sidewall spacers SW are formed on the side walls of gate electrodes G1, G2, G3, and G4.

[0104] Next, as shown in Figures 35 and 36, n-type semiconductor regions D1b, S1b, D2b, S2b, D3b, S3b, D4a, and S4a are formed by ion implantation of n-type impurities (preferably vertical ion implantation). The n-type semiconductor regions D4b and S4b are formed on both sides of the structure consisting of the gate electrode G4 and the sidewall spacer SW on its sidewall in the semiconductor substrate SB (p-type well PW4) of the high-voltage MISFET formation region 4A. The n-type impurity concentration in the n-type semiconductor regions D4b and S4b is higher than the n-type impurity concentration in the n-type semiconductor regions D4a and S4a. The n-type semiconductor region D4b and the n-type semiconductor region D4a form one of the source and drain regions of the high-voltage MISFET 4, and the n-type semiconductor region S4b and the n-type semiconductor region S4a form the other of the source and drain regions of the high-voltage MISFET 4. n-type semiconductor regions D1b,S1b, n-type semiconductor regions D2b,S2b, n-type semiconductor regions D3b,S3b, and n-type semiconductor regions D4b,S4b can be formed by the same ion implantation process, in which case their impurity concentrations (n-type impurity concentrations) will be the same.

[0105] Next, if necessary, activation annealing is performed, which is a heat treatment to activate the impurities introduced by the ion implantation process. The subsequent steps are almost the same as those described with reference to Figures 20 and 21 above, so a repeated explanation will be omitted here.

[0106] In the manufacturing process of the second modified example, the ion implantation to form the n-type semiconductor regions D2a, S2a, D3a, and S3a of MISFETs 2 and 3, which do not have halo regions, and the ion implantation to form the n-type semiconductor regions D4a and S4a of the high-voltage MISFET 4 are performed by a common ion implantation. Furthermore, in the manufacturing process of the second modified example, the photoresist pattern PR4 for preventing ion implantation into the semiconductor substrate SB of MISFET formation regions 2A and 3A and the photoresist pattern PR4 for preventing ion implantation into the semiconductor substrate SB of the high-voltage MISFET formation region 4A are common to the ion implantation process for forming p-type halo regions HA1 and HA2 in the MISFET formation region 1A. Therefore, in the manufacturing process of the second modified example, even if MISFETs 2 and 3, which do not have halo regions, are not formed, the number of required ion implantation processes and the number of photoresist pattern formations remain unchanged. In other words, when manufacturing a semiconductor device having MISFET1 with a halo region and MISFET4 with high voltage resistance, applying the manufacturing process of the second modified example allows for the formation of MISFETs2 and3 without a halo region without increasing the number of manufacturing steps. Therefore, in the case of the manufacturing process of the second modified example, a semiconductor device having MISFET1 with a halo region, MISFETs2 and3 without a halo region, and MISFET4 with high voltage resistance can be manufactured while suppressing the number of manufacturing steps (and thus suppressing the manufacturing cost of the semiconductor device).

[0107] <Regarding the background of the consideration> The inventors of this invention are studying semiconductor devices that incorporate oscillator circuits (oscillating circuits), and in particular, microcontrollers that incorporate oscillator circuits.

[0108] To improve the performance of semiconductor devices (especially microcontrollers) that incorporate oscillator circuits, it is important to improve the accuracy of the oscillator circuit's oscillation frequency. To improve the accuracy of the oscillator circuit's oscillation frequency, it is effective to improve the relative precision of the paired transistors included in the oscillator circuit.

[0109] A paired transistor refers to a pair of MISFETs formed adjacent to each other on a semiconductor substrate (corresponding to the semiconductor substrate SB) that constitutes a semiconductor device, with their gate electrodes electrically connected to each other. MISFET2 and MISFET3, shown in Figures 4 to 6, are formed adjacent to each other on the semiconductor substrate SB, and the gate electrode G2 of MISFET2 and the gate electrode G3 of MISFET3 are electrically connected to each other via a plug PG and gate wiring M1G (or via a gate connection GC in the case of Figure 7). Therefore, MISFET2 and MISFET3 constitute a paired transistor.

[0110] Figure 37 is a circuit diagram showing an example of an oscillator circuit, illustrating a portion of the oscillator circuit. In the oscillator circuit of Figure 37, paired transistors are enclosed by dashed lines. Paired transistor PT1 is composed of two adjacent MISFETs (i.e., a pair of MISFETs) with their gates connected. While paired transistor PT1 is the basic form, in the oscillator circuit of Figure 37, paired transistor PT2 corresponds to two paired transistors (i.e., two pairs of MISFETs), and similarly, paired transistor PT3 also corresponds to two paired transistors (i.e., two pairs of MISFETs).

[0111] In an oscillator circuit, the pair of transistors comprising the MISFETs must have electrical characteristics (voltage-current characteristics, typically threshold voltage) that match as closely as possible. If the electrical characteristics (voltage-current characteristics) of the MISFETs comprising the pair of transistors in the oscillator circuit are mismatched, the oscillation frequency of the oscillator circuit may fluctuate. To make the oscillation frequency of the oscillator circuit match the design value, it is effective to match the electrical characteristics (voltage-current characteristics) of the MISFETs comprising the pair of transistors in the oscillator circuit as closely as possible. In other words, it is effective to minimize the difference in electrical characteristics (voltage-current characteristics) between the MISFETs comprising the pair of transistors in the oscillator circuit, and to ensure that the amount of this difference does not fluctuate.

[0112] Here, the difference (degree of difference) in the electrical characteristics (voltage-current characteristics, typically threshold voltage) between MISFETs constituting a pair of transistors will be referred to as the relative precision of the pair of transistors. Therefore, high relative precision of a pair of transistors means that the difference in the electrical characteristics between the MISFETs constituting the pair of transistors is small. Conversely, low relative precision of a pair of transistors means that the difference in the electrical characteristics between the MISFETs constituting the pair of transistors is large. Furthermore, variation (fluctuation) in the relative precision of a pair of transistors means that the difference in the electrical characteristics between the MISFETs constituting the pair of transistors varies (fluctuations) from one pair of transistor to another. Furthermore, large variation in the relative precision of a pair of transistors means that the difference in the electrical characteristics between the MISFETs constituting the pair of transistors varies (fluctuations) from one pair of transistor to another, and that the degree of this variation is large. Furthermore, suppressing variation in the relative precision of a pair of transistors means suppressing the variation (fluctuation) in the difference in the electrical characteristics between the MISFETs constituting the pair of transistors from one pair of transistor to another.

[0113] In semiconductor devices (especially microcontrollers) that incorporate oscillator circuits, it is important to improve the relative precision of the paired transistors included in the oscillator circuit and to suppress variations in the relative precision of the paired transistors included in the oscillator circuit. This improves the accuracy of the oscillation frequency of the oscillator circuit and enhances the performance of the semiconductor device (especially microcontrollers) that incorporates the oscillator circuit.

[0114] Incidentally, the source and drain regions of a MISFET have an LDD structure and consist of a low-concentration region and a high-concentration region. If a halo region (corresponding to the p-type halo regions HA1 and HA2 mentioned above) is formed adjacent to the low-concentration region and has the opposite conductivity to the low-concentration region, the short-channel effect can be suppressed. For this reason, it is common to use MISFETs with halo regions in the various circuits of a microcontroller.

[0115] However, the inventors' studies have shown that when MISFETs with a halo region are used to constitute a pair of transistors, the variation in the relative accuracy of the pair of transistors increases. The reason for this is as follows: When comparing a MISFET with a halo region to a MISFET without a halo region, the MISFET with a halo region has a higher impurity concentration in the channel formation region due to the presence of the halo region. Furthermore, the impurity concentration in the channel formation region of the MISFET may fluctuate due to unintended fluctuations in ion implantation conditions, and the degree of fluctuation in the impurity concentration in the channel formation region of the MISFET increases as the impurity concentration in the channel formation region of the MISFET increases. For this reason, the impurity concentration in the channel formation region of the MISFET is more susceptible to fluctuations due to unintended fluctuations in ion implantation conditions than the MISFET without a halo region, and as a result, the electrical characteristics of the MISFET (voltage-current characteristics, typically the threshold voltage) are more prone to fluctuation. As a result, when MISFETs with a halo region are used to constitute a pair of transistors, the variation in the relative accuracy of the pair of transistors increases.

[0116] Therefore, it has been found that in semiconductor devices (especially microcontrollers) that incorporate oscillator circuits, if MISFETs with a halo region are used for the paired transistors included in the oscillator circuit, the variation in the relative accuracy of the paired transistors increases, which can reduce the accuracy of the oscillation frequency of the oscillator circuit and potentially degrade the performance of the semiconductor device (especially microcontrollers) that incorporates the oscillator circuit.

[0117] Therefore, to suppress variations in the relative accuracy of paired transistors using MISFETs with a halo region, it is conceivable to increase the planar dimensions of the MISFETs with the halo region. Increasing the planar dimensions (channel area) of the MISFETs constituting the paired transistors can suppress variations in the relative accuracy of the paired transistors. However, increasing the planar dimensions (channel area) of the MISFETs constituting the paired transistors increases the area of ​​the semiconductor device, which is not a desirable approach.

[0118] <Regarding the circuit configuration of semiconductor devices> Figure 38 is a circuit block diagram of the semiconductor device of this embodiment. As shown in Figure 38, the semiconductor device 11 of this embodiment is a semiconductor device equipped with an oscillator circuit (oscillating circuit) 12, and more specifically, a microcontroller equipped with an oscillator circuit 12. The semiconductor device 11 includes the oscillator circuit 12, a CPU (Central Processing Unit) 13, flash memory (non-volatile memory) 14, SRAM (Random Access Memory) 15, registers 16, and peripheral circuits 17 other than the oscillator circuit. The oscillator circuit 12 is an on-chip oscillator circuit, and specifically, it is a clock generation circuit. The CPU 13 is composed of logic circuits. For this reason, the CPU 13 can also be considered as a logic circuit section. In addition, the flash memory 14, SRAM 15, and registers 16 all function as storage sections, and therefore can each be considered as storage circuits.

[0119] <Main Features and Effects> The semiconductor device of this embodiment, as shown in Figures 1 to 7, includes a semiconductor substrate SB and a plurality of MISFETs 1, 2, and 3 formed on the semiconductor substrate SB. Although only one MISFET 1 is shown in Figures 1 to 3, in reality, multiple MISFETs 1 are formed on the semiconductor substrate SB. Similarly, although only one MISFET 2 and one MISFET 3 are shown in Figures 4 to 7, in reality, multiple MISFETs 2 and 3 are formed on the semiconductor substrate SB. However, the gate electrodes of MISFET 2 and MISFET 3 are electrically connected to each other to form a pair transistor.

[0120] As described above, MISFET1 is a MISFET that has a halo region (corresponding to the p-type halo regions HA1 and HA2 above), while MISFET2 and 3 are MISFETs that do not have a halo region, as described above.

[0121] One of the main features of this embodiment is that the pair of transistors included in the oscillator circuit 12 of the semiconductor device 11 uses MISFETs 2 and 3, which do not have a halo region, instead of MISFET 1, which has a halo region.

[0122] As explained in the "Background of Consideration" section above, unlike this embodiment, if a MISFET with a halo region is used for the paired transistors included in the oscillator circuit 12, the variation in the relative accuracy of the paired transistors will increase, which may reduce the accuracy of the oscillation frequency of the oscillator circuit and potentially degrade the performance of the semiconductor device (especially the microcontroller) equipped with the oscillator circuit.

[0123] In contrast, in this embodiment, the pair of transistors included in the oscillator circuit 12 uses MISFETs 2 and 3 that do not have a halo region, rather than MISFETs that have a halo region. Therefore, variations in the relative accuracy of the pair of transistors included in the oscillator circuit 12 can be suppressed. The reason for this is as follows.

[0124] In other words, when comparing a MISFET with a halo region to one without a halo region, the MISFET without a halo region has a lower impurity concentration in the channel formation region because it lacks the halo region. Therefore, even if unintended fluctuations occur in the ion implantation conditions, the impurity concentration in the channel formation region of the MISFET without a halo region is less likely to fluctuate, and as a result, the electrical characteristics of the MISFET (voltage-current characteristics, typically the threshold voltage) are less likely to fluctuate. Consequently, when MISFETs 2 and 3 without a halo region are used as the pair transistors included in the oscillator circuit 12, variations in the relative accuracy of the pair transistors included in the oscillator circuit 12 can be suppressed. This improves the accuracy of the oscillation frequency of the oscillator circuit in the semiconductor device, and thus improves the performance of the semiconductor device equipped with the oscillator circuit.

[0125] Furthermore, by using MISFETs 2 and 3, which do not have a halo region, instead of MISFETs with a halo region, in the pair transistors included in the oscillator circuit 12, it is possible to suppress variations in the relative accuracy of the pair transistors without increasing the planar dimensions (channel area) of the MISFETs constituting the pair transistors. This is advantageous for miniaturizing (reducing the area of) the semiconductor device.

[0126] Among the various circuits provided by the semiconductor device 11, the pair of transistors included in the oscillator circuit 12 are required to suppress fluctuations in their electrical characteristics (voltage-current characteristics, typically threshold voltage) as much as possible. For this reason, MISFETs 2 and 3, which do not have a halo region, are used as the pair of transistors included in the oscillator circuit 12.

[0127] On the other hand, if the MISFET has a halo region, the short-channel effect can be suppressed. For this reason, in applications where some variation in electrical characteristics is acceptable, it is preferable to use MISFET1 which has a halo region. For this reason, among the various circuits of the semiconductor device 11, it is preferable to use MISFET1 which has a halo region in the CPU 13 and therefore in the logic circuits of the semiconductor device 11, rather than MISFET2 or MISFET3 which do not have a halo region. Also, among the various circuits of the semiconductor device 11, it is preferable to use MISFET1 which has a halo region in the flash memory 14, SRAM 15, and register 16 and therefore in the memory circuits of the semiconductor device 11, rather than MISFET2 or MISFET3 which do not have a halo region. Note that the flash memory 14 includes a transistor having a memory section (charge storage section). Furthermore, in the oscillator circuit 12 of the semiconductor device 11, it is preferable to use MISFET1 which has a halo region for MISFETs other than paired transistors, rather than MISFET2 or MISFET3 which do not have a halo region. For peripheral circuits 17 other than the oscillator circuit of the semiconductor device 11, it is preferable to use MISFET1, which has a halo region, rather than MISFET2 or MISFET3, which do not have a halo region.

[0128] Thus, in applications where it is necessary to suppress fluctuations in the electrical characteristics of the MISFETs in the various circuits of the semiconductor device 11 as much as possible, MISFETs 2 and 3 without a halo region are used, while in applications where some fluctuations in the electrical characteristics of the MISFETs are acceptable, MISFET 1 with a halo region is used. This improves the performance of the semiconductor device 11.

[0129] Furthermore, although the semiconductor device 11 has multiple MISFETs, it is preferable that the MISFET with the shortest gate length among the multiple MISFETs of the semiconductor device 11 has a halo region, like MISFET1. By providing a halo region in the MISFET (the MISFET with the shortest gate length) that is most susceptible to the effects of short-channel effects, the short-channel effects can be suppressed.

[0130] Furthermore, as described above, the gate insulating film GF1 of MISFET1, the gate insulating film GF2 of MISFET2, and the gate insulating film GF3 of MISFET3 have the same thickness. On the other hand, the high-voltage MISFET4 (see Figure 35) described above has a gate insulating film GF4 that is thicker than each of the gate insulating films GF1, GF2, and GF3. The thicknesses of the gate insulating films GF1, GF2, and GF3 are the same. This high-voltage MISFET4 does not have a halo region. The high-voltage MISFET4 is preferably used in applications requiring high voltage, such as the flash memory 14 and peripheral circuits 17. For this reason, the flash memory 14 and peripheral circuits 17 may include MISFET1 which has a thin gate insulating film GF1 and a halo region, and the high-voltage MISFET4 which has a thick gate insulating film GF4 and does not have a halo region. It is preferable that the CPU 13, flash memory 14, SRAM 15, register 16, and peripheral circuit 17 (and therefore circuits other than the oscillator circuit 12 provided in the semiconductor device 11) have a gate insulating film of the same thickness as the gate insulating film GF1 of the MISFET 1 which has a halo region, and do not include MISFETs that do not have a halo region (corresponding to MISFET 2 or MISFET 3).

[0131] Furthermore, the gate insulating films of MISFET1,2,3 are thinner than the gate insulating film GF4 of the high-voltage MISFET4, and the breakdown voltages of MISFET1,2,3 are lower than those of MISFET4. For this reason, MISFET1,2,3 can be considered low-voltage MISFETs. From this perspective, the technical concept of this embodiment can also be expressed as follows.

[0132] In other words, for the pair transistors included in the oscillator circuit 12 of the semiconductor device 11, it is preferable to use low-voltage MISFETs without a halo region, rather than MISFETs with a halo region. On the other hand, for the CPU 13 of the semiconductor device 11, it is preferable to use low-voltage MISFETs with a halo region, rather than low-voltage MISFETs without a halo region. Furthermore, for the flash memory 14, SRAM 15, and register 16 of the semiconductor device 11, and therefore for the memory circuits of the semiconductor device 11, it is preferable to use low-voltage MISFETs with a halo region, rather than low-voltage MISFETs without a halo region. Note that the flash memory 14 includes a transistor having a memory section (charge storage section). Furthermore, for the peripheral circuits 17 other than the oscillator circuit of the semiconductor device 11, it is preferable to use low-voltage MISFETs with a halo region, rather than low-voltage MISFETs without a halo region. In addition to the low-voltage MISFETs with a halo region, high-voltage MISFETs can also be used in the peripheral circuits 17 and memory circuits of the semiconductor device 11, other than the oscillator circuit. These high-voltage MISFETs do not need to have a halo region. Therefore, the most preferable configuration is to use low-voltage MISFETs without a halo region for the pair transistors included in the oscillator circuit 12 of the semiconductor device 11, and not to use low-voltage MISFETs without a halo region for the other transistors. Note that the gate insulating film thickness is the same for low-voltage MISFETs, while the gate insulating film of a high-voltage MISFET is thicker than that of a low-voltage MISFET.

[0133] <Regarding the direction of current> Figures 39 and 40 are cross-sectional views of the main parts of the semiconductor device of this embodiment, showing the cross-section corresponding to Figure 5 above. For the sake of clarity, the interlayer insulating film IL, plug PG, and wiring M1 are omitted from Figures 39 and 40.

[0134] In Figure 39, the n-type semiconductor region S2 of MISFET2 is the source region, to which the source potential is supplied, and the n-type semiconductor region D2 of MISFET2 is the drain region, to which the drain potential is supplied. Also in Figure 39, the n-type semiconductor region S3 of MISFET3 is the source region, to which the source potential is supplied, and the n-type semiconductor region D3 of MISFET3 is the drain region, to which the drain potential is supplied. Therefore, in Figure 39, the direction of the current flowing through MISFET2 YG1 (the direction in which current flows from the source region to the drain region) and the direction of the current flowing through MISFET3 YG2 (the direction in which current flows from the source region to the drain region) are the same.

[0135] On the other hand, in the case of Figure 40, the n-type semiconductor region S2 of MISFET2 is the source region and is supplied with source potential, and the n-type semiconductor region D2 of MISFET2 is the drain region and is supplied with drain potential. Also in the case of Figure 40, the n-type semiconductor region S3 of MISFET3 is the drain region and is supplied with drain potential, and the n-type semiconductor region D3 of MISFET3 is the source region and is supplied with source potential. Therefore, in the case of Figure 40, the direction of current flowing through MISFET2 YG1 (the direction in which current flows from the source region to the drain region) and the direction of current flowing through MISFET3 YG2 (the direction in which current flows from the source region to the drain region) are opposite (reverse directions).

[0136] The case where the direction of the current flowing through MISFET2 (YG1) and the direction of the current flowing through MISFET3 (YG2) are the same (Figure 39) is more preferable than the case where the direction of the current flowing through MISFET2 (YG1) and the direction of the current flowing through MISFET3 (YG2) are opposite to each other (Figure 40). The reason is as follows.

[0137] In other words, n-type semiconductor regions D2a, S2a, D3a, S3a and n-type semiconductor regions D2b, S2b, D3b, S3b are formed by vertical ion implantation, but implantation conditions may fluctuate unintentionally. To facilitate control of the ion implantation process, it is desirable to allow for slight fluctuations in ion implantation conditions (e.g., slight fluctuations in implantation angle). When the direction of the current flowing through MISFET2, YG1 and the direction of the current flowing through MISFET3, YG2, are the same (as in Figure 39), the risk of fluctuations in ion implantation conditions (e.g., fluctuations in implantation angle) degrading the relative accuracy of the paired transistors is lower when the direction of the current flowing through MISFET2, YG1 and the direction of the current flowing through MISFET3, YG2, are the same (as in Figure 39), compared with when the direction of the current flowing through MISFET2, YG1 and the direction of the current flowing through MISFET3, YG2, are opposite (as in Figure 40).

[0138] This is because, when the current direction YG1 of MISFET2 and the current direction YG2 of MISFET3 are the same, even if there are fluctuations in the ion implantation conditions (e.g., fluctuations in the implantation angle), the impurity implantation state will be almost the same in the source region of MISFET2 and the source region of MISFET3, and the impurity implantation state will be almost the same in the drain region of MISFET2 and the drain region of MISFET3. For this reason, the relative accuracy of the pair transistor consisting of MISFET2 and MISFET3 can be improved more when the current direction YG1 of MISFET2 and the current direction YG2 of MISFET3 are the same (as in Figure 39) than when the current direction YG1 of MISFET2 and the current direction YG2 of MISFET3 are opposite (as in Figure 40).

[0139] Furthermore, it is more preferable that an element isolation region ST is interposed between the active region where MISFET2 is formed (MISFET formation region 2A) and the active region where MISFET3 is formed (MISFET formation region 3A) in the semiconductor substrate SB. In other words, it is more preferable that the active region where MISFET2 is formed (MISFET formation region 2A) and the active region where MISFET3 is formed (MISFET formation region 3A) in the semiconductor substrate SB are separated by the element isolation region ST. This makes it easier to equalize the stress generated in the MISFET formation region 2A and the stress generated in the MISFET formation region 3A in the semiconductor substrate SB. As a result, the relative accuracy of the pair transistor consisting of MISFET2 and MISFET3 can be further improved.

[0140] <Regarding the testing and assembly processes> Figure 41 is a process flow diagram showing the manufacturing process of a semiconductor device. As shown in Figure 41, the manufacturing process of a semiconductor device consists of a wafer process, a wafer testing process, and an assembly process, in that order. The section described above in "About the Manufacturing Process of Semiconductor Devices" corresponds to the wafer process. The wafer process includes the process of forming multiple semiconductor elements, including the above-mentioned MISFETs 1, 2, and 3, on a semiconductor wafer (corresponding to the semiconductor substrate SB), and the process of forming a wiring structure, including the above-mentioned interlayer insulating film IL, plug PG, and wiring M1, on the semiconductor wafer.

[0141] In the wafer testing process, electrical testing of semiconductor elements formed on a semiconductor wafer is performed by pressing a test probe against the pads of the wiring structure formed on the semiconductor wafer. In this wafer testing process, the semiconductor wafer may be heated to a relatively high temperature (e.g., 250°C or higher) before the electrical testing is performed. This heating process is, for example, a retention bake process and is carried out for a relatively long time (e.g., 1 to 10 hours). In the assembly process, semiconductor chips are obtained by dicing the semiconductor wafer, and then semiconductor packages are manufactured using these semiconductor chips. In this assembly process, the semiconductor chips may be heated to a relatively high temperature (e.g., 250°C or higher). This heating process is, for example, a solder reflow process (more specifically, an infrared solder reflow process).

[0142] According to the inventors' research, when the MISFETs constituting a pair of transistors have a halo region, if the semiconductor wafer is heated to a temperature of 250°C or higher during the wafer testing process, or if the semiconductor chip is heated to a temperature of 250°C or higher during the assembly process, impurities contained in the halo region will diffuse, increasing the risk of a decrease in the relative accuracy of the pair of transistors.

[0143] In contrast, in this embodiment, the MISFETs 2 and 3 constituting the pair transistor do not have a halo region. Therefore, even if the semiconductor wafer is heated to a temperature of 250°C or higher during the wafer testing process (the heating process described above), or if the semiconductor chip is heated to a temperature of 250°C or higher during the assembly process (the heating process described above), it is possible to suppress or prevent a decrease in the relative accuracy of the pair transistor consisting of MISFETs 2 and 3. As a result, the performance of the manufactured semiconductor package can be improved.

[0144] <About paired transistors> As described above, a pair of transistors consists of a pair of MISFETs formed adjacent to each other on a semiconductor substrate SB, with their gate electrodes electrically connected to each other. Figures 42 to 45 are circuit diagrams showing example circuits of paired transistors.

[0145] Figure 42 shows a circuit diagram of the basic form of a pair of transistors. In the pair of transistors, MISFET2 and MISFET3, the gate electrode G2 of MISFET2 and the gate electrode G3 of MISFET3 are electrically connected to each other and connected to a common gate potential GE. The source (n-type semiconductor region S2) of MISFET2 is connected to the source potential SE1, the source (n-type semiconductor region S3) of MISFET3 is connected to the source potential SE2, the drain (n-type semiconductor region D2) of MISFET2 is connected to the drain potential DE1, and the drain (n-type semiconductor region D3) of MISFET3 is connected to the drain potential DE2. The gate electrodes G2 and G3 are connected via a plug PG and gate wiring M1G as shown in Figures 4 and 6, or via a gate connection GC as shown in Figure 7.

[0146] Figure 43 shows a circuit diagram of a modified example of a paired transistor. As shown in Figure 43, one or both of the MISFETs 2 and 3 constituting the paired transistor can also be composed of multiple MISFETs connected in parallel. As an example, Figure 43 shows a case where MISFET 2 constituting the paired transistor is composed of two MISFETs 2a and 2b connected in parallel, and MISFET 3 constituting the paired transistor is composed of three MISFETs 3a, 3b, and 3c connected in parallel, but the number of parallel connections is arbitrary. None of the MISFETs 2a, 2b, 3a, 3b, and 3c have a halo region. Therefore, there are cases where each of the MISFETs 2 and 3 constituting the paired transistor is composed of a single MISFET, where one of the MISFETs 2 and 3 constituting the paired transistor is composed of a single MISFET and the other is composed of multiple MISFETs connected in parallel, and where each of the MISFETs 2 and 3 constituting the paired transistor is composed of multiple MISFETs connected in parallel.

[0147] In this parallel-connected MISFET, the gate electrodes are electrically connected to each other, the source regions are electrically connected to each other, and the drain regions are electrically connected to each other. The gate electrodes are connected via the plug PG and gate wiring M1G as shown in Figures 4 and 6, or via the gate connection section GC as shown in Figure 7. The source regions are connected via the plug PG and wiring M1. The drain regions are connected via the plug PG and wiring M1.

[0148] Figure 44 shows a circuit diagram of another modified pair of transistors. As shown in Figure 44, the drains of the MISFETs 2 and 3 that constitute the pair of transistors may be electrically connected to each other. That is, in the case of Figure 44, the gate electrode G2 of MISFET2 and the gate electrode G3 of MISFET3 that constitute the pair of transistors are electrically connected to each other and connected to a common gate potential GE. Also, the drain (n-type semiconductor region D2) of MISFET2 and the drain (n-type semiconductor region D3) of MISFET3 are electrically connected to each other and connected to a common drain potential DE. The source (n-type semiconductor region S2) of MISFET2 is connected to the source potential SE1, and the source (n-type semiconductor region S3) of MISFET3 is connected to the source potential SE2. The connection between the gate electrodes G2 and G3 is made through the plug PG and gate wiring M1G as shown in Figures 4 and 6, or through the gate connection part GC as shown in Figure 7. The connection between the source regions can be made through the plug PG and wiring M1.

[0149] Figure 45 shows a circuit diagram of yet another modification of the paired transistor. As shown in Figure 45, the sources of the MISFETs 2 and 3 constituting the paired transistor may be electrically connected to each other. That is, in the case of Figure 45, the gate electrode G2 of MISFET2 and the gate electrode G3 of MISFET3 constituting the paired transistor are electrically connected to each other and connected to a common gate potential GE. Also, the source (n-type semiconductor region S2) of MISFET2 and the source (n-type semiconductor region S3) of MISFET3 are electrically connected to each other and connected to a common source potential SE. The drain (n-type semiconductor region D2) of MISFET2 is connected to the drain potential DE1, and the drain (n-type semiconductor region D3) of MISFET3 is connected to the drain potential DE2. The connection between the gate electrodes G2 and G3 is made through the plug PG and gate wiring M1G as shown in Figures 4 and 6, or through the gate connection part GC as shown in Figure 7. The connection between the drain regions can be made through the plug PG and wiring M1.

[0150] Next, we will explain an example of a paired transistor layout. Figure 4 or Figure 7 above shows the basic form of a paired transistor layout. In the case of Figure 4 above, the MISFET formation region 2A and the MISFET formation region 3A are separated by the element isolation region ST. A single MISFET, MISFET2 (which has one gate electrode), is formed in the MISFET formation region 2A, and a single MISFET, MISFET3 (which has one gate electrode), is formed in the MISFET formation region 3A. The gate electrode G2 of MISFET2 and the gate electrode G3 of MISFET3 are electrically connected to form a paired transistor.

[0151] Figures 46 to 48 are plan views showing other layout examples of paired transistors.

[0152] The layout in Figure 46 corresponds to the basic layout for the circuit configuration shown in Figure 43. Each of the active regions 2A1, 2A2, 3A1, 3A2, and 3A3 of the semiconductor substrate SB is surrounded by an element isolation region ST in a plan view. MISFET 2a is formed in active region 2A1, MISFET 2b is formed in active region 2A2, MISFET 3a is formed in active region 3A1, MISFET 3b is formed in active region 3A2, and MISFET 3c is formed in active region 3A3. Each MISFET 2a and 2b has a structure almost identical to MISFET 2 shown in Figures 4 to 6 and does not have a halo region. Similarly, each MISFET 3a, 3b, and 3c has a structure almost identical to MISFET 3 shown in Figures 4 to 6 and does not have a halo region. The gate electrodes G2 of MISFETs 2a and 2b are electrically connected to each other via the plug PG and wiring M1, the source regions (S2) of MISFETs 2a and 2b are electrically connected to each other via the plug PG and wiring M1, and the drain regions (D2) of MISFETs 2a and 2b are electrically connected to each other via the plug PG and wiring M1. Furthermore, the gate electrodes G3 of MISFETs 3a, 3b, and 3c are electrically connected to each other via the plug PG and wiring M1, the source regions (S3) of MISFETs 3a, 3b, and 3c are electrically connected to each other via the plug PG and wiring M1, and the drain regions (D3) of MISFETs 3a, 3b, and 3c are electrically connected to each other via the plug PG and wiring M1. A pair transistor is formed by MISFET 2, which consists of multiple MISFETs 2a and 2b connected in parallel, and MISFET 3, which consists of multiple MISFETs 3a, 3b, and 3c connected in parallel.

[0153] The layout in Figure 47 corresponds to a modified version of the layout for the circuit configuration in Figure 43. In plan view, each of the MISFET formation regions 2A and 3A of the semiconductor substrate SB is surrounded by an element isolation region ST. MISFETs 2a and 2b are formed in the MISFET formation region 2A, and MISFETs 3a, 3b, and 3c are formed in the MISFET formation region 3A. Each of the MISFETs 2a and 2b has a structure similar to the MISFET 2 shown in Figures 4 to 6, but differs from the MISFET 2 shown in Figures 4 to 6 in that MISFETs 2a and 2b share an n-type semiconductor region D2. Furthermore, each MISFET3a,3b, and3c has a structure similar to MISFET3 shown in Figures 4 to 6 above, but differs from MISFET3 shown in Figures 4 to 6 above in that MISFET3a and MISFET3b share an n-type semiconductor region D3, and MISFET3b and MISFET3c share an n-type semiconductor region S3.

[0154] Therefore, the gate electrodes G2 of MISFET2a and MISFET2b extend in the Y direction across the MISFET formation region 2A and are aligned in the X direction. In the MISFET formation region 2A, n-type semiconductor regions S2 and D2 are arranged alternately in the X direction with the gate electrodes G2 in between. The gate electrodes G2 of MISFET2a and 2b are electrically connected to each other via the plug PG and wiring M1. The source regions (n-type semiconductor region S2 in this case) of MISFET2a and 2b are electrically connected to each other via the plug PG and wiring M1. The drain regions (n-type semiconductor region D2 in this case) of MISFET2a and 2b are electrically connected by being shared. No halo region is formed in the MISFET formation region 2A.

[0155] Furthermore, the gate electrodes G3 of MISFET3a, MISFET3b, and MISFET3c each extend in the Y direction across the MISFET formation region 3A and are aligned in the X direction. In the MISFET formation region 3A, n-type semiconductor regions S3 and D3 are arranged alternately in the X direction with the gate electrodes G3 in between. The gate electrodes G3 of MISFETs 3a, 3b, and 3c are electrically connected to each other via the plug PG and wiring M1. The source regions (in this case, n-type semiconductor regions S2) of MISFETs 3a, 3b, and 3c are electrically connected to each other via the plug PG and wiring M1. In addition, the drain regions (in this case, n-type semiconductor regions D2) of MISFETs 3a, 3b, and 3c are electrically connected to each other via the plug PG and wiring M1. No halo region is formed in the MISFET formation region 3A.

[0156] In the case of Figure 47, a paired transistor is formed by MISFET2, which consists of multiple MISFETs 2a and 2b (MISFETs without a halo region) formed in the MISFET formation region 2A and connected in parallel, and MISFET3, which consists of multiple MISFETs 3a, 3b, and 3c (MISFETs without a halo region) formed in the MISFET formation region 3A and connected in parallel.

[0157] In the case of Figure 47, the same number of gate electrodes G2 as the number of MISFETs (parallel-connected MISFETs) constituting MISFET2 are formed in the MISFET formation region 2A, and the same number of gate electrodes G3 as the number of MISFETs (parallel-connected MISFETs) constituting MISFET3 are formed in the MISFET formation region 3A.

[0158] The layout in Figure 48 corresponds to a further modification of the layout in the circuit configuration shown in Figure 43. In Figure 48, there is no element isolation region ST between the MISFET formation region 2A and the MISFET formation region 3A of the semiconductor substrate SB, and the MISFET formation region 2A and the MISFET formation region 3A are connected. In this case, the entire active region including the MISFET formation region 2A and the MISFET formation region 3A will be referred to here as the MISFET formation region 10A. In a plan view, the MISFET formation region 10A is surrounded by the element isolation region ST. MISFETs 2a and 2b are formed in the MISFET formation region 2A of the MISFET formation region 10A, and MISFETs 3a, 3b, and 3c are formed in the MISFET formation region 3A of the MISFET formation region 10A. Except for the absence of an element isolation region ST between the MISFET formation region 2A and the MISFET formation region 3A, the structure in Figure 48 is basically the same as the structure in Figure 47, so a repeated explanation will be omitted here.

[0159] Figure 49 is a schematic cross-sectional view of a semiconductor device when the layout of Figure 47 is applied. Figure 49 shows a cross-sectional view (approximately perpendicular to the Y direction) of the MISFET formation region 3A when the MISFET 3 constituting the pair transistor is composed of multiple MISFETs connected in parallel. The gate electrode G3 of the MISFET formation region 3A will be described below with reference to Figure 49. The same technical concept applies to the gate electrode G2 of the MISFET formation region 2A, and in Figure 49 and the following explanation, "MISFET formation region 3A" should be read as "MISFET formation region 2A", "gate electrode G3" as "gate electrode G2", "n-type semiconductor region S3" as "n-type semiconductor region S2", and "n-type semiconductor region D3" as "n-type semiconductor region D2".

[0160] In the case of Figure 49, the MISFET3 constituting the pair transistor is composed of multiple MISFETs connected in parallel, so that multiple gate electrodes G3 extend in the Y direction across the MISFET formation region 3A and are aligned in the X direction. In the MISFET formation region 3A, n-type semiconductor regions S3 and n-type semiconductor regions D3 are arranged alternately in the X direction with the gate electrodes G3 in between. Note that in the case of Figure 49, there are 8 gate electrodes G3, but the number is not limited to this.

[0161] In the case of Figure 49, the spacing P1 between adjacent gate electrodes G3 in the X direction is constant. That is, multiple gate electrodes G3 extending in the Y direction are arranged in the X direction at a constant spacing P1. Here, one of the gate electrodes G3 located at both ends in the X direction among the multiple gate electrodes G3 arranged in the X direction will be called gate electrode G3a, and the other will be called gate electrode G3b. The spacing P2 between gate electrode G3a and the element isolation region ST (spacing in the X direction) is preferably greater than spacing P1 (i.e., P2 > P1). Also, the spacing P3 between gate electrode G3b and the element isolation region ST (spacing in the X direction) is preferably greater than spacing P1 (i.e., P3 > P1). The reason for this is as follows.

[0162] In other words, in the active region (MISFET formation region 3A), the distribution of impurities is more prone to fluctuation in the region adjacent to the device isolation region ST compared to other regions. Therefore, when forming a MISFET 3 consisting of multiple MISFETs connected in parallel in the MISFET formation region 3A, there is a concern that the electrical characteristics of the MISFETs having gate electrodes G3a and G3b will fluctuate more than those of the other MISFETs.

[0163] Therefore, as shown in Figure 49, the spacing P2 and P3 between the gate electrodes G3a and G3b located at both ends in the X direction of the multiple gate electrodes G3 formed in the MISFET formation region 3A and the element isolation region ST is made larger than the spacing P1 between adjacent gate electrodes G3 (P2 > P1 and P3 > P1). As a result, the gate electrodes G3a and G3b are farther from the element isolation region ST, so even if the distribution of impurities changes in the region close to the element isolation region ST in the active region (MISFET formation region 3A), it is possible to suppress the effect of this on the electrical characteristics of the MISFET having gate electrode G3a or the MISFET having gate electrode G3b. This makes it possible to more accurately suppress or prevent changes in the electrical characteristics of the MISFET 3 when the MISFET 3 constituting a pair transistor is composed of multiple MISFETs connected in parallel. A similar technical concept applies to the gate electrode G2 of the MISFET formation region 2A. When the MISFET2 constituting a pair transistor is composed of multiple MISFETs connected in parallel, it is possible to more accurately suppress or prevent fluctuations in the electrical characteristics of MISFET2. This makes it possible to suppress variations in the relative precision of the pair transistor consisting of MISFET2 and MISFET3.

[0164] Figure 50 is a schematic cross-sectional view of a semiconductor device when the layout of Figure 47 is applied. Figure 50 shows a cross-sectional view (approximately perpendicular to the Y direction) of the MISFET formation region 3A when the MISFET 3 constituting the pair transistor is composed of multiple MISFETs connected in parallel, and shows a cross-section corresponding to Figure 49. Below, the gate electrode G3 of the MISFET formation region 3A will be explained with reference to Figure 50. The same technical concept applies to the gate electrode G2 of the MISFET formation region 2A, and in Figure 50 and the following explanation, "MISFET formation region 3A" should be read as "MISFET formation region 2A", "gate electrode G3" as "gate electrode G2", "n-type semiconductor region S3" as "n-type semiconductor region S2", and "n-type semiconductor region D3" as "n-type semiconductor region D2".

[0165] In the case of Figure 50, the MISFET3 constituting the pair transistor is composed of multiple MISFETs connected in parallel, so that multiple gate electrodes G3 extend in the Y direction across the MISFET formation region 3A and are aligned in the X direction. In the MISFET formation region 3A, n-type semiconductor regions S3 and n-type semiconductor regions D3 are arranged alternately in the X direction with the gate electrodes G3 in between. Note that in the case of Figure 50, there are 6 gate electrodes G3, but the number is not limited to this.

[0166] In the case of Figure 50, the spacing P1 between adjacent gate electrodes G3 in the X direction is constant. That is, multiple gate electrodes G3, each extending in the Y direction, are arranged in the X direction at a constant spacing P1. Dummy gate electrodes DG1 and DG2 are positioned on both sides (both sides in the X direction) of the multiple gate electrodes G3 arranged in the X direction. That is, dummy gate electrode DG1 is positioned on one side (both sides in the X direction) of the multiple gate electrodes G3 arranged in the X direction, and dummy gate electrode DG2 is positioned on the other side. Dummy gate electrodes DG1 and DG2 each extend in the Y direction. In other words, dummy electrode DG1, which extends in the Y direction, is positioned between gate electrode G3a and the element isolation region ST of the multiple gate electrodes G3 arranged in the X direction, and dummy electrode DG2, which extends in the Y direction, is positioned between gate electrode G3b and the element isolation region ST of the multiple gate electrodes G3 arranged in the X direction. As described above, gate electrodes G3a and G3b are gate electrodes G3 located at both ends in the X direction of the multiple gate electrodes G3 arranged in the X direction. The distance P4 between gate electrode G3a and the adjacent dummy electrode DG1, and the distance P5 between gate electrode G3b and the adjacent dummy electrode DG2, can be the same as the distance P1 between adjacent gate electrodes G3 in the X direction (i.e., P1=P4=P5).

[0167] The dummy gate electrodes DG1 and DG2 are pseudo (dummy) gate electrodes and do not function as gate electrodes of a transistor. The dummy gate electrodes DG1 and DG2 are not connected to the gate electrode G3 through a conductor, and the gate voltage applied to the gate electrode G3 is not applied to the dummy gate electrodes DG1 and DG2. Since the dummy gate electrodes DG1 and DG2 are formed in the same process as the gate electrode G3, they are made of the same material (e.g., polysilicon) as the gate electrode G3 and have the same thickness as the gate electrode G3. Like the gate electrode G3, the dummy gate electrodes DG1 and DG2 extend in the Y direction across the MISFET formation region 3A. In the semiconductor substrate SB (p-type well PW2), an n-type semiconductor region S3c is formed between each of the dummy gate electrodes DG1 and DG2 and the element isolation region ST. This n-type semiconductor region S3c is formed together with the formation of the n-type semiconductor regions D3 and S3 in the semiconductor substrate SB. This n-type semiconductor region S3c does not function as the source or drain region of the transistor.

[0168] Therefore, the dummy gate electrodes DG1 and DG2, and the multiple gate electrodes G3, which extend in the Y direction, are arranged in the X direction. However, dummy gate electrodes DG1 and DG2 are positioned at both ends of this X-direction arrangement, and the multiple gate electrodes G3, which extend in the Y direction, are positioned between the dummy gate electrode DG1 and the dummy gate electrode DG2 that extend in the Y direction. Consequently, of the dummy gate electrodes DG1 and DG2 and the multiple gate electrodes G3, the ones adjacent to the element isolation region ST in the X direction (i.e., the ones closest to the element isolation region ST in the X direction) are not gate electrodes G3 but dummy gate electrodes DG1 and DG2. The reasons why it is preferable to provide dummy electrodes DG1 and DG2 are as follows.

[0169] In other words, as described above, in the active region (MISFET formation region 3A), the distribution of impurities is more prone to fluctuation in the region adjacent to the device isolation region ST compared to other regions. Therefore, when forming a MISFET 3 consisting of multiple MISFETs connected in parallel in the MISFET formation region 3A, there is a concern that the electrical characteristics of the MISFETs having gate electrodes G3a and G3b will fluctuate more than those of the other MISFETs.

[0170] Therefore, as shown in Figure 50, dummy electrodes DG1 and DG2 are provided on both sides of the multiple gate electrodes G3 formed in the MISFET formation region 3A. As a result, in the X direction, dummy electrodes DG1 and DG2 are present between the gate electrodes G3 and the device isolation region ST. Therefore, even if the distribution state of impurities changes in the region adjacent to the device isolation region ST in the active region (MISFET formation region 3A), it is possible to suppress or prevent this from affecting the MISFET having the gate electrodes G3.

[0171] This makes it possible to more accurately suppress or prevent fluctuations in the electrical characteristics of MISFET3 when the MISFET3 constituting the paired transistor is composed of multiple MISFETs connected in parallel. A similar technical concept applies to the gate electrode G2 of the MISFET formation region 2A, making it possible to more accurately suppress or prevent fluctuations in the electrical characteristics of MISFET2 when the MISFET2 constituting the paired transistor is composed of multiple MISFETs connected in parallel. This further suppresses variations in the relative precision of the paired transistor consisting of MISFET2 and MISFET3.

[0172] Figures 51 and 52 are a plan view (Figure 51) and a cross-sectional view (Figure 52) of the main parts of the semiconductor device showing the layout of the MISFET formation region 2A in Figure 47. Figure 51 shows a plan view of the MISFET formation region 2A, and the cross-sectional view at the position of line B1-B1 in Figure 51 corresponds to Figure 52.

[0173] The layout in Figure 51 corresponds to the layout of the MISFET formation region 2A in Figure 47. Therefore, in Figures 51 and 52, the MISFET formation region 2A of the semiconductor substrate SB is surrounded by an element isolation region ST in a plan view, and MISFETs 2a and 2b are formed in the MISFET formation region 2A. The gate electrodes G2 of MISFET 2a and MISFET 2b extend in the Y direction across the MISFET formation region 2A and are aligned in the X direction. In the case of Figure 51, the gate electrodes G2 of MISFET 2a and MISFET 2b are integrally connected to a gate connection portion GC that extends in the X direction, and are electrically connected to each other through this gate connection portion GC. Sidewall spacers SW are formed on the side wall of the gate electrode G2 and on the side wall of the gate connection portion GC. In the MISFET formation region 2A, n-type semiconductor regions S2 and n-type semiconductor regions D2 are arranged alternately in the X direction with the gate electrode G2 in between. MISFET2a and MISFET2b share an n-type semiconductor region D2. In the MISFET formation region 2A, no halo region is formed on the semiconductor substrate SB.

[0174] Figures 53 and 54 are plan views (Figure 53) and cross-sectional views (Figure 54) of the main parts of a semiconductor device showing a modified structure from those shown in Figures 51 and 52. Figure 53 shows a plan view of the MISFET formation region 2A, and the cross-sectional view at the position of line B2-B2 in Figure 53 corresponds to Figure 54.

[0175] The structures in Figures 53 and 54 differ from those in Figures 51 and 52 in the following respects.

[0176] In other words, the gate electrode G2 extends in the Y direction so as to cross the MISFET formation region 2A, but in the cases of Figures 53 and 54, the conductive portion CP, which extends on the semiconductor substrate SB along the outer periphery of the MISFET formation region 2A (active region) (i.e., along the boundary between the element isolation region ST and the active region), is integrally connected to the gate electrode G2. Since the conductive portion CP is formed in the same process as the gate electrode G2, it is made of the same material (e.g., polysilicon) as the gate electrode G2, has the same thickness as the gate electrode G2, and is integrally formed with the gate electrode G2. Since the conductive portion CP is integrally formed with the gate electrode G2, the gate voltage applied to the gate electrode G2 can also be applied to the conductive portion CP, but the conductive portion CP does not function as the gate electrode of the transistor. The conductive portion CP extends along the outer periphery of the MISFET formation region 2A, overlapping both the element isolation region ST and the active region (MISFET formation region 2A). Sidewall spacers SW are formed on the sidewall of the gate electrode G2, the sidewall of the gate connection GC, and the sidewall of the conductor CP. Between the conductor CP and the semiconductor substrate SB (p-type well PW2), an insulating film GF2a of the same layer as the gate insulating film GF2 is interposed. In the ion implantation process that forms the n-type semiconductor regions D2a and S2a, and the ion implantation process that forms the n-type semiconductor regions D2b and S2b, n-type impurities are not implanted in the region below the gate electrode G2 and the region below the conductor CP in the semiconductor substrate SB (p-type well PW2). Therefore, the n-type semiconductor regions D2a, S2a and n-type semiconductor regions D2b and S2b are not formed in the region below the conductor CP in the semiconductor substrate SB (p-type well PW2).

[0177] In the cases of Figures 53 and 54, the conductive portion CP extends along the outer circumference of the MISFET formation region 2A, and the n-type semiconductor regions D2 and S2 are not formed in the region below the conductive portion CP. Therefore, in the active region (MISFET formation region 2A), the n-type semiconductor regions D2 and S2 are not formed in the region adjacent to the device isolation region ST. When the conductive portion CP is provided as shown in Figures 53 and 54, the following advantages can be obtained.

[0178] In other words, in the active region (MISFET formation region 2A), the distribution of impurities is more prone to fluctuation in the region adjacent to the element isolation region ST compared to other regions. However, as shown in Figures 53 and 54, when a conductive portion CP is provided, n-type semiconductor regions D2 and S2 are not formed in the region adjacent to the element isolation region ST in the active region (MISFET formation region 2A). This makes it possible to suppress or prevent fluctuations in the distribution of impurities in the region adjacent to the element isolation region ST in the active region (MISFET formation region 2A) from affecting the MISFET having the gate electrode G2. This makes it possible to more accurately suppress or prevent fluctuations in the electrical characteristics of the MISFET 2 constituting the pair transistor. A similar technical concept applies to the gate electrode G3 of the MISFET formation region 3A, making it possible to more accurately suppress or prevent fluctuations in the electrical characteristics of its MISFET 3. This makes it possible to suppress variations in the relative accuracy of the pair transistor consisting of MISFETs 2 and 3.

[0179] On the other hand, when the conductive portion CP is not formed, as shown in Figures 51 and 52, the semiconductor device can be miniaturized (reduced in area) compared to the cases shown in Figures 53 and 54, because the conductive portion CP is not provided.

[0180] Furthermore, for the MISFET 1 formed in the MISFET formation region 1A, it is preferable to apply a structure without a conductive portion CP, as shown in Figures 51 and 52. This is because, compared to MISFETs 2 and 3, MISFET 1 can tolerate some variation in its electrical characteristics, and therefore a structure with a halo region is applied. This makes it possible to miniaturize (reduce the area of) the semiconductor device.

[0181] The present invention has been described in detail above based on its embodiments, but it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence. [Explanation of Symbols]

[0182] 1,2,2a,2b,3,3a,3b,3c,4 MISFET 1A,2A,3A,4A MISFET formation area 5A resistance element formation area 11 Semiconductor Equipment 12 Oscillator Circuits 13 CPU 14 Flash memory 15 SRAM 16 registers 17 Peripheral Circuits CP conductor section D1, D1a, D1b, D2, D2a, D2b, D3, D3a, D3b, D4, D4a, D4b, n-type semiconductor region DE, DE1, DE2 Drain Potential G1, G2, G3, G4 gate electrodes GE gate potential GC gate connection GF1, GF2, GF3, GF4 gate insulating film HA1, HA2 p-type halo regions IL interlayer film M1 Wiring M1G Gate Wiring PG Plug PR1, PR2, PR3, PR4, PR5 Photoresist Patterns PT1, PT2, PT3 Paired Transistors PS Resistor PW1, PW2, PW4 p-type well S1,S1a,S1b,S2,S2a,S2b,S3,S3a,S3b,S4,S4a,S4b, n-type semiconductor region SE, SE1, SE2 Source Potential ST element isolation area SW Sidewall Spacer

Claims

1. Semiconductor device equipped with an oscillator circuit, including the following: Semiconductor substrate; Element isolation region formed on the semiconductor substrate; First MISFET and second MISFET used in the pair transistors included in the oscillation circuit; Here, The first MISFET is, A first semiconductor region of a first conductivity type for source or drain, formed in a first active region surrounded by the element isolation region of the semiconductor substrate, It has a plurality of first gate electrodes formed on the semiconductor substrate via a plurality of first gate insulating films, The second MISFET is, A second semiconductor region of the first conductivity type for source or drain, formed in a second active region surrounded by the element isolation region in the semiconductor substrate, The semiconductor substrate has a second gate electrode formed on it via a second gate insulating film, The first MISFET does not have a halo region of a second conductivity type opposite to the first conductivity type at a position adjacent to the first semiconductor region on the semiconductor substrate. The second MISFET does not have a halo region of the second conductivity type adjacent to the second semiconductor region on the semiconductor substrate. The plurality of first gate electrodes and the second gate electrodes are electrically connected to each other. Each of the plurality of first gate electrodes extends across the first active region in a plan view, The second gate electrode extends across the second active region in a plan view, Each of the plurality of first gate electrodes extends in a first direction and is arranged in a second direction perpendicular to the first direction. A first dummy electrode extending in the first direction is positioned between one of the first gate electrodes located at both ends of the second direction among the plurality of first gate electrodes arranged in the second direction and the element isolation region. A second dummy electrode extending in the first direction is positioned between the other first gate electrode located at both ends of the plurality of first gate electrodes arranged in the second direction and the element isolation region.

2. In the semiconductor device described in claim 1, It further includes a third MISFET used in logic circuits, The third MISFET comprises a third semiconductor region of the first conductivity type formed on the semiconductor substrate for source or drain, a third gate electrode formed on the semiconductor substrate via a third gate insulating film, and a first halo region of the second conductivity type formed on the semiconductor substrate adjacent to the first semiconductor region. A semiconductor device in which the thicknesses of the first gate insulating film, the second gate insulating film, and the third gate insulating film are all the same.

3. In the semiconductor device described in claim 1, A semiconductor device in which the direction of the current flowing through the semiconductor substrate by the first MISFET and the direction of the current flowing through the semiconductor substrate by the second MISFET are the same.

4. A semiconductor device comprising an oscillator circuit, including the following: Semiconductor substrate; Element isolation region formed on the semiconductor substrate; First MISFET and second MISFET used in the pair transistors included in the oscillation circuit; Here, The first MISFET is, A first semiconductor region of a first conductivity type for source or drain, formed in a first active region surrounded by the element isolation region of the semiconductor substrate, The semiconductor substrate has a first gate electrode formed on it via a first gate insulating film, The second MISFET is, A second semiconductor region of the first conductivity type for source or drain, formed in a second active region surrounded by the element isolation region in the semiconductor substrate, The semiconductor substrate has a second gate electrode formed on it via a second gate insulating film, The first MISFET does not have a halo region of a second conductivity type opposite to the first conductivity type at a position adjacent to the first semiconductor region on the semiconductor substrate. The second MISFET does not have a halo region of the second conductivity type adjacent to the second semiconductor region on the semiconductor substrate. The first gate electrode and the second gate electrode are electrically connected to each other. The first gate electrode extends across the first active region in a plan view, The second gate electrode extends across the second active region in a plan view, A first conductive portion extending on the semiconductor substrate along the outer periphery of the first active region is integrally formed with the first gate electrode.

5. In the semiconductor device according to claim 4, It further includes a third MISFET used in logic circuits, The third MISFET comprises a third semiconductor region of the first conductivity type formed on the semiconductor substrate for source or drain, a third gate electrode formed on the semiconductor substrate via a third gate insulating film, and a first halo region of the second conductivity type formed on the semiconductor substrate adjacent to the first semiconductor region. A semiconductor device in which the thicknesses of the first gate insulating film, the second gate insulating film, and the third gate insulating film are all the same.

6. In the semiconductor device according to claim 4, A semiconductor device in which the direction of the current flowing through the semiconductor substrate by the first MISFET and the direction of the current flowing through the semiconductor substrate by the second MISFET are the same.

7. A method for manufacturing a semiconductor device equipped with an oscillator circuit, including the following steps: (a) A process of preparing a semiconductor substrate; (b) The process of forming a first gate electrode for a first MISFET on the semiconductor substrate via a first gate insulating film, forming a second gate electrode for a second MISFET on the semiconductor substrate via a second gate insulating film, forming a third gate electrode for a third MISFET on the semiconductor substrate via a third gate insulating film, and forming a fourth gate electrode for a fourth MISFET on the semiconductor substrate via a fourth gate insulating film; (c1) After step (b), a step of forming a first resist pattern that covers the region on the semiconductor substrate where the second MISFET is to be formed, the region where the third MISFET is to be formed, and the region where the fourth MISFET is to be formed, and exposes the region on the semiconductor substrate where the first MISFET is to be formed. (c2) After step (c1), a step of forming a first low-concentration region of a first conductivity type on the semiconductor substrate by first vertical ion implantation, (c3) After step (c1), a step of forming a first halo region of a second conductivity type adjacent to the first low-concentration region and opposite to the first conductivity type on the semiconductor substrate by oblique ion implantation. (c4) After the steps of (c2) and (c3), a step of removing the first resist pattern, (c5) After step (c4), a step of forming a second resist pattern that covers the region on the semiconductor substrate where the first MISFET is to be formed, and exposes the region on the semiconductor substrate where the second MISFET is to be formed, the region where the third MISFET is to be formed, and the region where the fourth MISFET is to be formed. (c6) After step (c5), a step of forming a second low-concentration region of the first conductivity type, a third low-concentration region of the first conductivity type, and a fourth low-concentration region of the first conductivity type on the semiconductor substrate by a second vertical ion implantation. (c7) After step (c6), a step of removing the second resist pattern, (c8) After step (c7), a step of forming sidewall spacers on the side walls of the first gate electrode, the second gate electrode, the third gate electrode and the fourth gate electrode, (c9) After step (c8), a third vertical ion implantation is performed to form a first high-concentration region of the first conductivity type, a second high-concentration region of the first conductivity type, a third high-concentration region of the first conductivity type, and a fourth high-concentration region of the first conductivity type on the semiconductor substrate. (d) After step (c9), a step of forming an interlayer insulating film on the semiconductor substrate so as to cover the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode; (e) A step of forming a conductive plug embedded in the interlayer insulating film after step (d); (f) A step of forming wiring on the interlayer insulating film after step (e); Here, The fourth gate insulating film is thicker than each of the first gate insulating film, the second gate insulating film, and the third gate insulating film. The first high-concentration region has a higher impurity concentration than the first low-concentration region. The second high-concentration region has a higher impurity concentration than the second low-concentration region. The third high-concentration region has a higher impurity concentration than the third low-concentration region. The fourth high-concentration region has a higher impurity concentration than the fourth low-concentration region. The first low-concentration region and the first high-concentration region form the first semiconductor region of the first conductivity type for the source or drain of the first MISFET. The second low-concentration region and the second high-concentration region form the second semiconductor region of the first conductivity type for the source or drain of the second MISFET. The third low-concentration region and the third high-concentration region form the third semiconductor region of the first conductivity type for the source or drain of the third MISFET. The fourth low-concentration region and the fourth high-concentration region form the fourth semiconductor region of the first conductivity type for the source or drain of the fourth MISFET. After step (b), no halo region of the second conductivity type is formed in the semiconductor substrate adjacent to the second semiconductor region, and no halo region of the second conductivity type is formed in the semiconductor substrate adjacent to the third semiconductor region. The second gate electrode and the third gate electrode are electrically connected to each other. The second MISFET and the third MISFET are used as a pair of transistors included in the oscillation circuit.

8. In the method for manufacturing a semiconductor device according to claim 7, The first MISFET is a method for manufacturing a semiconductor device used in logic circuits.

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