Wiring board and probe card

Abstract

This insulating substrate has a central region closer to the center and an outer peripheral region closer to the outer periphery in a transparent plan view, wherein, of a plurality of second via-conductors positioned in the outer peripheral region, the number of the second via-conductors of which a part is positioned at half the thickness of the insulating substrate from the first surface is greater than the number of the second via-conductors that are not positioned at half the thickness of the insulating substrate from the first surface.

Description

Wiring board and probe card

[0001] The present disclosure relates to a wiring board and a probe card.

[0002] Japanese Patent Application Laid-Open Publication No. 2011-009694 describes a wiring substrate for a probe card, which has a plurality of wiring conductors extending from one substrate surface to the other substrate surface.

[0003] a first via conductor positioned between the film conductor and the first electrode; and a second via conductor positioned between the film conductor and the second electrode, wherein the insulating substrate has, when a line segment is drawn connecting the center and the periphery of the insulating substrate in a planar perspective view, a central region occupying a range of two-thirds of the line segment toward the center in any direction, and a peripheral region occupying one-third of the line segment toward the periphery in any direction, wherein the first electrodes are positioned in the central region, and at least a portion of the second electrodes are positioned in the peripheral region, Of the multiple second via conductors located in the peripheral region, the number of second via conductors whose portions are located half the thickness of the insulating substrate from the first surface is greater than the number of second via conductors whose portions are not located half the thickness of the insulating substrate from the first surface.

[0004] A probe card according to the present disclosure includes the above wiring substrate and a plurality of probe pins.

[0005] FIG. 1 is a plan view of a wiring board according to embodiment 1 of the present disclosure. FIG. 2 is a back view of the wiring board according to embodiment 1 of the present disclosure. FIG. 3 is a longitudinal sectional view showing the wiring board of embodiment 1. FIG. 4 is a view illustrating a central region and a peripheral region of the wiring board in embodiment 1. FIG. 5 is a view illustrating a central region and a peripheral region of the wiring board in modification 1. FIG. 6 is a view illustrating a central region and a peripheral region of the wiring board in modification 2. FIG. 7 is a view showing the wiring pattern of embodiment 1, illustrating a first surface. FIG. 8 is a view showing the wiring pattern of embodiment 1, illustrating a third wiring layer. FIG. 9 is a view showing the wiring pattern of embodiment 1, illustrating a fifth wiring layer. FIG. 10 is a view showing the wiring pattern of embodiment 1, illustrating a seventh wiring layer. FIG. 11 is a view showing the wiring pattern of embodiment 1, illustrating a ninth wiring layer. FIG. 12 is a view showing the wiring pattern of embodiment 1, illustrating an eleventh wiring layer. FIG. 13 is a view showing the wiring pattern of embodiment 1, illustrating a second surface. FIG. 14 is a longitudinal sectional view showing the wiring board of embodiment 2. FIG. 15 is a view showing the wiring pattern of embodiment 2, illustrating a first surface. FIG. 16 is a view showing the wiring pattern of embodiment 2, illustrating a third wiring layer. FIG. 1 is a diagram showing a wiring pattern of embodiment 2, illustrating the fourth wiring layer; FIG. 2 is a diagram showing a wiring pattern of embodiment 2, illustrating the sixth wiring layer; FIG. 3 is a diagram showing a wiring pattern of embodiment 2, illustrating the ninth wiring layer; FIG. 4 is a diagram showing a wiring pattern of embodiment 2, illustrating the eleventh wiring layer; FIG. 5 is a diagram showing a wiring pattern of embodiment 2, illustrating the thirteenth wiring layer; FIG. 6 is a diagram showing a wiring pattern of embodiment 2, illustrating the second surface; FIG. 7 is a diagram showing a wiring pattern of a wiring board of embodiment 3, illustrating the first surface; FIG. 8 is a diagram showing a wiring pattern of a wiring board of embodiment 3, illustrating the third wiring layer; FIG. 9 is a diagram showing a wiring pattern of a wiring board of embodiment 3, illustrating the fifth wiring layer; FIG. 10 is a diagram showing a wiring pattern of a wiring board of embodiment 3, illustrating the seventh wiring layer; FIG. 11 is a diagram showing a wiring pattern of a wiring board of embodiment 3, illustrating the ninth wiring layer; FIG. 12 is a diagram showing a wiring pattern of a wiring board of embodiment 3, illustrating the eleventh wiring layer; FIG. 13 is a diagram showing a wiring pattern of a wiring board of embodiment 3, illustrating the second surface.1A and 1B are diagrams illustrating a probe card according to an embodiment of the present disclosure and a probe card according to a modified example.

[0006] Hereinafter, each embodiment of the present disclosure will be described in detail with reference to the drawings.

[0007] 1A and 1B are a plan view and a back view, respectively, of a wiring board according to a first embodiment of the present disclosure. Fig. 2 is a longitudinal cross-sectional view showing the wiring board of the first embodiment. In the figures, when there are many identical components, only some of them are assigned reference numerals. This also applies to the following figures.

[0008] The wiring board 1 according to the first embodiment of the present disclosure is a wiring board for a probe card. The probe card is a card incorporated into a test device for electronic circuits (specifically, multiple semiconductor circuits on a semiconductor wafer). More specifically, the probe card is interposed between a signal processing circuit that inputs and outputs test signals or voltages and the electronic circuit to be tested, and is connected to the electronic circuit to be tested via multiple probe pins.

[0009] The wiring board 1 comprises an insulating substrate 10 having a first surface S1, a second surface S2, and a plurality of wiring layers a2 to a12, a plurality of first electrodes 21 located on the first surface S1, a plurality of second electrodes 22 located on the second surface S2, a plurality of wiring conductors 30 respectively located between the plurality of first electrodes and the plurality of second electrodes, and a ground conductor 40.

[0010] The multiple wiring layers a2 to a12 may be layers extending substantially parallel to the first surface S1 and the second surface S2. The insulating substrate 10 may have multiple laminated insulating layers 11, and one surface of each insulating layer 11, i.e., the space between two insulating layers 11 stacked one above the other, may form one wiring layer. The insulating substrate 10 may be made of ceramic.

[0011] Each wiring conductor 30 includes a film conductor 33 located on one of the wiring layers a2 to a12, a first via conductor 31 located between the film conductor 33 and the first electrode 21, and a second via conductor 32 located between the film conductor 33 and the second electrode 22. The film conductor 33 is located along one wiring layer and is a layer-like, strip-like conductor. The film conductor 33 has a long shape along its wiring path. The wiring path may be linear or curved, or may have one or more curved portions along the wiring path. The first via conductor 31 may be located between the first surface S1 and the wiring layer on which the film conductor 33 is located, and may penetrate one or more insulating layers 11 located therebetween. The first via conductor 31 may extend in a direction intersecting (e.g., perpendicular to) the first surface S1. The second via conductor 32 may be located between the second surface S2 and the wiring layer on which the film conductor 33 is located, and may penetrate one or more insulating layers 11 located therebetween. The second via conductor 32 may extend in a direction intersecting (e.g., perpendicular to) the second surface S2. The first via conductor 31 may be connected to one end of the film conductor 33, and the second via conductor 32 may be connected to the other end of the film conductor 33.

[0012] The ground conductor 40 may be located in the wiring layers a2, a4, a6, a8, a10, and a12 where the film conductor 33 is not located, avoiding the first via conductor 31 and the second via conductor 32, and may extend in two directions along the wiring layers. The ground conductor 40 may be a solid conductor that extends in a planar shape.

[0013] Next, the structure of the plurality of wiring conductors 30 will be described by dividing the wiring substrate 1 into two regions, the central region 3 and the peripheral region 5 .

[0014] 3A to 3C are diagrams illustrating the central region and the peripheral region of the wiring substrate, where FIG. 3A is an explanatory diagram of the first embodiment, FIG. 3B is an explanatory diagram of the first modification, and FIG. 3C is an explanatory diagram of the second modification.

[0015] As shown in FIG. 3A , the central region 3 is the central region when the wiring board 1 is viewed from a perspective view. The peripheral region 5 is the peripheral region when the wiring board 1 is viewed from a perspective view, i.e., the region other than the central region 3. More specifically, when a line segment B is drawn connecting the center point b1 of the wiring board 1 in a perspective view to an arbitrary peripheral point b2, the central region 3 occupies two-thirds of the area toward the center of the line segment B in any direction. The center point b1 corresponds to the center of gravity of the plane figure corresponding to the shape of the wiring board 1 when viewed from a perspective view. Furthermore, the peripheral region 5 is the area occupying one-third of the area toward the periphery of the line segment B in any direction. The central region 3 may correspond to a region that vertically overlaps the terminals of the electronic circuit under test. Planar perspective refers to perspective from a direction perpendicular to the first surface S1. The vertical direction refers to a direction perpendicular to the first surface S1.

[0016] As shown in FIGS. 3B and 3C, if the planar shape of the wiring substrate 1 is different, the shapes of the central region 3 and the outer peripheral region 5 also differ in accordance with the planar shape.

[0017] 4A to 4D and 5A to 5C are diagrams showing the wiring pattern of embodiment 1, where Fig. 4A shows the first surface, Figs. 4B to 4D show the third, fifth, and seventh wiring layers, respectively, Figs. 5A and 5B show the ninth and eleventh wiring layers, respectively, and Fig. 5C shows the second surface. In Figs. 4A to 4D and 5A to 5B, first via conductors 31 are indicated by black circles, and second via conductors 32 are indicated by white circles.

[0018] As shown in Fig. 4A, the plurality of first electrodes 21 may be located in the central region 3. As shown in Fig. 5C, the plurality of second electrodes 22 may be at least partially located in the peripheral region 5. This configuration allows the plurality of second electrodes 22 to be spaced apart more widely, facilitating electrical connection between the wiring board 1 and the substrate of the test device. Furthermore, the plurality of first electrodes 21 can be densely arranged in correspondence with the plurality of terminals of the electronic circuit to be tested.

[0019] 2, 4B to 4D, 5A, and 5B, the multiple film conductors 33 may extend from the first via conductor 31 to the second via conductor 32 in a direction from the central region 3 toward the peripheral region 5. With this configuration, the multiple first electrodes can be densely arranged in the central region 3 while the spacing between the multiple second electrodes can be widened.

[0020] As shown in Figures 2, 4B to 4D, 5A and 5B, the number of second via conductors 32 (36 in the figure) located in the peripheral region 5a that is half the thickness from the first surface S1 of the wiring board 1 may be greater than the number of first via conductors 31 (0 in the figure) located in the peripheral region 5a that is half the thickness.

[0021] Furthermore, among the multiple second via conductors 32 located in the peripheral region 5, the number of second via conductors 32 whose portions are located half the thickness from the first surface S1 (e.g., wiring layers a3, a5) (36 in the illustration) may be greater than the number of second via conductors 32 whose portions are not located half the thickness from the first surface S1 (e.g., wiring layers a3, a5) (0 in the illustration).

[0022] This configuration allows many of the film conductors 33 connected to second electrodes 22 located near the periphery of the wiring substrate 1 to be arranged on wiring layers closer to the first surface S1. Additionally, many of the film conductors 33 connected to second electrodes 22 located near the center of the wiring substrate 1 can be arranged on wiring layers farther from the first surface S1. This configuration allows the multiple film conductors 33 to be distributed among areas closer to the first surface S1, areas farther from the first surface S1, the central region 3, and the peripheral region 5. This reduces the area allocated to each film conductor 33 from becoming too narrow. This improves the degree of freedom in routing the film conductors 33 and also allows the line width of the film conductors 33 to be wider. This reduces the resistance of the film conductors 33, thereby lowering the resistance of the wiring conductor 30.

[0023] As shown in Figures 4B to 4D, 5A and 5B, the number of film conductors 33 (36 in the illustration) located on the wiring layers a3 and a5, which are closer to the first surface S1 than the second surface S2, may be greater than the number of film conductors 33 (12 in the illustration) located on the wiring layers a9 and a11, which are closer to the second surface S2 than the first surface S1.

[0024] This configuration allows for a greater number of film conductors 33 located closer to the periphery of the wiring board 1 than those located closer to the center of the wiring board 1. Because the circumferential distance is longer in the region closer to the periphery of the wiring board 1, this configuration allows for a greater number of film conductors 33 to be distributed over a wider region in the circumferential direction. Therefore, the degree of freedom in routing the film conductors 33 is improved, and the line width of the film conductors 33 can be increased, both for the relatively few film conductors 33 located closer to the center and for the relatively many film conductors 33 located closer to the periphery. This allows for a uniformly low height for all wiring conductors 30.

[0025] As shown in Figures 4B to 4D, 5A and 5B, the film conductors 33 located in the wiring layers a3 and a5, which are closer to the first surface S1 than the second surface S2, may be longer than the film conductors 33 located in the wiring layers a9 and a11, which are closer to the second surface S2 than the first surface S1.

[0026] With this configuration, the film conductors 33 located closer to the periphery of the wiring board 1 are longer than the film conductors 33 located closer to the center of the wiring board 1. Because the circumferential distance is longer in the regions closer to the periphery of the wiring board 1, the above configuration allows the long film conductors 33 to be distributed over a wide region in the circumferential direction. This makes it easier to widen the line width of the long film conductors 33. This allows the resistivity of the long wiring conductors 30 to be lowered, making it possible to uniformly lower the resistivity of all wiring conductors 30.

[0027] As shown in FIG. 2 , the multiple film conductors 33 include two film conductors 33A and 33B adjacent to each other in the vertical direction. When such film conductors 33A and 33B are present, a ground conductor 40 may be located between the two film conductors 33A and 33B. This configuration reduces electrical interference between a wiring conductor 30A including the film conductor 33A and a wiring conductor 30B including the film conductor 33B. By locating the ground conductor 40 between all vertically adjacent film conductors 33, 33, electrical interference between adjacent wiring conductors 30 can be further reduced. However, the ground conductor 40 does not have to be located between all vertically adjacent film conductors 33, 33. The greater the proportion of ground conductors 40 located between adjacent pairs of film conductors 33, 33, the greater the effect of reducing electrical interference between adjacent wiring conductors 30.

[0028] (Embodiment 2) Fig. 6 is a longitudinal cross-sectional view showing a wiring board of embodiment 2. Figs. 7A to 7D and 8A to 8D are diagrams showing the wiring patterns of the wiring conductors of embodiment 2, where Fig. 7A shows the first surface S1, Figs. 7B to 7D show the third, fourth, and sixth wiring layers a3, a4, and a6, respectively, Figs. 8A to 8C show the ninth, eleventh, and thirteenth wiring layers a9, a11, and a13, respectively, and Fig. 8D shows the second surface S2. In Figs. 7A to 7D and 8A to 8C, first via conductors 31 are indicated by black circles, and second via conductors 32 are indicated by white circles.

[0029] The wiring board 1A of the second embodiment may be configured similarly to the wiring board 1 of the first embodiment, except for some different components. Similar components are denoted by the same reference numerals, and detailed description thereof will be omitted. The wiring board 1A of the second embodiment has a similar configuration to that of the first embodiment, with respect to the distribution of the first via conductors 31 and the second via conductors 32 (e.g., the magnitude of the number compared for each of a plurality of regions) and the distribution of the plurality of film conductors 33 (e.g., the magnitude of the number compared for each of a plurality of regions, the magnitude of the length compared for each of a plurality of regions, etc.).

[0030] In the wiring board 1A of the second embodiment, the wiring conductor 30C, in which the film conductor 33 is located at least half the thickness from the first surface S1 of the wiring board 1A, may include multiple film conductors 33a, 33b connected in parallel to each other. The multiple parallel-connected film conductors 33a, 33b may each be located in two wiring layers that differ by only one layer (e.g., wiring layers a3, a4, or wiring layers a6, a7, etc.). Note that the number of parallel-connected film conductors may be n (n is an integer of 3 or greater), and in this configuration, the n film conductors may each be located in n wiring layers that differ by one layer.

[0031] According to this configuration, it is possible to apply multiple film conductors 33a and 33b connected in parallel to the wiring conductor 30C having a relatively long film conductor 33 among the multiple film conductors 33. This makes it possible to reduce the resistance of the long film conductor 33. This makes it possible to uniformly reduce the resistance of all wiring conductors 30, including the wiring conductor 30C having the long film conductor 33 and the wiring conductors 30 having the short film conductors 33.

[0032] As shown in Figures 7B and 7C, the parallel-connected film conductors 33a, 33b may be located on consecutive wiring layers a3, a4 (i.e., on wiring layers a3, a4 that are different by one layer) and may have the same pattern. The same pattern allows the parallel-connected film conductors 33a, 33b to be fabricated using the same pattern fabrication configuration (e.g., pattern printing configuration). Using the same pattern fabrication configuration reduces line width variations among the film conductors 33a, 33b. This is because fabricating film conductors using different pattern fabrication configurations involves variations in the placement of components (e.g., pattern masks) in the pattern fabrication configuration, resulting in line width variations. Therefore, having the same pattern as described above reduces line width variations and reduces resistance variations among the film conductors 33a, 33b and the wiring conductor 30C (see Figure 6).

[0033] 9A to 12 are diagrams showing the wiring pattern of a wiring board according to embodiment 3. Fig. 9A shows the first surface S1, Figs. 9B, 10A, 10B, 11A, and 11B show the third, fifth, seventh, ninth, and eleventh wiring layers a3, a5, a7, a9, and a11, respectively, and Fig. 12 shows the second surface S2. In Figs. 9A to 11B, first via conductors 31 are indicated by black circles, and second via conductors 32 are indicated by white circles.

[0034] The wiring board 1B of embodiment 3 may be similar to embodiment 1 or embodiment 2, except for different patterns of the first electrode 21, the second electrode 22, the first via conductor 31, the second via conductor 32, and the film conductor 33. That is, in embodiment 3, as in embodiments 1 and 2, the number of second via conductors 32 (88 in the figures) located in the peripheral region 5a (see FIGS. 9B and 10A) half the thickness from the first surface S1 of the wiring board 1B may be greater than the number of first via conductors 31 (0 in the figures) located in the peripheral region 5a.

[0035] Furthermore, among the multiple second via conductors 32 located in the peripheral region 5, the number of second via conductors 32 whose portions are located half the thickness from the first surface S1 (i.e., wiring layers a2 to a6) (88 in the illustration) may be greater than the number of second via conductors 32 that are not located at all half the thickness from the first surface S1 (i.e., wiring layers a2 to a6) (28 in the illustration).

[0036] Furthermore, the film conductors 33 located in the wiring layers a3 and a5, which are closer to the first surface S1 than the second surface S2 (see Figures 9B and 10A), may be longer than the film conductors 33 located in the wiring layers a9 and a11, which are closer to the second surface S2 than the first surface S1 (see Figures 11A and 11B).

[0037] Furthermore, in the third embodiment, similarly to the first and second embodiments, the plurality of film conductors 33 may include two film conductors 33, 33 adjacent to each other in the vertical direction, and further, a ground conductor 40 may be located between the film conductors 33, 33. The vertical direction refers to the direction perpendicular to the first surface S1.

[0038] The same configuration as in the first embodiment as described above provides the same effects as in the first embodiment. In the third embodiment, the same components as in the first embodiment are denoted by the same reference numerals and detailed description thereof will be omitted.

[0039] The wiring board 1B of the third embodiment has a configuration applicable to a probe card for testing multiple (e.g., four) electronic circuits. That is, multiple electrode sets 25A-25D are located on the first surface S1 of the wiring board 1B. Each of the multiple electrode sets 25A-25D includes multiple first electrodes 21 and can be electrically connected to a single electronic circuit via the multiple first electrodes 21.

[0040] The relative arrangement of the plurality of first electrodes 21 included in one electrode set 25A may be the same as the relative arrangement of the plurality of first electrodes 21 included in the other electrode set 25B. The same applies to the other electrode sets 25C and 25D. "The relative arrangements are the same" means that the plurality of first electrodes 21 included in one electrode set 25A can be superimposed on the plurality of first electrodes 21 included in the other electrode set 25B by virtually translating the entire set or translating and rotating the entire set without changing the relative arrangement of the plurality of first electrodes 21 included in the other electrode set 25B.

[0041] Furthermore, the multiple electrode sets 25A to 25D may be arranged at second intervals that are wider (e.g., five times or more) than the first intervals that are the intervals between the multiple first electrodes 21. The first intervals refer to the average value of the intervals between adjacent first electrodes 21 among the multiple first electrodes 21 included in one electrode set 25A.

[0042] The configuration of the plurality of electrode sets 25A to 25D allows the plurality of electrode sets 25A to 25D to correspond one-to-one to the plurality of electronic circuits, and the plurality of wiring conductors 30 of the wiring board 1B can be electrically connected to the plurality of electronic circuits. Therefore, by using a probe card to which the wiring board 1B is applied, it becomes possible to test the plurality of electronic circuits in parallel.

[0043] 9A to 11B, the multiple film conductors 33 of the third embodiment include a film conductor 33c extending from the first via conductor 31 to the second via conductor 32 in a direction from the central region 3 toward the peripheral region 5, and a film conductor 33d extending in the central region 3 away from the peripheral region 5. In addition to the effects of the first embodiment, the inclusion of the film conductor 33d allows the film conductors 33 to be dispersed and arranged in the regions between the multiple electrode sets 25A to 25D. This improves the degree of freedom in routing the multiple film conductors 33, and allows the line width of the film conductors 33 to be increased. This reduces the resistance of the film conductors 33, thereby lowering the resistance of the wiring conductor 30.

[0044] As shown in FIGS. 9A to 12 , the multiple wiring layers a2 to a12 of the third embodiment include wiring layers a3, a5, and a7 in which a film conductor 33e extending from the central region 3 to the peripheral region 5 and a film conductor 33f extending within the central region 3 are located. In the wiring layers a3, a5, and a7, the film conductor 33e extending from the central region 3 to the peripheral region 5 may be longer than the film conductor 33f extending within the central region 3. When multiple electrode sets 25A to 25D are included, the film conductor 33f of one electrode set 25A may extend toward the film conductor 33f of the adjacent electrode set 25B. However, by configuring the film conductor 33f to be short, it is possible to prevent the wiring conductor 30 of one electrode set 25A from approaching the wiring conductor 30 of another electrode set 25B over a long distance, thereby reducing electrical interference between the multiple electrode sets 25A to 25D.

[0045] In addition, the configuration in which a plurality of film conductors 33 of the second embodiment are connected in parallel may also be applied to the third embodiment.

[0046] <Method for Manufacturing Wiring Board> Next, an example of a method for manufacturing the wiring boards 1, 1A, and 1B of Embodiments 1 to 3 will be described. For example, ceramic sintered bodies such as aluminum oxide sintered bodies, aluminum nitride sintered bodies, silicon carbide sintered bodies, mullite sintered bodies, or glass ceramics can be used as the material for the insulating layer 11. When an aluminum oxide sintered body is used as the material for the insulating layer 11, the insulating substrate 10 can be manufactured as follows. First, a raw material powder containing aluminum oxide powder and a sintering aid powder such as silicon oxide powder as its main components is kneaded with an organic solvent and a binder to form a slurry. This slurry is then formed into a sheet using a forming method such as a doctor blade method or a lip coater method to produce a ceramic green sheet (hereinafter also referred to as a green sheet) that will become the insulating layer 11. Next, multiple green sheets are stacked to form a laminate. The laminate is then fired at a temperature of approximately 1300°C to 1600°C to produce the insulating substrate 10.

[0047] The first electrode 21, the second electrode 22, the wiring conductor 30, and the ground conductor 40 contain, as their conductive components, metal materials such as tungsten, molybdenum, manganese, or copper, or alloys of these metal materials. For example, if the first electrode 21, the second electrode 22, the film conductor 33, and the ground conductor 40 are tungsten metallized layers, they can be formed by printing a metal paste made by mixing tungsten powder with an organic solvent and an organic binder at a predetermined position on the green sheet that will become the insulating layer 11 using a method such as screen printing, and then firing the green sheet together. The first via conductor 31 and the second via conductor 32 can be formed by drilling through holes at predetermined positions on the green sheet prior to printing the metal paste and filling the through holes with the same metal paste as above. On the surfaces of the exposed conductor layers, such as the first electrode 21 and the second electrode 22, a nickel film approximately 1 to 10 μm thick and a gold film approximately 0.1 to 3 μm thick can be sequentially formed to protect the surface and improve the bonding properties of brazing materials, solder, etc. The nickel film and the gold film can be formed as a plated film or a thin film by electrolytic plating.

[0048] (Probe Card) Fig. 13A is a diagram showing a probe card according to an embodiment of the present disclosure, and Fig. 13B is a diagram showing a probe card according to a modified example.

[0049] The probe card 100 according to the first embodiment of the present disclosure includes a wiring substrate 1 and a plurality of probe pins 51 respectively joined to a plurality of first electrodes 21. The probe pins 51 may be joined to the first electrodes 21 via a joining material such as solder. The wiring substrate 1 may be replaced by wiring substrates 1A and 1B.

[0050] The probe card 100 is supported by a frame 222. The probe card 100 is electrically connected to a circuit board 220 connected to an inspection device (not shown) via a plurality of contact conductors 221. The plurality of contact conductors 221 are connected to a plurality of second electrodes 22. The plurality of contact conductors 221 may be integrated by having their central portions supported on an insulating plate or insulating sheet (not shown); this configuration may be called an interposer.

[0051] In the probe card 100 having this configuration, the probe pins 51 of the probe card 100 are connected to electrodes of an electronic circuit to be inspected (for example, an electronic circuit formed on a silicon wafer). An inspection device (not shown) connected to the circuit board 220 exchanges signals and / or power supply voltages with the electronic circuit to be inspected via the circuit board 220, the plurality of contact conductors 221, the wiring board 1, and the probe pins 51, thereby inspecting the inspection object.

[0052] The multiple probe pins 51 do not need to be directly bonded to the first electrodes 21. Instead, as shown in FIG. 13B , they may be electrically connected to the multiple first electrodes 21 via a resin substrate 130 having a thin-film wiring layer. The resin substrate 130 may have multiple resin layers. For example, polyimide may be used as the material of the resin substrate 130. The resin substrate 130 may have multiple electrodes on its surface facing the wiring substrate 1, and multiple electrodes to which the multiple probe pins 51 are bonded on its opposite surface. Furthermore, the resin substrate 130 may have thin-film wiring that electrically connects the electrodes on one surface to the electrodes on the opposite surface. Using the resin substrate 130 makes it easier to miniaturize the wiring conductors and electrodes of the resin substrate 130 and to increase the density of the probe pins 51.

[0053] The above describes the embodiments of the present disclosure. However, the probe card and wiring board of the present disclosure are not limited to the above embodiments and can be modified as appropriate without departing from the spirit of the invention. For example, in the above embodiments, an example was shown in which all electrodes located on the first surface of the wiring board are first electrodes. However, electrodes other than the first electrodes may be located on the first surface of the wiring board. Such electrodes may be located in the peripheral region. Furthermore, in the above embodiments, an example was shown in which all conductors located inside the wiring board (more specifically, conductors other than the ground conductor) are wiring conductors in which first via conductors, film conductors, and second via conductors are connected. However, the wiring conductors may include a wiring conductor consisting of a single via conductor, or may include several wiring conductors connected in a multi-stage staircase pattern. The components of the above-described embodiments may be partially interchangeable or partially added to other embodiments, as long as they are not inconsistent.

[0054] An embodiment of the present disclosure will be described below. In one embodiment, (1) a wiring board comprises: an insulating substrate including a first surface, a second surface opposite to the first surface, and a plurality of wiring layers; a plurality of first electrodes located on the first surface; a plurality of second electrodes located on the second surface; and a plurality of wiring conductors located between the plurality of first electrodes and the plurality of second electrodes, each of the plurality of wiring conductors including: a film conductor located on one of the plurality of wiring layers; a first via conductor located between the film conductor and the first electrode; and a second via conductor located between the film conductor and the second electrode, wherein the insulating substrate has, when a line segment is drawn connecting the center and the periphery of the insulating substrate in a planar perspective view, a central region occupying a range of two-thirds of the line segment toward the center in any direction, and a peripheral region occupying one-third of the line segment toward the periphery in any direction, wherein the plurality of first electrodes are located in the central region, and at least a portion of the plurality of second electrodes are located in the peripheral region, (2) In the wiring board of (1) above, the number of the film conductors located in a wiring layer closer to the first surface than the second surface is greater than the number of the film conductors located in a wiring layer closer to the second surface than the first surface. (3) In the wiring board of (1) or (2) above, the film conductors located in a wiring layer closer to the first surface than the second surface are longer than the film conductors located in a wiring layer closer to the second surface than the first surface. (4) In any one of the wiring boards of (1) to (3) above, among the plurality of wiring conductors, at least the wiring conductors located half the thickness from the first surface of the insulating substrate have a plurality of the film conductors connected in parallel to each other. (5) In the wiring board of (4) above, the film conductors connected in parallel to one another are located in a plurality of wiring layers that are different from one another, and have the same pattern as one another.(6) In the wiring substrate of any one of (1) to (5) above, the plurality of wiring conductors include a first wiring conductor and a second wiring conductor, and in a longitudinal cross section, the film conductor of the first wiring conductor and the film conductor of the second wiring conductor are adjacent to each other in the vertical direction, and a ground conductor is located between the film conductor of the first wiring conductor and the film conductor of the second wiring conductor. (7) In the wiring substrate of any one of (1) to (6) above, in a wiring layer in which, of the plurality of wiring layers, the film conductor extending from the central region to the outer periphery region and the film conductor extending within the central region are located, the film conductor extending from the central region to the outer periphery region is longer than the film conductor extending within the central region. In one embodiment, (8) A probe card comprises: the wiring substrate of any one of (1) to (7) above; and a plurality of probe pins.

[0055] The present invention can be used in circuit boards and probe cards.

[0056] 1, 1A, 1B Wiring substrate 3 Central region 5 Peripheral region 5a Peripheral region half the thickness from first surface 10 Insulating substrate S1 First surface a2 to a14 Wiring layer S2 Second surface 21 First electrode 22 Second electrode 30, 30A to 30C Wiring conductor 31 First via conductor 32 Second via conductor 33, 33a to 33f Film conductor 40 Ground conductor 51 Probe pin 100 Probe card 130 Resin substrate

Claims

1. an insulating substrate including a first surface, a second surface located opposite to the first surface, and a plurality of wiring layers; a plurality of first electrodes located on the first surface; a plurality of second electrodes located on the second surface; a plurality of wiring conductors respectively positioned between the plurality of first electrodes and the plurality of second electrodes; Equipped with Each of the plurality of wiring conductors is a film conductor located in any one of the plurality of wiring layers; a first via conductor located between the film conductor and the first electrode; a second via conductor located between the film conductor and the second electrode; Including, the insulating substrate has, when a line segment is drawn connecting the center and the periphery of the insulating substrate in a planar perspective view, a central region occupying a range of two-thirds of the line segment closer to the center in any direction, and a peripheral region occupying one-third of the line segment closer to the periphery in any direction, the plurality of first electrodes are located in the central region; At least a portion of the plurality of second electrodes is located in the outer circumferential region, Among the plurality of second via conductors located in the outer peripheral region, the number of the second via conductors whose parts are located at a depth half the thickness of the insulating substrate from the first surface is greater than the number of the second via conductors whose parts are not located at a depth half the thickness of the insulating substrate from the first surface. Wiring board.

2. the number of the film conductors located in a wiring layer closer to the first surface than to the second surface is greater than the number of the film conductors located in a wiring layer closer to the second surface than to the first surface; The wiring board according to claim 1.

3. the film conductor located in a wiring layer closer to the first surface than the second surface is longer than the film conductor located in a wiring layer closer to the second surface than the first surface; The wiring board according to claim 1 or 2.

4. Among the plurality of wiring conductors, the wiring conductors located at least at a position half the thickness from the first surface of the insulating substrate include a plurality of the film conductors connected in parallel to each other. The wiring board according to claim 1 or 2.

5. the plurality of film conductors connected in parallel to one another are located in a plurality of wiring layers that are different from one another, and have the same pattern as one another; The wiring board according to claim 4.

6. the plurality of wiring conductors include a first wiring conductor and a second wiring conductor; In a vertical cross section, the film conductor of the first wiring conductor and the film conductor of the second wiring conductor are adjacent to each other in the up-down direction, a ground conductor is located between the film conductor of the first wiring conductor and the film conductor of the second wiring conductor; The wiring board according to claim 1 or 2.

7. Among the plurality of wiring layers, in a wiring layer in which the film conductor extending from the central region to the peripheral region and the film conductor extending within the central region are located, the film conductor extending from the central region to the peripheral region is longer than the film conductor extending within the central region; The wiring board according to claim 1 or 2.

8. The wiring board according to claim 1 or 2; a plurality of probe pins; A probe card comprising: