Array substrate, manufacturing method therefor, and display apparatus

Abstract

Provided in the present disclosure are an array substrate, a manufacturing method therefor, and a display apparatus. The array substrate comprises: a substrate structure; an active layer on the substrate structure; a patterned first insulation layer on the side of the active layer away from the substrate structure, the first insulation layer being provided with a first through hole exposing part of the active layer; a first conductive layer in the first through hole and in contact with the active layer; and a first connection member on the side of the first insulation layer away from the substrate structure, the first connection member being in contact with the first conductive layer, and the first connection member covering a first portion of the first conductive layer and not covering a second portion of the first conductive layer. The present disclosure can reduce the possibility of occurrence of missing portions of an active layer, thereby improving the performance of an array substrate and a display apparatus formed by same.

Description

Array substrate, manufacturing method thereof, and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on the application with CN application number 202210590935.4 and application date May 27, 2022, and claims its priority. The disclosed content of the CN application is hereby introduced as a whole into this application. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, and a display device. Background Art

[0004] OLED (Organic Light-Emitting Diode) technology is becoming increasingly mature. In some OLED display panels, the array substrate can utilize a five-mask process (also known as a 5-mask process). During the array substrate manufacturing process, thin film transistors (TFTs) are fabricated.

[0005] Summary of the Invention

[0006] According to one aspect of the present disclosure, an array substrate is provided, comprising: a substrate structure; an active layer on the substrate structure; a patterned first insulating layer on a side of the active layer away from the substrate structure, the first insulating layer having a first through hole exposing a portion of the active layer; a first conductive layer in the first through hole and in contact with the active layer; and a first connector on a side of the first insulating layer away from the substrate structure, the first connector in contact with the first conductive layer, the first connector covering a first portion of the first conductive layer and not covering a second portion of the first conductive layer.

[0007] In some embodiments, the first insulating layer further has a second through hole exposing another portion of the active layer; the array substrate further includes: a second conductive layer in the second through hole; a second connector electrically connected to the second conductive layer; and a gate located on a side of the first insulating layer away from the active layer; wherein the second connector and the gate are in the same layer, and the first connector and the second connector are both isolated from the gate.

[0008] In some embodiments, the substrate structure includes: a substrate; a light-shielding layer and a third conductive layer on the substrate, the orthographic projection of the light-shielding layer on the substrate at least partially overlaps with the orthographic projection of the active layer on the substrate, wherein the third conductive layer is covered on the light-shielding layer, or the light-shielding layer is covered on the third conductive layer; and a buffer layer between the third conductive layer and the active layer.

[0009] In some embodiments, an orthographic projection of the first conductive layer on the base substrate at least partially overlaps with an orthographic projection of the light shielding layer on the base substrate.

[0010] In some embodiments, the second through hole further exposes a portion of the buffer layer; and the second conductive layer includes: a third portion located on the surface of the active layer and a fourth portion located on the surface of the buffer layer.

[0011] In some embodiments, materials of the first conductive layer, the second conductive layer, and the third conductive layer all include transparent conductive materials.

[0012] In some embodiments, the thickness of the third conductive layer is greater than the thickness of the second conductive layer, and the thickness of the second conductive layer is equal to the thickness of the first conductive layer.

[0013] In some embodiments, the thickness of the first conductive layer is greater than the thickness of the active layer.

[0014] In some embodiments, an area of ​​an overlapping portion of the first connecting member and the first conductive layer is smaller than an area of ​​an overlapping portion of the second connecting member and the second conductive layer.

[0015] In some embodiments, the first insulating layer includes a gate insulating layer located below the gate; the active layer includes: a first conductive region electrically connected to the first connector, a second conductive region electrically connected to the second connector, and a channel region between the first conductive region and the second conductive region, wherein the channel region is flush with an edge of the gate insulating layer.

[0016] In some embodiments, a width of an overlapping portion of the first connector and the first conductive layer in a direction from the first connector to the gate is smaller than a distance between an edge of the first conductive layer and the channel region.

[0017] In some embodiments, an area of ​​the first conductor layer is larger than an area of ​​an overlapping portion of the first connecting member and the first conductive layer.

[0018] In some embodiments, an area of ​​the first conductor layer is smaller than an area of ​​the channel region.

[0019] In some embodiments, a width of an overlapping portion of the first conductive layer and the active layer in a direction from the first connector to the gate is smaller than a width of an overlapping portion of the second conductive layer and the active layer in a direction from the first connector to the gate.

[0020] In some embodiments, the distance between the first conductive layer and the gate is greater than the width of the overlapping portion of the first connector and the first conductive layer along the direction from the first connector to the gate, and the width of the overlapping portion of the first connector and the first conductive layer along the direction from the first connector to the gate is greater than the width of the second portion of the first conductive layer along the direction from the first connector to the gate.

[0021] In some embodiments, the array substrate further includes: a second insulating layer covering the first connector, the second connector and the gate; a planarization layer on the side of the second insulating layer away from the substrate structure; a first electrode layer and a pixel defining layer on the side of the planarization layer away from the substrate structure, the first electrode layer being electrically connected to the second connector, the pixel defining layer having a first opening exposing at least a portion of the first electrode layer; a light-emitting layer located at least in the first opening; and a second electrode layer electrically connected to the light-emitting layer.

[0022] In some embodiments, the width of the overlapping portion between the orthographic projection of the second conductive layer on the substrate and the orthographic projection of the third conductive layer on the substrate along the direction from the first connector to the gate is smaller than the width of the overlapping portion between the orthographic projection of the second conductive layer on the substrate and the orthographic projection of the first electrode layer on the substrate along the direction from the first connector to the gate.

[0023] In some embodiments, the width of the overlapping portion between the orthographic projection of the second conductive layer on the substrate and the orthographic projection of the third conductive layer on the substrate along the direction from the first connector to the gate is smaller than the width of the overlapping portion between the orthographic projection of the third conductive layer on the substrate and the orthographic projection of the first electrode layer on the substrate along the direction from the first connector to the gate.

[0024] According to another aspect of the present disclosure, an array substrate is provided, comprising: a substrate structure; and a thin film transistor on the substrate structure, the thin film transistor comprising: an active layer on the substrate structure; a patterned first insulating layer on a side of the active layer away from the substrate structure, the first insulating layer having a first through hole exposing a portion of the active layer; a first conductive layer in the first through hole and in contact with the active layer; and a first connector, a second connector, and a gate on a side of the first insulating layer away from the substrate structure, wherein the first connector is in contact with the first conductive layer, the first connector, the second connector, and the gate are on the same layer and are isolated from each other. The gate is located between the first connector and the second connector; the active layer includes: a first conductive region electrically connected to the first connector, a second conductive region electrically connected to the second connector, and a channel region between the first conductive region and the second conductive region, wherein the channel region is below the gate; the first conductive layer includes a first portion away from the gate and a second portion close to the gate, the first portion is completely covered by the first connector, and the second portion is not covered by the first connector, and the orthographic projection of the first conductive layer on the substrate structure is located inside the orthographic projection of the active layer on the substrate structure.

[0025] In some embodiments, a width of the second portion along a direction from the first connector to the gate is smaller than a width of the first portion along a direction from the first connector to the gate.

[0026] In some embodiments, a width of the second portion along a direction from the first connector to the gate is smaller than a width of the channel region along the direction from the first connector to the gate.

[0027] In some embodiments, the thickness of the second portion is less than the thickness of the first portion.

[0028] In some embodiments, the width of the first portion is 2 to 5 times the width of the second portion.

[0029] In some embodiments, the active layer further includes a semiconductor region, which is located on a side of the first conductive region away from the channel region; wherein a width of the second portion along a direction from the first connector to the gate is smaller than a width of the semiconductor region along a direction from the first connector to the gate.

[0030] According to another aspect of the present disclosure, a display device is provided, comprising: the array substrate as described above.

[0031] According to another aspect of the present disclosure, a method for manufacturing an array substrate is provided, comprising: forming an active layer on a substrate structure; forming a patterned first insulating layer on a side of the active layer away from the substrate structure, the first insulating layer having a first through hole exposing a portion of the active layer; performing a first conductorization treatment on the exposed portion of the active layer; forming a first conductive layer in contact with the active layer in the first through hole; forming a connecting material layer on a side of the first insulating layer away from the substrate structure through a deposition process; patterning the connecting material layer using a patterned mask layer to form a first connector, the first connector being in contact with the first conductive layer, the first connector covering a first portion of the first conductive layer and not covering a second portion of the first conductive layer; etching the first insulating layer using the mask layer through a self-alignment process to enlarge the first through hole, wherein the enlarged first through hole exposes another portion of the active layer; and performing a second conductorization treatment on the exposed another portion of the active layer.

[0032] Other features and advantages of the present disclosure will become apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0034] The present disclosure can be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0035] FIG1 is a schematic cross-sectional view showing an array substrate according to an embodiment of the present disclosure;

[0036] FIG2 is a schematic cross-sectional view showing an array substrate according to another embodiment of the present disclosure;

[0037] FIG3 is an enlarged schematic diagram schematically showing the array substrate in FIG1 at block 201;

[0038] FIG4 is a top view schematically showing a partial structure of an array substrate according to an embodiment of the present disclosure;

[0039] FIG5 is a flow chart illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure;

[0040] 6A to 6I are schematic cross-sectional views illustrating structures at several stages in a manufacturing process of an array substrate according to some embodiments of the present disclosure;

[0041] 7 is a schematic cross-sectional view showing the structure of an array substrate at a stage in a manufacturing process according to another embodiment of the present disclosure;

[0042] 8 is a schematic cross-sectional view showing the structure of an array substrate at a stage in a manufacturing process according to another embodiment of the present disclosure;

[0043] 9A to 9C are schematic cross-sectional views showing structures at several stages in a manufacturing process of an array substrate according to other embodiments of the present disclosure;

[0044] 10A to 10C are schematic cross-sectional views illustrating structures at several stages in a manufacturing process of an array substrate according to other embodiments of the present disclosure.

[0045] It should be understood that the size of each part shown in the drawings is not drawn according to the actual proportional relationship.In addition, the same or similar reference numerals represent the same or similar components. DETAILED DESCRIPTION

[0046] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the present disclosure, its application, or use. The present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to make the present disclosure thorough and complete and to fully convey the scope of the present disclosure to those skilled in the art. It should be noted that unless otherwise specifically stated, the relative arrangement of parts and steps, the composition of materials, numerical expressions, and numerical values ​​set forth in these embodiments should be interpreted as being merely exemplary and not as limiting.

[0047] The terms "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different parts. The terms "include" or "comprises" and similar terms mean that the elements before the term include the elements listed after the term, and do not exclude the possibility of also including other elements. The terms "upper", "lower", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0048] In the present disclosure, when a specific device is described as being located between a first device and a second device, an intervening device may or may not be present between the specific device and the first device or the second device. When a specific device is described as being connected to another device, the specific device may be directly connected to the other device without an intervening device, or may be not directly connected to the other device but with an intervening device.

[0049] All terms (including technical or scientific terms) used in this disclosure have the same meaning as those understood by one of ordinary skill in the art to which this disclosure belongs, unless otherwise specifically defined. It should also be understood that terms defined in, for example, general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or highly formal sense, unless explicitly defined herein.

[0050] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0051] The inventors of this disclosure discovered that in related art, during the formation of TFTs on array substrates, the active layer undergoes a second etching process at the junction of the source or drain electrode and the active layer, resulting in missing portions of the active layer. This shortens the conduction path at the junction of the source or drain electrode and the active layer, potentially limiting current flow and causing poor contact, thus impacting the performance of display products.

[0052] In view of this, embodiments of the present disclosure provide an array substrate to reduce the possibility of missing portions in the active layer.

[0053] FIG. 1 is a schematic cross-sectional view illustrating an array substrate according to an embodiment of the present disclosure.

[0054] As shown in FIG. 1 , the array substrate includes a substrate structure 110 .

[0055] As shown in Fig. 1, the array substrate includes an active layer 120 on a substrate structure 110. For example, the material of the active layer includes a semiconductor material such as IGZO (Indium Gallium Zinc Oxide).

[0056] As shown in FIG1 , the array substrate further includes a patterned first insulating layer 130 on a side of the active layer 120 away from the substrate structure. The first insulating layer 130 has a first through hole 141 that exposes a portion of the active layer 120. The first insulating layer 130 covers the active layer 120. For example, the material of the first insulating layer includes an inorganic insulating material (e.g., silicon dioxide or silicon nitride).

[0057] As shown in FIG1 , the array substrate further includes a first conductive layer 151 in the first through hole 141 and in contact with the active layer 120. In some embodiments, the material of the first conductive layer includes a metal material. For example, the material of the first conductive layer includes a transparent conductive material. For example, the transparent conductive material includes ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). Here, the first conductive layer uses a transparent conductive material to improve the light transmittance of the array substrate.

[0058] As shown in FIG1 , the array substrate further includes a first connector 161 on a side of the first insulating layer 130 away from the substrate structure 110. The first connector 161 contacts the first conductive layer 151. The material of the first connector 161 includes a metal material such as copper. For example, the first connector can be a source electrode or a drain electrode. The first connector 161 covers a first portion of the first conductive layer 151 and does not cover a second portion of the first conductive layer 151 (described later in conjunction with FIG3 ).

[0059] Thus, an array substrate according to some embodiments of the present disclosure is provided. The array substrate includes: a substrate structure; an active layer on the substrate structure; a patterned first insulating layer on a side of the active layer away from the substrate structure, the first insulating layer having a first through hole exposing a portion of the active layer; a first conductive layer in the first through hole and in contact with the active layer; and a first connector on a side of the first insulating layer away from the substrate structure, the first connector in contact with the first conductive layer, the first connector covering a first portion of the first conductive layer and not covering a second portion of the first conductive layer. In this embodiment, since the first conductive layer is formed in the first through hole of the first insulating layer, during the manufacturing process, the first conductive layer can protect a portion of the active layer thereunder to a certain extent, thereby reducing the possibility of missing portions of the active layer, thereby improving the performance of the array substrate and the display device formed thereby.

[0060] As shown in FIG. 1 , the first insulating layer 130 further has a second through hole 142 exposing another portion of the active layer 120 .

[0061] In some embodiments, as shown in FIG1 , the array substrate further includes a second conductive layer 152 in the second through hole 142. The second conductive layer 152 fills the second through hole 142. For example, the second conductive layer may be made of a transparent conductive material, such as ITO or IZO. Using a transparent conductive material for the second conductive layer can improve the light transmittance of the array substrate.

[0062] Similar to the aforementioned first conductive layer, the second conductive layer can protect a portion of the active layer thereunder, thereby reducing the possibility of missing portions of the active layer, thereby improving the performance of the array substrate and the display device formed thereby.

[0063] In some embodiments, as shown in Figure 1, the width of the overlapping portion of the first conductive layer 151 and the active layer 120 in the direction from the first connector to the gate is smaller than the width of the overlapping portion of the second conductive layer 152 and the active layer 120 in the direction from the first connector to the gate. In other words, the second conductive layer 152 is made relatively large. For example, the area or width of the second conductive layer 152 (i.e., the lateral dimension shown in the cross-sectional view) is larger than the area or width of the first conductive layer 151. In this way, the second conductive layer can also serve as an electrode plate of a capacitor. This is conducive to forming a transparent capacitor structure and improving capacitance and conductivity.

[0064] In some embodiments, as shown in FIG1 , the array substrate further includes a second connector 162 electrically connected to the second conductive layer 152 . The second connector 162 contacts the second conductive layer 152 . The second connector 162 is made of a metal such as copper. The second connector can be a source or a drain. For example, the first connector 161 is a source, and the second connector 162 is a drain. In another example, the first connector 161 is a drain, and the second connector 162 is a source.

[0065] In some embodiments, as shown in FIG1 , the array substrate further includes a gate 163 located on a side of the first insulating layer 130 away from the active layer 120. The gate 163 is made of a metal material such as copper.

[0066] As shown in FIG1 , the second connector 162 and the gate 163 are on the same layer. The first connector 161 and the gate 163 are also on the same layer. The first connector 161 and the second connector 162 are both isolated from the gate 163. The gate 163 is located between the first connector 161 and the second connector 162.

[0067] It should be noted that "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then patterning the film layer using the same mask through a single patterning process. For example, two structural layers in the same layer can be located on the same structural layer or on different structural layers. Two structural layers in the same layer can be at different heights or have different thicknesses.

[0068] In some embodiments, as shown in FIG1 , the substrate structure 110 includes a substrate 111. The substrate includes a rigid substrate or a flexible substrate, etc. For example, the substrate may include a glass substrate, etc.

[0069] As shown in FIG1 , the substrate structure 110 further includes a light shielding layer 112 on the base substrate 111. The orthographic projection of the light shielding layer 112 on the base substrate 111 at least partially overlaps with the orthographic projection of the active layer 120 on the base substrate 111. For example, the light shielding layer may be made of a metal material such as aluminum, molybdenum, or copper.

[0070] As shown in Figure 1, the substrate structure 110 further includes a third conductive layer 113 covering the light shielding layer 112. The third conductive layer may extend from the light shielding layer 112 to the base substrate 111. The third conductive layer 113 may serve as another electrode plate of the capacitor.

[0071] It should be noted that in some other embodiments, the positions of the light shielding layer 112 and the third conductive layer 113 can be interchanged. For example, the third conductive layer 113 can be located on the base substrate 111, and the light shielding layer 112 can be located on the side of the third conductive layer 113 away from the base substrate, that is, the light shielding layer covers the third conductive layer.

[0072] In some embodiments, the material of the third conductive layer 113 includes a transparent conductive material. For example, the transparent conductive material includes ITO or IZO. Here, the third conductive layer uses a transparent conductive material to improve the light transmittance of the array substrate.

[0073] As shown in FIG1 , the substrate structure 110 further includes a buffer layer 114 between the third conductive layer 113 and the active layer 120. For example, the buffer layer may include an inorganic insulating material such as silicon dioxide. The buffer layer 114 covers the third conductive layer 113 and the substrate 111.

[0074] In some embodiments, as shown in FIG1 , the substrate 110 may further include a trace 115 . The first connector 161 may be electrically connected to the trace 115 via a third through hole (serving as a conductive via) 143 that passes through the first insulating layer 130 and the buffer layer 114 . The trace 115 may be located on the same layer as the light shielding layer 112 . For example, the material of the trace 115 is the same as that of the light shielding layer 112 . The trace 115 is isolated from the light shielding layer 112 .

[0075] In some embodiments, an orthographic projection of the first conductive layer 151 on the base substrate 111 at least partially overlaps with an orthographic projection of the light shielding layer 112 on the base substrate 111. The light shielding layer can play a role in shielding light.

[0076] In some embodiments, the thickness of the third conductive layer 113 is greater than that of the second conductive layer 152. The thickness of the second conductive layer 152 is equal to the thickness of the first conductive layer 151. This makes the second conductive layer thinner, thereby further improving the light transmittance of the array substrate. In addition, the thickness of the third conductive layer 113 is relatively thick, which can reduce resistance.

[0077] For example, the thickness of the third conductive layer 113 is 3000 angstroms to 5000 angstroms. For example, the thickness of the second conductive layer 152 (or the first conductive layer 151 ) is 500 angstroms to 1000 angstroms.

[0078] In some embodiments, the thickness of the first conductive layer 151 is greater than the thickness of the active layer 120. For example, the thickness of the active layer 120 is 300 angstroms to 500 angstroms.

[0079] In some embodiments, the overlapping area of ​​the first connector 161 and the first conductive layer 151 is smaller than the overlapping area of ​​the second connector 162 and the second conductive layer 151. Here, the larger overlapping area of ​​the second connector and the second conductive layer can reduce contact resistance.

[0080] In some embodiments, as shown in FIG. 1 , the first insulating layer 130 includes a gate insulating layer 131 located below the gate 163 .

[0081] As shown in FIG1 , the active layer 120 includes a first conductive region 121 electrically connected to a first connector 161, a second conductive region 122 electrically connected to a second connector 162, and a channel region 123 between the first conductive region 121 and the second conductive region 122. The channel region 123 is flush with the edge of the gate insulating layer 131. Here, the first conductive layer 151 contacts the first conductive region 121, and the second conductive layer 152 contacts the second conductive region 122. By partially conductively ...

[0082] FIG. 3 is an enlarged schematic diagram schematically showing the array substrate at block 201 in FIG. 1 .

[0083] 3 , the first conductive layer 151 includes a first portion 1511 away from the gate 163 and a second portion 1512 close to the gate 163 . The first portion 1511 is completely covered by the first connector 161 , while the second portion 1512 is not covered by the first connector 161 .

[0084] 3 , a width d1 of the overlapping portion of the first connector 161 and the first conductive layer 151 in a direction from the first connector 161 to the gate 163 is smaller than a distance d4 between an edge of the first conductive layer 151 and the channel region 123 .

[0085] In some embodiments, the area of ​​the first conductive layer 151 is larger than the area of ​​the overlapping portion (i.e., the portion corresponding to width d1) of the first connector 161 and the first conductive layer 151. This facilitates full contact between the first connector and the first conductive layer, preventing poor contact.

[0086] In some embodiments, the area of ​​the first conductive layer 151 is smaller than the area of ​​the channel region 123. A larger area of ​​the channel region is beneficial for improving the performance of the thin film transistor.

[0087] It should be noted that the "area" used in this disclosure refers to the area of ​​the surface of the structural layer parallel to the plane of the substrate. For example, this area can be the area of ​​the top surface of the structural layer. For example, the area of ​​the top surface of the first conductor layer 151 is the area of ​​the first conductor layer 151; the area of ​​the top surface of the channel region 123 is the area of ​​the channel region 123, and so on.

[0088] In some embodiments, the distance d3 between the first conductive layer 151 and the gate 163 is greater than the width d1 of the overlapping portion of the first connector 161 and the first conductive layer 151 along the direction from the first connector to the gate, and the width d1 of the overlapping portion of the first connector 161 and the first conductive layer 151 along the direction from the first connector to the gate is greater than the width d2 of the second portion 1512 of the first conductive layer 151 (i.e., the portion not covered by the first connector 161) along the direction from the first connector to the gate. In other words, d3 > d1 > d2. This dimensional design helps improve the performance of the thin film transistor, thereby improving the performance of the array substrate and the display device formed therefrom.

[0089] In addition, as shown in FIG. 3 , a gap 301 exists between the first conductive layer 151 and the gate insulating layer 131 .

[0090] 1 , in some embodiments, the array substrate further includes a second insulating layer 171 covering the first connector 161, the second connector 162, and the gate 163. For example, the material of the second insulating layer 171 includes at least one of silicon dioxide and silicon nitride.

[0091] As shown in Fig. 1 , the array substrate further includes a planarization layer 172 on a side of the second insulating layer 171 away from the substrate structure 110. For example, the material of the planarization layer includes an organic insulating material such as resin.

[0092] As shown in FIG1 , the array substrate further includes a first electrode layer 181 and a pixel defining layer 174 on a side of the planarization layer 172 away from the substrate structure 110. The first electrode layer 181 is electrically connected to the second connector 162 (e.g., via a conductive via). The pixel defining layer 174 has a first opening 1742 that exposes at least a portion of the first electrode layer 181. For example, the first electrode layer is an anode layer. For example, the material of the first electrode layer 181 includes a metal such as copper, silver, aluminum, or an aluminum alloy, or a transparent conductive material such as ITO or IZO.

[0093] 1 , the array substrate further includes a light emitting layer 180 located at least in the first opening 1742. The light emitting layer may include a light emitting layer for emitting red light, a light emitting layer for emitting green light, or a light emitting layer for emitting blue light.

[0094] As shown in FIG1 , the array substrate further includes a second electrode layer 182 electrically connected to the light-emitting layer 180. The second electrode layer 182 covers the pixel defining layer 174 and the light-emitting layer 180. The second electrode layer 182 may be a cathode layer. For example, the material of the second electrode layer 182 includes a metal such as copper, silver, aluminum, or an aluminum alloy, or a transparent conductive material such as ITO or IZO.

[0095] In some embodiments, the array substrate may further include other functional layers between the first electrode layer 181 and the second electrode layer 182, such as an electron transport layer, a hole transport layer, an electron blocking layer, or a hole blocking layer, etc. Therefore, the scope of the present disclosure is not limited thereto.

[0096] In some embodiments, as shown in FIG1 , the width of the overlapping portion between the orthographic projection of the second conductive layer 152 on the base substrate 111 and the orthographic projection of the third conductive layer 113 on the base substrate 111, along the direction from the first connector to the gate, is smaller than the width of the overlapping portion between the orthographic projection of the second conductive layer 152 on the base substrate 111 and the orthographic projection of the first electrode layer 181 on the base substrate 111, along the direction from the first connector to the gate. This helps improve the light transmittance of the array substrate.

[0097] In some embodiments, as shown in FIG1 , the width of the overlapping portion between the orthographic projection of the second conductive layer 152 on the base substrate 111 and the orthographic projection of the third conductive layer 113 on the base substrate 111, along the direction from the first connector to the gate, is smaller than the width of the overlapping portion between the orthographic projection of the third conductive layer 113 on the base substrate 111 and the orthographic projection of the first electrode layer 181 on the base substrate 111, along the direction from the first connector to the gate. This helps improve the light transmittance of the array substrate.

[0098] The present disclosure provides an array substrate. As shown in FIG1 , the array substrate includes a substrate structure 110 and thin film transistors on the substrate structure 110 .

[0099] The thin film transistor includes an active layer 120 on a substrate structure 110. The thin film transistor also includes a patterned first insulating layer 130 on a side of the active layer 120 away from the substrate structure. The first insulating layer 130 has a first through hole 141 that exposes a portion of the active layer 120. The thin film transistor also includes a first conductive layer 151 in the first through hole 141 and in contact with the active layer 120. The thin film transistor also includes a first connector 161, a second connector 162, and a gate 163 on a side of the first insulating layer 130 away from the substrate structure. The first connector 161 is in contact with the first conductive layer 151. The first connector 161, the second connector 162, and the gate 163 are on the same layer and are isolated from each other. The gate 163 is located between the first connector 161 and the second connector 162.

[0100] As shown in Figures 1 and 3, active layer 120 includes a first conductive region 121 electrically connected to first connector 161, a second conductive region 122 electrically connected to second connector 162, and a channel region 123 between first conductive region 121 and second conductive region 122. Channel region 123 is below gate 163.

[0101] As shown in FIG3 , the first conductive layer 151 includes a first portion 1511 away from the gate 163 and a second portion 1512 near the gate 163. The first portion 1511 is completely covered by the first connector 161, while the second portion 1512 is not covered by the first connector 161. The orthographic projection of the first conductive layer 151 on the substrate structure 110 is located inside the orthographic projection of the active layer 120 on the substrate structure 110.

[0102] In the above embodiment, since a first conductive layer is formed in the first through hole of the first insulating layer, during the manufacturing process, the first conductive layer can protect a portion of the active layer thereunder to a certain extent, thereby reducing the possibility of missing portions of the active layer, thereby improving the performance of the array substrate and the display device formed thereby.

[0103] 3 , a width d2 of the second portion 1512 in the direction from the first connector to the gate is smaller than a width d1 of the first portion 1511 in the direction from the first connector to the gate. Here, the width of the first portion 1511 is equal to the width of the overlapping portion of the first connector 161 and the first conductive layer 151, both being d1.

[0104] For example, the width d1 of the first portion 1511 is 2 to 5 times the width d2 of the second portion 1512 .

[0105] In some embodiments, as shown in FIG. 3 , a width d2 of the second portion 1512 in the direction from the first connector to the gate is smaller than a width d5 ​​of the channel region 123 in the direction from the first connector to the gate.

[0106] In some embodiments, as shown in FIG. 3 , the thickness H2 of the second portion 1512 is less than the thickness H1 of the first portion 1511 .

[0107] In some embodiments, as shown in Figures 1 and 3, the active layer 120 may further include a semiconductor region (which may be referred to as a first semiconductor region) 124. The semiconductor region 124 is located on a side of the first conductive region 121 away from the channel region 123. The width d2 of the second portion 1512 along the direction from the first connector to the gate is smaller than the width d6 of the semiconductor region 124 along the direction from the first connector to the gate.

[0108] In some other embodiments, the active layer may further include another semiconductor region, which may be referred to as a second semiconductor region (not shown in the figure). The second semiconductor region is located on a side of the second conductive region 122 away from the channel region 123 .

[0109] FIG. 2 is a schematic cross-sectional view illustrating an array substrate according to another embodiment of the present disclosure.

[0110] The structure of the array substrate shown in FIG2 is similar to that of the array substrate shown in FIG1 . However, the difference from the structure of the array substrate shown in FIG1 is that in the array substrate shown in FIG2 , the second through-hole 142 further exposes a portion of the buffer layer 114, and the second conductive layer 152 includes a third portion 1521 located on the surface of the active layer 120 and a fourth portion 1522 located on the surface of the buffer layer 114. For example, in the structure shown in FIG2 , the lateral dimensions of the active layer 120 are smaller than those of the active layer shown in FIG1 , and the area of ​​the third portion of the second conductive layer 152 is smaller than the area of ​​the overlapping portion between the second conductive layer and the active layer shown in FIG1 . Therefore, in the array substrate shown in FIG2 , the area of ​​the overlapping portion between the second conductive layer and the active layer is reduced, which can improve the light transmittance of the array substrate.

[0111] FIG. 4 is a top view schematically showing a partial structure of an array substrate according to an embodiment of the present disclosure.

[0112] For ease of illustration, Figure 4 shows the first conductive region 121, first conductive layer 151, and first connector 161 of the active layer of the array substrate. As shown in Figure 4, due to the presence of first conductive layer 151, there is no missing portion in first conductive region 121. Therefore, current can flow relatively evenly from the first connector through first conductive region 121, improving the signal transmission capability of the array substrate.

[0113] In some embodiments of the present disclosure, a display device is further provided, including the array substrate described above, for example, the array substrate shown in Figure 1 or Figure 2. For example, the display device can be any product or component with a display function, such as a display panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system.

[0114] Figure 5 is a flow chart illustrating a method for manufacturing an array substrate according to one embodiment of the present disclosure. As shown in Figure 5, the manufacturing method includes steps S502 to S508. Figures 6A to 6I are schematic cross-sectional views illustrating the structure of an array substrate at several stages during the manufacturing process according to some embodiments of the present disclosure. Figures 9A to 9C are schematic cross-sectional views illustrating the structure of an array substrate at several stages during the manufacturing process according to other embodiments of the present disclosure. The manufacturing process of an array substrate according to some embodiments of the present disclosure will be described in detail below in conjunction with Figure 5, Figures 6A to 6I, and Figures 9A to 9C.

[0115] As shown in FIG. 5 , in step S502 , an active layer is formed on a substrate structure.

[0116] 6A , an active layer 120 is formed on a substrate structure 110 by a deposition process, for example. The specific structure of the substrate structure 110 has been described in detail above and will not be repeated here.

[0117] Returning to FIG. 5 , in step S504 , a patterned first insulating layer is formed on a side of the active layer away from the substrate structure, wherein the first insulating layer has a first through hole exposing a portion of the active layer.

[0118] For example, a process of forming the patterned first insulating layer may be described in detail with reference to FIGS. 6A to 6F .

[0119] As shown in FIG. 6A , a first insulating layer 130 is formed on a side of the active layer 120 away from the substrate structure 110 , for example, by a deposition process.

[0120] 6B , a first mask layer 610 is formed on a side of the first insulating layer 130 away from the substrate structure 110. For example, the material of the first mask layer is positive photoresist.

[0121] Next, as shown in FIG6B and FIG6C , the first mask layer 610 is patterned using a patterned first mask plate 621 to form a patterned first mask layer 610 , such that the patterned first mask layer has a second opening 6102 exposing a portion of the first insulating layer 130 , for example, by exposure and development techniques.

[0122] 6D and 6E , the portion of the first insulating layer 130 exposed by the second opening 6102 is removed by an etching process (e.g., dry etching) using the patterned first mask layer 610 to form a first through hole 141, thereby forming a patterned first insulating layer 130. The first through hole 141 exposes a portion of the active layer 120.

[0123] Returning to FIG. 5 , in step S506 , a first conductorization process is performed on the exposed portion of the active layer.

[0124] 6E , a first conductive treatment may be performed on the exposed portion of the active layer 120. For example, the first conductive treatment may be performed using a dry etching process and He gas (helium).

[0125] Next, as shown in FIG6F , the first mask layer 610 is removed.

[0126] Returning to FIG. 5 , in step S508 , a first conductive layer contacting the active layer is formed in the first through hole.

[0127] For example, a process of forming the first conductive layer may be described in detail with reference to FIG. 6G to FIG. 6I .

[0128] 6G , a first conductive layer 151 is formed by a deposition process on the side of the patterned first insulating layer 130 away from the substrate structure 110 and in the first through hole 141. For example, the material of the first conductive layer 151 includes a transparent conductive material.

[0129] 6H , a second mask layer 612 is formed on the side of the first conductive layer 151 away from the substrate structure 110, and the second mask layer 612 is exposed and developed using the aforementioned first mask plate 621, thereby forming the structure of the second mask layer 612 shown in FIG6H . For example, the material of the second mask layer is a negative photoresist.

[0130] 6H , the first conductive layer 151 is etched to remove the portion of the first conductive layer 151 not blocked by the second mask layer 612 and retain the portion of the first conductive layer 151 blocked by the second mask layer 612 , thereby forming the structure shown in FIG. 6I .

[0131] Next, as shown in FIG. 6I , the second mask layer 612 is removed.

[0132] Thus, a patterned first conductive layer 151 is formed, and the first conductive layer 151 can protect the active layer 120 thereunder from being etched as much as possible.

[0133] Returning to FIG. 5 , in step S510 , a connection material layer is formed on a side of the first insulating layer away from the substrate structure by a deposition process.

[0134] 9A , a connection material layer 160 is formed on a side of the first insulating layer 130 away from the substrate structure 110 through a deposition process. The connection material layer 160 may be made of a metal such as copper.

[0135] Returning to FIG. 5 , in step S512 , the connection material layer is patterned using the patterned mask layer to form a first connector, which contacts the first conductive layer and covers a first portion of the first conductive layer but does not cover a second portion of the first conductive layer.

[0136] 9A , a patterned mask layer (also referred to as a third mask layer) 637 is formed on the side of the connection material layer away from the substrate structure 110. For example, the material of the third mask layer is photoresist.

[0137] Next, as shown in FIG9B , the connection material layer 160 is patterned using the third mask layer 637, for example, through a wet etching process to form a first connector 161. In addition, a second connector 162 and a gate 163 may also be formed during this process. During this wet etching process, the etching solution may etch a portion of the connection material layer below the edge of the third mask layer, resulting in the first connector being recessed inward.

[0138] In this way, the first connecting member is formed.

[0139] Returning to FIG. 5 , in step S514 , the first insulating layer is etched by a self-alignment process using the mask layer to enlarge the first through hole, wherein the enlarged first through hole exposes another portion of the active layer.

[0140] For example, as shown in FIG9C , the first insulating layer 130 is etched using a patterned mask layer (i.e., a third mask layer) 637 through a self-aligned process to enlarge the first through-hole 141, wherein the enlarged first through-hole 141 exposes another portion of the active layer 120. For example, the etching is performed using a dry etching method. Here, the entire surface of the first insulating layer is etched to form a gap between the first conductive layer and the gate insulating layer, i.e., the gap 301 described above.

[0141] Returning to FIG. 5 , in step S516 , a second conductorization process is performed on the other exposed portion of the active layer.

[0142] For example, as shown in FIG9C , a second conductive process is performed on the exposed portion of the active layer 120. For example, the second conductive process can be performed using a dry etching process and He gas (helium). During this process, the portion of the active layer directly below the first conductive layer 151 can be protected from etching due to the presence of the first conductive layer 151.

[0143] Next, the third mask layer 637 is removed.

[0144] Thus, a manufacturing method for an array substrate according to some embodiments of the present disclosure is provided. The manufacturing method includes: forming an active layer on a substrate structure; forming a patterned first insulating layer on a side of the active layer away from the substrate structure, the first insulating layer having a first through-hole exposing a portion of the active layer; performing a first conductorization process on the exposed portion of the active layer; forming a first conductive layer in contact with the active layer in the first through-hole; forming a connecting material layer on a side of the first insulating layer away from the substrate structure through a deposition process; patterning the connecting material layer using a patterned mask layer to form a first connector, the first connector contacting the first conductive layer, the first connector covering a first portion of the first conductive layer and not covering a second portion of the first conductive layer; etching the first insulating layer using the mask layer through a self-aligned process to enlarge the first through-hole, wherein the enlarged first through-hole exposes another portion of the active layer; and performing a second conductorization process on the exposed portion of the active layer. This manufacturing method can reduce the possibility of missing portions of the active layer, thereby improving the performance of the array substrate and the display device formed therefrom.

[0145] Furthermore, in the above manufacturing process, the second mask layer uses negative photoresist, so that the first mask plate mentioned above can be used for exposure and development without the need to additionally manufacture a mask plate, thereby reducing process complexity.

[0146] Figure 7 is a schematic cross-sectional view showing a structure of a stage in a process of manufacturing an array substrate according to another embodiment of the present disclosure. Figure 7 is a schematic cross-sectional view showing a structure of a stage in a process of forming a first conductive layer according to some other embodiments.

[0147] For example, as shown in FIG. 7 , after the structure shown in FIG. 6E is formed, a first conductive layer 151 is formed on the patterned first mask layer 610 and in the first through hole 141 of the first insulating layer 130 through a deposition process.

[0148] Next, the first mask layer 610 and the portion of the first conductive layer 151 on the first mask layer 610 are removed by a lift-off process, leaving the portion of the first conductive layer 151 in the first through hole 141, thereby forming the structure shown in FIG. 6I.

[0149] In this embodiment, a lift-off process is adopted, which does not require an additional mask process, thereby further reducing process complexity.

[0150] Figure 8 is a schematic cross-sectional view showing a structure of a stage in a process of manufacturing an array substrate according to another embodiment of the present disclosure. Figure 8 is a schematic cross-sectional view showing a structure of a stage in a process of forming a first conductive layer according to some other embodiments.

[0151] For example, as shown in FIG8 , after forming the structure shown in FIG6F , a first conductive layer 151 is formed in the first through-hole 141 of the first insulating layer 130 using a patterned second mask 630 and an evaporation process, thereby forming the structure shown in FIG6I . As shown in FIG8 , the second mask 630 has a through-hole (which may be referred to as a fourth through-hole), and the opening is aligned with the first through-hole 141. For example, the second mask is an FMM mask (Fine Metal Mask). In addition, FIG8 also shows an evaporation source 635. The material of the evaporation source includes a transparent conductive material (such as ITO or IZO).

[0152] In this embodiment, the first conductive layer is formed by an evaporation process, which can reduce process complexity.

[0153] 10A to 10C are cross-sectional schematic diagrams showing structures at several stages in the manufacturing process of an array substrate according to other embodiments of the present disclosure. The manufacturing process of an array substrate according to other embodiments of the present disclosure will be described in detail below in conjunction with FIG10A to FIG10C and FIG1 .

[0154] First, as shown in FIG10A , a substrate structure is provided, which includes the following steps.

[0155] For example, as shown in FIG10A , a light shielding layer 112 is formed on a base substrate 111 through deposition and patterning processes. In addition, traces 115 are also formed.

[0156] Next, as shown in FIG. 10A , a third conductive layer 113 covering the light shielding layer 112 is formed by deposition and patterning processes.

[0157] In some other embodiments, the third conductive layer 113 may be first formed on the base substrate 111 through a deposition and patterning process; and then, the light shielding layer 112 may be formed on the third conductive layer 113 through a deposition and patterning process.

[0158] Next, as shown in FIG. 10A , a buffer layer 114 is formed covering the third conductive layer 113 through a deposition process.

[0159] At this point, the substrate structure 110 is formed.

[0160] 10B , the active layer 120, the first insulating layer 130, the first through-hole 141, the first conductive layer 151, and the first connector 161 are formed using the aforementioned process. Here, the second through-hole 142, the third through-hole 143, the second conductive layer 152, the second connector 162, and the gate 163 are also formed.

[0161] It should be noted that the second conductive layer 152 is formed using the same process as the first conductive layer 151, and the second connector 162 and the gate 163 are formed using the same patterning process as the first connector 161. Detailed description will be omitted here.

[0162] It should also be noted that, while forming the first through hole 141, the second through hole 142 and the third through hole 143 may also be formed. The formation process of the second through hole 142 and the third through hole 143 is similar to that of the first through hole 141, and will not be repeated here.

[0163] Next, as shown in FIG. 10B , a second insulating layer 171 covering the first connector 161 , the second connector 162 and the gate 163 is formed by a deposition process.

[0164] Next, as shown in FIG. 10C , a planarization layer 172 is formed on a side of the second insulating layer 171 away from the substrate structure 110 .

[0165] Next, as shown in FIG. 10C , a first electrode layer 181 electrically connected to the second connector 162 is formed on a side of the planarization layer 172 away from the substrate structure 110 .

[0166] 10C , a pixel defining layer 174 is formed on the side of the planarization layer 172 away from the substrate structure 110 . The pixel defining layer 174 has a first opening 1742 exposing at least a portion of the first electrode layer 181 .

[0167] Next, as shown in FIG. 1 , the light emitting layer 180 is formed at least in the first opening 1742 .

[0168] Next, as shown in FIG. 1 , a second electrode layer 182 electrically connected to the light emitting layer 180 is formed by a deposition process.

[0169] Thus, a method for manufacturing an array substrate according to some embodiments of the present disclosure is provided. This method can reduce the possibility of missing portions in the active layer, thereby improving the performance of the array substrate and the display device formed therefrom.

[0170] Thus far, various embodiments of the present disclosure have been described in detail. To avoid obscuring the concept of the present disclosure, some details known in the art have not been described. Based on the above description, those skilled in the art can fully understand how to implement the technical solutions disclosed herein.

[0171] Although some specific embodiments of the present disclosure have been described in detail through examples, those skilled in the art will understand that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. Those skilled in the art will understand that the above embodiments may be modified or some technical features may be replaced with equivalents without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. An array substrate, comprising: Substrate structure; an active layer on the substrate structure; a patterned first insulating layer on a side of the active layer away from the substrate structure, the first insulating layer having a first through hole exposing a portion of the active layer; a first conductive layer in the first through hole and in contact with the active layer; and A first connector is located on a side of the first insulating layer away from the substrate structure, the first connector contacts the first conductive layer, and the first connector covers a first portion of the first conductive layer but does not cover a second portion of the first conductive layer.

2. The array substrate according to claim 1, wherein: The first insulating layer further has a second through hole exposing another portion of the active layer; The array substrate further includes: a second conductive layer in the second through hole; a second connecting member electrically connected to the second conductive layer; and a gate located on a side of the first insulating layer away from the active layer; The second connecting member and the gate are located in the same layer, and both the first connecting member and the second connecting member are isolated from the gate.

3. The array substrate according to claim 2, wherein: The substrate structure comprises: substrate; a light-shielding layer and a third conductive layer on the base substrate, wherein an orthographic projection of the light-shielding layer on the base substrate at least partially overlaps with an orthographic projection of the active layer on the base substrate, wherein the third conductive layer covers the light-shielding layer, or the light-shielding layer covers the third conductive layer; and A buffer layer is formed between the third conductive layer and the active layer.

4. The array substrate according to claim 3, wherein: An orthographic projection of the first conductive layer on the base substrate at least partially overlaps with an orthographic projection of the light shielding layer on the base substrate.

5. The array substrate according to claim 3, wherein: The second through hole further exposes a portion of the buffer layer; The second conductive layer includes a third portion located on a surface of the active layer and a fourth portion located on a surface of the buffer layer.

6. The array substrate according to claim 3, wherein: The materials of the first conductive layer, the second conductive layer and the third conductive layer all include transparent conductive materials.

7. The array substrate according to claim 3, wherein: The thickness of the third conductive layer is greater than that of the second conductive layer, and the thickness of the second conductive layer is equal to that of the first conductive layer.

8. The array substrate according to claim 1, wherein: The thickness of the first conductive layer is greater than that of the active layer.

9. The array substrate according to claim 2, wherein: An area of ​​an overlapping portion of the first connecting member and the first conductive layer is smaller than an area of ​​an overlapping portion of the second connecting member and the second conductive layer.

10. The array substrate according to claim 3, wherein: The first insulating layer includes a gate insulating layer located below the gate; The active layer includes a first conductive region electrically connected to the first connector, a second conductive region electrically connected to the second connector, and a channel region between the first conductive region and the second conductive region, wherein the channel region is flush with an edge of the gate insulating layer.

11. The array substrate according to claim 10, wherein: A width of an overlapping portion of the first connector and the first conductive layer in a direction from the first connector to the gate is smaller than a distance between an edge of the first conductive layer and the channel region.

12. The array substrate according to claim 1, wherein: An area of ​​the first conductor layer is larger than an area of ​​an overlapping portion of the first connecting member and the first conductive layer.

13. The array substrate according to claim 10, wherein: The area of ​​the first conductor layer is smaller than the area of ​​the channel region.

14. The array substrate according to claim 2, wherein: A width of an overlapping portion of the first conductive layer and the active layer in a direction from the first connecting member to the gate is smaller than a width of an overlapping portion of the second conductive layer and the active layer in a direction from the first connecting member to the gate.

15. The array substrate according to claim 2, wherein: The distance between the first conductive layer and the gate is greater than the width of the overlapping portion of the first connector and the first conductive layer along the direction from the first connector to the gate, and the width of the overlapping portion of the first connector and the first conductive layer along the direction from the first connector to the gate is greater than the width of the second portion of the first conductive layer along the direction from the first connector to the gate.

16. The array substrate according to claim 3, further comprising: a second insulating layer covering the first connecting member, the second connecting member and the gate; a planarization layer on a side of the second insulating layer away from the substrate structure; a first electrode layer and a pixel defining layer on a side of the planarization layer away from the substrate structure, the first electrode layer being electrically connected to the second connecting member, and the pixel defining layer having a first opening exposing at least a portion of the first electrode layer; a light-emitting layer at least located in the first opening; and A second electrode layer is electrically connected to the light emitting layer.

17. The array substrate according to claim 16, wherein: The width of the overlapping part between the orthographic projection of the second conductive layer on the substrate and the orthographic projection of the third conductive layer on the substrate along the direction from the first connecting member to the gate is smaller than the width of the overlapping part between the orthographic projection of the second conductive layer on the substrate and the orthographic projection of the first electrode layer on the substrate along the direction from the first connecting member to the gate.

18. The array substrate according to claim 16, wherein: The width of the overlapping part between the orthographic projection of the second conductive layer on the substrate and the orthographic projection of the third conductive layer on the substrate along the direction from the first connecting member to the gate is smaller than the width of the overlapping part between the orthographic projection of the third conductive layer on the substrate and the orthographic projection of the first electrode layer on the substrate along the direction from the first connecting member to the gate.

19. An array substrate, comprising: Substrate structure; and A thin film transistor on the substrate structure, the thin film transistor comprising: an active layer on the substrate structure; a patterned first insulating layer on a side of the active layer away from the substrate structure, the first insulating layer having a first through hole exposing a portion of the active layer; a first conductive layer in the first through hole and in contact with the active layer; and a first connector, a second connector, and a gate on a side of the first insulating layer away from the substrate structure, wherein the first connector contacts the first conductive layer, the first connector, the second connector, and the gate are on the same layer and isolated from each other, and the gate is located between the first connector and the second connector; The active layer includes: a first conductive region electrically connected to the first connector, a second conductive region electrically connected to the second connector, and a channel region between the first conductive region and the second conductive region, wherein the channel region is below the gate; The first conductive layer includes a first part away from the gate and a second part close to the gate, the first part is completely covered by the first connecting member, the second part is not covered by the first connecting member, and the orthographic projection of the first conductive layer on the substrate structure is located inside the orthographic projection of the active layer on the substrate structure.

20. The array substrate according to claim 19, wherein: A width of the second portion along a direction from the first connector to the gate is smaller than a width of the first portion along the direction from the first connector to the gate.

21. The array substrate according to claim 19, wherein: A width of the second portion along a direction from the first connector to the gate is smaller than a width of the channel region along the direction from the first connector to the gate.

22. The array substrate according to claim 19, wherein: The thickness of the second portion is smaller than the thickness of the first portion.

23. The array substrate according to claim 20, wherein: The width of the first portion is 2 to 5 times the width of the second portion.

24. The array substrate according to claim 20, wherein: The active layer further comprises a semiconductor region, wherein the semiconductor region is located on a side of the first conductive region away from the channel region; The width of the second portion along the direction from the first connector to the gate is smaller than the width of the semiconductor region along the direction from the first connector to the gate.

25. A display device comprising: The array substrate according to any one of claims 1 to 24.

26. A method for manufacturing an array substrate, comprising: forming an active layer on the substrate structure; forming a patterned first insulating layer on a side of the active layer away from the substrate structure, wherein the first insulating layer has a first through hole exposing a portion of the active layer; performing a first conductorization process on the exposed portion of the active layer; forming a first conductive layer in contact with the active layer in the first through hole; forming a connection material layer on a side of the first insulating layer away from the substrate structure by a deposition process; Patterning the connection material layer using a patterned mask layer to form a first connection member, wherein the first connection member contacts the first conductive layer and covers a first portion of the first conductive layer but does not cover a second portion of the first conductive layer; Using the mask layer, etching the first insulating layer through a self-alignment process to enlarge the first through hole, wherein the enlarged first through hole exposes another portion of the active layer; and A second conductorization process is performed on the exposed another portion of the active layer.

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