Display substrate and display panel

Abstract

A display substrate. The display substrate has a display area and a frame area, the frame area at least partially surrounding the display area; the display substrate comprises: a base, which is located in the display area and the frame area; a plurality of pixel circuits, which are located on one side of the base and located in the display area; a plurality of light-emitting elements, which are located on the side of the plurality of pixel circuits that is away from the base and are located in the display area, wherein the plurality of pixel circuits are configured to drive the plurality of light-emitting elements to emit light, and at least one of the plurality of light-emitting elements comprises a first electrode, a light-emitting layer and a second electrode, which are arranged in sequence away from the base; a first signal line, which is located in the frame area and is electrically connected to the second electrode; and a plurality of second signal lines, which are located on one side of the base and are configured to be connected to functional parts, wherein at least some of the plurality of second signal lines are located in the frame area, and the orthographic projections of at least some of the second signal lines on the base overlap with the orthographic projection of the first signal line on the base.

Description

Display substrate and display panel Technical Field

[0001] The embodiments of the present disclosure belong to the field of display technology, and particularly relate to a display substrate and a display panel. Background Art

[0002] In recent years, the development of full-screen displays has been very rapid, which has put forward new requirements for the screen shape. As displays move towards the full-screen era, in order to increase the screen-to-body ratio, narrow-border products are attracting more and more attention.

[0003] Summary of the Invention

[0004] In a first aspect, an embodiment of the present disclosure provides a display substrate, wherein the display substrate has a display area and a frame area, wherein the frame area at least partially surrounds the display area, and the display substrate includes:

[0005] a substrate, located in the display area and the frame area;

[0006] A plurality of pixel circuits are located on one side of the substrate and in the display area;

[0007] a plurality of light-emitting elements, located on a side of the plurality of pixel circuits away from the substrate and located in the display area, the plurality of pixel circuits being configured to drive the plurality of light-emitting elements to emit light, at least one of the plurality of light-emitting elements comprising a first electrode, a light-emitting layer, and a second electrode sequentially disposed away from the substrate;

[0008] a first signal line located in the border area and electrically connected to the second electrode;

[0009] A plurality of second signal lines are located on one side of the substrate and are configured to be connected to the functional component, at least some of the plurality of second signal lines are located in the border area, and the orthographic projection of at least some of the second signal lines on the substrate overlaps with the orthographic projection of the first signal line on the substrate.

[0010] In some embodiments, an orthographic projection of each of the plurality of second signal lines on the substrate overlaps with an orthographic projection of the first signal line on the substrate.

[0011] In some embodiments, an orthographic projection of each of the plurality of second signal lines on the substrate is located within an orthographic projection of the first signal line on the substrate.

[0012] In some embodiments, the first signal line includes at least two conductive layers located in different layers and electrically connected, and the at least two conductive layers include a first conductive layer and a second conductive layer.

[0013] In some embodiments, one of the first conductive layer and the second conductive layer is located in the same layer as the at least portion of the second signal line, and the orthographic projection of the other of the first conductive layer and the second conductive layer on the substrate overlaps with the orthographic projection of the at least portion of the second signal line on the substrate.

[0014] In some embodiments, the second conductive layer is located on a side of the first conductive layer away from the substrate, the first conductive layer and at least part of the second signal line are located on the same layer, and the orthographic projection of the second conductive layer on the substrate overlaps with the orthographic projection of at least part of the second signal line on the substrate.

[0015] In some embodiments, the second conductive layer is located on a side of the first conductive layer away from the substrate, the second conductive layer and at least part of the second signal line are located on the same layer, and the orthographic projection of the first conductive layer on the substrate overlaps with the orthographic projection of at least part of the second signal line on the substrate.

[0016] In some embodiments, the first signal line further includes a third conductive layer located on a side of the first conductive layer and the second conductive layer away from the substrate, and the first conductive layer, the second conductive layer, and the third conductive layer are electrically connected.

[0017] In some embodiments, an orthographic projection of the third conductive layer on the substrate overlaps with an orthographic projection of at least a portion of the second signal line on the substrate.

[0018] In some embodiments, the first signal line further includes a fourth conductive layer located on a side of the first conductive layer and the second conductive layer close to the substrate.

[0019] The fourth conductive layer, the first conductive layer and the second conductive layer are stacked in sequence away from the substrate,

[0020] An orthographic projection of the fourth conductive layer on the substrate overlaps with an orthographic projection of at least a portion of the second signal line on the substrate.

[0021] In some embodiments, the first signal line further includes a fourth conductive layer and a fifth conductive layer located on a side of the first conductive layer and the second conductive layer close to the substrate, and a third conductive layer and a sixth conductive layer located on a side of the first conductive layer and the second conductive layer away from the substrate.

[0022] The fifth conductive layer, the fourth conductive layer, the first conductive layer, the second conductive layer, the third conductive layer and the sixth conductive layer are stacked in sequence away from the substrate,

[0023] The first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer and the sixth conductive layer are electrically connected, the at least part of the second signal line and the fourth conductive layer are located on the same layer, and the orthographic projections of the fifth conductive layer and the sixth conductive layer on the substrate overlap with the orthographic projection of at least part of the second signal line on the substrate.

[0024] In some embodiments, the device further includes a first connecting electrode, a second connecting electrode, and at least one touch electrode layer located on a side of the pixel circuit away from the substrate, and a shielding layer located on a side of the pixel circuit close to the substrate.

[0025] The pixel circuit includes at least one thin film transistor, wherein the thin film transistor includes an active layer located on one side of the substrate, a gate located on a side of the active layer away from the substrate, and a source and a drain located on a side of the gate away from the substrate;

[0026] The orthographic projection of the shielding layer on the substrate overlaps with the orthographic projection of the active layer on the substrate;

[0027] The first connecting electrode is located on a side of the thin film transistor away from the substrate and is electrically connected to the thin film transistor;

[0028] The second connecting electrode is located on a side of the first connecting electrode away from the substrate and is electrically connected to the first connecting electrode;

[0029] The light emitting element is located on a side of the second connecting electrode away from the substrate and is electrically connected to the second connecting electrode;

[0030] The at least one touch electrode layer is located on a side of the light emitting element away from the substrate;

[0031] The first conductive layer and the first connecting electrode are located in the same layer;

[0032] The second conductive layer and the second connecting electrode are located in the same layer;

[0033] The third conductive layer and the first electrode are located in the same layer;

[0034] The fourth conductive layer is located on the same layer as the source electrode and the drain electrode;

[0035] The fifth conductive layer and the shielding layer are located on the same layer;

[0036] The sixth conductive layer is located on the same layer as any one of the at least one touch electrode layer.

[0037] In some embodiments, the frame area includes a first side frame area, a second side frame area, a third side frame area, and a fourth side frame area sequentially arranged around the display area, and the functional component is located in the display area, and the functional component is arranged close to the first side frame area.

[0038] The functional component is connected to the plurality of second signal lines respectively through a plurality of signal lead-out lines, and the signal lead-out lines extend from the position of the functional component to the first side frame area and are connected to the plurality of second signal lines located in the first side frame area;

[0039] The display substrate further includes a signal input pad, and the signal input pad is located in the third side frame area.

[0040] The plurality of second signal lines extend from the first side frame area through the second side frame area to the third side frame area and are connected to the signal input pad.

[0041] In some embodiments, the first signal line is located at least in the first side frame area, the second side frame area and the fourth side frame area, and the orthographic projection of at least part of the second signal line on the substrate overlaps with the orthographic projection of the first signal line located in the second side frame area on the substrate.

[0042] In a second aspect, an embodiment of the present disclosure provides a display substrate, wherein the display substrate has a display area and a frame area, wherein the frame area at least partially surrounds the display area.

[0043] The display substrate includes a base, a plurality of pixel units, a functional component, a first signal line and a second signal line;

[0044] The pixel unit, the functional component, the first signal line and the second signal line are respectively located on one side of the substrate;

[0045] The pixel unit includes a pixel circuit and a light-emitting element, wherein the light-emitting element is located on a side of the pixel circuit away from the substrate, and the pixel circuit is electrically connected to the light-emitting element;

[0046] The pixel unit and the functional component are located in the display area, and the pixel unit at least partially surrounds the functional component;

[0047] The first signal line and the second signal line are located in the border area;

[0048] The first signal line is electrically connected to the pixel unit, and the second signal line is electrically connected to the functional component;

[0049] The first signal line includes at least two conductive layers, the at least two conductive layers are located in different layers, an insulating layer is provided between any two adjacent conductive layers, and any two adjacent conductive layers are connected via a via hole provided in the insulating layer;

[0050] The second signal line is disposed in the same layer as one of the at least two conductive layers, and an orthographic projection of the second signal line on the substrate overlaps with an orthographic projection of at least one of the at least two conductive layers on the substrate.

[0051] In some embodiments, the first signal line includes at least three conductive layers, two adjacent layers of the at least three conductive layers form a group, and the at least three conductive layers include at least two groups.

[0052] An orthographic projection of the second signal line on the substrate overlaps with an orthographic projection of the connecting vias between at least one of the at least two groups of adjacent two conductive layers on the substrate.

[0053] In some embodiments, at least two of the at least three conductive layers are located on a side of the second signal line facing away from the substrate, and any two adjacent conductive layers of the at least two conductive layers are connected via a first via hole provided in the insulating layer;

[0054] The orthographic projection of the second signal line on the substrate is located within the orthographic projection area of ​​the first via hole on the substrate.

[0055] In some embodiments, the conductive layer on the same layer as the second signal line and the conductive layer adjacent to the second signal line and located on a side of the second signal line facing away from the substrate are connected through a second via hole provided in the insulating layer.

[0056] The orthographic projection of the second via hole on the substrate is located within the orthographic projection area of ​​the first via hole on the substrate.

[0057] In some embodiments, at least one of the at least three conductive layers is located on a side of the second signal line close to the substrate.

[0058] The conductive layer on the same layer as the second signal line and the conductive layer located on a side of the second signal line close to the substrate and adjacent to the second signal line are connected via a third via hole provided in the insulating layer.

[0059] The orthographic projection of the third via hole on the substrate is located within the orthographic projection area of ​​the first via hole on the substrate.

[0060] In some embodiments, there are multiple second signal lines, and the multiple second signal lines are distributed at intervals;

[0061] The total distribution width of the orthographic projections of the plurality of second signal lines on the substrate is greater than the orthographic projection width of the second via hole on the substrate.

[0062] The total distribution width of the orthographic projections of the plurality of second signal lines on the substrate is greater than the orthographic projection width of the third via hole on the substrate.

[0063] In some embodiments, at least two of the at least three conductive layers are located on a side of the second signal line close to the substrate, and any adjacent two of the at least two conductive layers are connected via a fourth via hole provided in the insulating layer;

[0064] An orthographic projection of the second signal line on the substrate overlaps with an orthographic projection of the fourth via hole on the substrate.

[0065] In some embodiments, at least one of the at least three conductive layers is located on a side of the second signal line facing away from the substrate.

[0066] The orthographic projection of the fourth via and the second signal line on the substrate is located within an orthographic projection region of the conductive layer on the substrate at a side of the second signal line facing away from the substrate.

[0067] In some embodiments, the conductive layer on the same layer as the second signal line and the conductive layer located on a side of the second signal line close to the substrate and adjacent to the second signal line are connected through a fifth via hole provided in the insulating layer;

[0068] The conductive layer on the same layer as the second signal line and the conductive layer located on a side of the second signal line away from the substrate and adjacent to the second signal line are connected via a sixth via hole provided in the insulating layer;

[0069] The orthographic projections of the fifth via hole and the sixth via hole on the substrate coincide with each other.

[0070] In some embodiments, there are multiple second signal lines, and the multiple second signal lines are distributed at intervals;

[0071] The total distribution width of the orthographic projections of the plurality of second signal lines on the substrate is greater than the orthographic projection width of the fifth via hole on the substrate.

[0072] In some embodiments, an orthographic projection of the second signal line on the substrate does not overlap with an orthographic projection of a connecting via between any two adjacent conductive layers among the at least three conductive layers on the substrate.

[0073] In some embodiments, there are multiple second signal lines, and the multiple second signal lines are distributed at intervals;

[0074] The total distribution width of the orthographic projections of the plurality of second signal lines on the substrate is greater than the orthographic projection width of the connecting via between any two adjacent conductive layers in the at least three conductive layers on the substrate.

[0075] In some embodiments, at least one of the at least three conductive layers is located on a side of the second signal line facing away from the substrate, and at least one of the at least three conductive layers is located on a side of the second signal line close to the substrate.

[0076] In a third aspect, an embodiment of the present disclosure further provides a display panel, which includes the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing the detailed exemplary embodiments with reference to the accompanying drawings, in which:

[0078] FIG. 1 a is a schematic top view of a display screen in the related art.

[0079] FIG1b is an enlarged schematic top view of portion P in FIG1a.

[0080] FIG1c is a schematic cross-sectional view of the structure along the AA′ section line in FIG1b.

[0081] FIG2 a is a schematic top view of a display substrate provided by an embodiment of the present disclosure.

[0082] FIG2 b is an enlarged schematic top view of portion B in FIG2 a .

[0083] FIG2c is a schematic cross-sectional view of the structure along the CC′ section line in FIG2a.

[0084] FIG2 d is another schematic top view of a display substrate provided in an embodiment of the present disclosure.

[0085] FIG. 3 a is a schematic cross-sectional view of a structure of a substrate along the DD′ section line in FIG. 2 d according to an embodiment of the present disclosure.

[0086] FIG. 3 b is a schematic cross-sectional view of another structure of the substrate along the DD′ section line in FIG. 2 d according to an embodiment of the present disclosure.

[0087] FIG. 3 c is a schematic cross-sectional view of another structure of the substrate along the DD′ section line in FIG. 2 d according to an embodiment of the present disclosure.

[0088] FIG. 3 d is a schematic cross-sectional view of another structure of the substrate along the DD′ section line in FIG. 2 d in an embodiment of the present disclosure.

[0089] FIG. 3 e is a schematic cross-sectional view of another structure of the substrate along the DD′ section line in FIG. 2 d according to an embodiment of the present disclosure.

[0090] FIG. 3 f is a schematic cross-sectional view of another structure of the substrate along the DD′ section line in FIG. 2 d in an embodiment of the present disclosure.

[0091] FIG. 3 g is a schematic cross-sectional view of another structure of the substrate along the DD′ section line in FIG. 2 d according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0092] In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, a display substrate and a display panel provided by the embodiments of the present disclosure are further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0093] The embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings, but the illustrated embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully enable those skilled in the art to understand the scope of this disclosure.

[0094] The embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings are schematic in nature, and the shapes of the regions shown in the drawings illustrate specific shapes of the regions, but are not intended to be limiting.

[0095] At present, the borders of display screens are gradually getting smaller, and major manufacturers have to integrate various functional components such as antennas, NFC, and photoelectric sensors into the screen. Since these functional components need to lead out signal lines in the border area of ​​the display screen, the width of the border area of ​​the display screen will increase.

[0096] Referring to Figure 1a, there is a top view schematic diagram of a display screen in the related art. A camera placement hole 21 is provided in the display area 101 of the display screen. Figure 1b is an enlarged top view schematic diagram of the P portion in Figure 1a. As shown in Figure 1b, a circular photoelectric sensor 22 is accommodated in the frame of the camera placement hole 21. The photoelectric sensor 22 can be used to control the display brightness of the display screen or to control the display screen to be turned off when making or receiving a call. The photoelectric sensor 22 uses a photosensitive diode. The photosensitive surface of the photosensitive diode is divided into multiple areas. The multiple areas are respectively covered with color resists of different colors. The areas covered by the different color resists are used to sense light signals of different colors. The photoelectric sensor 22 generally has five groups of output signals in white, red, green, blue and black, and one group of input signals, for a total of six groups of signals. Each group of signals is transmitted through a signal line, requiring a total of six signal lines. The six signal lines 23 of the photoelectric sensor 22 need to be led out from the border area of ​​the display screen, and finally led to the binding end 24 of the peripheral circuit board located in the lower border area of ​​the display screen and bound and connected to the binding end 24. The peripheral circuit board provides it with a voltage signal through the input signal lines among the six signal lines 23, and receives its output voltage signal through five output signal lines among the six signal lines.

[0097] To meet the resistance requirements of the signal lines 23 , we require that the width of each signal line 23 is no less than 10 μm, the gap between two adjacent signal lines 23 is 5 μm, and the six signal lines 23 need to occupy a total of 90 μm of the border area width.

[0098] Referring to Figure 1c, which is a schematic cross-sectional view of the structure along the AA' section line in Figure 1b, in the related art, the six signal lines 23 are designed on the outside of the power line (VSS) 25 in the border area of ​​the display screen, away from the display area 101, and are located on the outside of the boundary of the packaging layer 14, away from the display area 101. The six signal lines 23 are arranged on the same layer as the source 203 and the drain 204 of the transistor in the gate drive circuit 17 located in the border area 102. Therefore, the width of the border area 102 of the display screen will increase by 90μm on the basis of the original border area width, which is not conducive to achieving a narrow border of the display screen.

[0099] In order to solve the above-mentioned problems existing in the disclosed technology, on the first aspect, an embodiment of the present disclosure provides a display substrate, referring to Figures 2a, 2b, 2c and 2d, Figure 2a is a schematic top view of a display substrate provided by an embodiment of the present disclosure; Figure 2b is an enlarged schematic top view of part B in Figure 2a; Figure 2c is a schematic cross-sectional view of the structure along the CC' section line in Figure 2a; Figure 2d is another schematic top view of a display substrate provided by an embodiment of the present disclosure; wherein the display substrate has a display area 101 and a frame area 102, and the frame area 102 at least partially surrounds the display area 101, and the display substrate includes: a substrate 1, located in the display area 101 and the frame area 102; a plurality of pixel circuits 2, located on one side of the substrate 1, and Located in the display area 101; multiple light-emitting elements 3, located on a side of the multiple pixel circuits 2 away from the substrate 1 and located in the display area 101, the multiple pixel circuits 2 are configured to drive the multiple light-emitting elements 3 to emit light, and at least one light-emitting element 3 among the multiple light-emitting elements 3 includes a first electrode 31, a light-emitting layer 32, and a second electrode 33 arranged in sequence away from the substrate 1; a first signal line 4, located in the border area 102, and electrically connected to the second electrode 33; multiple second signal lines 5, located on one side of the substrate 1, are configured to be connected to the functional part 6, at least some of the multiple second signal lines 5 are located in the border area 102, and the orthographic projection of at least some of the second signal lines 5 on the substrate 1 overlaps with the orthographic projection of the first signal line 4 on the substrate 1.

[0100] The orthographic projection of at least a portion of the second signal line 5 on the substrate 1 may partially overlap or completely overlap with the orthographic projection of the first signal line 4 on the substrate 1 .

[0101] In some embodiments, referring to FIG. 2 d , the second electrode 33 extends from the display area 101 to the frame area 102 , and the second electrode 33 partially overlaps with an orthographic projection of the first signal line 4 on the substrate 1 .

[0102] In this embodiment, by making the orthographic projection of at least part of the second signal line 5 on the substrate 1 overlap with the orthographic projection of the first signal line 4 on the substrate 1, compared with the arrangement design scheme of the signal lines in the border area in the related technical Figure 1c, the occupied width of at least part of the second signal line 5 in the border area 102 can be achieved by occupying part of the width of the first signal line 4, thereby reducing the additional occupied width of at least part of the second signal line 5 in the border area 102 or at least part of the second signal line 5 in the border area 102 no longer occupies the additional border width, thereby achieving the effect of reducing the width of the border area 102, which is beneficial for the display substrate to achieve a narrow border or an extremely narrow border.

[0103] In some embodiments, the first signal line 4 is a power line, such as a signal line with a signal voltage of VSS, a signal line with a signal voltage of VGH, or a signal line with a signal voltage of VGL. In some embodiments, the first signal line 4 can also be other signal lines, such as a signal line with a signal voltage of Vinit for resetting the first electrode 31 of the light-emitting element 3 in the pixel circuit 2. First signal lines 4 distributed in the border area 102, and with a portion of the line width space occupied by the second signal line 5, are all within the protection scope of this solution.

[0104] In some embodiments, the functional component 6 may be any functional component that requires a signal line to be drawn out within the border area 102 , such as a photoelectric sensor, an antenna, or NFC.

[0105] In some embodiments, the orthographic projection of each second signal line 5 among the plurality of second signal lines 5 on the substrate 1 overlaps with the orthographic projection of the first signal line 4 on the substrate 1. The orthographic projection of each second signal line 5 on the substrate 1 may partially overlap with the orthographic projection of the first signal line 4 on the substrate 1, or may completely overlap. That is, only a portion of the width of each second signal line 5 may occupy the width space of the first signal line 4, or the entire width of each second signal line 5 may occupy the width space of the first signal line 4.

[0106] In some embodiments, the orthographic projection of each of the plurality of second signal lines 5 on the substrate 1 is located within the orthographic projection of the first signal line 4 on the substrate 1. That is, the entire width of each second signal line 5 occupies the width space of the first signal line 4; for the plurality of second signal lines 5 arranged in parallel, the width of the gap between any two adjacent second signal lines 5 also occupies the width space of the first signal line 4, thereby greatly reducing the width space occupied by the plurality of second signal lines 5 in the border area 102.

[0107] In some embodiments, referring to Figures 3a, 3b, 3c, 3d, 3e, 3f, and 3g, Figure 3a is a schematic cross-sectional view of a structure of the substrate along the DD' section line in Figure 2d in an embodiment of the present disclosure; Figure 3b is another schematic cross-sectional view of a structure of the substrate along the DD' section line in Figure 2d in an embodiment of the present disclosure; Figure 3c is yet another schematic cross-sectional view of a structure of the substrate along the DD' section line in Figure 2d in an embodiment of the present disclosure; Figure 3d is another schematic cross-sectional view of a structure of the substrate along the DD' section line in Figure 2d in an embodiment of the present disclosure. Another structural cross-sectional schematic diagram; Figure 3e is another structural cross-sectional schematic diagram showing the substrate along the DD' section line in Figure 2d in an embodiment of the present disclosure; Figure 3f is another structural cross-sectional schematic diagram showing the substrate along the DD' section line in Figure 2d in an embodiment of the present disclosure; Figure 3g is another structural cross-sectional schematic diagram showing the substrate along the DD' section line in Figure 2d in an embodiment of the present disclosure; wherein, the first signal line 4 includes at least two conductive layers located in different layers and electrically connected, and the at least two conductive layers include a first conductive layer 41 and a second conductive layer 42.

[0108] Among them, by setting the first signal line 4 to at least two conductive layers located in different layers and electrically connected, the resistance of the first signal line 4 can be reduced, thereby reducing the display power consumption of the display substrate, and at the same time making the display picture of the display substrate more uniform, thereby improving the display effect of the display substrate.

[0109] In some embodiments, referring to Figure 3a, the second electrode 33 is electrically connected to the third conductive layer 43; referring to Figure 3b, the second electrode 33 is electrically connected to the third conductive layer 43; referring to Figure 3c, the second electrode 33 is electrically connected to the third conductive layer 43; referring to Figure 3d, the second electrode 33 is electrically connected to the third conductive layer 43; referring to Figure 3e, the second electrode 33 is electrically connected to the third conductive layer 43; referring to Figure 3f, the second electrode 33 is electrically connected to the third conductive layer 43; referring to Figure 3g, the second electrode 33 is electrically connected to the third conductive layer 43.

[0110] In some embodiments, referring to Figures 3b, 3c, 3d, 3e, 3f and 3g, one of the first conductive layer 41 and the second conductive layer 42 is located on the same layer as at least a portion of the second signal line 5, and the orthographic projection of the other of the first conductive layer 41 and the second conductive layer 42 on the substrate 1 overlaps with the orthographic projection of at least a portion of the second signal line 5 on the substrate 1.

[0111] In some embodiments, referring to Figures 3b and 3c, the second conductive layer 42 is located on the side of the first conductive layer 41 away from the substrate 1, the first conductive layer 41 and at least part of the second signal line 5 are located on the same layer, and the orthographic projection of the second conductive layer 42 on the substrate 1 overlaps with the orthographic projection of at least part of the second signal line 5 on the substrate 1.

[0112] The second conductive layer 42 can shield at least a portion of the second signal line 5, ensuring that at least a portion of the second signal line 5 is not interfered with by signals from other signal lines located on the side of the second signal line 5 facing away from the substrate 1. The first conductive layer 41 and at least a portion of the second signal line 5 are located on the same layer, which means that the first conductive layer 41 and at least a portion of the second signal line 5 are formed simultaneously using a single patterning process. The first conductive layer 41 and at least a portion of the second signal line 5 are not necessarily located on the same plane in structure.

[0113] In some embodiments, referring to Figures 3d, 3e, 3f and 3g, the second conductive layer 42 is located on the side of the first conductive layer 41 away from the substrate 1, the second conductive layer 42 and at least part of the second signal line 5 are located on the same layer, and the orthographic projection of the first conductive layer 41 on the substrate 1 overlaps with the orthographic projection of at least part of the second signal line 5 on the substrate 1.

[0114] The first conductive layer 41 can shield at least a portion of the second signal line 5, ensuring that at least a portion of the second signal line 5 is not interfered with by signals from other signal lines located on the side of the second signal line 5 closer to the substrate 1. The second conductive layer 42 and at least a portion of the second signal line 5 are located on the same layer, meaning that the second conductive layer 42 and at least a portion of the second signal line 5 are formed simultaneously using a single patterning process. The second conductive layer 42 and at least a portion of the second signal line 5 are not necessarily located on the same plane in structure.

[0115] In some embodiments, referring to Figures 3a, 3b, 3c, 3d, 3e, 3f and 3g, the first signal line 4 also includes a third conductive layer 43 located on a side of the first conductive layer 41 and the second conductive layer 42 away from the substrate 1, and the first conductive layer 41, the second conductive layer 42 and the third conductive layer 43 are electrically connected.

[0116] 3 b , 3 c , 3 d , 3 e , and 3 f , an orthographic projection of the third conductive layer 43 on the substrate 1 overlaps with an orthographic projection of at least a portion of the second signal line 5 on the substrate 1 in some embodiments.

[0117] The third conductive layer 43 can shield at least a portion of the second signal lines 5 , ensuring that at least a portion of the second signal lines 5 are not interfered with by signals on other signal lines on the side of the second signal lines facing away from the substrate 1 .

[0118] In some embodiments, referring to FIG. 3 g , an orthographic projection of the third conductive layer 43 on the substrate 1 does not overlap with an orthographic projection of at least a portion of the second signal line 5 on the substrate 1 .

[0119] In some embodiments, referring to Figures 3b, 3d, 3e and 3g, the first signal line 4 further includes a fourth conductive layer 44 located on the side of the first conductive layer 41 and the second conductive layer 42 close to the substrate 1. The fourth conductive layer 44, the first conductive layer 41 and the second conductive layer 42 are stacked in sequence away from the substrate 1, and the orthographic projection of the fourth conductive layer 44 on the substrate 1 overlaps with the orthographic projection of at least part of the second signal line 5 on the substrate 1.

[0120] The fourth conductive layer 44 can shield at least a portion of the second signal line 5 , thereby ensuring that at least a portion of the second signal line 5 is not interfered with by signals on other signal lines located on the side of the second signal line close to the substrate 1 .

[0121] In some embodiments, referring to Figure 3a, the first signal line 4 also includes a fourth conductive layer 44 and a fifth conductive layer 45 located on the side of the first conductive layer 41 and the second conductive layer 42 close to the substrate 1, and a third conductive layer 43 and a sixth conductive layer 46 located on the side of the first conductive layer 41 and the second conductive layer 42 away from the substrate 1. The fifth conductive layer 45, the fourth conductive layer 44, the first conductive layer 41, the second conductive layer 42, the third conductive layer 43 and the sixth conductive layer 46 are stacked in sequence away from the substrate 1, the first conductive layer 41, the second conductive layer 42, the third conductive layer 43, the fourth conductive layer 44, the fifth conductive layer 45 and the sixth conductive layer 46 are electrically connected, at least part of the second signal line 5 and the fourth conductive layer 44 are located on the same layer, and the orthographic projections of the fifth conductive layer 45 and the sixth conductive layer 46 on the substrate 1 overlap with the orthographic projection of at least part of the second signal line 5 on the substrate 1.

[0122] Among them, the fifth conductive layer 45 and the sixth conductive layer 46 can play a signal shielding role for at least part of the second signal line 5, ensuring that at least part of the second signal line 5 is not interfered with by the signals on other signal lines located on the side close to the substrate 1 and the signals on other signal lines located on the side far from the substrate 1.

[0123] In some embodiments, the fourth conductive layer 44 and at least part of the second signal line 5 are located in the same layer, which means that the fourth conductive layer 44 and at least part of the second signal line 5 are formed simultaneously using one patterning process, and the fourth conductive layer 44 and at least part of the second signal line 5 are not necessarily located in the same plane in structure.

[0124] In some embodiments, referring to FIG3a and FIG2c, the display substrate further comprises a first connection electrode 7, a second connection electrode 8, and at least one touch electrode layer 9 located on a side of the pixel circuit 2 away from the substrate 1, and a shielding layer 10 located on a side of the pixel circuit 2 close to the substrate 1. The pixel circuit 2 comprises at least one thin film transistor 20, and the thin film transistor 20 comprises an active layer 201 located on one side of the substrate 1, a gate 202 located on a side of the active layer 201 away from the substrate 1, and a source 203 and a drain 204 located on a side of the gate 202 away from the substrate 1; the orthographic projection of the shielding layer 10 on the substrate 1 overlaps with the orthographic projection of the active layer 201 on the substrate 1; the first connection electrode 7 is located on a side of the thin film transistor 20 away from the substrate 1 and overlaps with the thin film transistor 20. The body tube 20 is electrically connected; the second connecting electrode 8 is located on the side of the first connecting electrode 7 away from the substrate 1, and is electrically connected to the first connecting electrode 7; the light-emitting element 3 is located on the side of the second connecting electrode 8 away from the substrate 1, and is electrically connected to the second connecting electrode 8; at least one touch electrode layer 9 is located on the side of the light-emitting element 3 away from the substrate 1; the first conductive layer 41 and the first connecting electrode 7 are located on the same layer; the second conductive layer 42 and the second connecting electrode 8 are located on the same layer; the third conductive layer 43 and the first electrode 31 are located on the same layer; the fourth conductive layer 44 and the source 203 and the drain 204 are located on the same layer; the fifth conductive layer 45 and the shielding layer 10 are located on the same layer; the sixth conductive layer 46 and any one of the at least one touch electrode layer 9 are located on the same layer.

[0125] In some embodiments, the shielding layer 10 may be made of metal material.

[0126] In some embodiments, two conductive film layers located in the same layer refer to two conductive film layer patterns formed simultaneously using one patterning process, and the two conductive film layer patterns are not necessarily located in the same plane in structure.

[0127] In some embodiments, the orthographic projection of the shielding layer 10 on the substrate 1 overlaps with the orthographic projection of the active layer 201 on the substrate 1, which can stabilize the output capacity of the thin film transistor 20, adjust the device characteristics, suppress the floating effect of the thin film transistor 20, suppress the short channel effect of the thin film transistor 20, and improve the thermal effect of the thin film transistor 20.

[0128] 3a and 2c, an insulating layer 11 is provided between any two adjacent conductive layers. The insulating layer 11 may be an inorganic insulating layer, such as silicon nitride, silicon oxide, or silicon oxynitride, or an organic insulating layer, such as polyimide, polyurethane, or the like.

[0129] In some embodiments, referring to Figures 3a to 3g and Figure 2c, a pixel defining layer 12 and a spacer layer 13 are further provided on the side of the first electrode 31 facing away from the substrate 1. Openings are provided in the pixel defining layer 12 and the spacer layer 13, and at least a portion of the light-emitting layer 32 and at least a portion of the second electrode 33 are located in the openings. The display substrate also includes an encapsulation layer 14, which is located on the side of the light-emitting element 3 facing away from the substrate 1 and is used to encapsulate the light-emitting element. The encapsulation layer 14 includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked in sequence. A buffer layer 15 is provided on the side of the encapsulation layer 14 facing away from the substrate 1, and at least one touch electrode layer 9 is located on the side of the buffer layer 15 facing away from the substrate 1. A protective layer 16 is also provided on the side of the touch electrode layer 9 facing away from the substrate 1 to protect the touch electrode layer 9.

[0130] In some embodiments, referring to Figures 2b, 3a, 3b, 3c, 3d, 3e and 3g, the display substrate further includes a gate drive circuit (GOA circuit) 17, which is located in the border area 102, and the gate drive circuit 17 partially overlaps with the orthographic projection of the first signal line 4 on the substrate 1.

[0131] In some embodiments, the GOA circuit may be an EM GOA circuit (luminescence control GOA circuit) or a Gate GOA circuit (gate drive GOA circuit). In each drawing, only one transistor is used to represent the GOA circuit, and the entire GOA circuit is not shown.

[0132] In some embodiments, referring to FIG. 3 f , the orthographic projection of the first signal line 4 on the substrate 1 is located within the orthographic projection region of the gate driving circuit 17 on the substrate 1 .

[0133] In some embodiments, referring to Figure 2b and Figure 3a-3g, the gate driving circuit 17 includes at least one thin film transistor 20, and the film layers of the thin film transistor 20 in the gate driving circuit 17 (such as the active layer 201, the gate 202, the source 203 and the drain 204) and the same film layers of the thin film transistor 20 in the pixel circuit 2 (such as the active layer 201, the gate 202, the source 203 and the drain 204) are simultaneously prepared through a single preparation process.

[0134] In some embodiments, referring to Figure 2a, the border area 102 includes a first side border area 102a, a second side border area 102b, a third side border area 102c and a fourth side border area 102d which are sequentially arranged around the display area 101, the functional part 6 is located in the display area 101, and the functional part 6 is arranged close to the first side border area 102a, the functional part 6 is respectively connected to the plurality of second signal lines 5 through a plurality of signal lead lines 18, the signal lead lines 18 extend from the position of the functional part 6 to the first side border area 102a, and are connected to the plurality of second signal lines 5 located in the first side border area 102a; the display substrate also includes a signal input pad 19, the signal input pad 19 is located in the third side border area 102c, and the plurality of second signal lines 5 extend from the first side border area 102a through the second side border area 102b to the third side border area 102c, and are connected to the signal input pad 19. Referring to Figure 2d, the display substrate also includes a binding connection pad 26, which is located in the third side frame area 102c. The first signal line 4 extends to the third side frame area 102c and is connected to the binding connection pad 26. The binding connection pad 26 is used to bind and connect to a peripheral circuit board (FPC) so that the peripheral circuit board provides a signal (such as a VSS signal) to the first signal line 4.

[0135] In some embodiments, multiple signal lead lines 18 and signal input pads 19 can be prepared with any conductive film layer in the pixel circuit 2 through a single preparation process, so that the preparation of the signal lead lines 18 and signal input pads 19 does not require additional preparation process steps for the display substrate.

[0136] In some embodiments, referring to FIG. 2 a , the first signal line 4 is located at least in the first side frame region 102 a, the second side frame region 102 b, and the fourth side frame region 102 d. At least a portion of the orthographic projection of the second signal line 5 on the substrate 1 overlaps with the orthographic projection of the first signal line 4 located in the second side frame region 102 b on the substrate 1. This reduces the width of the space occupied by the second signal line 5 in the second side frame region 102 b, thereby reducing the width of the second side frame region 102 b.

[0137] In some embodiments, functional component 6 is a photosensor housed within the frame of camera aperture 21 defined in display area 101. The photosensor can be used to control the display brightness or to turn off the display when making or receiving a call. The photosensor comprises at least two conductive film layers, which can be fabricated together with any of the conductive film layers in pixel circuit 2 through a single fabrication process. This eliminates the need for additional steps in the display substrate fabrication process to fabricate the photosensor.

[0138] In some embodiments, the functional component 6 may also be an antenna distributed in the display area 101 or an NFC device integrated in the display area 101. The setting position of the antenna or NFC device in the display area 101 may be any position and is not limited here.

[0139] In a second aspect, the embodiment of the present disclosure further provides a display substrate, referring to Figures 2a, 2b, and 2c, wherein the display substrate has a display area 101 and a frame area 102, the frame area 102 at least partially surrounding the display area 101, the display substrate includes a substrate 1, a plurality of pixel units, a functional component 6, a first signal line 4, and a second signal line 5; the pixel unit includes a pixel circuit 2 and a light-emitting element 3, the light-emitting element 3 is located on the side of the pixel circuit 2 away from the substrate 1, and the pixel circuit 2 is electrically connected to the light-emitting element 3; the pixel unit, the functional component 6, the first signal line 4, and the second signal line 5 are respectively located on one side of the substrate 1; the pixel unit and the functional component 6 are located in the display area 101, and the pixel unit is at least Partially surrounds the functional part 6; the first signal line 4 and the second signal line 5 are located in the border area 102; the first signal line 4 is electrically connected to the second electrode of the light-emitting element in the pixel unit, such as the cathode, and the second signal line 5 is electrically connected to the functional part 6; the first signal line 4 includes at least two conductive layers, the at least two conductive layers are located in different layers and an insulating layer 11 is provided between any two adjacent ones, and any two adjacent ones of the at least two conductive layers are connected by a via provided in the insulating layer 11; the second signal line 5 is provided in the same layer as one of the at least two conductive layers, and the orthographic projection of the second signal line 5 on the substrate 1 overlaps with the orthographic projection of at least one of the at least two conductive layers on the substrate 1.

[0140] The orthographic projection of the second signal line 5 on the substrate 1 and the orthographic projection of at least one of the at least two conductive layers on the substrate 1 may partially overlap or completely overlap.

[0141] In this embodiment, by making the orthographic projection of the second signal line 5 on the substrate 1 overlap with the orthographic projection of at least one of the at least two conductive layers on the substrate 1, compared with the arrangement design scheme of the signal line in the border area in the related technology Figure 1c, the occupied width of at least part of the second signal line 5 in the border area 102 can be achieved by occupying part of the width of the first signal line 4, thereby reducing the additional occupied width of at least part of the second signal line 5 in the border area 102 or at least part of the second signal line 5 in the border area 102 no longer occupies the additional border width, thereby achieving the effect of reducing the width of the border area 102, which is beneficial for the display substrate to achieve a narrow border or an extremely narrow border.

[0142] In some embodiments, referring to Figures 3b, 3c, 3d and 3e, the first signal line 4 includes at least three conductive layers, two adjacent layers of the at least three conductive layers form a group, the at least three conductive layers include at least two groups, and the orthographic projection of the second signal line 5 on the substrate 1 overlaps with the orthographic projection of the connecting via between at least one adjacent two conductive layers in the at least two groups on the substrate 1.

[0143] In some embodiments, referring to Figures 3b and 3c, at least two of the at least three conductive layers are located on the side of the second signal line 5 facing away from the substrate 1, and any two adjacent ones of the at least two conductive layers are connected by a first via 110 provided in the insulating layer 11; the orthographic projection of the second signal line 5 on the substrate 1 is located within the orthographic projection area of ​​the first via 110 on the substrate 1.

[0144] 3 b and 3 c , the conductive layer located on the side of the second signal line 5 away from the substrate 1 can shield the second signal line 5 , ensuring that the second signal line 5 is not interfered with by signals on other signal lines located on its side away from the substrate 1 .

[0145] In some embodiments, referring to Figures 3b and 3c, the conductive layer on the same layer as the second signal line 5 and the conductive layer adjacent to the second signal line 5 and located on the side of the second signal line 5 facing away from the substrate 1 are connected through a second via 111 opened in the insulating layer 11, and the orthographic projection of the second via 111 on the substrate 1 is located in the orthographic projection area of ​​the first via 110 on the substrate 1.

[0146] 3b and 3c , the second signal line 5 occupies part of the width of the connection via between the conductive layer where the second signal line 5 is located and the conductive layer adjacent to the second signal line 5 in the first signal line 4. This means that the width of the connection via between the conductive layer where the second signal line 5 is located and the conductive layer adjacent to the conductive layer where the second signal line 5 is located in the first signal line 4 is reduced. The width of the connection via is the dimension of the connection via along the width direction of the second signal line 5 or the dimension of the connection via along the arrangement direction of the multiple second signal lines 5.

[0147] In some embodiments, referring to Figures 3b and 3c , the first signal line 4 includes a first conductive layer 41, a second conductive layer 42, and a third conductive layer 43. The first conductive layer 41, the second conductive layer 42, and the third conductive layer 43 are stacked in order away from the substrate 1. The second signal line 5 is located on the same layer as the first conductive layer 41. The orthographic projection of the second signal line 5 on the substrate 1 is located within the orthographic projection of the first via 110 connecting the second conductive layer 42 and the third conductive layer 43. The orthographic projection of the second via 111 connecting the first conductive layer 41 and the second conductive layer 42 is located within the orthographic projection of the first via 110 on the substrate 1. The second signal line 5 occupies part of the width of the second via 111, thereby reducing the width of the second via 111. Referring to Figures 3b and 3c , the width of the second via 111 and the first via 110 are both m1. In this embodiment, the second signal line 5 occupies part of the width n1 of the second via 111, reducing the width of the second via 111 to (m1-n1).

[0148] In some embodiments, referring to Figure 3b, at least one of the at least three conductive layers is located on the side of the second signal line 5 close to the substrate 1, and the conductive layer on the same layer as the second signal line 5 and the conductive layer located on the side of the second signal line 5 close to the substrate 1 and adjacent to the second signal line 5 are connected through a third via 112 opened in the insulating layer 11, and the orthographic projection of the third via 112 on the substrate 1 is located in the orthographic projection area of ​​the first via 110 on the substrate 1.

[0149] In some embodiments, referring to Figure 3b, the first signal line 4 also includes a fourth conductive layer 44, the second signal line 5 is on the same layer as the first conductive layer 41, the fourth conductive layer 44 is located on the side of the second signal line 5 close to the substrate 1 and is adjacent to the first conductive layer 41, the first conductive layer 41 and the fourth conductive layer 44 are connected through a third via 112, and the orthographic projection of the third via 112 on the substrate 1 is located within the orthographic projection area of ​​the first via 110 on the substrate 1.

[0150] In some embodiments, referring to Figures 3b and 3c, there are multiple second signal lines 5, and the multiple second signal lines 5 are distributed at intervals; the total distribution width s of the orthographic projections of the multiple second signal lines 5 on the substrate 1 is greater than the orthographic projection width (m1-n1) of the second via 111 on the substrate 1, and the total distribution width s of the orthographic projections of the multiple second signal lines 5 on the substrate 1 is greater than the orthographic projection width m2 of the third via 112 on the substrate 1.

[0151] The total distribution width of the orthographic projections of the plurality of second signal lines 5 on the substrate 1 refers to the sum of the orthographic projection widths of the plurality of second signal lines 5 on the substrate 1 and the orthographic projection width of the interval between any two adjacent second signal lines 5 on the substrate 1. The orthographic projection width of the second via 111 on the substrate 1 refers to the dimension of the second via 111 along the arrangement direction of the plurality of second signal lines 5. The orthographic projection width of the third via 112 on the substrate 1 refers to the dimension of the third via 112 along the arrangement direction of the plurality of second signal lines 5.

[0152] In some embodiments, referring to Figures 3d, 3e and 3g, at least two of the at least three conductive layers are located on the side of the second signal line 5 close to the substrate 1, and any adjacent two of the at least two conductive layers are connected by a fourth via 113 opened in the insulating layer 11; the orthographic projection of the second signal line 5 on the substrate 1 overlaps with the orthographic projection of the fourth via 113 on the substrate 1.

[0153] The conductive layer located on the side of the second signal line 5 close to the substrate 1 can shield the second signal line 5 , ensuring that the second signal line 5 is not interfered by signals on other signal lines located on the side of the second signal line close to the substrate 1 .

[0154] In some embodiments, referring to Figures 3d and 3e, at least one of the at least three conductive layers is located on the side of the second signal line 5 facing away from the substrate 1, and the fourth via 113 and the orthographic projection of the second signal line 5 on the substrate 1 are located within the orthographic projection area of ​​the conductive layer on the side of the second signal line 5 facing away from the substrate 1 on the substrate 1.

[0155] The conductive layer on the side of the second signal line 5 facing away from the substrate 1 can shield the second signal line 5 , ensuring that the second signal line 5 is not interfered by signals on other signal lines on the side facing away from the substrate 1 .

[0156] In some embodiments, referring to Figures 3d, 3e and 3g, the conductive layer on the same layer as the second signal line 5 and the conductive layer located on the side of the second signal line 5 close to the substrate 1 and adjacent to the second signal line 5 are connected through a fifth via 114 opened in the insulating layer 11; the conductive layer on the same layer as the second signal line 5 and the conductive layer located on the side of the second signal line 5 away from the substrate 1 and adjacent to the second signal line 5 are connected through a sixth via 115 opened in the insulating layer 11; the orthographic projections of the fifth via 114 and the sixth via 115 on the substrate 1 coincide.

[0157] 3d, 3e, and 3g, the second signal line 5 occupies part of the width of the connection via between the conductive layer where the second signal line 5 is located and the conductive layer adjacent to the second signal line 5 in the first signal line 4. This means that the width of the connection via between the conductive layer where the second signal line 5 is located and the conductive layer adjacent to the conductive layer where the second signal line 5 is located in the first signal line 4 is reduced. The width of the connection via is the dimension of the connection via along the width direction of the second signal line 5 or the dimension of the connection via along the arrangement direction of multiple second signal lines 5.

[0158] In some embodiments, referring to Figures 3d, 3e, and 3g, the first signal line 4 includes a fourth conductive layer 44, a first conductive layer 41, a second conductive layer 42, and a third conductive layer 43. The fourth conductive layer 44, the first conductive layer 41, the second conductive layer 42, and the third conductive layer 43 are stacked in this order, away from the substrate 1. Referring to Figures 3d and 3g, the second signal line 5 is located on the same layer as the second conductive layer 42; and referring to Figure 3e, the second signal line 5 is located on the same layer as the third conductive layer 43. The fourth conductive layer 44 and the first conductive layer 41 are located on the side of the second signal line 5 closer to the substrate 1. The fourth conductive layer 44 and the first conductive layer 41 are connected via a fourth via 113; the second conductive layer 42 and the first conductive layer 41 are connected via a fifth via 114; and the second conductive layer 42 and the third conductive layer 43 are connected via a sixth via 115. The second signal line 5 occupies part of the width of the fifth and sixth vias 114, 115, thereby reducing the width of the fifth and sixth vias 114, 115. 3d , 3e and 3g , in this embodiment, the second signal line 5 occupies part of the width n2 of the fifth via 114 and the sixth via 115 , so that the widths of the fifth via 114 and the sixth via 115 are reduced to (m3 −n2).

[0159] 3d, 3e, and 3g, the widths of the fourth via hole 113, the fifth via hole 114, and the sixth via hole 115 can be further reduced to further reduce the width of the display substrate border region 102. For example, the widths of the fourth via hole 113, the fifth via hole 114, and the sixth via hole 115 can be reduced to 4-5 μm.

[0160] In some embodiments, referring to Figures 3d, 3e and 3g, there are multiple second signal lines 5, and the multiple second signal lines 5 are distributed at intervals; the total distribution width s of the orthographic projections of the multiple second signal lines 5 on the substrate 1 is greater than the orthographic projection width (m3-n2) of the fifth via 114 on the substrate 1.

[0161] The total distribution width s of the orthographic projections of the plurality of second signal lines 5 on the substrate 1 refers to the sum of the orthographic projection widths of the plurality of second signal lines 5 on the substrate 1 and the orthographic projection width of the spacing between any two adjacent second signal lines 5 on the substrate 1. The orthographic projection width m4 of the fourth via 113 on the substrate 1 refers to the dimension of the fourth via 113 along the arrangement direction of the plurality of second signal lines 5. The orthographic projection widths (m3-n2) of the fifth and sixth vias 114, 115 on the substrate 1 refer to the dimensions of the fifth and sixth vias 114, 115 along the arrangement direction of the plurality of second signal lines 5.

[0162] In some embodiments, referring to FIG. 3 a and FIG. 3 f , the orthographic projection of the second signal line 5 on the substrate 1 does not overlap with the orthographic projection of the connecting via between any two adjacent conductive layers in the at least three conductive layers on the substrate 1 .

[0163] Referring to Figures 3a and 3f, the second signal line 5 occupies part of the width of the connection via between any two adjacent conductive layers in at least three conductive layers, which reduces the width of the connection via between any two adjacent conductive layers. The width of the connection via is the dimension of the connection via along the width direction of the second signal line 5 or the dimension of the connection via along the arrangement direction of multiple second signal lines 5.

[0164] In some embodiments, referring to Figures 3a and 3f, there are multiple second signal lines 5, and the multiple second signal lines 5 are distributed at intervals; the total distribution width s of the orthographic projections of the multiple second signal lines 5 on the substrate 1 is greater than the orthographic projection width m (m') of the connecting via between any two adjacent conductive layers in at least three conductive layers on the substrate 1.

[0165] In some embodiments, referring to FIG. 3 a , the first signal line 4 includes a fifth conductive layer 45, a fourth conductive layer 44, a first conductive layer 41, a second conductive layer 42, a third conductive layer 43, and a sixth conductive layer 46. The fifth conductive layer 45, the fourth conductive layer 44, the first conductive layer 41, the second conductive layer 42, the third conductive layer 43, and the sixth conductive layer 46 are stacked in this order away from the substrate 1, and the second signal line 5 is located on the same layer as the fourth conductive layer 44. The second signal line 5 occupies part of the width of the connecting via between any two adjacent conductive layers among the fifth conductive layer 45, the fourth conductive layer 44, the first conductive layer 41, the second conductive layer 42, the third conductive layer 43, and the sixth conductive layer 46. This reduces the width of the connecting via between any two adjacent conductive layers among the fifth conductive layer 45, the fourth conductive layer 44, the first conductive layer 41, the second conductive layer 42, the third conductive layer 43, and the sixth conductive layer 46.

[0166] In some embodiments, referring to FIG. 3 f , the first signal line 4 includes a first conductive layer 41, a second conductive layer 42, and a third conductive layer 43. The first conductive layer 41, the second conductive layer 42, and the third conductive layer 43 are stacked in this order away from the substrate 1, and the second signal line 5 is located on the same layer as the second conductive layer 42. The second signal line 5 occupies part of the width of the connecting via between any two adjacent conductive layers among the first conductive layer 41, the second conductive layer 42, and the third conductive layer 43, thereby reducing the width of the connecting via between any two adjacent conductive layers among the first conductive layer 41, the second conductive layer 42, and the third conductive layer 43.

[0167] In some embodiments, the minimum width of the connecting via hole between any two adjacent conductive layers of the first signal line 4 is in the range of 4 to 5 micrometers, that is, the minimum width of the connecting via hole that can be achieved by the manufacturing process is sufficient.

[0168] In some embodiments, referring to Figures 3a, 3b, 3d, 3e and 3f, among the at least two conductive layers overlapping with the orthographic projection of the second signal line 5 on the substrate 1, at least one conductive layer is located on the side of the second signal line 5 facing away from the substrate 1, and at least one conductive layer is located on the side of the second signal line 5 close to the substrate 1.

[0169] The conductive layer located on the side of the second signal line 5 facing away from the substrate 1 can shield the second signal line 5, ensuring that the second signal line 5 is not interfered with by signals on other signal lines located on the side facing away from the substrate 1. The conductive layer located on the side of the second signal line 5 close to the substrate 1 can shield the second signal line 5, ensuring that the second signal line 5 is not interfered with by signals on other signal lines located on the side close to the substrate 1.

[0170] 3 c and 3 g , at least two conductive layers overlapping the orthographic projection of the second signal line 5 on the substrate 1 are located on a side of the second signal line 5 facing away from the substrate 1 or on a side of the second signal line 5 close to the substrate 1 .

[0171] In some embodiments, the pixel unit includes multiple layers of conductive patterns, and at least two conductive layers of the first signal line 4 are respectively provided in the same layer as conductive patterns of different layers.

[0172] In some embodiments, referring to FIG3a, the display substrate further includes a first connecting electrode 7, a second connecting electrode 8, and at least one touch electrode layer 9 located on a side of the pixel circuit 2 away from the substrate 1, and a shielding layer 10 located on a side of the pixel circuit 2 close to the substrate 1. The pixel circuit 2 includes at least one thin film transistor 20, and the thin film transistor 20 includes an active layer 201 located on one side of the substrate 1, a gate 202 located on a side of the active layer 201 away from the substrate 1, and a source 203 and a drain 204 located on a side of the gate 202 away from the substrate 1; the orthographic projection of the shielding layer 10 on the substrate 1 overlaps with the orthographic projection of the active layer 201 on the substrate 1; the first connecting electrode 7 is located on the side of the thin film transistor 20 away from the substrate 1, and overlaps with the thin film transistor 20. The thin film transistor 20 is electrically connected; the second connecting electrode 8 is located on the side of the first connecting electrode 7 away from the substrate 1, and is electrically connected to the first connecting electrode 7; the light-emitting element 3 is located on the side of the second connecting electrode 8 away from the substrate 1, and is electrically connected to the second connecting electrode 8; at least one touch electrode layer 9 is located on the side of the light-emitting element 3 away from the substrate 1; the first conductive layer 41 and the first connecting electrode 7 are located on the same layer; the second conductive layer 42 and the second connecting electrode 8 are located on the same layer; the third conductive layer 43 and the first electrode 31 are located on the same layer; the fourth conductive layer 44 and the source 203 and / or drain 204 are located on the same layer; the fifth conductive layer 45 and the shielding layer 10 are located on the same layer; the sixth conductive layer 46 and any touch electrode layer 9 are located on the same layer.

[0173] In some embodiments, referring to Figure 2c, multiple insulating layers 11 are respectively located in different layers, and the multiple insulating layers 11 are respectively a first buffer layer (Buffer1) 1101 located between the substrate 1 and the shielding layer 10, a second buffer layer (Buffer2) 1102 located between the shielding layer 10 and the active layer 201, a first gate insulating layer (GI1) 1103 located between the active layer 201 and the gate 202, a second gate insulating layer (GI2) 1104 and an intermediate dielectric layer (ILD) 1105 located between the gate 202 and the source 203 and the drain 204, a passivation layer (PVX) 1106 and a first planar layer (PLN1) 1107 located between the source 203 and the drain 204 and the first connecting electrode 7, a second planar layer (PLN2) 1108 located between the first connecting electrode 7 and the second connecting electrode 8, and a third planar layer (PLN3) 1109 located between the second connecting electrode 8 and the first electrode 31.

[0174] In some embodiments, referring to FIG3a , a first buffer layer (Buffer1) 1101, a second buffer layer (Buffer2) 1102, a first gate insulating layer (GI1) 1103, a second gate insulating layer (GI2) 1104, an interlayer dielectric layer (ILD) 1105, a passivation layer (PVX) 1106, a first planar layer (PLN1) 1107, a second planar layer (PLN2) 1108, and a third planar layer (PLN3) 1109, as well as a pixel defining layer 12, a spacer layer 13, an encapsulation layer 14, a buffer layer 15, and a protective layer 16 extend from the display area 101 to the border area 102. The insulating layers 11 in FIG3b to FIG3g are collectively labeled as insulating layers 11.

[0175] In some embodiments, referring to Figures 3a-3g and Figure 2c, the display substrate further includes an encapsulation layer 14, which is located on the side of the pixel unit facing away from the substrate 1, and the orthographic projection of the encapsulation layer 14 on the substrate 1 at least covers the orthographic projections of the pixel unit, the functional component 6, the first signal line 4 and the second signal line 5 on the substrate 1.

[0176] In some embodiments, the width of the edge of the metal trace farthest from the display area 101 in the border area 102 away from the display area 101 can be narrowed to 0.6-1.1 mm.

[0177] In the embodiment of the present disclosure, by making the orthographic projection of at least part of the second signal line 5 on the substrate 1 overlap with the orthographic projection of the first signal line 4 on the substrate 1, compared with the arrangement design scheme of the signal lines in the border area in the related technical Figure 1c, the occupied width of at least part of the second signal line 5 in the border area 102 can be achieved by occupying part of the width of the first signal line 4, thereby reducing the additional occupied width of at least part of the second signal line 5 in the border area 102 or at least part of the second signal line 5 in the border area 102 no longer occupies the additional border width, thereby achieving the effect of reducing the width of the border area 102, which is beneficial for the display substrate to achieve a narrow border or an extremely narrow border.

[0178] In a third aspect, an embodiment of the present disclosure further provides a display panel, comprising the display substrate in the above embodiment.

[0179] By adopting the display substrate in the above embodiment, the display panel can achieve a narrow frame or an extremely narrow frame.

[0180] The display panel provided in the embodiments of the present disclosure may be any product or component with a display function, such as an OLED panel, an OLED TV, an OLED billboard, a display, a mobile phone, or a navigation device.

[0181] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display substrate, wherein: The display substrate has a display area and a frame area, wherein the frame area at least partially surrounds the display area, and the display substrate includes: A substrate, located in the display area and the frame area; A plurality of pixel circuits are located on one side of the substrate and in the display area; A plurality of light-emitting elements are located on a side of the plurality of pixel circuits away from the substrate and located in the display area, the plurality of pixel circuits are configured to drive the plurality of light-emitting elements to emit light, and at least one of the plurality of light-emitting elements comprises a first electrode, a light-emitting layer, and a second electrode which are sequentially arranged away from the substrate; A first signal line, located in the frame area and electrically connected to the second electrode; A plurality of second signal lines are located on one side of the substrate and are configured to be connected to the functional component, at least some of the plurality of second signal lines are located in the border area, and the orthographic projection of at least some of the second signal lines on the substrate overlaps with the orthographic projection of the first signal line on the substrate.

2. The display substrate according to claim 1, wherein: An orthographic projection of each of the plurality of second signal lines on the substrate overlaps with an orthographic projection of the first signal line on the substrate.

3. The display substrate according to claim 1, wherein: An orthographic projection of each of the plurality of second signal lines on the substrate is located within an orthographic projection of the first signal line on the substrate.

4. The display substrate according to claim 1, wherein: The first signal line includes at least two conductive layers located in different layers and electrically connected, and the at least two conductive layers include a first conductive layer and a second conductive layer.

5. The display substrate according to claim 4, wherein: One of the first conductive layer and the second conductive layer is located in the same layer as the at least part of the second signal line, and the orthographic projection of the other of the first conductive layer and the second conductive layer on the substrate overlaps with the orthographic projection of the at least part of the second signal line on the substrate.

6. The display substrate according to claim 5, wherein: The second conductive layer is located on a side of the first conductive layer away from the substrate, the first conductive layer and at least part of the second signal line are located in the same layer, and the orthographic projection of the second conductive layer on the substrate overlaps with the orthographic projection of at least part of the second signal line on the substrate.

7. The display substrate according to claim 5, wherein: The second conductive layer is located on a side of the first conductive layer away from the substrate, the second conductive layer and at least part of the second signal line are located in the same layer, and the orthographic projection of the first conductive layer on the substrate overlaps with the orthographic projection of at least part of the second signal line on the substrate.

8. The display substrate according to any one of claims 5 to 7, wherein: The first signal line further includes a third conductive layer located on a side of the first conductive layer and the second conductive layer away from the substrate, and the first conductive layer, the second conductive layer and the third conductive layer are electrically connected.

9. The display substrate according to claim 8, wherein: An orthographic projection of the third conductive layer on the substrate overlaps with an orthographic projection of at least a portion of the second signal line on the substrate.

10. The display substrate according to claim 9, wherein: The first signal line further includes a fourth conductive layer located on a side of the first conductive layer and the second conductive layer close to the substrate. The fourth conductive layer, the first conductive layer and the second conductive layer are stacked in sequence away from the substrate, An orthographic projection of the fourth conductive layer on the substrate overlaps with an orthographic projection of at least a portion of the second signal line on the substrate.

11. The display substrate according to claim 4, wherein: The first signal line further includes a fourth conductive layer and a fifth conductive layer located on a side of the first conductive layer and the second conductive layer close to the substrate, and a third conductive layer and a sixth conductive layer located on a side of the first conductive layer and the second conductive layer away from the substrate. The fifth conductive layer, the fourth conductive layer, the first conductive layer, the second conductive layer, the third conductive layer and the sixth conductive layer are stacked in sequence away from the substrate, The first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer and the sixth conductive layer are electrically connected, the at least part of the second signal line is located on the same layer as the fourth conductive layer, and the orthographic projections of the fifth conductive layer and the sixth conductive layer on the substrate overlap with the orthographic projection of at least part of the second signal line on the substrate.

12. The display substrate according to claim 11, wherein: It also includes a first connecting electrode, a second connecting electrode, and at least one touch electrode layer located on a side of the pixel circuit away from the substrate, and a shielding layer located on a side of the pixel circuit close to the substrate. The pixel circuit includes at least one thin film transistor, wherein the thin film transistor includes an active layer located on one side of the substrate, a gate located on a side of the active layer away from the substrate, and a source and a drain located on a side of the gate away from the substrate; The orthographic projection of the shielding layer on the substrate overlaps with the orthographic projection of the active layer on the substrate; The first connecting electrode is located at a side of the thin film transistor away from the substrate and is electrically connected to the thin film transistor; The second connecting electrode is located at a side of the first connecting electrode away from the substrate and is electrically connected to the first connecting electrode; The light emitting element is located at a side of the second connecting electrode away from the substrate, and is electrically connected to the second connecting electrode; The at least one touch electrode layer is located on a side of the light emitting element away from the substrate; The first conductive layer and the first connecting electrode are located in the same layer; The second conductive layer and the second connecting electrode are located in the same layer; The third conductive layer and the first electrode are located in the same layer; The fourth conductive layer is located at the same layer as the source electrode and the drain electrode; The fifth conductive layer and the shielding layer are located at the same layer; The sixth conductive layer and any one of the at least one touch electrode layer are located on the same layer.

13. The display substrate according to claim 1, wherein: The frame area includes a first side frame area, a second side frame area, a third side frame area and a fourth side frame area which are sequentially arranged around the display area, the functional part is located in the display area, and the functional part is arranged close to the first side frame area, The functional component is connected to the plurality of second signal lines respectively through a plurality of signal lead-out lines, and the signal lead-out lines extend from the position of the functional component to the first side frame area and are connected to the plurality of second signal lines located in the first side frame area; The display substrate further includes a signal input pad, and the signal input pad is located in the third side frame area. The plurality of second signal lines extend from the first side frame area through the second side frame area to the third side frame area and are connected to the signal input pad.

14. The display substrate according to claim 1, wherein: The first signal line is at least located in the first side frame area, the second side frame area and the fourth side frame area, and the orthographic projection of at least part of the second signal line on the substrate overlaps with the orthographic projection of the first signal line located in the second side frame area on the substrate.

15. A display substrate, wherein: The display substrate has a display area and a frame area, wherein the frame area at least partially surrounds the display area. The display substrate includes a base, a plurality of pixel units, a functional component, a first signal line and a second signal line; The pixel unit, the functional component, the first signal line and the second signal line are respectively located on one side of the substrate; The pixel unit comprises a pixel circuit and a light-emitting element, wherein the light-emitting element is located on a side of the pixel circuit away from the substrate, and the pixel circuit is electrically connected to the light-emitting element; The pixel unit and the functional component are located in the display area, and the pixel unit at least partially surrounds the functional component; The first signal line and the second signal line are located in the border area; The first signal line is electrically connected to the pixel unit, and the second signal line is electrically connected to the functional component; The first signal line includes at least two conductive layers, the at least two conductive layers are located in different layers, an insulating layer is provided between any two adjacent conductive layers, and any two adjacent conductive layers of the at least two conductive layers are connected via a via hole provided in the insulating layer; The second signal line is disposed in the same layer as one of the at least two conductive layers, and an orthographic projection of the second signal line on the substrate overlaps an orthographic projection of at least one of the at least two conductive layers on the substrate.

16. The display substrate according to claim 15, wherein: The first signal line includes at least three conductive layers, two adjacent layers of the at least three conductive layers form a group, and the at least three conductive layers include at least two groups. The orthographic projection of the second signal line on the substrate overlaps with the orthographic projection of at least one group of connecting vias between two adjacent conductive layers in the at least two groups on the substrate.

17. The display substrate according to claim 16, wherein: At least two of the at least three conductive layers are located on a side of the second signal line away from the substrate, and any two adjacent conductive layers of the at least two conductive layers are connected via a first via hole provided in the insulating layer; The orthographic projection of the second signal line on the substrate is located within the orthographic projection area of ​​the first via hole on the substrate.

18. The display substrate according to claim 17, wherein: The conductive layer on the same layer as the second signal line and the conductive layer adjacent to the second signal line and located on the side of the second signal line away from the substrate are connected through a second via hole opened in the insulating layer. The orthographic projection of the second via hole on the substrate is located within the orthographic projection region of the first via hole on the substrate.

19. The display substrate according to claim 18, wherein: At least one of the at least three conductive layers is located on a side of the second signal line close to the substrate, The conductive layer on the same layer as the second signal line and the conductive layer located on a side of the second signal line close to the substrate and adjacent to the second signal line are connected via a third via hole provided in the insulating layer. The orthographic projection of the third via hole on the substrate is located within the orthographic projection region of the first via hole on the substrate.

20. The display substrate according to claim 19, wherein: There are a plurality of second signal lines, and the plurality of second signal lines are distributed at intervals; The total distribution width of the orthographic projections of the plurality of second signal lines on the substrate is greater than the orthographic projection width of the second via hole on the substrate. The total distribution width of the orthographic projections of the plurality of second signal lines on the substrate is greater than the orthographic projection width of the third via hole on the substrate.

21. The display substrate according to claim 16, wherein: At least two of the at least three conductive layers are located on a side of the second signal line close to the substrate, and any adjacent two of the at least two conductive layers are connected via a fourth via hole provided in the insulating layer; An orthographic projection of the second signal line on the substrate overlaps with an orthographic projection of the fourth via hole on the substrate.

22. The display substrate according to claim 21, wherein: At least one of the at least three conductive layers is located on a side of the second signal line away from the substrate, The orthographic projection of the fourth via hole and the second signal line on the substrate is located within an orthographic projection region of the conductive layer on the substrate at a side of the second signal line facing away from the substrate.

23. The display substrate according to claim 22, wherein: The conductive layer on the same layer as the second signal line and the conductive layer located on a side of the second signal line close to the substrate and adjacent to the second signal line are connected via a fifth via hole provided in the insulating layer; The conductive layer on the same layer as the second signal line and the conductive layer located on a side of the second signal line away from the substrate and adjacent to the second signal line are connected via a sixth via hole provided in the insulating layer; The orthographic projections of the fifth via hole and the sixth via hole on the substrate coincide with each other.

24. The display substrate according to claim 23, wherein: There are a plurality of second signal lines, and the plurality of second signal lines are distributed at intervals; The total distribution width of the orthographic projections of the plurality of second signal lines on the substrate is greater than the orthographic projection width of the fifth via hole on the substrate.

25. The display substrate according to claim 16, wherein: The orthographic projection of the second signal line on the substrate does not overlap with the orthographic projection of the connecting via between any two adjacent conductive layers among the at least three conductive layers on the substrate.

26. The display substrate according to claim 25, wherein: There are a plurality of second signal lines, and the plurality of second signal lines are distributed at intervals; The total distribution width of the orthographic projections of the plurality of second signal lines on the substrate is greater than the orthographic projection width of the connecting via between any two adjacent conductive layers of the at least three conductive layers on the substrate.

27. The display substrate according to claim 16, wherein: At least one of the at least three conductive layers is located on a side of the second signal line away from the substrate, and at least one of the conductive layers is located on a side of the second signal line close to the substrate.

28. A display panel, wherein: A display substrate comprising any one of claims 1-27.

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