Wafer-level burn-in test fixture, wafer-level burn-in test device, test method, and wafer-level burn-in test system

Abstract

A wafer-level burn-in test fixture, a wafer-level burn-in test device, a test method, and a wafer-level burn-in test system, which relate to the technical field of wafer testing. The wafer-level burn-in test device comprises a wafer-level burn-in test fixture and a lifting mechanism, wherein the wafer-level burn-in test fixture comprises a cover plate assembly, a lower sealing assembly, a heat sink and a heating device, wherein the heat sink is configured to bear a wafer; the cover plate assembly comprises a first PCB and a test micropositioner connected to the first PCB; the lower sealing assembly comprises a lower sealing cover, which is connected to the cover plate assembly to form a test cavity; the heat sink and the heating device are located in the test cavity; and the heating device is located between the lower sealing cover and the heat sink. The lifting mechanism is configured to be controlled to extend and retract vertically, and movably abuts against the wafer-level burn-in test fixture so as to drive the lower sealing assembly to move upwards to be connected to the cover plate assembly to form the test cavity.

Description

Wafer-level aging test fixture, test device, method and system Technical Field

[0001] The present invention relates to the field of wafer testing technology, and in particular to a wafer-level aging test fixture, a wafer-level aging test device, a testing method and a testing system. Background Art

[0002] In the field of wafer-level aging testing, it is necessary to place the wafer in a sealed test chamber for high-voltage and high-temperature testing. In the prior art, the PCB board is generally directly connected to the lower sealing cover to form a sealed test chamber, and then the wafer in the lower sealing cover is subjected to high-voltage and high-temperature testing. The technical solution for performing high-temperature and high-voltage testing on the wafer in the lower sealing cover is generally to drive the PCB board and the lower sealing cover to a position that cooperates with the heating device, so as to perform high-temperature testing on the wafer in the lower sealing cover. This solution does not prevent the PCB board from being subjected to excessive pressure. However, during the testing of 8-inch wafers, due to the large size of the wafer, it is easy to curl and deform under the high-temperature and high-pressure test environment, affecting the high-temperature and high-pressure test results of the wafer. In addition, the cavity pressure required for the 8-inch wafer is relatively large. If the wafer is not pressed tightly, the wafer may be punctured. Because 8-inch wafers are large in area and prone to curling and deformation in high-temperature and high-pressure environments during wafer-level aging tests, which affects the test results, a better fixing method is needed. For example, separating the PCB board and the lower sealing cover and using a top-down clamping method can compress the wafer and prevent it from curling and deformation. However, this method is not used in the existing technology. During the clamping process, if the PCB board is subjected to excessive pressure, it will deform, and the test probe may not be in contact with the wafer or have poor contact, which may cause test errors.

[0003] Currently, probes are used to connect PCBs to external test devices. This rigid connection method places high demands on the position and structure of the PCB and external test devices. The external test device and fixture are highly correlated, their positions are fixed, installation and maintenance are relatively complex, and the structural layout lacks flexibility. Furthermore, the probes have multiple contact points with the PCB in the circuit, and the probes have a limited service life. Damage to any one probe can affect the connection between the PCB and external test device, even directly affecting their service life and reducing reliability and stability. The fixture has one end of the probe in contact with a contact point on the fixture surface, while the other end of the probe is directly connected to the external test device. This requires high precision in the processing and installation of the related structures, which limits the size of the related structures, resulting in a smaller wafer size that the fixture can accommodate and a smaller number of powered channels.

[0004] In addition, during the wafer-level aging test, it is usually necessary to perform power-on testing and heating testing on the wafer to test the wafer-level aging performance of the wafer. Among them, the heating test is to use a heating device to heat the wafer at high temperature, so as to test the high-temperature resistance of the wafer. In the prior art, the heating device is usually set at the bottom of the lower sealing cover assembly, and the lower sealing cover assembly is heated by multiple heating plates, so as to perform a high-temperature test on the wafer in the lower sealing cover assembly. However, the method of heating by multiple heating plates will cause uneven heating of the wafer, and since the heating device is located on the outside of the lower sealing cover assembly, the heat transfer rate is low, which affects the test efficiency of the wafer.

[0005] Summary of the Invention

[0006] An object of one aspect of the present invention is to provide a wafer-level aging test device that prevents wafers from curling in a high-temperature and high-pressure test environment.

[0007] A further object of one aspect of the present invention is to improve the wafer aging test accuracy of a wafer-level aging test device.

[0008] Another further object of one aspect of the present invention is to optimize the structure of a wafer-level burn-in test device.

[0009] Another object of the present invention is to provide a wafer-level aging test system including the wafer-level aging test device.

[0010] Another object of the present invention is to provide a testing method applied to the above-mentioned wafer-level aging testing device.

[0011] Another object of the present invention is to provide a wafer-level aging test fixture to solve the technical problem in the prior art that the number of power supply channels for the wafer is small due to the use of probe connection.

[0012] A further object of yet another aspect of the present invention is to prevent deformation of the test needle holder and the connector when they expand due to heat.

[0013] A further object of yet another aspect of the present invention is to prevent damage to the PCB board when the pressing force in the test chamber is too large.

[0014] Yet another object of the present invention is to provide a wafer-level aging test fixture to solve the technical problem of uneven heating of wafers during high-temperature aging tests in the prior art.

[0015] Another object of still another aspect of the present invention is to simplify the structure of the heating device.

[0016] Yet another object of yet another aspect of the present invention is to avoid damaging the wafer when the heating device directly contacts the wafer by properly setting the position of the ceramic plate.

[0017] In particular, according to one aspect of the present invention, a wafer-level aging test device is provided, comprising:

[0018] A wafer-level aging test fixture includes a cover assembly, a lower sealing assembly, a heat sink, and a heating device. The heat sink is used to support wafers. The cover assembly includes a first PCB board and a test needle holder connected to the first PCB board. The lower sealing assembly includes a lower sealing cover, which is connected to the cover assembly to form a test cavity. The heat sink and the heating device are located in the test cavity, and the heating device is located between the lower sealing cover and the heat sink.

[0019] A lifting mechanism is configured to extend and retract in a controlled manner, and the lifting mechanism is in active contact with the wafer-level aging test fixture to drive the lower sealing assembly to move upward and connect with the cover assembly to form the test chamber.

[0020] Optionally, the wafer-level aging test device further includes:

[0021] The mounting bracket includes a top plate assembly and a bottom plate assembly, wherein the top plate assembly and the bottom plate assembly are connected by pillars, the wafer-level aging test fixture is arranged below the top plate assembly and connected to the top plate assembly, and the lifting mechanism is installed on the bottom plate assembly; and a floating mechanism is arranged at the top plate assembly, wherein the floating mechanism is configured to float when the cover plate assembly is squeezed by the lower sealing cover, thereby preventing the cover plate assembly from deforming.

[0022] In particular, according to another aspect of the present invention, a wafer-level aging test system is provided, the wafer-level aging test system comprising loading and unloading equipment, at least one test instrument, and at least one wafer-level aging test device as described above;

[0023] The loading and unloading equipment is used to place the wafers in the corresponding wafer-level aging test device to perform a wafer-level aging test;

[0024] Any of the wafer-level aging test devices is connected to the corresponding test instrument to perform a wafer-level aging test.

[0025] In particular, according to another aspect of the present invention, a testing method applied to the above-mentioned wafer-level aging testing device is provided, comprising the following steps:

[0026] After the wafer loading is completed, the lifting mechanism is controlled to rise to a first height so that the lifting mechanism is connected to the lower sealing assembly;

[0027] Controlling the lifting mechanism to continue to drive the lower sealing assembly to rise to a second height, so that the lower sealing assembly moves to connect with the cover assembly to form a test cavity;

[0028] The heating device, the heat sink and the test pin holder included in the cover assembly are powered on to perform a wafer-level aging test on the wafer.

[0029] In particular, according to another aspect of the present invention, a wafer-level aging test fixture is provided, comprising a cover assembly and a lower sealing assembly, wherein the cover assembly and the lower sealing assembly are connected to form a test cavity for accommodating wafers.

[0030] Optionally, the cover assembly includes: a PCB board, including a first area and a second area, the first area and the second area are respectively located on different sides of the PCB board, and any first contact set in the first area is electrically connected to the corresponding second contact set in the second area; a test needle holder, located at the bottom of the PCB board and connected to the PCB board, the test needle holder having a plurality of test probes, one end of any one of the test probes contacts the corresponding first contact, and the other end contacts the wafer to perform a wafer-level aging test on the wafer; and at least one connector installed at the second area of ​​the PCB board, any one of the connectors being connected to the corresponding second contact, and any one of the connectors being connected to an external testing device through a wiring harness for performing a wafer-level aging test on the wafer.

[0031] Optionally, the wafer-level aging test fixture further includes a heat sink for supporting the wafer, and a heating device, wherein the heat sink and the heating device are located in the test chamber, the heat sink is stacked above the heating device, and the heating device is electrically connected to an electrical component located below the lower sealing component, and the heating device includes:

[0032] A heating film layer having uniformly arranged resistance wires and at least one power-on interface connected to the resistance wires, wherein the heating film layer is arranged on a side of the heat sink away from the wafer so as to heat the wafer through the heat sink; and a connecting component comprising at least one group of first connecting probe groups passing through the lower sealing cover component, wherein one end of any first connecting probe group is in contact with the corresponding power-on interface, and the other end passes through the lower sealing component and in contact with the electrical component, so that the electrical component supplies power to heat the heating film layer.

[0033] According to the solutions of some embodiments of the present invention, by arranging a heating device in the lower sealing cover and placing the wafer on the heat sink, a lifting mechanism that can be extended and retracted up and down is used to drive the lower sealing assembly to move upward and connect with the cover assembly to form a test cavity, and the heat sink is pressed tightly. Under the action of the flat heat sink, the wafer is also flat and will not curl, and the wafer can be pressed tightly to avoid the wafer being punctured.

[0034] Furthermore, the lifting mechanism of the present invention includes a lifting assembly and an electrical assembly. After the sealing assembly is driven by the lifting mechanism to move upward and connect with the cover assembly, the electrical assembly of the lifting mechanism is used to power the heating device and the heat sink in the test chamber. This is equivalent to the lifting mechanism not only achieving the lifting to press the wafer, but also achieving the power supply to the heating device and the heat sink, thereby optimizing the structure of the wafer-level aging test device.

[0035] According to some other embodiments of the present invention, a floating mechanism is provided at the top plate assembly of the mounting bracket, and the floating mechanism is configured to float when the cover plate assembly is squeezed by the lower sealing cover. This can avoid deformation of the cover plate assembly under pressure, ensure that the test probes on the cover plate assembly are in contact with the wafer, improve the stability of the contact, and thereby improve the accuracy of the wafer-level aging test.

[0036] Furthermore, during the lifting process of the lifting mechanism, the present invention utilizes the Pad on the top of the second PCB board of the electrical component to cooperate with the lower sealing cover to power the heating device and the heat sink, thereby realizing high-voltage and high-temperature testing of the wafer. This is equivalent to the lifting mechanism realizing the lifting to press the wafer, and providing the test conditions for the wafer in the lower sealing cover, thereby optimizing the structure of the wafer-level aging test device.

[0037] According to some further embodiments of the present invention, by adding a connector to the second area of ​​the PCB board and connecting the connector to an external test device using a wiring harness, the prior art probe connection method is eliminated. This is equivalent to replacing a rigid connection with a flexible connection. This allows the relative positions of the wafer-level burn-in test fixture and the external test device to be flexibly arranged, thereby increasing the number of channels for powering the wafer. In addition, the use of probes to connect to the external test device results in many contact points, which reduces the reliability of the circuit connection. However, the present invention uses a wiring harness connection, which eliminates contact points and thus improves the reliability of the circuit connection.

[0038] Furthermore, the present invention provides at least one groove at the edge of the test needle holder, and at least one positioning post is provided on the support portion of the connector. Each positioning post is arranged corresponding to a groove to position the test needle holder. The cooperation between the positioning post and the groove defines the position of the test needle holder. However, the groove is not closed, and the positioning post only contacts the two side edges of the groove along the circumference of the needle holder. When the test needle holder and the connector expand due to heat, the positioning post can slide slightly in the groove along the radial direction of the test needle holder without squeezing the groove, thereby eliminating stress caused by expansion of the test needle holder and the connector, and preventing deformation of the test needle holder and the connector.

[0039] Furthermore, the present invention provides a load-bearing column that passes through the PCB. One end of the column is connected to the upper sealing cover located on top of the PCB, and the other end protrudes from the bottom surface of the PCB. If the compressive force within the test chamber is too strong and the lower sealing cover is too close to the PCB, the column contacts the lower sealing cover before the PCB, absorbing the compressive force of the test chamber, thereby preventing damage to the PCB from excessive pressure.

[0040] According to some further embodiments of the present invention, the heating device of the wafer-level aging test fixture includes a heating film layer and a connecting component. The heating film layer has uniformly arranged resistance wires and at least one power-on interface connected to the resistance wires. The heating film layer is arranged on the side of the heat sink away from the wafer to heat the wafer through the heat sink. The connecting component includes at least one group of first connection probe groups passing through the lower sealing component. One end of any first connection probe group contacts the corresponding power-on interface, and the other end passes through the lower sealing component and contacts the electrical component, so that the electrical component supplies power to the heating film layer, thereby causing the heating film layer to heat the wafer on the heat sink. The above technical solution uses a heating film layer with uniformly arranged resistance wires, eliminating the technical solution of using multiple heating plates in the prior art, which can make the wafer heated evenly and avoid local overheating of the wafer. In addition, setting the heating device inside the lower sealing cover assembly is equivalent to integrating the lower sealing cover assembly with the heating device. Compared with the solution in the prior art that requires the setting of an auxiliary structure to contact the lower sealing cover assembly with the heating device, the structure of the wafer-level aging test device is simplified, and the heating efficiency of the heating device on the wafer is improved, thereby improving the testing efficiency of the wafer.

[0041] Furthermore, the heating film layer of the heating device of the present invention has evenly arranged resistance wires and at least one power-on interface connected to the resistance wires. The first connecting probe group is directly connected to the resistance wires through the power-on interface to achieve uniform heating of the heating film layer, avoiding the need to set up multiple probe assemblies corresponding to multiple heating plates, thereby simplifying the structure of the heating device.

[0042] Furthermore, the heating device of the present invention also includes a ceramic plate, which is located between the second thermal insulation member and the heat sink, and is used to transfer the heat generated by the heating film layer to the heat sink, thereby avoiding damage to the wafer when the heating device directly contacts the wafer, thereby reducing the defective rate of the wafer during the wafer-level aging test.

[0043] Based on the following detailed description of specific embodiments of the present invention in conjunction with the accompanying drawings, those skilled in the art will become more aware of the above and other objects, advantages and features of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Hereinafter, some specific embodiments of the present invention will be described in detail in an illustrative and non-limiting manner with reference to the accompanying drawings. The same reference numerals in the accompanying drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale.

[0045] In the attached figure:

[0046] FIG1 is a schematic structural diagram of a wafer-level aging test device according to one embodiment of the present invention;

[0047] FIG2 is a schematic structural diagram of a cover plate assembly in the wafer-level aging test apparatus shown in FIG1 ;

[0048] FIG3 is a schematic cross-sectional view of the lower sealing cover in the wafer-level aging test device shown in FIG1 ;

[0049] FIG4 is a schematic enlarged view of portion A in FIG3 ;

[0050] FIG5 is a schematic structural diagram of the lower sealing cover in the wafer-level aging test device shown in FIG1 ;

[0051] FIG6 is a schematic structural diagram of the lifting mechanism in the wafer-level aging test apparatus shown in FIG1 ;

[0052] FIG7 is a schematic structural diagram of the adapter plate in the lifting mechanism shown in FIG6;

[0053] FIG8 is a schematic connection block diagram of a wafer-level aging test system according to an embodiment of the present invention;

[0054] 9 is a schematic flow chart of a testing method of a wafer-level aging test apparatus according to an embodiment of the present invention;

[0055] FIG10 is a schematic structural diagram of a wafer-level aging test device according to one embodiment of the present invention;

[0056] FIG11 is a schematic cross-sectional view of a floating mechanism and a top plate assembly in the wafer aging test apparatus shown in FIG1 ;

[0057] FIG12 is a schematic enlarged view of portion A in FIG11 ;

[0058] FIG13 is a schematic structural diagram of the lower cover plate in the wafer-level aging test device shown in FIG10;

[0059] FIG14 is a schematic installation diagram of the floating plate and the lower cover plate in the wafer-level aging test apparatus shown in FIG10 ;

[0060] FIG15 is a schematic structural diagram of the upper cover plate in the wafer-level aging test device shown in FIG10 ;

[0061] FIG16 is a schematic structural diagram of the lifting mechanism in the wafer-level aging test apparatus shown in FIG10 ;

[0062] FIG17 is a schematic structural diagram of a wafer-level aging test fixture according to one embodiment of the present invention;

[0063] FIG18 is a schematic exploded view of a wafer-level burn-in test fixture according to one embodiment of the present invention;

[0064] 19 is a schematic diagram showing the positions of a wafer-level burn-in test fixture and external test equipment according to one embodiment of the present invention;

[0065] FIG20 is a schematic structural diagram of the PCB board shown in FIG18;

[0066] FIG21 is a schematic structural diagram of a test needle holder according to an embodiment of the present invention;

[0067] FIG22 is a schematic enlarged view of point A in FIG21;

[0068] FIG23 is a schematic structural diagram of a connecting member according to one embodiment of the present invention;

[0069] FIG24 is a schematic enlarged view of point B in FIG23;

[0070] FIG25 is a schematic position diagram of a load-bearing component according to one embodiment of the present invention;

[0071] FIG26 is a schematic structural diagram of the load-bearing component shown in FIG25;

[0072] FIG27 is a schematic structural diagram of a lifting mechanism according to one embodiment of the present invention;

[0073] FIG28 is a schematic structural diagram of a heating device according to one embodiment of the present invention;

[0074] FIG29 is a schematic cross-sectional view of a heating device according to one embodiment of the present invention;

[0075] FIG30 is a schematic partial enlarged view of point A shown in FIG29;

[0076] FIG31 is a schematic cross-sectional view of a heating device according to an embodiment of the present invention from another angle;

[0077] FIG32 is a schematic partial enlarged view of point B shown in FIG31;

[0078] FIG33 is a schematic structural diagram of a wafer-level aging test device according to one embodiment of the present invention;

[0079] 34 is a schematic cross-sectional view of a portion of a wafer-level aging test apparatus according to one embodiment of the present invention;

[0080] FIG35 is a schematic partial enlarged view of point C shown in FIG34. DETAILED DESCRIPTION

[0081] The following describes embodiments of the present invention in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and are not to be construed as limiting the present invention.

[0082] In the description of the present invention, it should be understood that the terms "upper" and "lower" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0083] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features, that is, include one or more of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. When a feature "includes or contains" one or more of the features it covers, unless otherwise specifically described, this indicates that other features are not excluded and may further include other features.

[0084] Unless otherwise specified or limited, the terms "connection" and "installation" should be interpreted broadly. For example, they can refer to fixed or detachable connections, or integration; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components or interaction between two components, unless otherwise specified. Those skilled in the art should be able to understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0085] Unless otherwise defined, all terms (including technical terms and scientific terms) used in the description of this embodiment have the same meaning as commonly understood by ordinary technicians in the technical field to which this application belongs.

[0086] FIG1 is a schematic structural diagram of a wafer-level burn-in test apparatus 100A according to one embodiment of the present invention, and FIG2 is a schematic structural diagram of a cover plate assembly 70A in the wafer-level burn-in test apparatus 100A shown in FIG1 . As shown in FIG1 and FIG2 , in this embodiment, the wafer-level burn-in test apparatus 100A includes a wafer-level burn-in test fixture 10A and a lifting mechanism 30A. The wafer-level burn-in test fixture 10A includes a cover plate assembly 70A, a lower sealing assembly, a heat sink 22A, and a heating device. The heat sink 22A is used to support wafers. The cover plate assembly 70A includes a first PCB board 11A and a test pin holder 12A connected to the first PCB board 11A. The lower sealing assembly includes a lower sealing cover 20A. The lower sealing cover 20A is connected to the cover plate assembly 70A to form a test cavity 21A. The heat sink 22A and the heating device are located within the test cavity 21A, and the heating device is located between the lower sealing cover 20A and the heat sink 22A. The lifting mechanism 30A is configured to extend and retract in a controlled manner up and down. The lifting mechanism 30A is movably connected to the wafer-level aging test fixture 10A to drive the lower sealing assembly to move upward and connect with the cover assembly 70A to form a test chamber 21A. Here, the test needle holder 12A has a plurality of test probes for testing wafers. The lower sealing cover 20A is located below the wafer-level aging test fixture 10A. When the lower sealing cover 20A and the cover assembly 70A form the test chamber 21A, the test needle holder 12A is located in the test chamber 21A, so that the plurality of test probes on the test needle holder 12A are connected to the wafer, thereby realizing a wafer-level aging test on the wafer.

[0087] This embodiment arranges a heating device in the lower sealing cover 20A, places the wafer on the heat sink 22A, and utilizes a lifting mechanism 30A that can be extended and retracted up and down to drive the lower sealing assembly to move upward and connect with the cover assembly to form a test cavity 21A, and presses the heat sink 22A tightly. Under the action of the flat heat sink 22A, the wafer is also flat and will not curl, and the wafer can be pressed tightly to avoid the wafer being punctured.

[0088] In this embodiment, the lifting mechanism 30A includes a lifting component 32A and an electrical component 31A. The electrical component 31A is arranged at the free end of the lifting component 32A. The electrical component 31A is movably connected to the lower sealing component. The electrical component 31A is configured to power the heating device and the heat sink 22A, thereby performing wafer-level aging testing on the wafer.

[0089] The lifting mechanism 30A of this embodiment includes a lifting component 32A and an electrical component 31A. After the sealing component is driven by the lifting mechanism 30A to move upward and connect with the cover assembly 70A, the electrical component 31A of the lifting mechanism 30A is used to power the heating device and the heat sink 22A in the test cavity 21A. This is equivalent to the lifting mechanism 30A both rising to press the wafer and powering the heating device and the heat sink 22A, thereby optimizing the structure of the wafer-level aging test device 100A.

[0090] In this embodiment, the lower sealing assembly further includes a sealing strip 211A disposed on the top of the lower sealing cover 20A, and the sealing strip 211A is used to seal the test cavity 21A.

[0091] Figure 3 is a schematic cross-sectional view of the lower sealing cover 20A in the wafer-level burn-in test apparatus 100A shown in Figure 1, and Figure 4 is a schematic enlarged view of section A in Figure 3. As shown in Figures 3 and 4, in this embodiment, the heating device includes a heating film layer 26A and at least one first connection probe group 27A. The heating film layer 26A has uniformly arranged resistance wires 262A and at least one power supply interface 261A connected to the resistance wires 262A. The first connection probe groups 27A pass through the lower sealing cover 20A. One end of each first connection probe group 27A contacts one power supply interface 261A and the other end contacts an electrical component 31A, so that the electrical component 31A energizes the heating film layer 26A, thereby heating the wafer on the heat sink 22A. Here, the heating film layer 26A can be a mica heating plate or a ceramic heating plate. The resistance wires 262A are disposed between the two mica film layers or ceramic film layers, and the resistance wires 262A are uniformly arranged within the extended plane. In this embodiment, the number of the first connection probes and power supply interfaces 261A is two, and the first connection probe group 27A includes multiple connection probes. In other embodiments, the number of the first connection probes and power supply interfaces 261A can also be set according to specific design requirements.

[0092] In this embodiment, the heating device also includes a second thermal insulation member 25A and a first thermal insulation member 24A. The test cavity 21A is provided with a second thermal insulation member 25A, a first thermal insulation member 24A, a heating film layer 26A, a ceramic plate 23A and a heat sink 22A from bottom to top. The heating film layer 26A is arranged on the top of the first thermal insulation member 24A, that is, below the ceramic plate 23A. Here, the ceramic plate 23A has the function of thermal insulation. The first connection probe group 27A passes through the lower sealing cover 20A, the second thermal insulation member 25A, and the first thermal insulation member 24A in sequence, thereby contacting the power interface 261A of the heating film layer 26A. This embodiment arranges the heating device in the test cavity 21A, which is equivalent to integrating the lower sealing cover 20A with the heating device. Compared with the solution in the prior art that requires an auxiliary structure to contact the lower sealing cover 20A with the heating device, the structure of the wafer-level aging test device 100A is simplified, and the heating efficiency of the heating device on the wafer is improved, thereby improving the test efficiency of the wafer.

[0093] FIG5 is a schematic structural diagram of the lower sealing cover 20A in the wafer-level burn-in test apparatus 100A shown in FIG1 , and FIG6 is a schematic structural diagram of the lifting mechanism 30A in the wafer-level burn-in test apparatus 100A shown in FIG1 . As shown in FIG5 and FIG6 , in this embodiment, the electrical assembly 31A includes a second PCB board 311A, which is connected to the external circuit. The top of the second PCB board 311A ​​is provided with at least one first pad position 33A. Each first pad position 33A is arranged corresponding to a first connection probe group 27A. When the first pad position 33A contacts the first connection probe group 27A, the external circuit powers the heating device through the second PCB board 311A, thereby performing a heating test on the wafer. When the lifting assembly 32A of the lifting mechanism 30A drives the electrical assembly upward until it abuts the lower sealing cover 20A, the first pad position 33A contacts the first connection probe group 27A, thereby achieving electrical connection. Here, there are two first pad positions 33A, and the second connection probe group 28A includes multiple connection probes. In other embodiments, the number of first Pad positions 33A may be set according to actual needs.

[0094] In this embodiment, the lower sealing cover 20A is also provided with at least one second connection probe group 28A in contact with the heat sink 22A. The top of the second PCB board 311A ​​is also provided with at least one second Pad position 34A, and each second Pad position 34A is arranged corresponding to a second connection probe group 28A, so that when in contact with the second connection probe group 28A, the external circuit powers the heat sink 22A through the second PCB board 311A, thereby performing a power-on test on the wafer. In this embodiment, the second connection probe group 28A passes through the lower sealing cover 20A, the second thermal insulation member 25A, the first thermal insulation member 24A and the ceramic board 23A in sequence, thereby contacting the bottom of the heat sink 22A to power the heat sink 22A and realize high-voltage testing of the wafer. Here, the wafer undergoes a high-voltage test of about 2000V.

[0095] In this embodiment, the lower sealing cover 20A is also provided with a third connection probe group and at least one fourth connection probe group. The top of the second PCB board 311A ​​is also provided with a third pad position and at least one fourth pad position. The bottom of the heat sink 22A is provided with a groove for accommodating a first temperature sensor. One end of the third connection probe group contacts the first temperature sensor, and the other end contacts the third pad position, thereby obtaining the temperature of the heat sink 22A. At least one second temperature sensor is provided on the heating film layer 26A. The fourth connection probe group corresponds to one second temperature sensor and one fourth pad position. It can be understood that one end of the fourth connection probe group contacts the second temperature sensor, and the other end contacts the fourth pad position. In this embodiment, there are two second temperature sensors, one of which is used to obtain the temperature of the heating film layer 26A, and the other is used for overheating protection.

[0096] Figure 7 is a schematic structural diagram of the adapter plate 314A in the lifting mechanism 30A shown in Figure 6. As shown in Figure 7 and with reference to Figure 6, in this embodiment, the bottom of the lower sealing cover 20A is provided with a plurality of first air holes 29A, and the second PCB board 311A ​​is provided with a plurality of second air holes 312A, each second air hole 312A corresponding to a first air hole 29A. The electrical assembly 31A further includes an adapter plate 314A, which is disposed below the second PCB board 311A. The adapter plate 314A has an air channel 316A communicating with the plurality of second air holes 312A. This allows an external air path to evacuate the interior of the lower sealing cover 20A through the air channel 316A, the second air holes 312A, and the first air holes 29A, thereby adsorbing the heat sink 22A and the wafer. In this embodiment, to attach heat sink 22A, first air hole 29A of lower sealing cover 20A must be connected to the bottom of heat sink 22A, that is, it must penetrate ceramic plate 23A to attach the bottom of heat sink 22A. To attach a wafer, first air hole 29A must penetrate heat sink 22A to attach the wafer. Air channel 316A has an air channel interface 317A, which is connected to an external air circuit via a connector.

[0097] In this embodiment, when performing wafer-level aging testing on the wafer, nitrogen needs to be filled into the test chamber 21A. Specifically, nitrogen is filled into the test chamber 21A through the external air path from the air channel 316A, the second air hole 312A and the first air hole 29A. Nitrogen serves as a protective gas to prevent high-voltage ignition of the wafer during the high-voltage test.

[0098] In this embodiment, a sealing assembly 313A is further provided on the top of the second PCB board 311A ​​for sealing the first air hole 29A and the second air hole 312A during ventilation to prevent air leakage.

[0099] In this embodiment, the adapter board 314A further includes an adapter probe group 318A, and the electrical component 31A further includes a third PCB board 315A disposed at the bottom of the adapter board. The third PCB board 315A is connected to the adapter probe group 318A and is connected to an external circuit.

[0100] In this embodiment, the first PCB board 11A includes a first interface group 112A and a second interface group 111A, and the test needle holder 12A includes a plurality of test probes. The first interface group 112A is provided on the first side of the first PCB board 11A facing the lower sealing assembly, one end of any test probe is connected to the corresponding first interface included in the first interface group 112A, and the other end is connected to the wafer to perform a wafer-level aging test on the wafer, and the second interface group 111A is provided on any second side of the first PCB board 11A except the first side. The wafer-level aging test fixture 10A also includes a plurality of connectors 14A, and the plurality of connectors 14A are installed on the second side of the first PCB board 11A, and any connector 14A is connected to the corresponding second interface included in the second interface group 111A, and any connector 14A is connected to an external test device via a wiring harness for performing a wafer-level aging test on the wafer.

[0101] In this embodiment, a heat dissipation assembly 13A is further provided between the first interface group 112A and the second interface group 111A of the first PCB board 11A, thereby isolating the heat generated by the first interface group 112A during the wafer-level aging test to avoid affecting the normal operation of the connector 14A.

[0102] This embodiment adds a connector 14A to the second interface group 111A and uses a wiring harness to connect connector 14A to an external test device, eliminating the probe connection used in the prior art. This is equivalent to replacing a rigid connection with a flexible one. This allows for flexible positioning of the wafer-level burn-in test fixture 10A and the external test device, increasing the number of channels available for powering the wafer. Furthermore, using a probe to connect to an external test device results in numerous contact points, which reduces circuit connection reliability. The present invention uses a wiring harness to connect, eliminating these contact points and improving circuit connection reliability.

[0103] In this embodiment, the wafer-level burn-in test apparatus 100A further includes a mounting bracket 50A, which includes a base plate assembly 51A, a support platform 55A, and a pair of first slide grooves 54A. The support platform 55A is used to support the lower sealing assembly. The pair of first slide grooves 54A are connected to the base plate assembly 51A, and each first slide groove 54A extends horizontally. The ends of the support platform 55A are slidably connected to the corresponding first slide groove 54A. The lower sealing assembly moves along the extension direction of the first slide groove 54A driven by the support platform 55A. When loading or unloading wafers, the lower sealing assembly slides out of the mounting bracket 50A along the first slide groove 54A. After the wafer loading or unloading is completed, the lower sealing assembly retracts into the mounting bracket 50A along the first slide groove 54A.

[0104] In this embodiment, the mounting bracket 50A further includes a top plate assembly 53A and a pair of second chutes 40A. The top plate assembly 53A is connected to the bottom plate assembly 51A via a plurality of struts 52. The pair of second chutes 40A are connected to the top plate assembly 53A, with each second chutes 40A extending horizontally. The ends of the cover plate assembly 70A are slidably connected to the corresponding second chutes 40A, allowing the cover plate assembly 70A to be withdrawn to replace the test needle holder 12A. In addition, the cover plate assembly 70A can be withdrawn to replace the corresponding wafer-level burn-in test fixture 10A for different types of wafers, facilitating the replacement of the wafer-level burn-in test fixture 10A and improving the convenience of performing wafer-level burn-in tests on wafers.

[0105] In this embodiment, the wafer-level aging test device 100A further includes a camera 60A mounted on the mounting bracket 50A for detecting whether the lower sealing cover 20A and the cover plate assembly 70A are connected to form the test chamber 21A.

[0106] Figure 8 is a schematic block diagram of a wafer-level burn-in test system according to one embodiment of the present invention. As shown in Figure 8 , in this embodiment, a wafer-level burn-in test system 1000A includes a loading and unloading device 200A, at least one test instrument 300A, and at least one wafer-level burn-in test apparatus 100A as described above. The loading and unloading device 200A is used to place wafers into corresponding wafer-level burn-in test apparatus 100A for wafer-level burn-in testing. Each wafer-level burn-in test apparatus 100A is connected to a corresponding test instrument to perform wafer-level burn-in testing.

[0107] FIG9 is a schematic flow chart of a test method of a wafer-level aging test apparatus 100A according to an embodiment of the present invention. As shown in FIG9 , the test method of the wafer-level aging test apparatus 100A includes the following steps:

[0108] Step S100: After wafer loading is completed, the lifting mechanism 30A is controlled to rise to a first height so that the lifting mechanism 30A is connected to the lower sealing assembly;

[0109] Step S200 , controlling the lifting mechanism 30A to continue lifting the lower sealing assembly to a second height, so that the lower sealing assembly moves to the cover assembly 70A to connect with the test chamber 21A;

[0110] In step S300 , power is supplied to the heating device, the heat sink 22A, and the test pin holder 12A included in the cover assembly 70A to perform a wafer-level aging test on the wafer.

[0111] This embodiment utilizes a lifting mechanism 30A that can be raised and lowered to drive the lower sealing cover 20A to rise and connect with the cover plate assembly 70A to form a test cavity 21A, and to press the heat sink 22A tightly. Under the action of the flat heat sink 22A, the wafer is also flat and will not curl. At the same time, the wafer can be pressed tightly to avoid the wafer being punctured.

[0112] In this embodiment, the following steps are further included after step S300:

[0113] The lifting mechanism 30A is controlled to move downward so that the lower sealing assembly returns to its original position.

[0114] Figure 10 is a schematic structural diagram of a wafer-level burn-in test apparatus 100B according to one embodiment of the present invention, Figure 11 is a schematic cross-sectional view of a floating mechanism 60B and a top plate assembly 11B in the wafer-level burn-in test apparatus 100B shown in Figure 10, Figure 12 is a schematic enlarged view of portion A in Figure 11, and Figure 13 is a schematic structural diagram of a lower cover plate 111B in the wafer-level burn-in test apparatus 100B shown in Figure 10. As shown in Figures 10 to 13, in this embodiment, the wafer-level burn-in test apparatus 100B includes a mounting bracket 10B, a wafer-level burn-in test fixture, a lifting mechanism 40B, and a floating mechanism 60B, wherein the mounting bracket 10B includes a top plate assembly 11B and a bottom plate assembly 12B, which are connected by pillars 13B. The wafer-level burn-in test fixture is disposed below and connected to the top plate assembly 11B. The wafer-level burn-in test fixture includes a cover plate assembly 20B and a lower sealing assembly. The lower sealing assembly includes a lower sealing cover 30B, which is connected to the cover plate assembly 20B to form a test chamber for placing wafers. The cover plate assembly 20B has a test probe holder 21B. A lifting mechanism 40B is mounted on the base plate assembly 12B and located below the lower sealing cover 30B. The lifting mechanism 40B is configured to move up and down in a controlled manner. The lifting mechanism 40B movably abuts against the wafer-level burn-in test fixture to drive the lower sealing assembly upward to connect with the cover plate assembly 20B to form a test chamber. A floating mechanism 60B is disposed on the top plate assembly 11B. The floating mechanism 60B is configured to float when the cover plate assembly 20B is squeezed by the lower sealing cover 30B, thereby preventing deformation of the cover plate assembly 20B.

[0115] This embodiment provides a floating mechanism 60B at the top plate assembly 11B of the mounting bracket 10B. The floating mechanism 60B is configured to float when the cover plate assembly 20B is squeezed by the lower sealing cover 30B, thereby avoiding compression deformation of the cover plate assembly 20B and ensuring that the test probe on the cover plate assembly 20B contacts the wafer, thereby improving the contact stability and thus improving the accuracy of the wafer-level aging test.

[0116] In this embodiment, the top plate assembly 11B includes an upper cover plate 112B and a lower cover plate 111B. The lower cover plate 111B has a retaining groove 114B. The floating mechanism 60B includes a floating plate 61B and a telescopic assembly 63B. The floating plate 61B is disposed on top of the cover plate assembly 20B, located in the retaining groove 114B, and protrudes from the bottom of the lower cover plate 111B. The telescopic assembly 63B is connected to the upper cover plate 112B, and its bottom is connected to or abuts the floating plate 61B. When the floating plate 61B is squeezed by the cover plate assembly 20B, it is compressed and moves upward. This prevents the cover plate assembly 20B from being deformed by pressure, which could affect the wafer burn-in test.

[0117] In this embodiment, the cover assembly 20B includes a first PCB 22B and a test probe holder 21B mounted below the first PCB 22B. This embodiment primarily prevents deformation of the first PCB 22B due to pressure. Because the first PCB 22B is connected to the test probe holder 21B, which is equipped with multiple test probes, deformation of the first PCB 22B is avoided, thereby preventing the test probes from moving and causing poor contact. Furthermore, the floating mechanism 60B provided in this embodiment prevents damage to the test probes due to excessive force, thereby increasing their service life.

[0118] Referring to Figure 12, the floating plate 61B is connected to the lower cover plate 111B, and there is a gap between it and the upper cover plate 112B. When the floating plate 61B is subjected to greater pressure, the floating plate 61B can move within this gap. In other words, this gap is the moving stroke of the floating plate 61B. The moving stroke of the floating plate 61B can be designed according to design requirements.

[0119] In this embodiment, the floating plate 61B is circular and positioned opposite the test needle holder 21B. Because the lower sealing cover 30B needs to seal the test needle holder 21B within the lower sealing cover 30B when it moves upward to contact the cover assembly 20B, it primarily abuts against the periphery of the test needle holder 21B. The force acting on the cover assembly 20B is primarily near the test needle holder 21B. Therefore, in this embodiment, the floating plate 61B is positioned opposite the test needle holder 21B to better prevent compression and deformation of the first PCB 22B.

[0120] In a preferred embodiment, the size of the floating plate 61B is larger than the size of the test needle seat 21B and smaller than the size of the lower sealing cover 30B. In other embodiments, the size of the floating plate 61B can also be set according to specific design requirements, for example, set to be larger than the size of the lower sealing cover 30B.

[0121] Figure 14 is a schematic installation diagram of the floating plate 61B and lower cover plate 111B in the wafer-level burn-in test apparatus 100B shown in Figure 10 , and Figure 15 is a schematic structural diagram of the upper cover plate 112B in the wafer-level burn-in test apparatus 100B shown in Figure 10 . As shown in Figures 14 and 15 , and with reference to Figure 12 , in this embodiment, the bottom of the upper cover plate 112B is provided with at least one first mounting slot 113B, and the top of the floating plate 61B is provided with at least one second mounting slot 62B, each second mounting slot 62B corresponding to a first mounting slot 113B. The telescopic assembly 63B includes at least one elastic member 631B, each elastic member 631B being disposed within a first mounting slot 113B and a second mounting slot 62B. Here, each elastic member 631B is threaded through a connecting rod 632B, which is connected to the upper cover plate 112B.

[0122] In a preferred embodiment, there are multiple elastic members 631B, each evenly arranged on top of the floating plate 61B. This means that there are multiple first mounting slots 113B and multiple second mounting slots 62B, each evenly arranged at positions corresponding to the floating plate 61B, and multiple second mounting slots 62B evenly arranged on the floating plate 61B. This ensures that the first PCB 22B of the cover assembly 20B is evenly stressed, preventing localized deformation of the first PCB 22B.

[0123] In this embodiment, the mounting bracket 10B further includes a pair of slide slots 70B connected to the lower cover plate 111B. Each of the slide slots 70B extends horizontally, and the ends of the cover plate assembly 20B are slidably connected to the corresponding slide slots 70B. It can be understood that the cover plate assembly 20B can be removed from the top plate assembly 11B, and the corresponding cover plate assembly 20B can be replaced for different types of wafers. This facilitates replacement of the cover plate assembly 20B, improves the convenience of wafer-level burn-in testing, and also facilitates replacement of the test probe tray on the cover plate assembly 20B.

[0124] In this embodiment, the wafer-level aging test device 100B further includes a camera device 50B, which is mounted on the mounting bracket 10B and is used to detect whether the first PCB board 22B is connected to form a test cavity when the lower sealing cover 30B abuts the cover assembly 20B.

[0125] Figure 16 is a schematic structural diagram of the powered ventilation device in the wafer-level burn-in test apparatus shown in Figure 10. As shown in Figure 16 and with reference to Figure 10, in this embodiment, the wafer-level burn-in test fixture further includes a heat sink and a heating device, both of which are located within the test chamber. The lifting mechanism 40B includes an electrical assembly 41B, which includes a second PCB board 411B. The top of the second PCB board 411B has a pad 412B for powering the heat sink and heating device, enabling wafer-level burn-in testing of the wafers.

[0126] In this embodiment, the lifting mechanism 40B also includes a lifting component 42B connected to the electrical component 41B. The electrical component 41B is arranged at the free end of the lifting component 42B. The lifting component 42B is used to drive the electrical component 41B to move upward so that the pad position 412B cooperates with the lower sealing cover 30B and drives the lower sealing cover 30B to move upward until it abuts and connects with the cover plate assembly 20B to form a test cavity.

[0127] In this embodiment, during the lifting process of the lifting mechanism 40B, the pad on the top of the second PCB board 411B of the electrical component 41B cooperates with the lower sealing cover 30B to supply power to the heating device and the heat sink, thereby realizing high-voltage and high-temperature testing of the wafer. This is equivalent to the lifting mechanism 40B achieving both rising to press the wafer and providing test conditions for the wafer in the lower sealing cover 30B, thereby optimizing the structure of the wafer-level aging test device 100B.

[0128] In this embodiment, the lifting assembly 42B includes multiple worm gear assemblies 422B and a motor 421B. The multiple worm gear assemblies 422B are respectively connected to the electrical assembly 41B, and the motor 421B is connected to the multiple worm gear assemblies 422B to drive the multiple worm gear assemblies 422B to move the electrical assembly 41B up and down. In other embodiments, the lifting assembly 42B can also use other components, such as a cylinder.

[0129] The present invention also provides a wafer-level aging test fixture. The wafer-level aging test fixture includes a cover assembly and a lower sealing assembly. The cover assembly and the lower sealing assembly are connected to form a test cavity for accommodating wafers.

[0130] Figure 17 is a schematic structural diagram of a wafer-level burn-in test fixture 100C according to one embodiment of the present invention. Figure 18 is a schematic exploded view of the wafer-level burn-in test fixture 100C according to one embodiment of the present invention. Figure 19 is a schematic positional diagram of the wafer-level burn-in test fixture 100C and an external test device 200C according to one embodiment of the present invention. Figure 20 is a schematic structural diagram of the PCB board 10C shown in Figure 18. In some embodiments, as shown in Figures 17-20, the wafer-level burn-in test fixture 100C includes a cover assembly 110C and a lower sealing assembly 120C. The cover assembly 110C and the lower sealing assembly 120C are connected to form a test chamber 121C for accommodating wafers. The cover assembly 110C includes a PCB board 10C, a test probe holder 20C, and at least one connector 30C. The PCB board 10C includes a first area 11C and a second area 12C, the first area 11C and the second area 12C being located on different sides of the PCB board 10C. Any first contact 13C provided in the first area 11C is electrically connected to a corresponding second contact 14C provided in the second area 12C. A test needle holder 20C is located at the bottom of the PCB board 10C and is connected to the PCB board 10C. The test needle holder 20C has a plurality of test probes 21C. One end of each test probe 21C contacts the corresponding first contact 13C and the other end contacts the wafer to perform wafer-level aging testing on the wafer. A connector 30C is mounted on the second area 12C of the PCB board 10C. Any connector 30C is connected to the corresponding second contact 14C. Any connector 30C is connected to an external test device 200C via a wiring harness 300C for performing wafer-level aging testing on the wafer.

[0131] Here, it can be understood that the test needle holder 20C is machined with a pinhole, and the test probe 21C is a spring probe installed in the pinhole. The test probe 21C punctures the chip on the wafer to energize the chip. The first area 11C and the second area 12C are two non-overlapping and electrically connected areas on the PCB board 10C. The surface of the first area 11C is provided with a first contact 13C. Any first contact is electrically connected to a corresponding second contact 14C provided in the second area 12C through the internal circuit of the PCB board 10C. The external test device 200C is connected to the connector 30C on the second area 12C via a flexible harness 300C or cable. The second area 12C transmits the test signal to the first area 11C. The first area 11C transmits the signal to the wafer in the test chamber 121C through the test probe 21C, thereby performing wafer-level burn-in testing on the wafer. The connector 30C and the external test device 200C are flexibly connected, with a simple structure and a flexible and reliable layout.

[0132] This embodiment adds a connector 30C to the second area 12C of the PCB board 10C and connects the connector 30C to the external test device 200C using a wiring harness 300C, thereby eliminating the probe connection method used in the prior art. This is equivalent to replacing a rigid connection with a flexible connection, so that the relative positions of the wafer-level aging test fixture 100C and the external test device 200C can be flexibly arranged, reducing the structural correlation between the wafer-level aging test fixture 100C and the external test device 200C, and increasing the number of channels for powering the wafer. In addition, the use of a probe to connect to the external test device 200C will result in many contact points, which will lead to lower circuit connection reliability. However, the present invention uses a wiring harness 300C for connection, which eliminates contact points, thereby improving circuit connection reliability. In addition, the wafer-level aging test fixture 100C can be independently and conveniently installed and disassembled, improving maintainability.

[0133] The wafer-level aging test fixture 100C of the present invention has a compact structure and high integration. It provides a larger number of channels for connecting to hardware in a smaller size. It can support wafer-level aging tests on SiC wafers up to 8 inches in size and provides more than 2,000 channels for power-on and wafer-level aging tests.

[0134] In this embodiment, multiple connectors 30C are arranged in an array on the PCB 10C. These connectors 30C are densely mounted on the second area 12C and connected to the external test device 200C via a flexible harness 300C or cable. The array arrangement of connectors 30C fully utilizes the second area 12C of the PCB 10C, conserving the PCB 10C's usable area. It also increases the number of powered channels per unit area, enabling high-density, multi-channel wafer-level burn-in testing.

[0135] Figure 21 is a schematic structural diagram of a test needle holder 20C according to one embodiment of the present invention. Figure 22 is a schematic enlarged view of point A in Figure 21. Figure 23 is a schematic structural diagram of a connector 40 according to the present invention. Figure 24 is a schematic enlarged view of point B in Figure 23. As shown in Figures 21-24, in this embodiment, the test needle holder 20C is circular. The wafer-level burn-in test fixture 100C also includes a ring-shaped connector 40C, which is connected to the PCB board 10C. The connector 40C is disposed around the periphery of the test needle holder 20C and is connected to the test needle holder 20C. Here, the connector 40C presses against the test needle holder 20C and engages with the test needle holder 20C, thereby securing the test needle holder 20C relative to the PCB board 10C and improving the structural stability of the wafer-level burn-in test fixture 100C. In this embodiment, the connector 40C is connected to the PCB board via bolts.

[0136] In this embodiment, the test needle holder 20C is made of a material with high hardness and low expansion coefficient. During the use of the wafer-level aging test fixture 100C, the test needle holder 20C and the PCB board 10C must be fixed to each other in a specific position, and there must be no relative displacement, otherwise the test probe 21C on the test needle holder 20C may not be able to contact the PCB board 10C and the circuit will be broken. The existing test needle holder 20C and the connector 40C are positioned by the cooperation of the pin and the cylindrical hole. Since the ambient temperature of the test needle holder 20C is close to 200°C when in use, the high temperature will inevitably cause the test needle holder 20C and the connector 40C to expand. The two are made of different materials and have a large difference in expansion coefficients, which will cause the pin and the cylindrical hole to squeeze each other and generate great stress, which will then lead to problems such as the test needle holder 20C being squeezed and damaged or the connector 40C being deformed and difficult to disassemble.

[0137] In this embodiment, at least one groove 22C is provided at the edge of the test needle holder 20C. The connector 40C has a support portion 41C for supporting the test needle holder 20C. The support portion 41C is provided with at least one positioning post 42C. Each positioning post 42C is arranged corresponding to a groove 22C to position the test needle holder 20C. The cooperation between the positioning post 42C and the groove 22C defines the position of the test needle holder 20C. When the test needle holder 20C and the connector 40C expand due to heat, the positioning post 42C can slide slightly within the groove 22C without squeezing the groove 22C, thereby eliminating the stress of the test needle holder 20C and the connector 40C during expansion and preventing deformation of the test needle holder 20C and the connector 40C. In this embodiment, the number of grooves 22C and positioning posts 42C is set to three, and the three grooves 22C are distributed at intervals along the circumference of the test needle holder 20C at the edge of the needle holder.

[0138] In this embodiment, the groove 22C opens toward the corresponding positioning post 42C. Here, the groove 22C is not enclosed, and the positioning post 42C only contacts two side edges of the groove 22C along the circumference of the needle hub. When the test needle hub 20C and the connector 40C expand due to heat, the positioning post 42C can slide slightly within the groove 22C along the radial direction of the test needle hub 20C. The positioning post 42C does not squeeze the groove 22C, thus preventing stress and deformation caused by the expansion of the test needle hub 20C and the connector 40C.

[0139] Cover assembly 110C connects to lower sealing assembly 120C to form an airtight test chamber 121C. A sealing ring 122C is located at the top of lower sealing assembly 120C. As lower sealing assembly 120C moves upward, sealing ring 122C first connects with PCB 10C and then compresses, creating an airtight seal. Airtight test chamber 121C maintains a certain pressure, generating a compressive force that binds lower sealing assembly 120C to PCB 10C. However, if the compressive force within test chamber 121C is too great, lower sealing assembly 120C may contact PCB 10C, transferring the excessive force to it.

[0140] Figure 25 is a schematic position diagram of a load-bearing component 60C according to one embodiment of the present invention, and Figure 26 is a schematic structural diagram of the load-bearing component 60C shown in Figure 25. As shown in Figures 25 and 26, in this embodiment, the wafer-level burn-in test fixture 100C further includes a circular upper sealing cover 50C, which is located on top of the PCB board 10C. The wafer-level burn-in test fixture 100C further includes a plurality of load-bearing components 60C spaced apart along the circumference of the upper sealing cover 50C. Each load-bearing component 60C includes a load-bearing column 61C, which passes through the PCB board 10C and is connected to the upper sealing cover 50C. The load-bearing column 61C protrudes from the bottom surface of the PCB board 10C. Here, the upper sealing cover 50C is tightly connected to the PCB board 10C via the sealing ring 122C of the lower sealing assembly 120C, providing airtightness to the top of the first area 11C. Load-bearing columns 61C are provided on the PCB 10C and are spaced apart circumferentially around the upper sealing cover 50C. The load-bearing columns 61C protrude from the bottom surface of the PCB 10C. When the compressive force within the test cavity 121C is too great and the lower sealing cover 120C is too close to the PCB 10C, the load-bearing columns 61C contact the lower sealing cover 120C before the PCB 10C, thereby bearing the compressive force of the test cavity 121C and protecting the PCB 10C from excessive pressure.

[0141] In this embodiment, the height of the support column 61C protruding from the bottom surface of the PCB board 10C is within a range of 0.1 mm to 0.2 mm. If the height of the support column 61C is too high, it will affect the seal between the PCB board 10C and the lower sealing cover 120C. If it is too low, it will not effectively bear the load. In this embodiment, the height of the support column 61C protruding from the bottom surface of the PCB board 10C is 0.1 mm. This allows the support column 61C to connect with the lower sealing cover 120C before the PCB board 10C is connected when the pressure of the test chamber 121C is too high, thus preventing damage to the PCB board 10C caused by excessive pressure.

[0142] In this embodiment, the load-bearing component 60C further includes at least one shim 62C mounted on the load-bearing column 61C to adjust the height of the load-bearing column 61C protruding from the bottom surface of the PCB 10C. In this embodiment, each shim 62C is 0.1 mm thick. The height of the load-bearing column 61C protruding from the bottom surface of the PCB 10C can be adjusted by adjusting the number of shims 62C.

[0143] In this embodiment, the wafer-level burn-in test fixture 100C further includes a heat sink 70C mounted on the PCB 10C. The heat sink 70C is located between the first region 11C and the second region 12C and is used to isolate the heat generated by the first region 11C. During the wafer-level burn-in test, the wafer is continuously heated. The higher temperature in the first region 11C can cause the heat to spread and affect other regions of the PCB 10C. This high temperature can adversely affect the connector 30C, thereby affecting the accuracy of the wafer-level burn-in test. To prevent high temperatures from affecting the connector 30C, the present invention provides a heat sink 70C between the first region 11C and the second region 12C.

[0144] In this embodiment, copper is laid on the surface of the PCB board 10C where the heat sink 70C is mounted, concentrating heat dissipated from the first region 11C at the location where the heat sink 70C is mounted. The heat sink 70C includes a fan and a heat sink. The fan is located at one edge of the PCB board 10C along the width direction, generating an airflow that can remove heat. The airflow blows from one side of the PCB board 10C along the width direction to the other side, preventing heat from the first region 11C from dissipating to the second region 12C. This prevents high temperatures from affecting the connector 30C, protects the wafer-level burn-in test fixture 100C, and improves the accuracy of the wafer-level burn-in test.

[0145] In this embodiment, the wafer-level aging test fixture 100C further includes a structural member 80C located on top of the PCB board 10C and connected to the upper sealing cover 50C. The wafer-level aging test fixture 100C further includes a plurality of reinforcement members 90C located on top of the PCB board 10C. The plurality of reinforcement members 90C are respectively arranged around the structural member 80C, at the edge of the PCB board 10C, and in the second area 12C. Here, the reinforcement members 90C are connected by screws around the PCB board 10C and between adjacent groups of connectors 30C in the second area 12C, thereby improving the structural strength of the wafer-level aging test fixture 100C. The structural member 80C is simultaneously connected to the reinforcement members 90C on the first area 11C and the PCB board 10C, and can provide strength to the stress-bearing parts of the PCB board 10C.

[0146] Figure 27 is a schematic structural diagram of a lifting mechanism 400C according to one embodiment of the present invention. As shown in Figure 27 , this embodiment also provides a wafer-level burn-in test apparatus, comprising a wafer-level burn-in test fixture 100C and a lifting mechanism 400C. The lifting mechanism 400C is configured to controllably extend and retract upward. The lifting mechanism 400C flexibly engages the wafer-level burn-in test fixture 100C, driving the lower sealing assembly 120C upward until it connects with the cover assembly 110C to form a test chamber 121C.

[0147] Before using the wafer-level aging test fixture 100C of the present invention, the connector 30C is first connected to the external test device 200C and the hardware circuit. When the wafer-level aging test fixture 100C is in operation, the cover assembly 110C is connected to the lower sealing assembly 120C to form an airtight test chamber 121C to perform a wafer-level aging test on the wafer. Specifically, the wafer is placed in a specific position in the test chamber 121C, the cover assembly 110C does not move, and the lower sealing assembly 120C is lifted upward from the bottom of the test needle holder 20C until the sealing ring 122C of the lower sealing assembly 120C is connected to the PCB board 10C and is slightly compressed to form an airtight test chamber 121C.

[0148] During the lifting process of the lower sealing component 120C, the test probe 21C on the test needle holder 20C will pierce the test point at a specific position on the surface of the wafer. The test probe 21C is a spring probe and will compress to a certain stroke. The needle tip of the test probe 21C contacts the surface of the wafer and generates a certain pressure, forming a circuit for power-on aging and testing of the wafer. At this time, the wafer can be powered on for aging and testing. The lower sealing component 120C, the PCB board 10C and the upper sealing cover 50C together form an airtight space, which can be filled with a specific compressed gas to protect the wafer. During high-voltage testing, the compressed gas can prevent high-voltage arcs from damaging the test probe 21C or the wafer.

[0149] Figure 28 is a schematic structural diagram of a heating device according to an embodiment of the present invention, Figure 29 is a schematic cross-sectional view of a heating device according to an embodiment of the present invention, Figure 30 is a schematic partial enlarged view of point A in Figure 29, Figure 31 is a schematic cross-sectional view of a heating device according to an embodiment of the present invention from another angle, and Figure 32 is a schematic partial enlarged view of point B in Figure 31. In some embodiments, as shown in Figures 28 to 32, the present invention provides a wafer-level burn-in test fixture 400D. The wafer-level aging test fixture 400D includes a cover assembly 80D, a lower sealing assembly 210D, and a heat sink 230D for carrying a wafer 300D. The cover assembly 80D is connected to the lower sealing assembly 210D to form a test cavity 211D. The heat sink 230D is located in the test cavity 211D. The heating device 100D is located in the test cavity 211D. The heat sink 230D is stacked above the heating device 100D. The heating device 100D is electrically connected to the electrical component 226D located below the lower sealing assembly 210D. The heating device 100D includes a heating film layer 10D and has uniformly arranged resistance wires 11D. and at least one powered interface 12D connected to the resistance wire 11D, the heating film layer 10D is arranged on the side of the heat sink 230D away from the wafer 300D to heat the wafer 300D through the heat sink 230D, the connecting component 20D includes at least one group of first connecting probe groups 21D passing through the lower sealing component 210D, one end of any first connecting probe group 21D is in contact with the corresponding powered interface 12D, and the other end passes through the lower sealing component 210D and contacts the electrical component 226D, so that the electrical component 226D supplies power to heat the heating film layer 10D, thereby heating the wafer 300D on the heat sink 230D.

[0150] The heating film layer 10D contacts the lifting mechanism 220D through the first connection probe group 21D, so that the lifting mechanism 220D supplies power to the resistance wire 11D inside the heating film layer 10D, so that the heating film layer 10D is evenly conductively heated through the power interface 12D, thereby achieving uniform heating of the wafer 300D by the heating device 100D, thereby preventing the wafer 300D from being damaged or affecting the test effect due to uneven heating. Here, the test chamber 211D of the lower sealing cover assembly 210D is sequentially provided with the wafer 300D, the heat sink 230D, and the heating device 100D from top to bottom. The number of the first connection probe group 21D can be one or more, and the number of the power interface 12D can be one or more.

[0151] As shown in FIG30 , in this embodiment, uniformly arranged resistance wires 11D are provided within the heating film layer 10D, and a first connection probe group 21D is used to electrically connect and heat the resistance wires 11D, thereby achieving uniform heating of the wafer 300D on the heat sink 230D by the heating film layer 10D, thereby preventing damage to the wafer 300D due to uneven heating and improving the yield rate of the wafer 300D. Here, the heating film layer 10D is connected to the lifting mechanism 220D via the first connection probe group 21D to achieve conductive heating. The heat transfer path is sequentially through the heating film layer 10D, the heat sink 230D, and the wafer 300D. This can prevent the wafer 300D from being damaged by direct contact with the heating device 100D, thereby reducing the defective rate of the wafer 300D.

[0152] In this embodiment, the heating film layer 10D of the heating device 100D has evenly arranged resistance wires 11D and at least one power interface 12D connected to the resistance wires 11D. The first connecting probe group 21D is directly connected to the resistance wire 11D through the power interface 12D to achieve uniform heating of the heating film layer 10D, avoiding the need to set up multiple probe assemblies corresponding to multiple heating plates, thereby simplifying the structure of the heating device 100D.

[0153] In this embodiment, the heating film layer 10D is a mica heater or a ceramic heater. Specifically, resistance wires 11D are evenly distributed within the mica heater or ceramic heater, allowing the lifting mechanism 220D to connect to the resistance wires 11D via the first connection probe assembly 21D. This conducts conductive heating on the mica heater or ceramic heater, thereby uniformly heating the wafer 300D positioned above the heating device 100D. The dimensions of the mica heater or ceramic heater are consistent with those of the heat sink 230D, enabling the heating device 100D to uniformly heat the heat sink 230D, thereby uniformly heating the wafer 300D.

[0154] In a preferred embodiment, the heating film layer 10D is a mica heating sheet. The preparation cost of the mica heating sheet is relatively low, thereby reducing the manufacturing cost of the heating device 100D.

[0155] In this embodiment, the heating device 100D further includes a first thermal insulator 30D positioned below the heat sink 230D. The heating film 10D and the first thermal insulator 30D are integrated. Specifically, the first thermal insulator 30D is integrated with the heating film 10D and positioned at the bottom of the heating film 10D. This prevents the heating film 10D from directly contacting the lower sealing cover assembly 210D when heated to a high temperature, thereby preventing damage to the wafer-level burn-in test apparatus 200D.

[0156] In this embodiment, the heating film layer 10D is located on a side of the first thermal insulation member 30D near the heat sink 230D. The first thermal insulation member 30D is provided with a first through-hole 31D at a position corresponding to the power supply interface 12D, so that any first connection probe group 21D can pass through the first through-hole 31D and contact the power supply interface 12D. Specifically, the heating film layer 10D and the first thermal insulation member 30D are integrated into one body. The first connection probe group 21D is connected to the power supply interface 12D of the heating film layer 10D through the first through-hole 31D of the first thermal insulation member 30D, so that the lifting mechanism 220D is in contact with the resistance wire 11D inside the heating film layer 10D, thereby conducting heat to the heating film layer 10D, thereby achieving uniform heating of the wafer 300D by the heating film layer 10D. Here, there are two first through holes 31D and two first connection probe groups 21D. Each first through hole 31D corresponds to one first connection probe group 21D, and the two first through holes 31D are symmetrically arranged about the center line of the first thermal insulation member 30D.

[0157] In this embodiment, a second thermal insulation member 40D is also included. The second thermal insulation member 40D is located on the side of the first thermal insulation member 30D away from the heat sink 230D. The second thermal insulation member 40D has a second through-hole 41D corresponding to the first through-hole 31D. Any first connection probe group 21D passes through the first through-hole 31D and the second through-hole 41D to contact the power interface 12D. Specifically, a second thermal insulation member 40D is further provided below the first thermal insulation member 30D to isolate the heat of the heating film layer 10D. Here, the number of second through-holes 41D is two. One end of each first connection probe group 21D passes through the first through-hole 31D to contact and connect with the power interface 12D of the heating film layer 10D, and the other end passes through the second through-hole 41D to contact and connect with the power interface 12D of the heating film layer 10D, so that the heating device 100D is connected to the lifting mechanism 220D through the first connection probe group 21D, so that the heating film layer 10D is conductively heated, thereby heating the wafer 300D.

[0158] In this embodiment, the heating device 100D further includes a ceramic plate 50D, which is positioned between the heating film layer 10D and the heat sink 230D and is configured to transfer heat generated by the heating film layer 10D to the heat sink 230D. Specifically, the ceramic plate 50D is positioned between the heating film layer 10D and the heat sink 230D, and the dimensions of the ceramic plate 50D are consistent with those of the heating film layer 10D and the heat sink 230D. This allows the ceramic plate 50D to evenly transfer heat from the heating film layer 10D to the heat sink 230D, and then to the wafer 300D, thereby preventing the heating film layer 10D from directly contacting the heat sink 230D, which could cause overheating of the heat sink 230D and thus damage to the wafer 300D.

[0159] As shown in FIG32 , in this embodiment, the heating device 100D further includes at least one first temperature sensor 60D and at least one second connection probe group 22D. The first temperature sensor 60D is disposed at the heating film layer 10D and is used to detect the temperature of the heating film layer 10D. Each second connection probe group 22D corresponds to one first temperature sensor 60D and passes through the lower sealing cover assembly 210D. One end of the second connection probe group 22D contacts the first temperature sensor 60D, and the other end contacts the lifting mechanism 220D. Specifically, the second connection probe group 22D is used to connect the first temperature sensor 60D located at the heating film layer 10D and the lifting mechanism 220D, so that the first temperature sensor 60D can detect the temperature of the heating film layer 10D in real time, thereby preventing the heating film layer 10D from causing irreversible damage to the heat sink 230D and the wafer 300D when the temperature is too high. At the same time, it can also prevent the lifting mechanism 220D located below the lower sealing cover assembly 210D from being damaged due to overheating. Here, there are two first temperature sensors 60D and two second connection probe groups 22D. Each first temperature sensor 60D corresponds to one second connection probe group 22D. The two second connection probe groups 22D are respectively the main temperature control test probe group and the overheating protection probe group of the heating film layer 10D.

[0160] In this embodiment, the heating device 100D also includes a second temperature sensor 70D and a third connection probe group 23D. The second temperature sensor 70D is arranged at the heat sink 230D for detecting the temperature of the heat sink 230D. Each third connection probe group 23D corresponds to a second temperature sensor 70D, and passes through the lower sealing cover assembly 210D, the second thermal insulation member 40D, the first thermal insulation member 30D, the heating film layer 10D and the ceramic plate 50D in sequence. One end of the third connection probe group 23D contacts the second temperature sensor 70D, and the other end contacts the lifting mechanism 220D, so that the second temperature sensor 70D detects the temperature of the heat sink 230D when it is powered on, so as to avoid the heat sink 230D from being overheated and damaging the wafer 300D, thereby improving the yield of the wafer 300D.

[0161] In this embodiment, the heating device 100D also includes a fourth connection probe group 24D that is in direct contact with the heat sink 230D. Each fourth connection probe group 24D passes through the lower sealing cover assembly 210D, the second thermal insulation member 40D, the first thermal insulation member 30D, the heating film layer 10D and the ceramic plate 50D in sequence until it abuts against the heat sink 230D. One end of the fourth connection probe group 24D is in contact with the heat sink 230D, and the other end is in contact with the lifting mechanism 220D, so that the lifting mechanism 220D powers on the heat sink 230D, thereby performing power-on testing on the wafer 300D.

[0162] FIG33 is a schematic structural diagram of a wafer-level burn-in test apparatus according to one embodiment of the present invention, FIG34 is a schematic cross-sectional view of a portion of the structure of the wafer-level burn-in test apparatus according to one embodiment of the present invention, and FIG35 is a schematic partial enlarged view of point C in FIG34 . As shown in FIG33 to FIG35 , the present invention further provides a wafer-level burn-in test apparatus 200D, comprising a wafer-level burn-in test fixture 400D and a lifting mechanism 220D. The lifting mechanism 220D comprises a lifting assembly 225D and an electrical assembly 226D. The electrical assembly 226D is disposed at the free end of the lifting assembly 225D. The electrical assembly 226D is configured to, when connected to the wafer-level burn-in test fixture 400D, energize the heating device 100D to heat the wafer 300D for wafer-level burn-in testing.

[0163] Specifically, the wafer-level burn-in test apparatus 200D of this embodiment includes a lower sealing cover assembly 210D. A wafer 300D, a heat sink 230D, and a heating device 100D are sequentially arranged from top to bottom within a test chamber 211D of the lower sealing cover assembly 210D. A lifting mechanism 220D is disposed below the lower sealing cover assembly 210D to energize the heating film layer 10D. In other words, the two ends of a first connection probe group 21D within the heating device 100D are connected to the lifting mechanism 220D and the heating film layer 10D, respectively, to electrically heat the heating film layer 10D, thereby heating the heat sink 230D and the wafer 300D located above the heat sink 230D, thereby enabling the wafer-level burn-in test apparatus 200D to perform a high-temperature wafer-level burn-in test on the wafer 300D.

[0164] In this embodiment, the surface of the lifting mechanism 220D facing the wafer-level burn-in test fixture is provided with at least one first pad position 221D. Each first connection probe group 21D of the heating device 100D passes through the lower sealing cover assembly 210D and contacts a first pad position 221D, so that the electrical component 226D can power the heating film layer 10D. Specifically, the first connection probe group 21D passes through the lower sealing cover assembly 210D and contacts the first pad position at the top of the lifting mechanism 220D, so that the lifting mechanism 220D can power and heat the heating film layer 10D. Here, there are two first pad positions 221D, each of which is arranged corresponding to one power interface 12D of the heating film layer 10D.

[0165] In this embodiment, at least one second pad position 222D is provided on the top of the lifting mechanism 220D. One end of each second connection probe group 22D of the heating device 100D passes through the lower sealing cover assembly 210D and contacts a second pad position 222D, and the other end contacts the first temperature sensor 60D inside the heating film layer 10D. This allows the lifting mechanism 220D to power the first temperature sensor 60D and detect the temperature of the heating film layer 10D in real time, preventing the heating film layer 10D from overheating and damaging other structures of the wafer-level burn-in test device 200D. Here, there are two second pad positions 222D, each of which is arranged corresponding to a first temperature sensor 60D of the heating film layer 10D.

[0166] In this embodiment, a third Pad position 223D is provided on the top of the lifting mechanism 220D, one end of the third connecting probe group 23D of the heating device 100D passes through the lower sealing cover assembly 210D and contacts a third Pad position 223D, and the other end contacts the second temperature sensor 70D inside the heat sink 230D, so that the lifting mechanism 220D supplies power to the second temperature sensor 70D and detects the temperature of the heat sink 230D in real time, thereby preventing the heat sink 230D from being overheated and damaging the wafer 300D.

[0167] In this embodiment, a fourth Pad position 224D is provided on the top of the lifting mechanism 220D, one end of the fourth connection probe group 24D of the heating device 100D passes through the lower sealing cover assembly 210D and contacts a fourth Pad position 224D, and the other end contacts the heat sink 230D, so that the lifting mechanism 220D powers on the heat sink 230D, thereby performing power-on testing on the wafer 300D.

[0168] In this embodiment, the number of first pad positions 221D is consistent with the number of first connection probe groups 21D, and they correspond one to one. Specifically, each first pad position 221D corresponds to a first connection probe group 21D, so that each power supply interface 12D of the heating film layer 10D is arranged corresponding to a first connection probe group 21D. This allows the two power supply interfaces 12D of the heating film layer 10D to be heated simultaneously by electrical conduction, thereby improving the heating efficiency of the heating film layer 10D.

[0169] The heating device 100D of this embodiment includes a heating film layer 10D and a connecting component 20D. The heating film layer 10D has uniformly arranged resistance wires 11D and at least one power interface 12D connected to the resistance wires 11D. The heating film layer 10D is arranged on the side of the heat sink 230D away from the wafer 300D to heat the wafer 300D through the heat sink 230D. The connecting component 20D includes at least one group of first connecting probes 21D passing through the lower sealing component 210D. Any first connecting probe group 21D One end of the probe group 21D contacts the corresponding power interface 12D, and the other end passes through the lower sealing component 210D and contacts the electrical component 226D, so that the electrical component 226D supplies power to the heating film layer 10D for heating, thereby heating the wafer 300D on the heat sink 230D. The heating film layer 10D having the evenly distributed resistance wire 11D can evenly heat the wafer 300D, preventing the wafer 300D from being damaged due to uneven heating, thereby improving the yield rate of the wafer 300D. In addition, the heating device 100D of the present invention also includes a ceramic plate 50D, which is located between the second thermal insulation member 40D and the heat sink 230D and is used to transfer the heat generated by the heating film layer 10D to the heat sink 230D, thereby preventing the heating device 100D from being locally overheated when it is in direct contact with the wafer 300D, thereby reducing the defective rate of the wafer 300D during the wafer-level aging test.

[0170] At this point, those skilled in the art will recognize that, although a number of exemplary embodiments of the present invention have been shown and described in detail herein, many other variations or modifications consistent with the principles of the present invention may be directly determined or derived from the disclosure of the present invention without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention should be understood and deemed to cover all such other variations or modifications.

Claims

1. A wafer-level aging test device, comprising: A wafer-level aging test fixture comprises a cover plate assembly, a lower sealing assembly, a heat sink and a heating device, wherein the heat sink is used to carry the wafer; The cover assembly includes a first PCB board and a test needle holder connected to the first PCB board; the lower sealing assembly includes a lower sealing cover, the lower sealing cover is connected to the cover assembly to form a test cavity, the heat sink and the heating device are located in the test cavity, and the heating device is located between the lower sealing cover and the heat sink; A lifting mechanism is configured to extend and retract up and down in a controlled manner, and the lifting mechanism is movably abutted against the wafer-level aging test fixture to drive the lower sealing assembly to move upward and connect with the cover assembly to form the test chamber.

2. The wafer-level aging test device according to claim 1, wherein: The lifting mechanism includes a lifting component and an electrical component. The electrical component is arranged at the free end of the lifting component. The electrical component is movably connected to the lower sealing component. The electrical component is configured to power the heating device and the heat sink, thereby performing a wafer-level aging test on the wafer.

3. The wafer-level aging test device according to claim 2, wherein: The heating device comprises: A heating film layer having uniformly arranged resistance wires and at least one energizing interface connected to the resistance wires; At least one group of first connection probe groups passes through the lower sealing cover, and one end of each of the first connection probe groups contacts one of the power-on interfaces, and the other end contacts the electrical component, so that the electrical component energizes the heating film layer, thereby heating the wafer on the heat sink.

4. The wafer-level aging test device according to claim 3, wherein: The electrical components include: A second PCB board is connected to an external circuit. At least one first Pad position is provided on the top of the second PCB board. Each of the first Pad positions is arranged corresponding to one of the first connection probe groups, so that when the first connection probe group comes into contact with the external circuit, the heating device is powered through the second PCB board, thereby performing a heating test on the wafer.

5. The wafer-level aging test device according to claim 4, wherein: The lower sealing cover is also provided with at least one second connection probe group in contact with the heat sink; At least one second Pad position is further provided on the top of the second PCB board, and each of the second Pad positions is arranged corresponding to one of the second connection probe groups, so that when the second connection probe group is in contact, the external circuit powers the heat sink through the second PCB board, thereby performing a power-on test on the wafer; wherein a plurality of first air holes are provided on the bottom of the lower sealing cover, a plurality of second air holes are provided on the second PCB board, and each of the second air holes corresponds to one of the first air holes, and the electrical component further comprises: The adapter plate is arranged below the second PCB board, and the adapter plate has an air channel connected with the plurality of second air holes, so that the external air path can evacuate the lower sealing cover through the air channel, the second air holes and the first air holes, thereby adsorbing the heat sink and the wafer.

6. The wafer-level aging test device according to any one of claims 1 to 5, wherein: The first PCB board includes a first interface group and a second interface group, and the test needle seat includes a plurality of test probes; The first interface group is arranged on the first side of the first PCB board facing the lower sealing assembly, one end of any of the test probes is connected to the corresponding first interface included in the first interface group, and the other end is connected to the wafer, so as to perform a wafer-level aging test on the wafer; The second interface group is arranged on any second side surface of the first PCB board except the first side surface; The wafer-level aging test fixture further includes: Multiple connectors are installed on the second side of the first PCB board, any of the connectors is connected to the corresponding second interface included in the second interface group, and any of the connectors is connected to an external testing device through a wiring harness, for performing wafer-level aging test on the wafer.

7. The wafer-level aging test device according to any one of claims 1 to 5, further comprising a mounting bracket, wherein the mounting bracket comprises: Base plate assembly; A supporting platform for supporting the lower sealing assembly; A pair of first slide grooves connected to the bottom plate assembly, any of the first slide grooves extending in the horizontal direction, two ends of the support platform are respectively slidably connected to the corresponding first slide grooves, and the lower sealing assembly moves along the extension direction of the first slide grooves driven by the support platform; When loading or unloading wafers, the lower sealing assembly slides out of the mounting bracket along the first slide groove; After the wafer loading or unloading is completed, the lower sealing assembly is retracted into the mounting bracket along the first slide groove.

8. The wafer-level aging test device according to claim 7, wherein: The mounting bracket also includes: A top plate assembly connected to the bottom plate assembly via a plurality of struts; A pair of second slide grooves are connected to the top plate assembly, any one of the second slide grooves extends in the horizontal direction, and both ends of the cover plate assembly are respectively slidably connected to the corresponding second slide grooves.

9. The wafer-level aging test device according to claim 1, further comprising: The mounting bracket comprises a top plate assembly and a bottom plate assembly, wherein the top plate assembly and the bottom plate assembly are connected by pillars, the wafer-level aging test fixture is arranged below the top plate assembly and connected to the top plate assembly, and the lifting mechanism is mounted on the bottom plate assembly; as well as A floating mechanism is arranged at the top plate assembly, and the floating mechanism is arranged to float when the cover plate assembly is squeezed by the lower sealing cover, so as to avoid deformation of the cover plate assembly.

10. The wafer-level aging test device according to claim 9, wherein: The top plate assembly comprises an upper cover plate and a lower cover plate, the lower cover plate has a limiting groove, and the floating mechanism comprises: A floating plate, arranged on the top of the cover plate assembly and located at the limiting groove, the floating plate protruding from the bottom of the lower cover plate; The telescopic assembly is connected to the upper cover plate, and the bottom is connected to or abuts against the floating plate, so that when the floating plate is squeezed by the cover plate assembly, the floating plate is compressed to move upward.

11. The wafer-level aging test device according to claim 10, wherein: The floating plate is circular and arranged opposite to the test needle seat; The size of the floating plate is larger than that of the test needle seat and smaller than that of the lower sealing cover.

12. The wafer-level aging test device according to claim 11, wherein: The bottom of the upper cover plate is provided with at least one first mounting groove, the top of the floating plate is provided with at least one second mounting groove, each of the second mounting grooves corresponds to one of the first mounting grooves, and the telescopic assembly includes: At least one elastic member, each of the elastic members is correspondingly arranged in one of the first mounting groove and the second mounting groove; Optionally, there are a plurality of elastic members, and the plurality of elastic members are evenly arranged on the top of the floating plate.

13. The wafer-level aging test device according to any one of claims 9 to 12, wherein: The lifting mechanism comprises: An electrical component, comprising a second PCB board, the top of the second PCB board having a pad position for supplying power to the heating device and the heat sink, so as to perform a wafer-level aging test on the wafer; and A lifting assembly, wherein the electrical assembly is arranged at the free end of the lifting assembly, and the lifting assembly is used to drive the electrical assembly to move upward so that the pad position cooperates with the lower sealing cover and drives the lower sealing cover to move upward until it is connected with the cover plate assembly to form the test cavity.

14. The wafer-level aging test device according to claim 13, wherein: The lifting assembly comprises: A plurality of turbine worm components, respectively connected to the electrical components; The motor is connected to the plurality of worm gear assemblies to drive the plurality of worm gear assemblies to drive the electrical assembly to move up and down.

15. A wafer-level aging test system, wherein: The wafer-level aging test system comprises loading and unloading equipment, at least one test instrument, and at least one wafer-level aging test device according to any one of claims 1 to 14; The loading and unloading equipment is used to place the wafer in the corresponding wafer-level aging test device to perform a wafer-level aging test; Any of the wafer-level aging test devices is connected to the corresponding test instrument to perform a wafer-level aging test.

16. A testing method for the wafer-level aging testing device according to any one of claims 1 to 8, comprising the following steps: After the wafer loading is completed, the lifting mechanism is controlled to rise to a first height so that the lifting mechanism is connected to the lower sealing assembly; Controlling the lifting mechanism to continue to drive the lower sealing assembly to rise to a second height, so that the lower sealing assembly moves to connect with the cover assembly to form a test cavity; The heating device, the heat sink and the test pin holder included in the cover assembly are powered on to perform a wafer-level aging test on the wafer.

17. A wafer-level aging test fixture, comprising a cover plate assembly and a lower sealing assembly, wherein the cover plate assembly and the lower sealing assembly are connected to form a test cavity for accommodating wafers.

18. The wafer-level aging test fixture according to claim 17, wherein: The cover plate assembly comprises: A PCB board, comprising a first area and a second area, wherein the first area and the second area are respectively located on different sides of the PCB board, and any first contact point arranged in the first area is electrically connected to a corresponding second contact point arranged in the second area; A test needle holder, located at the bottom of the PCB board and connected to the PCB board, the test needle holder having a plurality of test probes, one end of any of the test probes contacts the corresponding first contact point, and the other end contacts the wafer, so as to perform a wafer-level aging test on the wafer; At least one connector is installed at the second area of ​​the PCB board, any one of the connectors is connected to the corresponding second contact, and any one of the connectors is connected to an external testing device through a wiring harness for performing a wafer-level aging test on the wafer.

19. The wafer-level aging test fixture according to claim 18, wherein: There are multiple connectors, and the multiple connectors are arranged on the PCB in an array; The test needle holder is circular, and the wafer-level aging test fixture further includes: A connecting piece, which is ring-shaped and connected to the PCB board, is arranged around the periphery of the test needle holder and is connected to the test needle holder; At least one groove is provided at the edge of the test needle holder; The connector has a supporting portion for supporting the test needle seat, and at least one positioning column is provided on the supporting portion. Each positioning column is arranged corresponding to one of the grooves to position the test needle seat, wherein the groove opening is arranged toward the corresponding positioning column.

20. The wafer-level aging test fixture according to claim 19, further comprising a circular upper sealing cover, the upper sealing cover being located on the top of the PCB board; and a plurality of load-bearing components spaced apart and arranged along the circumference of the upper sealing cover, each of the load-bearing components comprising: A load-bearing column, passing through the PCB board and connected to the upper sealing cover, the load-bearing column protruding from the bottom surface of the PCB board, and the height of the load-bearing column protruding from the bottom surface of the PCB board is any value in the range of 0.1 mm to 0.2 mm; and At least one gasket is sleeved on the load-bearing column to adjust the height of the load-bearing column protruding from the bottom surface of the PCB board.

21. The wafer-level aging test fixture according to any one of claims 18 to 20, further comprising: A heat dissipation component is mounted on the PCB board, and the heat dissipation component is located between the first area and the second area, and is used to isolate the heat generated by the first area.

22. The wafer-level aging test fixture according to claim 20, further comprising a structural member located on the top of the PCB board and connected to the upper sealing cover; the wafer-level aging test fixture further comprises: A plurality of reinforcing members are located on the top of the PCB board, and the plurality of reinforcing members are respectively arranged on the peripheral side of the structural member, the edge of the PCB board and the second area.

23. The wafer-level aging test fixture according to claim 17, further comprising a heat sink for carrying wafers, and a heating device, wherein the heat sink and the heating device are located in the test chamber, the heat sink is stacked above the heating device, the heating device is electrically connected to an electrical component located below the lower sealing component, and the heating device comprises: A heating film layer, comprising uniformly arranged resistance wires and at least one energized interface connected to the resistance wires, wherein the heating film layer is disposed on a side of the heat sink away from the wafer so as to heat the wafer through the heat sink; The connecting component includes at least one first connecting probe group passing through the lower sealing cover component, one end of any first connecting probe group contacts the corresponding power-on interface, and the other end passes through the lower sealing component and contacts the electrical component, so that the electrical component supplies power to heat the heating film layer.

24. The wafer-level aging test fixture according to claim 23, wherein: The heating film layer is a mica heating sheet or a ceramic heating sheet; The wafer-level aging test fixture further includes: A first thermal insulation member is located below the heat sink, and the heating film layer is integrated with the first thermal insulation member; The heating film layer is located on a side of the first thermal insulation member close to the heat sink. The first thermal insulation member is provided with a first through hole corresponding to the power interface, so that any of the first connection probe groups can pass through the first through hole and contact the power interface.

25. The wafer-level aging test fixture according to claim 24, further comprising: A second thermal insulation member is located at a side of the first thermal insulation member away from the heat sink, the second thermal insulation member has a second through hole corresponding to the first through hole, and any of the first connection probe groups passes through the first through hole and the second through hole to contact the power-on interface; as well as The ceramic plate is located between the heating film layer and the heat sink and is used to transfer the heat generated by the heating film layer to the heat sink.

26. The wafer-level aging test fixture according to any one of claims 23 to 25, further comprising: At least one temperature sensor, disposed at the heating film layer, for detecting the temperature of the heating film layer; At least one second connection probe set, any of which corresponds to one temperature sensor and passes through the lower sealing cover assembly, one end of the second connection probe set contacts the temperature sensor, and the other end contacts the lifting mechanism.

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