Chip package structure

Abstract

A chip package structure, comprising: an isolation frame (10), a first, a second, a third and a fourth base island, a first and a second substrate, and a first, a second, a third and a fourth chip. The first, second, third and fourth base islands are distributed in a matrix in a closed area formed by the isolation frame (10), are not connected to each other, and are soldered to the isolation frame (10) by means of a plurality of frame bonding pads (103) provided on the inner sides of frame edges of the isolation frame (10); the first and second substrates are respectively arranged on the first and second base islands, and are connected to the frame bonding pads (103) by means of first and second bonding wires; the first and second chips are flip chips respectively arranged on the first and second substrates; the third and fourth chips are wire bonding chips respectively arranged on the third and fourth base islands, and are connected to the frame bonding pads (103) by means of third and fourth bonding wires; a plastic package body (40) is provided in a space formed by the isolation frame (10) and wraps the first, second, third and fourth chips and the plurality of frame bonding pads (103). Arranging the flip and wire bonding chips on the separate base islands, and implementing plastic packaging and trimming achieve complete electrical isolation.

Description

Chip packaging structure Technical Field

[0001] The utility model relates to the technical field of semiconductor packaging, in particular to a chip packaging structure. Background Art

[0002] Chip projects involving high-frequency signals, built-in antennas, and complex peripheral circuits typically utilize substrate packaging solutions. Standard substrate manufacturing processes typically lack trenching, and the isolation performance of the substrate material is relatively weak, making it difficult to achieve electrical isolation that meets standard requirements. Furthermore, uneven grounding on the substrate directly impacts the chip's isolation performance, while uneven grounding can lead to substrate warping, posing risks to both process feasibility and reliability. Therefore, traditional substrate packaging solutions struggle to meet the demands of chips that combine complex circuit designs with isolation and voltage withstand requirements.

[0003] To achieve isolation performance that meets standard requirements, current isolation devices generally utilize a traditional packaging solution combining a frame and wire bonding. This solution achieves electrical isolation by adding an isolation layer between the chip and substrate, ensuring signal stability and reliability. However, due to the inherent resistance and inductance of wire bonding, high-frequency signal transmission can result in significant energy loss and signal distortion, leading to reduced signal quality. Furthermore, the complex structure of the peripheral circuitry makes it difficult to arrange the isolation layer, further limiting the application of traditional packaging solutions. This solution cannot meet design requirements for high-frequency signals and built-in antennas.

[0004] Utility Model Content

[0005] The technical problem to be solved by the utility model is to provide a chip packaging structure.

[0006] In order to solve the above technical problems, a technical solution adopted by the present invention is: a chip packaging structure, comprising: an isolation frame, a first base island, a second base island, a third base island, a fourth base island, a first substrate, a second substrate, a first chip, a second chip, a third chip, and a fourth chip; a plurality of frame pads are distributed on the inner side of the side frame of the isolation frame; the first base island, the second base island, the third base island and the fourth base island are distributed in a matrix in a closed area formed by the isolation frame, and are not connected to each other, and are welded to the isolation frame by welding with corresponding frame pads; the first substrate is arranged on the first base island, and is welded to the isolation frame by welding with corresponding frame pads; The first chip is flip-chip arranged on the first substrate; the second substrate is arranged on the second base island and connected to the corresponding frame pad through the second welding wire; the second chip is flip-chip arranged on the second substrate; the third chip is upright arranged on the third base island and connected to the corresponding frame pad through the third welding wire; the fourth chip is upright arranged on the fourth base island and connected to the corresponding frame pad through the fourth welding wire; the plastic package is arranged inside the space formed by the isolation frame, wrapping the first chip, the second chip, the third chip, the fourth chip and a number of frame pads.

[0007] Among them, one end of the frame pad is fixedly connected to the isolation frame, and the other end is a suspended free end; the first base island, the second base island, the third base island and the fourth base island are all welded through the free ends of the corresponding frame pads, thereby being welded to the isolation frame.

[0008] The first base island and the second base island are arranged side by side in the closed area formed by the isolation frame, and are both adjacent to the first side frame of the isolation frame; the third base island and the fourth base island are arranged side by side in the closed area formed by the isolation frame, and are both adjacent to the second side frame of the isolation frame; the first side frame and the second side frame of the isolation frame are two opposite frames.

[0009] Among them, a plurality of first substrate pads are further provided on the first substrate for welding with corresponding frame pads through first welding wires; a plurality of second substrate pads are further provided on the second substrate for welding with corresponding frame pads through second welding wires.

[0010] A cutting line is provided along the inner edge of the isolation frame and away from the free end of the frame pad, for cutting a separate flip chip package and a face-up chip package along the cutting line on the package body after chip packaging is completed through a cutting process.

[0011] Among them, the antenna, high-frequency wiring and complex peripheral circuits are integrated on the first substrate and the second substrate.

[0012] Wherein, the third chip and the fourth chip are both low-speed signal and power supply circuits.

[0013] The beneficial effects of the present invention are as follows: the chip packaging structure provided by the present invention physically isolates the upright chip and the flip-chip by flip-chipping the first chip on the first base island where the first substrate is provided, flip-chipping the second chip on the second base island where the second substrate is provided, upright mounting the third chip on the third base island, and upright mounting the fourth chip on the fourth base island; further, through traditional packaging processes such as plastic sealing and rib cutting, the complete electrical isolation of the above-mentioned base island isolation frame units is achieved. By utilizing the present invention, direct wire bonding is used to connect chips with simple circuits or low signal requirements, which can reduce packaging costs and meet the requirements of product antennas, high-frequency signals, and complex peripheral routing designs, thereby achieving the complete electrical isolation performance required by enhanced isolation devices; further, the number of base islands for placing substrates and chips, as well as main components such as substrates and chips, distributed in the package body is not limited and can be modified according to the circuit design, so that the package body of the present invention has good scalability. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG1 is a schematic diagram of a package structure of a chip package structure according to an embodiment of the present invention;

[0015] FIG2 is a top view of FIG1 ;

[0016] FIG3 is a cross-sectional view along line AA of FIG2 .

[0017] Reference numerals: Chip package 1 Isolation frame 10 First side frame 101 Second side frame 102 Frame pad 103 First base island 11 Second base island 12 Third base island 13 Fourth base island 14 First substrate 21 First substrate pad 210 Second substrate 22 Second substrate pad 220 First chip 31 Second chip 32 Third chip 33 Fourth chip 34 Plastic package 40 Cutting line 50 First welding wire 61 Second welding wire 62 Third welding wire 63 Fourth welding wire 64 DETAILED DESCRIPTION

[0018] First, the prior art terms that appear in this utility model are explained.

[0019] Wire bonding is a semiconductor assembly process that involves attaching metal wires (usually gold or aluminum) to the contact points of a semiconductor device. These wires are bonded to the contact points using specialized tools called wire bonders. This process is used to create electrical connections between different parts of a semiconductor device, such as between a chip and its lead frame, or between multiple chips in a single package. Wire bonding is a critical step in the manufacturing process for many electronic devices, including integrated circuits, sensors, and LEDs.

[0020] Wire bonding is a method of connecting microelectronic devices (such as transistors, integrated circuits, etc.) to PCBs (Printed Circuit Boards). In this technique, metal wires are soldered to the chip and then connected to the PCB or other devices.

[0021] Flip-chip substrate packaging is an advanced semiconductor packaging technology that flips the chip directly onto the substrate and connects the circuits via tiny solder joints, eliminating the traditional cable connections and pinout steps. This packaging method offers advantages such as high density, high performance, low power consumption, and high-speed signal transmission, making it suitable for high-end electronic products such as mobile phones, tablets, and servers. Flip-chip substrate packaging enables smaller and lighter product designs while improving product reliability and performance.

[0022] Plastic encapsulation is a method of protecting chips. It places the chip on a plastic substrate and covers it with plastic material to form a protective shell to prevent the chip from mechanical, thermal, and other damage. Plastic encapsulation can also improve the chip's reliability and anti-interference capabilities.

[0023] Rib cutting is the process of cutting individual chips from the packaged frame. This is typically performed using a diamond saw blade or laser cutter. Rib cutting requires high precision to ensure the exact size and position of each chip. Once rib cutting is complete, each chip can be used individually or placed into other packaged devices.

[0024] In order to explain the technical content, structural features, achieved objectives and effects of the present invention in detail, the present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0025] Please refer to Figures 1 to 3 for schematic diagrams of the three-dimensional structure of a chip package according to an embodiment of the present invention. The chip package 1 includes an isolation frame 10, a first base island 11, a second base island 12, a third base island 13, a fourth base island 14, a first substrate 21, a second substrate 22, a first chip 31, a second chip 32, a third chip 33, a fourth chip 34, and a plastic package 40.

[0026] The isolation frame 10 forms an approximately square closed area, and the first base island 11 , the second base island 12 , the third base island 13 and the fourth base island 14 are distributed in a matrix in the closed area formed by the isolation frame 10 .

[0027] Several frame pads 103 are distributed on the inner side of the side frame of the isolation frame 10 (located within the enclosed area). One end of each frame pad 103 is fixedly connected to the isolation frame 10, and the other end is a free end suspended in the air. The first base island 11, the second base island 12, the third base island 13, and the fourth base island 14 are each welded to the isolation frame 10 via the free ends of the corresponding frame pads 103. Furthermore, the first base island 11, the second base island 12, the third base island 13, and the fourth base island 14 are separated and not connected to each other.

[0028] Specifically, the first base island 11 and the second base island 12 are arranged side by side in the closed area formed by the isolation frame 10, and are adjacent to the first side frame 101 of the isolation frame 10; the third base island 13 and the fourth base island 14 are also arranged side by side in the closed area formed by the isolation frame 10, and are adjacent to the second side frame 102 of the isolation frame 10; wherein, the first side frame 101 and the second side frame 102 of the isolation frame 10 are two opposite frames.

[0029] The first substrate 21 is disposed on the first base island 11, and the second substrate 22 is disposed on the second base island 12. In this embodiment, antennas, high-frequency traces, and complex peripheral circuits can be integrated on the first substrate 21 and the second substrate 22 according to chip design requirements.

[0030] Furthermore, the first chip 31 is flip-chip mounted on the first substrate 21, the second chip 32 is flip-chip mounted on the second substrate 22, the third chip 33 is face-mounted on the third base island 13, and the fourth chip 34 is face-mounted on the fourth base island 14.

[0031] In this embodiment, the first chip 31 and the second chip 32 are flip chip chips; the third chip 33 and the fourth chip are wire bonding chips. The first chip 31 utilizes flip chip substrate packaging technology, with the chip placed face down on the first substrate 21 and connected to the circuitry on the first substrate 21 via chip solder joints, thereby mounting the first chip 31 on the first substrate 21. Similarly, the second chip 32 utilizes flip chip substrate packaging technology, with the chip placed face down on the second substrate 22 and connected to the circuitry on the second substrate 22 via chip solder joints, thereby mounting the second chip 32 on the second substrate. Flip chip substrate packaging technology is conventional and will not be described in detail here. The third chip 33 and the fourth chip 34 are both low-speed signal and power circuits and can be packaged using conventional methods, with the chips mounted face-down on the corresponding base islands. Specifically, the third chip 33 is mounted face-down on the third base island 13 and connected to the corresponding frame pads 103 via third bonding wires 63. The fourth chip 34 is mounted face-down on the fourth base island 14 and connected to the corresponding frame pads 103 via fourth bonding wires 64. Wirebonding packaging technology is conventional and will not be described in detail here.

[0032] With this setup, direct wire bonding can be used to connect chips with simple circuits or low signal requirements, thereby reducing packaging costs.

[0033] Furthermore, a plurality of first substrate pads 210 are provided on the first substrate 21 for welding with corresponding frame pads 103 via first welding wires 61 ; a plurality of second substrate pads 220 are provided on the second substrate 22 for welding with corresponding frame pads 103 via second welding wires 62 .

[0034] Thus, the first chip 31, the first substrate 21, and the first base island 11 form a complete frame-based island structure unit; the second chip 32, the second substrate 22, and the second base island 12 form a complete frame-based island structure unit; the third chip 33 and the third base island 13 form a complete frame-based island structure unit; and the fourth chip 34 and the fourth base island 14 form a complete frame-based island structure unit. Each frame-based island structure unit is connected to the corresponding frame pad 103 via a bonding wire.

[0035] As described above, in this embodiment, four base islands are distributed in the internal area formed by the isolation frame 10, two of which (i.e., the first base island 11 and the second base island 12) are used to place the substrate of the flip-chip, and the other two base islands are used to place the face-up chip.

[0036] In other embodiments, the number of islands, substrates, and chips distributed in the inner area formed by the isolation frame 10 can be adjusted according to circuit design requirements.

[0037] The plastic encapsulation body 40 is made of an insulating material and fills the space within the entire package structure. Its shape is rectangular, thereby completing the chip packaging. Specifically, the plastic encapsulation body 40 is disposed within the space formed by the isolation frame 10, encapsulating the first chip 32, the second chip 32, the third chip 33, the fourth chip 34, and the plurality of frame pads 103.

[0038] Furthermore, a cutting line 70 is provided along the inner edge of the isolation frame 10, away from the free end of the frame pad 103. This is used to cut individual island isolation frame units along the cutting line 50 from the package 1 after chip encapsulation, thereby obtaining a complete flip-chip package and a face-up chip package, thereby achieving complete electrical isolation of some circuits. Specifically, since the isolation frame 10 has several islands distributed within it for placing substrates and chips, and these islands are connected by several frame pads 103 distributed along the edge of the isolation frame 10, the cutting process severs these connection points, and these blocks will subsequently become independent islands, thus achieving excellent isolation performance.

[0039] As described above, the chip packaging structure provided by the present invention physically isolates the upright chip and the flip-chip by flip-chipping the first chip on the first base island where the first substrate is provided, flip-chipping the second chip on the second base island where the second substrate is provided, upright mounting the third chip on the third base island, and upright mounting the fourth chip on the fourth base island; further, through traditional packaging processes such as plastic encapsulation and rib cutting, complete electrical isolation of the above-mentioned base island isolation frame units is achieved. Utilizing the present invention, direct wire bonding can be used to connect chips with simple circuits or low signal requirements, thereby reducing packaging costs and meeting the requirements of product antennas, high-frequency signals, and complex peripheral routing designs, achieving the complete electrical isolation performance required by enhanced isolation devices; further, there is no limit to the number of base islands for placing substrates and chips, as well as major components such as substrates and chips, distributed within the package body, and these can be modified according to the circuit design, so that the package body of the present invention has good scalability.

[0040] The above description is only an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of the present invention, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A chip packaging structure, It is characterized in that include: An isolation frame, a first base island, a second base island, a third base island, a fourth base island, a first substrate, a second substrate, a first chip, a second chip, a third chip, and a fourth chip; A plurality of frame pads are distributed inside the side frame of the isolation frame; The first base island, the second base island, the third base island and the fourth base island are distributed in a matrix in a closed area formed by the isolation frame, are not connected to each other, and are welded to the isolation frame by welding with corresponding frame pads; The first substrate is arranged on the first base island and connected to the corresponding frame pad through a first bonding wire; the first chip is flip-chip arranged on the first substrate; The second substrate is arranged on the second base island and connected to the corresponding frame pad through a second bonding wire; the second chip is flip-chip arranged on the second substrate; The third chip is disposed upright on the third base island and connected to the corresponding frame pad via a third bonding wire; The fourth chip is disposed upright on the fourth base island and connected to the corresponding frame pad via a fourth bonding wire; The plastic package is arranged inside the space formed by the isolation frame, and wraps the first chip, the second chip, the third chip, the fourth chip and a plurality of frame pads.

2. The chip packaging structure according to claim 1, It is characterized in that One end of the frame pad is fixedly connected to the isolation frame, and the other end is a suspended free end; the first base island, the second base island, the third base island and the fourth base island are all welded to the isolation frame through the free ends of the corresponding frame pads.

3. The chip packaging structure according to claim 1, It is characterized in that The first base island and the second base island are arranged side by side in the closed area formed by the isolation frame, and are both adjacent to the first side frame of the isolation frame; the third base island and the fourth base island are arranged side by side in the closed area formed by the isolation frame, and are both adjacent to the second side frame of the isolation frame; wherein the first side frame and the second side frame of the isolation frame are two opposite frames.

4. The chip packaging structure according to claim 1, It is characterized in that A plurality of first substrate pads are also provided on the first substrate, which are used for welding with corresponding frame pads through first welding wires; A plurality of second substrate pads are also provided on the second substrate for welding with corresponding frame pads through second welding wires.

5. The chip packaging structure according to claim 2, It is characterized in that A cutting line is provided along the inner edge of the isolation frame and away from the free end of the frame pad, and is used to cut a separate flip chip package and a face-up chip package along the cutting line on the package body after chip packaging through a cutting process.

6. The chip packaging structure according to claim 1, It is characterized in that Antennas, high-frequency wiring and complex peripheral circuits are integrated on the first substrate and the second substrate.

7. The chip packaging structure according to claim 1, It is characterized in that The third chip and the fourth chip are both low-speed signal and power supply circuits.

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