Diamond FET, electromechanical instrument, and method for manufacturing diamond fet

Abstract

Provided are a diamond FET, an electromechanical instrument, and a method for manufacturing the diamond FET that are capable of contributing to ensuring the contact properties of a gate electrode even when the gate length is reduced to less than 100 nm. This diamond FET comprises a diamond semiconductor layer, a gate electrode that is disposed on the diamond semiconductor layer and has a gate length of less than 100 nm, and a passivation film that covers at least an element region of the diamond semiconductor layer including the gate electrode. (FIG. 9)

Description

Diamond FET, electrical device, and method for manufacturing diamond FET

[0001] [Description of Related Applications] The present invention is based on Japanese Patent Application No. 2023-108836 (filed June 30, 2023), the entire contents of which are incorporated herein by reference. The present invention relates to a diamond FET, an electrical device, and a method for manufacturing a diamond FET.

[0002] Recent advances in diamond CVD (Chemical Vapor Deposition) technology have led to the development of increasingly high-purity CVD diamonds, making it possible to obtain single-crystal diamonds with high carrier (electron, hole) mobility. This has raised expectations for their use in diamond FETs (Field Effect Transistors), which offer excellent device performance in terms of electrical properties, high-frequency characteristics, and other factors.

[0003] One method for manufacturing a diamond FET is the following self-alignment method (see, for example, Non-Patent Documents 1 and 2). First, a diamond semiconductor layer (e.g., a hydrogen-terminated diamond layer) is formed on the (001) plane of a diamond single crystal, gold is evaporated onto the surface of the diamond semiconductor layer, a first resist is formed in the element region on the gold, and using the first resist as a mask, the gold is wet-etched until the diamond semiconductor layer is exposed, and the first resist is removed. Next, a second resist having openings for forming a gate electrode and a source electrode / drain electrode is formed, and the gold exposed from the openings of the second resist is wet-etched to form source electrode / drain electrode made of gold, widely separated from the openings. Next, using the second resist as a mask, a gate electrode is formed by metal evaporation on the diamond semiconductor layer exposed from the openings of the second resist, and then the second resist and the metal layer thereon are lifted off. This completes a MESFET (Metal Semiconductor Field Effect Transistor) type diamond FET.

[0004] Compared with a non-self-aligned method (see, for example, Patent Document 1) in which the gate electrode and the source / drain electrodes are formed using separate resists, the self-aligned method allows the gate electrode to be positioned accurately relative to the source / drain electrodes, and is advantageous in forming a gate electrode with a reduced gate length in order to improve high-frequency characteristics.

[0005] JP 2020-161587 A

[0006] Carrier transport properties in diamond and its application to high-frequency FETs, Kawarada et al., Applied Physics, 73, 339-345, 2004-03-10, Japan Society of Applied Physics. Gate-metal interface of hydrogen-terminated diamond FETs, Kakazu et al., Surface Science, Vol. 29, No. 3, pp. 159-163, 2008. Special feature: "The forefront of diamond surface and interface research" (https: / / www.jstage.jst.go.jp / article / jsssj / 29 / 3 / 29_3_159 / _pdf / -char / ja). "High performance diamond MISFETs using CaF2 gate insulator", S. Miyamoto et al., Diamond and Related Materials, Volume 12, Issues 3-7, 2003 (https: / / doi.org / 10.1016 / S0925-9635(03)00034-7).

[0007] The following analysis is provided by the present inventors.

[0008] As the gate electrode is miniaturized, the surface morphology (shape, damage, poisoning, etc.) of the diamond semiconductor layer affects the contact of the gate electrode, making it difficult to obtain desired electrical characteristics. The same can be said for forming a miniaturized gate electrode by the self-alignment method described in Non-Patent Documents 1 and 2. In order to ensure the contact of the gate electrode, it is conceivable to cover the entire diamond semiconductor layer including the gate electrode, source electrode, and drain electrode with a passivation film as in Non-Patent Document 3. However, when the gate length is miniaturized to less than 100 nm, the contact of the gate electrode is significantly reduced, so it is unclear whether the contact of the gate electrode can be ensured even when covered with a passivation film. In Non-Patent Document 3, the gate length is 0.4 to 0.5 μm, and the reduction in contact between the gate electrode and the diamond semiconductor layer is not a problem in terms of scale.

[0009] A main object of the present invention is to provide a diamond FET, an electrical device, and a method for manufacturing a diamond FET that can contribute to ensuring contact of a gate electrode even when the gate length is miniaturized to less than 100 nm.

[0010] The diamond FET according to the first aspect comprises a diamond semiconductor layer, a gate electrode that is disposed on the diamond semiconductor layer and has a gate length of less than 100 nm, and a passivation film that covers at least the element region of the diamond semiconductor layer that includes the gate electrode.

[0011] An electrical device according to a second aspect includes the diamond FET according to the first aspect.

[0012] A method for manufacturing a diamond FET according to a third aspect includes the steps of forming a gate electrode having a gate length of less than 100 nm on a diamond semiconductor layer, and forming a passivation film on the diamond semiconductor layer including the gate electrode.

[0013] The first to third aspects can contribute to ensuring contact between the gate electrode and the diamond semiconductor layer even when the gate length is miniaturized to less than 100 nm.

[0014] 1 is a partial cross-sectional view schematically showing an example of the configuration of a diamond FET according to Form 1. FIG. 2 is a partial cross-sectional view schematically showing a modified example of the configuration of the diamond FET according to Form 1. FIG. 3 is a process cross-sectional view schematically showing an example of the manufacturing method of a diamond FET according to Form 1. FIG. 4 is a process cross-sectional view schematically showing an example of the manufacturing method of a diamond FET according to Form 1. FIG. 5 is a process cross-sectional view schematically showing an example of the manufacturing method of a diamond FET according to Form 1. FIG. 6 is a graph schematically showing the relationship between the drain voltage and the drain current for each predetermined gate voltage of the diamond FET according to Form 1. FIG. 7 is a graph schematically showing the relationship between the gate voltage and the drain current of the diamond FET according to Form 1 when the drain voltage is −6 V. FIG. 8 is a cross-sectional view schematically showing an example of the configuration of a diamond FET according to Form 2.

[0015] The following description of the embodiments will be made with reference to the drawings. Note that, when reference numerals are used in this application, they are intended solely to aid understanding and are not intended to limit the present invention to the illustrated embodiments. Furthermore, the following embodiments are merely examples and do not limit the present invention.

[0016] [Mode 1] A diamond FET according to Mode 1 will be described with reference to the drawings. Fig. 1 is a partial cross-sectional view schematically showing an example of the configuration of the diamond FET according to Mode 1. Fig. 2 is a partial cross-sectional view schematically showing a modified example of the configuration of the diamond FET according to Mode 1.

[0017] The diamond FET1 is a FET (Field Effect Transistor) having a source electrode 12a, a drain electrode 12b, and a gate electrode 14a in an element region 2 on a diamond semiconductor layer 11 (hydrogen termination portion 11a in FIG. 1) (see FIG. 1). In the diamond FET1, the diamond semiconductor layer 11 including the source electrode 12a, the drain electrode 12b, and the gate electrode 14a is covered with a passivation film 15. The diamond FET1 can be incorporated into electrical machinery and equipment such as semiconductor devices, power electronics devices, high-frequency devices, communication equipment, sensing equipment, automobiles, power transmission and distribution equipment, devices for harsh environments, equipment for high-temperature environments, equipment for radiation environments, space equipment, and nuclear reactor equipment.

[0018] When the diamond FET 1 is applied to a MESFET (Metal Semiconductor Field Effect Transistor) without a gate insulating film as shown in FIG. 1, it can have the following configuration.

[0019] In the diamond FET 1 of FIG. 1, a diamond semiconductor layer 11 is formed on a diamond substrate 10, with the upper surface ((001) plane) being a hydrogen-terminated portion 11a. In FIG. 1, the hydrogen-terminated portion 11a is configured to be present in the element region 2, but not outside the element region 2. A gate electrode 14a is disposed near the center of the hydrogen-terminated portion 11a so as to be in Schottky contact with the hydrogen-terminated portion 11a. On both sides of the gate electrode 14a on the hydrogen-terminated portion 11a, a source electrode 12a and a drain electrode 12b are disposed so as to be in ohmic contact with the hydrogen-terminated portion 11a. The source electrode 12a and the drain electrode 12b are disposed at intervals from the gate electrode 14a. The diamond semiconductor layer 11, including the source electrode 12a, the drain electrode 12b, and the gate electrode 14a, is covered with a passivation film 15. Contact holes 15a and 15b leading to the source electrode 12a and the drain electrode 12b are formed in the passivation film 15. Plugs 16a and 16b (which may be contact pads) are embedded in the contact holes 15a and 15b. The plugs 16a and 16b may be omitted. A contact hole (not shown) leading to the gate electrode 14a is formed in the passivation film 15 at a position different from the cross-sectional position of FIG. 1 , and a plug (not shown) is embedded in the contact hole. Depending on the size of the diamond FET 1, a multilayer wiring structure (not shown) may be formed on the passivation film 15 including the plugs 16a and 16b, or pads (not shown, which may be integrated with the plugs) for the source electrode 12a, the drain electrode 12b, and the gate electrode 14a may be formed. The diamond FET 1 may be applied to a MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a gate insulating film 13a between the gate electrode 14a and the hydrogen termination portion 11a as shown in FIG. 2, in addition to the MESFET shown in FIG. 1, or may be applied to a MIMSFET (Metal Insulator Metal Semiconductor Field Effect Transistor; not shown).

[0020] The diamond substrate 10 is a substrate made of a diamond single crystal (see FIG. 1). For example, a high-temperature, high-pressure synthetic diamond single crystal substrate can be used as the diamond substrate 10. It is preferable to use a diamond substrate 10 with a surface roughness (in accordance with ISO 4287) of 10 nm or less. If the surface roughness of the diamond substrate 10 exceeds 10 nm, it is preferable to polish the diamond substrate 10 so that the surface roughness is 10 nm or less. This has the advantage of reducing the surface roughness of the diamond semiconductor layer 11 synthesized on the diamond substrate 10 and improving the contact between the diamond semiconductor layer 11 and metals or insulating films.

[0021] The diamond semiconductor layer 11 is a layer that includes diamond and has a portion that functions as a semiconductor (see FIG. 1). The thickness of the diamond semiconductor layer 11 can be, for example, several μm or several tens of μm, but is not limited thereto. The diamond semiconductor layer 11 can be formed, for example, by chemical vapor deposition of diamond crystals (epitaxial diamond crystals) on the diamond substrate 10 using hydrogen and methane gas as raw materials using a microwave plasma CVD (Chemical Vapor Deposition) device. The diamond semiconductor layer 11 thus formed has a hydrogen termination portion 11a on the (001) plane (upper surface). The hydrogen termination portion 11a has a hole channel formed therein and exhibits p-type conductivity. By subjecting the region of the hydrogen termination portion 11a other than the element region 2 to ozone treatment to remove hydrogen, it is possible to configure the hydrogen termination portion 11a to be present in the element region 2, but not to be present in the region other than the element region 2. In addition, the diamond semiconductor layer 11 is not limited to the one that has hydrogen termination portion 11a, but may have the part that contains (is doped, is injected into) impurities (for example, boron, phosphorus, etc.) in diamond.In addition, instead of having the diamond semiconductor layer 11 on the diamond substrate 10, for example, it may be the diamond freestanding film that is obtained by using a microwave plasma CVD device, using hydrogen and methane gas as raw material, growing diamond crystal on a seed substrate through chemical vapor deposition, and then removing this seed substrate.

[0022] The source electrode 12a and the drain electrode 12b are electrodes made of a predetermined metal (see FIG. 1). For example, Au can be used for the source electrode 12a and the drain electrode 12b. The source electrode 12a and the drain electrode 12b are formed on the diamond semiconductor layer 11. In order to ensure adhesion with the diamond semiconductor layer 11, it is preferable that the source electrode 12a and the drain electrode 12b are formed on the diamond semiconductor layer 11 in a state that has not been exposed to an etching agent, a resist stripper, or oxygen plasma for resist ashing. The source electrode 12a and the drain electrode 12b are arranged so as to be in direct contact (ohmic contact) with the hydrogen termination portion 11a of the diamond semiconductor layer 11. The source electrode 12a and the drain electrode 12b can be formed, for example, by forming a metal layer on the diamond semiconductor layer 11 (for example, by vapor deposition or sputtering), forming a resist for forming the source electrode / drain electrode on the metal layer, etching using the resist as a mask, and removing the resist. The source-drain distance L between the source electrode 12a and the drain electrode 12b is ＳＤ In consideration of operation in a high frequency band (for example, a cutoff frequency of 50 to 100 GHz), the source-drain distance L is preferably less than 100 nm. ＳＤ The lower limit of the thickness of the source electrode 12a and the drain electrode 12b is the critical film thickness (the same applies to other thicknesses for which no lower limit is specified). The thicknesses of the source electrode 12a and the drain electrode 12b are preferably less than 100 nm in consideration of operation in a high frequency band, preferably less than 50 nm in consideration of obtaining desired RF (Radio Frequency) characteristics, and preferably less than 25 nm in consideration of operation in an even higher frequency band (for example, a cutoff frequency of more than 100 GHz). The lower limit of the thickness of the source electrode 12a and the drain electrode 12b is the critical film thickness (the same applies to other thicknesses for which no lower limit is specified).

[0023] For example, the gate electrode 14a can be made of a metal film consisting of a single layer structure of any of Al, Au, Ti, Mo, Cr, Ru, Cu, Pb, Zn, Pt or a laminated structure of any combination.For example, the gate electrode 14a can be made by forming a resist for gate electrode formation on the diamond semiconductor layer 11, and using this resist as a mask, forming (for example, vapor deposition, sputtering) a metal film for the gate electrode 14a on the diamond semiconductor layer 11 by self-alignment method, and then lifting off the resist and the metal film thereon.When forming the gate insulating film 13a between the gate electrode 14a and the hydrogen termination part 11a as shown in Figure 2, the gate insulating film 13a can be made of, for example, Al ２ O ３ , SiO ２ , HfO ２ , AlN, BN, Si ３ N ４ , SiON, Ta ２ O ５ , TiO ２ , W.O. ３ , CaF ２ , LaF ３ , and MgF ２ In consideration of the combination with the passivation film 15 and the improvement of carrier mobility (60 to 3800 cm / Vs), an insulating film having a single layer structure or a laminated structure of any combination of these can be used. ２ , LaF ３ , MgF ２ In order to improve the carrier mobility (60 to 3800 cm / Vs), an insulating film having a single layer structure or a laminated structure of any combination of the above can be used. ２ , LaF ３ , MgF ２Depending on the application of the device utilizing the present invention, it may be useful to use an insulating film having a single layer structure of any of the above or a laminated structure of any combination thereof. The gate insulating film 13a can be formed, for example, by depositing an insulating film for the gate insulating film 13a by CVD using a predetermined source gas before depositing the metal film for the gate electrode 14a, and then lifting off the insulating film between the resist and the metal film during lift-off. Taking into account the gate length, the thickness of the gate electrode 14a is preferably less than 100 nm.

[0024] The gate length, which is the width of gate electrode 14a, is preferably less than 100nm in order to improve frequency characteristics (shorten the transit time of carriers that travel through channel); in consideration of operating at higher frequency band (for example, cut-off frequency over 100GHz), it is preferably less than 60nm; in consideration of obtaining desired RF (Radio Frequency) characteristics, it is preferably less than 50nm.The lower limit of gate length is the limit length that functions as FET.In addition, the more miniaturized gate length progresses, the contact between gate electrode 14a and diamond semiconductor layer 11 decreases, and resistance component is generated or breaks and element is easily destroyed, so when gate length is made less than 100nm, it is preferable to cover gate electrode 14a with the following passivation film 15.

[0025] The passivation film 15 is made of, for example, Al ２ O ３ , SiO ２ , HfO ２ , AlN, BN, Si ３ N ４ , SiON, Ta ２ O ５ , TiO ２ , W.O. ３ , CaF ２ , LaF ３ , and MgF ２ In consideration of the improvement of carrier mobility and processability, an insulating film having a single layer structure or a laminated structure of any combination thereof can be used. Insulating materials containing F (fluorine), such as CaF２ , LaF ３ , MgF ２ Any one of the above or any combination thereof can be used. In order to prevent deterioration of electrical characteristics due to components such as ions, electrons, and radicals in the atmosphere, it is desirable that the passivation film 15 at least covers and protects the entire element region 2. The thickness of the passivation film 15 is preferably 100 nm or more in consideration of ensuring contact between the gate electrode 14a and the diamond semiconductor layer 11, and between the source electrode 12a and the drain electrode 12b and the diamond semiconductor layer 11, and is preferably 300 nm or more in consideration of the flatness or flattening processability of the upper surface of the passivation film 15.

[0026] The plugs 16a and 16b can be made of a metal having a single layer structure or a laminate structure of any combination of Au, Ru, Al, Ti, Mo, Cu, Cr, Pb, Zn, Pt, and W, for example, and it is preferable to use a metal different from the metal of the source electrode 12a and the drain electrode 12b in the layer in contact with the source electrode 12a and the drain electrode 12b.

[0027] The source electrode 12a and the drain electrode 12b have extensions 17a and 17b that extend (protrude) toward the gate electrode 14a beyond the end faces of the plugs 16a and 16b on the gate electrode 14a side. ｅｘｔ The length (from the end face of the plugs 16a, 16b on the gate electrode 14a side to the tip face of the extensions 17a, 17b) is preferably less than 200 nm in consideration of operation in the high frequency band, and is preferably less than 100 nm in consideration of the balance with the thicknesses of the source electrode 12a and the drain electrode 12b when operating in the high frequency band, and is preferably less than 50 nm (or may be 0 nm) in consideration of obtaining desired RF characteristics.

[0028] Next, a method for manufacturing a diamond FET according to embodiment 1 will be described with reference to the drawings. 3 to 6 are cross-sectional views showing steps in a typical example of a method for manufacturing a diamond FET according to embodiment 1.

[0029] First, a diamond semiconductor layer 11 is formed on a diamond substrate 10 (see Fig. 3(A)). The diamond semiconductor layer 11 can be formed by chemical vapor deposition of diamond crystal on the diamond substrate 10 using, for example, a microwave plasma CVD device, with hydrogen and methane gas without added impurities as raw materials (volume ratio of methane to hydrogen is 0.5%). The diamond semiconductor layer 11 thus formed is hydrogen-terminated diamond with hydrogen-terminated part 11a on the (001) plane (upper surface).

[0030] Next, the metal layer 12 is formed on the diamond semiconductor layer 11 (see FIG. 3(B)). The metal layer 12 can be formed by depositing a predetermined metal (for example, gold) on the diamond semiconductor layer 11 by, for example, RF sputtering.

[0031] Next, a resist 20 is formed to cover the element region 2 on the metal layer 12, and the metal layer 12 is etched using the resist 20 as a mask until the diamond semiconductor layer 11 is exposed (see FIG. 3(C)). The resist 20 can be formed by, for example, a lithography method. The etching of the metal layer 12 can be carried out using, for example, a wet etching agent.

[0032] Next, using the resist 20 as a mask, ozone treatment is performed to selectively eliminate the hydrogen termination 11a in the region other than the element region 2 in the diamond semiconductor layer 11 (see FIG. 3(D)). As a result, the region other than the element region 2 in the diamond semiconductor layer 11 (the region that has become the oxygen termination) becomes highly resistive, and the elements can be electrically insulated from each other.

[0033] Next, the resist (20 in FIG. 3D) on the metal layer 12 is removed (see FIG. 4A). The resist 20 can be removed, for example, with a resist remover or by ashing. After the resist 20 is removed, cleaning is performed.

[0034] Next, a resist 21 having openings 21a for forming gate electrodes and source / drain electrodes is formed on the diamond semiconductor layer 11 including the metal layer 12 (see FIG. 4(B)). The resist 21 can be formed by, for example, lithography.

[0035] Next, using the resist 21 as a mask, the metal layer (12 in FIG. 4B) exposed from the opening 21a is etched, and the metal layer 12 is separated into the source electrode 12a and the drain electrode 12b by under-etching, and then the distance between the end faces of the source electrode 12a and the drain electrode 12b is made wider than the width of the opening 21a by side-etching (see FIG. 4C). The metal layer 12 can be etched using, for example, a wet etching agent.

[0036] Next, metal layer 14 and gate electrode 14a are formed on the diamond semiconductor layer 11 that includes resist 21 (see Fig. 5(A)). In other words, by the self-alignment process that utilizes resist 21 as it is, gate electrode 14a is formed on the diamond semiconductor layer 11 that is in the region of the opening 21a of resist 21. Metal layer 14 and gate electrode 14a can be formed by, for example, sputtering method.

[0037] Next, the resist (21 in FIG. 5A) and the metal layer thereon (14 in FIG. 5A) are removed (see FIG. 5B). The resist 21 and the metal layer thereon can be removed by lifting off using a resist remover, for example. After the resist 21 is removed, cleaning is performed.

[0038] Next, by using a predetermined raw material gas, a passivation film 15 is formed on the diamond semiconductor layer 11 including the source electrode 12a, the drain electrode 12b and the gate electrode 14a by CVD method, and the upper surface of the passivation film 15 is planarized by CMP (Chemical Mechanical Polishing), and then a resist 22 is formed on the planarized passivation film 15, which has openings 22a and 22b for forming plugs (openings for gate electrodes are not shown) (see Fig. 5(C)).The resist 21 can be formed by, for example, lithography method.In addition, planarization of the passivation film 15 is not essential, and the planarization method is not limited to CMP method.

[0039] Next, using the resist 22 as a mask, the passivation film 15 exposed from the openings 22a and 22b (openings for the gate electrodes are not shown) is etched until the source electrode 12a, the drain electrode 12b, and the gate electrode 14a appear, thereby forming contact holes 15a and 15b (contact holes on the gate electrodes are not shown) (see FIG. 6A). Etching of the passivation film 15 can be performed by, for example, dry etching.

[0040] Next, the resist (22 in FIG. 6A) on the passivation film 15 is removed (see FIG. 6B). The resist 22 can be removed using, for example, a resist remover. After the resist 22 is removed, cleaning is performed.

[0041] Next, a metal layer 16 (e.g., a metal layer formed by laminating Au on Ti) is formed on the passivation film 15 including the source electrode 12a, the drain electrode 12b, and the gate electrode 14a so as to fill the contact holes 15a and 15b (the contact hole on the gate electrode is not shown) (see FIG. 6C). The metal layer 16 can be formed by, for example, RF sputtering or vapor deposition.

[0042] Next, the metal layer 16 is polished and removed by CMP until the entire upper surface of the passivation film 15 is exposed, thereby forming plugs 16a and 16b (plugs on the gate electrodes are not shown) (see FIG. 1). After that, depending on the size of the diamond FET 1, a multilayer wiring structure (not shown) may be formed on the passivation film 15 including the plugs 16a and 16b. In addition, when forming plugs 16a and 16b having pads (not shown) on the top, pad-equipped plugs 16a and 16b (contact pads) can be formed using lithography and etching. Alternatively, the plugs 16a and 16b may be omitted.

[0043] Next, the characteristics and state of the sample of the diamond FET according to the embodiment 1 will be described. Figure 7 is a graph that shows the relationship between the drain voltage and the drain current for each predetermined gate voltage of the diamond FET according to the embodiment 1. Figure 8 is a graph that shows the relationship between the gate voltage and the drain current for the diamond FET according to the embodiment 1 when the drain voltage is -6V.

[0044] The sample of the diamond FET according to the first embodiment (see Fig. 1) was obtained as follows. First, on a diamond substrate 10 (4mm x 4mm x 0.5mm), a diamond semiconductor layer 11 (thickness 100nm) having a hydrogen termination 11a was formed (CVD method). Then, on the hydrogen termination 11a, a metal layer (Au, thickness 90nm; corresponding to 12 in Fig. 3(B)) for source electrode / drain electrode was formed (electron beam vacuum deposition apparatus: Eiko Engineering Co., Ltd. NPF023 used, deposition temperature 100 ° C or less), a resist (corresponding to 20 in Fig. 3(C); 200 μm square) was formed on the metal layer 12, and the resist 20 was used as a mask to etch the metal layer 12. Next, the resist (corresponding to 20 in Fig. 3(D)) was used as it was, and ozone treatment was carried out to selectively eliminate the hydrogen termination 11a in the region other than the element region 2 in the diamond semiconductor layer 11, and the resist was removed and washed. Next, on the diamond semiconductor layer 11 including the Au electrode (corresponding to 12 in Fig. 4(B)) for source electrode / drain electrode, a resist (corresponding to 21 in Fig. 4(B)) having an opening (width 80 nm) for forming gate electrode and for forming source electrode / drain electrode is formed, and the resist 21 is used as a mask to etch the metal layer (corresponding to 12 in Fig. 4(B)) exposed from the opening, to form source electrode 12a and drain electrode 12b. Next, on the diamond semiconductor layer 11 including the resist (corresponding to 21 in Fig. 5(A)) for forming gate electrode and for forming source electrode / drain electrode, a metal layer (14 in Fig. 5(A)) and a gate electrode 14a are formed (sputtered), and the resist 21 and the metal layer 14 thereon are lifted off and washed. Next, a passivation film 15 (thickness: 100 to 1000 nm) was formed on the diamond semiconductor layer 11 including the source electrode 12 a, the drain electrode 12 b, and the gate electrode 14 a by a CVD method using a predetermined raw material gas, and the upper surface of the passivation film 15 was flattened by a CMP method. After that, a resist (corresponding to 22 in FIG. 5(C)) having an opening for forming a plug was formed on the flattened passivation film 15.Next, using a resist (22 in FIG. 6A) as a mask, the passivation film 15 exposed from the openings was etched until the source electrode 12a, the drain electrode 12b, and the gate electrode 14a were revealed, thereby forming contact holes 15a and 15b (contact holes on the gate electrodes are not shown). Thereafter, the resist (22 in FIG. 6A) on the passivation film 15 was removed and the substrate was washed. Next, a metal layer (16 in FIG. 6C) was deposited (sputtered) on the passivation film 15 including the source electrode 12a, the drain electrode 12b, and the gate electrode 14a so as to fill the contact holes 15a and 15b (contact holes on the gate electrodes are not shown). Thereafter, the metal layer 16 was polished and planarized by CMP until the entire upper surface of the passivation film 15 was revealed, thereby forming plugs 16a and 16b (plugs on the gate electrodes are not shown). Thus, a sample was obtained. The thickness and length were measured using a scanning electron microscope (Hitachi High-Technologies Corporation: S-4800), and supplementary measurements were made using a stylus step profiler (KLA-Tencor Corporation: Alpha-Step IQ). Electrical properties were measured using a prober (Hybridge Corporation: Ultra-high vacuum microprober: HUMP-100) and a semiconductor parameter analyzer (Agilent Corporation: B1505A).

[0045] The contact properties of the gate electrodes of the above samples were measured once a day for one month (the probe was re-contacted each time), but no peeling or the like of the source electrode 12a, the drain electrode 12b, or the gate electrode 14a occurred. ２ It was also confirmed that the contact stabilization effect of the gate electrode was high when the thickness was 100 nm or more. It was also effective in the gate length range of less than 100 nm, which is essential for high-frequency operation in the millimeter-wave band or higher (30 GHz or higher). Furthermore, the stabilization of the contact of the gate electrode was particularly remarkable in the gate length range of 50 to 60 nm, which is aimed at even higher frequency operation.

[0046] Regarding the mobility of the above sample, the mobility of the above sample calculated from the current-voltage characteristics is ２ O ３It was confirmed that the performance was improved by more than two times compared to the diamond FET.

[0047] The electrical characteristics of the sample were compared to a diamond FET with the same design but without a passivation film, and the effects of atmospheric components on the device's electrical characteristics were suppressed. Furthermore, when the sample was remeasured after being left for one month, the maximum current value, transconductance, threshold voltage, and leakage current all changed by less than 40%.

[0048] Drain current I for each specified gate voltage (-2 to +3 V) Ｄ - drain voltage V Ｄ The characteristics are as shown in Figure 7, and the drain current I Ｄ - gate voltage V G The characteristics are shown in Figure 8. Note that the current values ​​in Figures 7 and 8 have been converted into absolute values.

[0049] According to the first embodiment, by covering the gate electrode 14a with the passivation film 15, even when the gate length is miniaturized to less than 100 nm, it can contribute to ensure the contact between the gate electrode 14a and the diamond semiconductor layer 11 (when the gate insulating film 13a exists, the contact between the gate electrode 14a and the gate insulating film 13a, and the contact between the gate insulating film 13a and the diamond semiconductor layer 11).As a result, it can improve the yield rate during manufacturing, and can be manufactured stably.In addition, even when used for a long period of time, it can stabilize the electrical characteristics of the diamond FET1.

[0050] Furthermore, according to form 1, by covering the source electrode 12a and the drain electrode 12b with the passivation film 15, even if the thickness of the source electrode 12a and the drain electrode 12b is set to less than 100 nm in order to suppress variations in the source-drain distance, the contact between the source electrode 12a and the drain electrode 12b and the diamond semiconductor layer 11 can be ensured, and breakdown of the element and deterioration of the electrical characteristics can be prevented.

[0051] Furthermore, according to form 1, the channel of the diamond semiconductor layer 11 is protected by the passivation film 15, so that the influence of components such as ions, electrons, and radicals in the atmosphere on the surface of the element region 2 (such as changes in structure and adsorbates) is reduced, the electrical characteristics can be stabilized, and durability can also be improved.

[0052] Furthermore, according to form 1, the channel of the diamond semiconductor layer 11 is protected by a passivation film 15 made of a fluorine-based insulating material, thereby suppressing the influence of increased resistance in the channel portion and improving reliability and electrical characteristics.

[0053] According to the first aspect, in the MISFET structure, the channel portion is covered with the passivation film 15 and the gate insulating film 13a made of a fluorine-based insulating material, so that, for example, Al ２ O ３ Compared to the case where the gate insulating film is covered with a passivation film using an oxide film, such as Al, the mobility can be improved, the transconductance can be improved, and the high frequency characteristics can be improved. ２ O ３ It is possible to manufacture highly reliable MISFETs by using oxide films such as Al as gate insulating films or passivation films. ２ O ３ In a MISFET using an oxide film such as the above, since charges are close to the interface, carrier mobility is low due to Coulomb scattering, making it difficult to improve transconductance and high frequency characteristics.

[0054] Furthermore, according to the first embodiment, by using a fluorine-based insulating material for the passivation film 15, it is possible to improve the electrical characteristics and safety compared to a process using an insulating material such as an oxide film. ２ O ３In the case of insulating materials such as oxide films, the surface of the channel is significantly deteriorated by the ALD (Atomic Layer Deposition) process, but in the case of fluorine-based insulating materials, they can be formed by resistance heating evaporation, and the deterioration of the surface of the channel can be suppressed. In addition, cleaning and wet etching using hydrofluoric acid treatment are very useful in semiconductor device processing, but Al ２ O ３ However, for elements that use a fluorine-based passivation film, such cleaning and processing is possible, broadening the process options and enabling more efficient element fabrication.

[0055] Furthermore, according to form 1, the gate electrode 14a is formed using a self-alignment method in which the resist 21 used to form the source electrode 12a and the drain electrode 12b is also used to form the gate electrode 14a, so there is no need to align the gate electrode 14a with the source electrode 12a and the drain electrode 12b, and a fine diamond FET 1 with a gate length of less than 100 nm can be stably formed.

[0056] Furthermore, according to form 1, even if the diamond substrate 10 is small and difficult to handle, the self-alignment process can ensure yield, reliability, and adhesion between the gold and the diamond semiconductor layer, while providing a high-performance element that operates stably even in harsh environments such as a high-temperature environment of 400°C, a high-voltage environment of 500V, or a radiation environment.

[0057] [Embodiment 2] A diamond FET according to embodiment 2 will be described with reference to the drawings. Fig. 9 is a cross-sectional view schematically showing an example of the configuration of a diamond FET according to embodiment 2.

[0058] The diamond FET 1 comprises a diamond semiconductor layer 11, a gate electrode 14a, and a passivation film 15. The gate electrode 14a is disposed on the diamond semiconductor layer 11 and has a gate length of less than 100 nm. The passivation film 15 covers at least the element region of the diamond semiconductor layer 11 including the gate electrode 14a.

[0059] According to the second embodiment, by covering the gate electrode 14a with the passivation film 15, it is possible to contribute to ensuring contact between the gate electrode 14a and the diamond semiconductor layer 11 even when the gate length is miniaturized to less than 100 nm.

[0060] Some or all of the above aspects may be described as, but are not limited to, the following supplementary notes.

[0061] [Appendix 1] A diamond FET comprising: a diamond semiconductor layer; a gate electrode disposed on the diamond semiconductor layer and having a gate length of less than 100 nm; and a passivation film covering at least an element region of the diamond semiconductor layer including the gate electrode. [Appendix 2] The diamond FET according to appendix 1, wherein the gate length is less than 60 nm. [Appendix 3] The diamond FET according to appendix 1 or 2, wherein the gate length is less than 50 nm. [Appendix 4] The diamond FET according to any one of appendices 1 to 3, wherein the passivation film is made of an insulating material containing fluorine. [Appendix 5] The passivation film is made of CaF ２ , LaF ３ , MgF ２ The diamond FET according to any one of Supplementary Notes 1 to 4, which has a single layer structure of any one of the above or a laminated structure of any combination thereof. [Supplementary Note 6] The diamond FET according to any one of Supplementary Notes 1 to 5, wherein the thickness of the passivation film is 100 nm or more. [Supplementary Note 7] The diamond FET according to any one of Supplementary Notes 1 to 6, wherein the gate electrode is in Schottky contact with the diamond semiconductor layer. [Supplementary Note 8] The diamond FET according to any one of Supplementary Notes 1 to 6, which comprises a gate insulating film interposed between the gate electrode and the diamond semiconductor layer. [Supplementary Note 9] The gate insulating film is made of CaF ２ , LaF ３ , MgF ２a diamond FET according to any one of appendices 1 to 10, having a single layer structure of any one of the above or a laminated structure of any combination thereof. [Appendix 10] The diamond FET according to any one of appendices 1 to 9, comprising source and drain electrodes arranged on both sides of the gate electrode on the diamond semiconductor layer at an interval, each electrode having a thickness of less than 100 nm and covered with the passivation film. [Appendix 11] The diamond FET according to any one of appendices 1 to 10, having a carrier mobility of 60 cm / Vs or more and 3800 cm / Vs or less. [Appendix 12] An electrical device comprising the diamond FET according to any one of appendices 1 to 11. [Appendix 13] A method for manufacturing a diamond FET, comprising: a step of forming a gate electrode having a gate length of less than 100 nm on a diamond semiconductor layer; and a step of forming a passivation film on the diamond semiconductor layer including the gate electrode.

[0062] The disclosures of the above-mentioned patent and non-patent documents are incorporated herein by reference and may be used as the basis or part of the present invention, as necessary. Modifications and adjustments of the embodiments and examples are possible within the scope of the entire disclosure of the present invention (including the claims and drawings), and further based on the basic technical concepts thereof. Furthermore, various combinations and selections (or non-selections, as necessary) of the various disclosed elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) are possible within the scope of the entire disclosure of the present invention. In other words, the present invention naturally includes various modifications and alterations that would be possible by a person skilled in the art in accordance with the entire disclosure and technical concepts, including the claims and drawings. Furthermore, with regard to the numerical values ​​and numerical ranges described in this application, any intermediate values, lower values, and smaller ranges are deemed to be included, even if not explicitly stated. Furthermore, the disclosures of the above-cited documents, when used in part or in whole in combination with the disclosures herein as part of the disclosure of the present invention, are also deemed to be included in (belong to) the disclosures of this application, in accordance with the spirit of the present invention.

[0063] REFERENCE SIGNS LIST 1 Diamond FET 2 Element region 10 Diamond substrate 11 Diamond semiconductor layer 11a Hydrogen termination portion 12 Metal layer 12a Source electrode 12b Drain electrode 13 Insulating layer 13a Gate insulating film 14 Metal layer 14a Gate electrode 15 Passivation film 15a, 15b Contact hole 16 Metal layer 16a, 16b Plug 17a, 17b Extension portion 20, 21, 22 Resist 21a, 22a, 22b Opening

Claims

1. A diamond FET comprising: a diamond semiconductor layer; a gate electrode disposed on the diamond semiconductor layer and having a gate length of less than 100 nm; and a passivation film covering at least an element region of the diamond semiconductor layer including the gate electrode.

2. A diamond FET according to claim 1, wherein said gate length is less than 60 nm.

3. A diamond FET according to claim 1 or 2, wherein the gate length is less than 50 nm.

4. A diamond FET according to any one of claims 1 to 3, wherein the passivation film is made of an insulating material containing fluorine.

5. The passivation film is made of CaF ２ , LaF ３ , MgF ２ 5. A diamond FET according to claim 1, which has a single layer structure of any one of the above or a laminated structure of any combination thereof.

6. A diamond FET according to any one of claims 1 to 5, wherein the passivation film has a thickness of 100 nm or more.

7. A diamond FET according to any one of claims 1 to 6, comprising a gate insulating film interposed between said gate electrode and said diamond semiconductor layer.

8. The gate insulating film is made of CaF ２ , LaF ３ , MgF ２ 8. The diamond FET according to claim 7, which has a single layer structure or a laminated structure in which any of the above is combined.

9. A diamond FET as described in any one of claims 1 to 8, comprising source and drain electrodes disposed on both sides of the gate electrode on the diamond semiconductor layer with a space therebetween, each electrode having a thickness of less than 100 nm and covered by the passivation film.

10. A diamond FET according to any one of claims 1 to 9, having a carrier mobility of 60 cm / Vs or more and 3800 cm / Vs or less.

11. An electrical device comprising a diamond FET according to any one of claims 1 to 10.

12. A method for manufacturing a diamond FET, comprising: forming a gate electrode having a gate length of less than 100 nm on a diamond semiconductor layer; and forming a passivation film on the diamond semiconductor layer including the gate electrode.

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