Radio frequency front-end module for optimizing dynamic error vector magnitude and electronic device

Abstract

Disclosed in the present invention is a radio frequency front-end module for optimizing dynamic error vector magnitude, comprising at least one transmitting channel. Each transmitting channel comprises a driving amplifier, a first bias circuit, a first dynamic power supply, a power amplifier, a second bias circuit, a second dynamic power supply, a logic circuit and a TX timer; upon receiving a TX instruction, the logic circuit controls the transmitting channel to enter a TX working mode, and the TX timer starts timing; and on the basis of a plurality of set time periods, at least one of the first dynamic power supply and the second dynamic power supply outputs dynamic power supply voltages that sequentially increase or decrease, and provides the dynamic power supply voltages to the first bias circuit and / or the second bias circuit, so as to dynamically compensate for the output power change caused by the temperature change of a circuit, ensuring that the dynamic error vector magnitude meets higher requirements.

Description

A radio frequency front-end module and electronic device for optimizing dynamic error vector magnitude Technical Field

[0001] The present invention relates to a radio frequency front-end module for optimizing dynamic error vector magnitude (DEVM), and also relates to electronic equipment including the radio frequency front-end module, belonging to the technical field of radio frequency integrated circuits. Background Art

[0002] With the rapid development of communication technology, WiFi7, the successor standard to WiFi6, introduces technologies such as 320M channel bandwidth, QAM modulation, and MIMO transmission based on WiFi6. This significantly improves WiFi7's transmission rate, reaching a staggering maximum data transmission rate of 46Gbps, 4.8 times that of WiFi6. The 4096-QAM modulation technology supported by WiFi7 places very high demands on the signal DEVM, reaching -38dB, and the signal packet length also reaches 4ms, 6ms, and even 10ms. Longer signal packet lengths mean a longer TX transmission period or duty cycle, which increases the temperature variation of the PA (power amplifier), thus increasing the requirements for PA temperature compensation.

[0003] Currently, typical communication platforms require a DEVM of -47dB for RF front-end modules. This means that in time-division duplex (TDD) mode, the amplitude variation within the TX duty cycle of the PA must be controlled to within 0.05dB. Furthermore, the TX duty cycle must range from 10% to 90%, and temperature compensation requirements vary for different TX duty cycles. Existing technologies typically achieve temperature compensation through layout optimization or by reducing current or voltage to lower junction temperature. However, these techniques can significantly impact temperature compensation effectiveness, causing output power variations to easily exceed 0.1dB, leading to a deterioration in DEVM.

[0004] Summary of the Invention

[0005] The primary technical problem to be solved by the present invention is to provide a radio frequency front-end module that optimizes the dynamic error vector amplitude.

[0006] Another technical problem to be solved by the present invention is to provide an electronic device including the radio frequency front-end module.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] According to a first aspect of an embodiment of the present invention, a radio frequency front-end module for optimizing a dynamic error vector magnitude is provided, comprising at least one transmit path; wherein each transmit path comprises:

[0009] A driver amplifier, configured to amplify the gain of an input radio frequency signal, wherein the input end of the driver amplifier is connected to the radio frequency signal input end, and the output end of the driver amplifier is connected to the input end of the power amplifier;

[0010] a first bias circuit, configured to provide a bias voltage for the driving amplifier, wherein an output terminal of the first bias circuit is connected to a bias terminal of the driving amplifier;

[0011] a first dynamic power supply, configured to provide a power supply voltage for the first bias circuit, wherein an output terminal of the first dynamic power supply is connected to a power supply terminal of the first bias circuit;

[0012] A power amplifier, used to amplify the power of the radio frequency signal, with its output end connected to the radio frequency signal output end;

[0013] a second bias circuit, configured to provide a bias voltage for the power amplifier, wherein an output terminal of the second bias circuit is connected to a bias terminal of the power amplifier;

[0014] a second dynamic power supply, configured to provide a power supply voltage for the second bias circuit, wherein an output terminal of the second dynamic power supply is connected to a power supply terminal of the second bias circuit;

[0015] a logic circuit, configured to generate a logic control signal to control the working state of a related unit according to a received baseband control signal; an input end of the logic circuit being connected to an input end of the baseband control signal, and an output end of the logic circuit being connected to a control end of a TX timer;

[0016] TX timer, used to record TX working time;

[0017] When the logic circuit receives a TX instruction, it controls the transmit path to enter a TX operating mode, and the TX timer starts timing. When a first time, a second time, a third time, ... an nth time are reached, at least one of the first dynamic power supply and the second dynamic power supply sequentially outputs a first voltage, a second voltage, a third voltage, ... an nth voltage, and provides the voltage to the first bias circuit and / or the second bias circuit to dynamically compensate for output power changes caused by circuit temperature changes, where n is a positive integer.

[0018] Preferably, the output end of the TX timer is connected to the control end of the first dynamic power supply and the control end of the second dynamic power supply respectively.

[0019] Preferably, when the output power decreases as the TX operating time increases, at least one of the first dynamic power supply and the second dynamic power supply sequentially outputs an increasing first voltage, a second voltage, a third voltage, ... an nth voltage at a first time, a second time, a third time, ... an nth time, and provides the voltage to the first bias circuit and / or the second bias circuit.

[0020] Preferably, when the output power increases with the increase of the TX operating time, at least one of the first dynamic power supply and the second dynamic power supply sequentially outputs a decreasing first voltage, a second voltage, a third voltage, ... an nth voltage at a first time, a second time, a third time, ... an nth time, and provides the voltage to the first bias circuit and / or the second bias circuit.

[0021] Preferably, the transmission path further includes a voltage detection circuit, an input end of which is connected to a power supply VDD; and an output end of which is respectively connected to the logic circuit and the TX timer.

[0022] Preferably, when the voltage of the power supply VDD is higher than a first threshold, the output power decreases as the TX operating time increases; the output voltage of at least one of the first dynamic power supply and the second dynamic power supply increases sequentially with the increase of the TX operating time, and is provided to the first bias circuit and / or the second bias circuit;

[0023] When the voltage of the power supply VDD is lower than the second threshold, the output power increases with the increase of the TX operating time; the output voltage of at least one of the first dynamic power supply and the second dynamic power supply decreases successively with the increase of the TX operating time, and is provided to the first bias circuit and / or the second bias circuit.

[0024] Preferably, the transmission path further includes a TX duty cycle detection circuit, which is connected to the logic circuit and the TX timer respectively; and is used to detect the duty cycle of TX transmission in the TDD working mode.

[0025] Preferably, when the TX duty cycle detected by the TX duty cycle detection circuit is lower than a third threshold, the output voltage of at least one of the first dynamic power supply and the second dynamic power supply increases or decreases in sequence with increasing TX operating time, the greater the compensation amplitude;

[0026] When the TX duty cycle detected by the TX duty cycle detection circuit is higher than a fourth threshold, the compensation amplitude by which the output voltage of at least one of the first dynamic power supply and the second dynamic power supply increases or decreases successively as the TX working time increases is smaller.

[0027] Preferably, the transmission path further includes a non-TX timer, which is connected to the logic circuit and the TX timer respectively, and is used to record the time of the non-TX working state.

[0028] Preferably, when the time for which the non-TX working state is recorded by the non-TX timer is lower than a fifth threshold, the compensation amplitude by which the output voltage of at least one of the first dynamic power supply and the second dynamic power supply increases or decreases successively as the TX working time increases is smaller;

[0029] When the time for which the non-TX working state is recorded by the non-TX timer is higher than the sixth threshold, the compensation amplitude by which the output voltage of at least one of the first dynamic power supply and the second dynamic power supply increases or decreases successively with increasing TX working time becomes larger.

[0030] Preferably, the first bias circuit and the second bias circuit in the transmitting path respectively adopt a first dynamic bias circuit and a second dynamic bias circuit;

[0031] The output end of the TX timer is connected to the control end of the first dynamic bias circuit and the control end of the second dynamic bias circuit respectively.

[0032] Preferably, when the output power decreases or increases with increasing TX operating time, the logic circuit sends a control signal through the TX timer to control at least one of the first dynamic bias circuit and the second dynamic bias circuit to output a bias current or voltage that increases or decreases sequentially with increasing TX operating time.

[0033] According to a second aspect of an embodiment of the present invention, an electronic device is provided, wherein the electronic device includes the above-mentioned radio frequency front-end module for optimizing dynamic error vector magnitude.

[0034] Compared with the prior art, the RF front-end module with optimized dynamic error vector magnitude (DEM) provided by the present invention utilizes a dynamic voltage compensation solution to dynamically compensate for changes in output power caused by temperature variations within the PA operating cycle, ensuring that the DEVM meets WiFi7 requirements. This also addresses the issue of inconsistent temperature compensation requirements caused by varying PA temperature variations under different packages or layouts, or at different voltages and TX duty cycles, thereby shortening the product development cycle. Therefore, the DEM-optimized DEM RF front-end module provided by the present invention offers the advantages of a clever and reasonable structural design, low design cost, and excellent circuit performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIG1 is a schematic diagram of the structure of a typical radio frequency front-end module in the prior art;

[0036] FIG2 is a schematic diagram of a bias circuit power supply providing a constant voltage in the prior art;

[0037] FIG3 is a schematic diagram showing the change of output power over time in the TX working state in the prior art;

[0038] FIG4 is a schematic structural diagram of a radio frequency front-end module for optimizing dynamic error vector magnitude according to the first embodiment of the present invention;

[0039] 5 is a schematic diagram of a bias circuit power supply providing a dynamically increasing bias voltage when the output power decreases as the TX operating time increases in the first embodiment of the present invention;

[0040] 6 is a schematic diagram showing that, when the output power increases with the increase of the TX operating time, the power supply of the bias circuit provides a dynamically decreasing bias voltage in the first embodiment of the present invention;

[0041] 7 is a schematic diagram showing the change in output power over time after dynamic compensation of the power supply of the bias circuit in the first embodiment of the present invention;

[0042] FIG8 is a schematic structural diagram of a radio frequency front-end module for optimizing dynamic error vector magnitude according to a second embodiment of the present invention;

[0043] 9 is a schematic diagram showing how the output power changes with increasing TX operating time when the voltage of the power supply VDD is different in the second embodiment of the present invention;

[0044] 10 is a schematic diagram showing the dynamic compensation of the power supply of the bias circuit when the voltage of the power supply VDD is different in the second embodiment of the present invention;

[0045] FIG11 is a schematic structural diagram of a radio frequency front-end module for optimizing dynamic error vector magnitude according to a third embodiment of the present invention;

[0046] 12 is a schematic diagram showing dynamic compensation of the bias circuit power supply when the duty cycle is small or large, for a case where the output power decreases as the TX operating time increases, in the third embodiment of the present invention;

[0047] FIG13 is a schematic diagram showing dynamic compensation of the bias circuit power supply when the duty cycle is small or large, for a case where the output power increases with increasing TX operating time, in accordance with the third embodiment of the present invention;

[0048] FIG14 is a schematic structural diagram of a radio frequency front-end module for optimizing dynamic error vector magnitude according to a fourth embodiment of the present invention;

[0049] FIG15 is a schematic diagram showing dynamic compensation of the bias circuit power supply when the non-TX operating time is short or long, for a case where the output power decreases as the TX operating time increases, in the fourth embodiment of the present invention;

[0050] FIG16 is a schematic diagram showing dynamic compensation of the bias circuit power supply when the non-TX operating time is short or long, for a case where the output power increases with increasing TX operating time, in the fourth embodiment of the present invention;

[0051] FIG17 is a schematic structural diagram of a radio frequency front-end module for optimizing dynamic error vector magnitude according to a fifth embodiment of the present invention;

[0052] FIG18 is a schematic diagram of the structures of a first dynamic bias circuit and a second dynamic bias circuit in a fifth embodiment of the present invention;

[0053] FIG19 is a schematic diagram of an electronic device using a radio frequency front-end module for optimizing dynamic error vector magnitude provided by the present invention. DETAILED DESCRIPTION

[0054] The technical content of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0055] As shown in Figure 1, a typical RF front-end module in the prior art includes a driver amplifier DA and its bias circuit Bias1, power supply Vreg1, a power amplifier PA and its bias circuit Bias2, power supply Vreg2, and a logic circuit unit Logic. When the GPIO interface provides a TX logic control signal, as shown in Figure 2, power supplies Vreg1 and Vreg2 begin to provide a constant voltage, and the driver amplifier DA and power amplifier PA begin operating, entering TX mode. The bias circuits Bias1 and Bias2 have temperature coefficients, providing temperature compensation to compensate for gain changes in the driver amplifier DA and power amplifier PA due to temperature rise during operation, thereby maintaining constant output power.

[0056] Typically, in circuit design, the temperature coefficient is controlled by adjusting the parameters of the bias circuits Bias1 and Bias2, or by controlling their relative positions on the layout of the driver amplifier DA and power amplifier PA to sense temperature changes and adjust the temperature compensation effect. Power supplies Vreg1 and Vreg2 are implemented using low-dropout (LDO) circuits, which provide a constant voltage or current to the driver amplifier DA and power amplifier PA.

[0057] Figure 3 shows the RF front-end module in TX mode. The horizontal axis represents the TX operating time, and the vertical axis represents the TX transmit power at a fixed input. When the operating time reaches 6ms, the change in output power (Power Gap) is defined as the power gap. To meet the DEVM requirements of WiFi 7, the absolute value of the power gap must be controlled within 0.05dB. The power gap is caused by the heat generated by the driver amplifier (DA) and power amplifier (PA) during TX operation, causing the temperature to rise. For HBT-based RF front-end modules, increasing temperature reduces gain, and when the TX input power remains constant, the output power decreases.

[0058] In order to solve the above-mentioned problems existing in the prior art, the present invention adopts a dynamic compensation method to dynamically compensate for the changes in output power caused by temperature changes during the PA working cycle to ensure that DEVM meets the requirements of WiFi7.

[0059] In a first embodiment of the present invention, as shown in FIG4 , a radio frequency front-end module for optimizing a dynamic error vector magnitude includes: a driving amplifier DA for performing gain amplification on an input radio frequency signal; a first bias circuit Bias1 for providing a bias voltage for the driving amplifier DA; a first dynamic power supply Vreg1 for providing a dynamic power supply voltage for the first bias circuit Bias1; a power amplifier PA for performing power amplification on the radio frequency signal; a second bias circuit Bias2 for providing a bias voltage for the power amplifier PA; a second dynamic power supply Vreg2 for providing a dynamic power supply voltage for the second bias circuit Bias2; a logic circuit Logic for generating a logic control signal to control the working state of related units based on a received baseband control signal; and a TX timer for recording TX working time. Among them, the RF signal input terminal TX_In is connected to the input terminal of the driving amplifier DA, the output terminal of the driving amplifier DA is connected to the input terminal of the power amplifier PA, and the output terminal of the power amplifier PA is connected to the RF signal output terminal TX_Out; the baseband control signal input terminal GPIO is connected to the input terminal of the logic circuit Logic, the output terminal of the logic circuit Logic is connected to the control terminal of the TX timer, and the output terminal of the TX timer is respectively connected to the control terminals of the first dynamic power supply Vreg1 and the second dynamic power supply Vreg2; the output terminal of the first dynamic power supply Vreg1 is connected to the power supply terminal of the first bias circuit Bias1, and the output terminal of the first bias circuit Bias1 is connected to the bias terminal of the driving amplifier DA; the output terminal of the second dynamic power supply Vreg2 is connected to the power supply terminal of the second bias circuit Bias2, and the output terminal of the second bias circuit Bias2 is connected to the bias terminal of the power amplifier PA.

[0060] When the logic circuit Logic receives a control signal indicating a TX command from the baseband via the GPIO port, the logic circuit Logic generates a logic control signal to control the relevant units to enter TX operating mode. The TX timer begins timing. When the timing reaches the first time t1, the second time t2, the third time t3, and so on, the nth time tn, the logic circuit Logic controls the first dynamic power supply Vreg1 and the second dynamic power supply Vreg2 to sequentially output a first voltage V1, a second voltage V2, a third voltage V3, and so on, the nth voltage Vn, which are supplied to the first bias circuit Bias1 and the second bias circuit Bias2, respectively. Here, n is a positive integer, and the nth time tn is less than the TX operating time, i.e., less than the packet duration of the transmitted signal. Consequently, within a TX operating time, the supply voltages of the first bias circuit Bias1 and the second bias circuit Bias2, i.e., the output voltages of the first dynamic power supply Vreg1 and the second dynamic power supply Vreg2, dynamically vary over time, providing different bias voltages to the driver amplifier DA and the power amplifier PA over time, thereby adjusting the gain variation in the TX operating mode.

[0061] As shown in Figure 5, when the output power decreases as the TX operating time increases, a design can be implemented so that each time the TX timer counts through a period Δt, the voltage output by the first dynamic power supply Vreg1 and the second dynamic power supply Vreg2 is increased by ΔV1 to compensate for the decrease in output power. The voltage increase ΔV1 can be set based on the power difference. As shown in Figure 5, the period Δt is 0.5ms. As time increases, the first voltage V1, the second voltage V2, the third voltage V3, and so on, the nth voltage Vn, increase by ΔV1 in sequence. The difference in output power corresponding to the maximum and minimum voltages is the power difference.

[0062] As shown in Figure 6, when the output power increases with the TX operating time, a design can be used where the TX timer controls the voltage output by the first dynamic power supply Vreg1 and the second dynamic power supply Vreg2 to decrease by ΔV2 each time the TX timer counts through a period Δt to compensate for the increase in output power. The voltage reduction ΔV2 can be set based on the magnitude of the power difference. As shown in Figure 6, the period Δt is 0.5ms. As time increases, the first voltage V1, the second voltage V2, the third voltage V3, and so on, the nth voltage Vn, decrease in sequence by ΔV2. The difference in output power corresponding to the maximum and minimum voltages is the power difference.

[0063] After the power supply of the bias circuit undergoes the above-mentioned dynamic compensation, as shown in FIG7 , the power difference of the output power can be controlled within 0.05 dB, meeting the DEVM requirements of WiFi7.

[0064] It should be noted that the control of the first dynamic power supply Vreg1 to sequentially output the first voltage V1, the second voltage V2, the third voltage V3, ..., and the nth voltage Vn, and the control of the second dynamic power supply Vreg2 to sequentially output the first voltage V1, the second voltage V2, the third voltage V3, ..., and the nth voltage Vn, can be equal or unequal during the same time period. Alternatively, depending on the specific circuit conditions, one of the first dynamic power supply Vreg1 and the second dynamic power supply Vreg2 can be a power supply with dynamic output and the other a power supply with fixed output.

[0065] In a second embodiment of the present invention, as shown in FIG8 , a radio frequency front-end module for optimizing dynamic error vector magnitude (DEM) includes: a driver amplifier DA, a first bias circuit Bias1, a first dynamic power supply Vreg1, a power amplifier PA, a second bias circuit Bias2, a second dynamic power supply Vreg2, a logic circuit Logic, a TX timer, and a voltage detection circuit. The difference from the first embodiment lies in the addition of a voltage detection circuit, the input of which is connected to the power supply VDD, and the output of which is connected to the logic circuit Logic and the TX timer, respectively. This circuit is used to detect the voltage of the power supply VDD and dynamically adjust the bias circuit supply voltage to accommodate application environments with varying power supply voltages VDD at the application end.

[0066] As shown in Figure 9, when the power supply VDD voltage is high (i.e., above the first threshold), assuming VDD = 5V, the circuit temperature is high, and the output power decreases as the TX operating time increases. When the power supply VDD voltage is low (i.e., below the second threshold), assuming VDD = 3.3V, the circuit temperature is low, and the output power increases as the TX operating time increases. Therefore, a voltage detection circuit is used to detect the power supply VDD voltage value, thereby dynamically adjusting the bias circuit's supply voltage compensation method.

[0067] As shown in Figure 10, when the voltage of the power supply VDD is high (i.e., higher than the preset first threshold), a compensation method is adopted in which the output voltage of the first dynamic power supply Vreg1 and / or the second dynamic power supply Vreg2 increases by ΔV1 as the TX operating time increases. When the voltage of the power supply VDD is low (i.e., lower than the preset second threshold), a compensation method is adopted in which the output voltage of the first dynamic power supply Vreg1 and / or the second dynamic power supply Vreg2 decreases by ΔV2 as the TX operating time increases. This achieves output power difference control within 0.05dB, meeting the DEVM requirements of WiFi7.

[0068] In a third embodiment of the present invention, as shown in FIG11 , a radio frequency front-end module for optimizing dynamic error vector magnitude (DEM) includes: a driver amplifier DA, a first bias circuit Bias1, a first dynamic power supply Vreg1, a power amplifier PA, a second bias circuit Bias2, a second dynamic power supply Vreg2, a logic circuit Logic, a TX timer, a voltage detection circuit, and a TX duty cycle detection circuit. The difference from the second embodiment lies in the addition of a TX duty cycle detection circuit, which is connected to the logic circuit Logic and the TX timer, respectively, and is used to detect the TX transmission duty cycle in a TDD operating mode, thereby dynamically adjusting the bias circuit supply voltage to adapt to different TX duty cycle applications at the application end.

[0069] As shown in Figures 12 and 13, for the two situations where the output power decreases or increases with increasing TX operating time, the compensation amplitude of the dynamic power supply voltage output by at least one of the first and second dynamic power supplies, according to multiple preset time periods, varies inversely with the TX duty cycle detected by the TX duty cycle detection circuit. Specifically, when the TX duty cycle detected by the TX duty cycle detection circuit is small (i.e., below a preset third threshold), assuming the duty cycle is 10%, the greater the compensation amplitude required for the output voltage of the first dynamic power supply Vreg1 and / or the second dynamic power supply Vreg2 to increase or decrease with increasing TX operating time. When the TX duty cycle detected by the TX duty cycle detection circuit is large (i.e., above a preset fourth threshold), assuming the duty cycle is 90%, the smaller the compensation amplitude required for the output voltage of the first dynamic power supply Vreg1 and / or the second dynamic power supply Vreg2 to increase or decrease with increasing TX operating time.

[0070] In a fourth embodiment of the present invention, as shown in FIG14 , a radio frequency front-end module for optimizing dynamic error vector magnitude (DEM) includes: a driver amplifier DA, a first bias circuit Bias1, a first dynamic power supply Vreg1, a power amplifier PA, a second bias circuit Bias2, a second dynamic power supply Vreg2, a logic circuit Logic, a TX timer, a non-TX timer, and a voltage detection circuit. The difference from the second embodiment lies in the addition of a non-TX timer, which is connected to the logic circuit Logic and the TX timer, respectively, and is used to record the time of the non-TX operating state. This allows the dynamic adjustment of the bias circuit supply voltage to adapt to different TX duty cycle application environments at the application end. The TX timer and the non-TX timer can be implemented using the same timer.

[0071] As shown in Figures 15 and 16, for the two situations where the output power decreases or increases with increasing TX operating time, the compensation amplitude of the dynamic power supply voltage output by at least one of the first and second dynamic power supplies, according to multiple preset time periods, varies in the same direction as the time the non-TX timer records the non-TX operating state. Specifically, when the non-TX timer records the non-TX operating state for a short time (i.e., below a preset fifth threshold), assuming the non-TX operating state lasts for 1ms, the smaller the compensation amplitude required for the output voltage of the first dynamic power supply Vreg1 and / or the second dynamic power supply Vreg2, which increases or decreases with increasing TX operating time. When the non-TX timer records the non-TX operating state for a long time (i.e., above a preset sixth threshold), assuming the non-TX operating state lasts for 6ms, the larger the compensation amplitude required for the output voltage of the first dynamic power supply Vreg1 and / or the second dynamic power supply Vreg2, which increases or decreases with increasing TX operating time. Furthermore, when the non-TX operating state lasts for a maximum time, Tmax, the compensation voltage difference between the output voltages of the first dynamic power supply Vreg1 and / or the second dynamic power supply Vreg2 also reaches its maximum value.

[0072] In the four aforementioned embodiments, a first dynamic power supply Vreg1 and a second dynamic power supply Vreg2 are used to power the bias circuit, and the gain variation in the TX operating mode is adjusted according to different control signals. In other embodiments of the present invention, a technical solution combining a dynamic output bias circuit with a fixed output bias power supply can also be used to adjust the gain variation in the TX operating mode according to different control signals. This solution is described in detail below in conjunction with the first and second embodiments.

[0073] In a fifth embodiment of the present invention, as shown in FIG17 , a radio frequency front-end module for optimizing dynamic error vector magnitude (DEM) includes: a driver amplifier DA, a first dynamic bias circuit Bias1, a first bias power supply Vreg1, a power amplifier PA, a second dynamic bias circuit Bias2, a second bias power supply Vreg2, a logic circuit Logic, a TX timer, and a voltage detection circuit. The first bias power supply Vreg1 and the second bias power supply Vreg2 are fixed-output power supplies that provide power to the first dynamic bias circuit Bias1 and the second dynamic bias circuit Bias2, respectively. The output of the voltage detection circuit is connected to the logic circuit Logic and the TX timer, and the output of the TX timer is connected to the control terminals of the first dynamic bias circuit Bias1 and the second dynamic bias circuit Bias2, respectively.

[0074] The voltage detection circuit is used to detect the voltage value of the power supply VDD and output a detection signal to the logic circuit Logic and the TX timer. For the two situations where the output power decreases or increases with the increase of TX working time, the logic circuit Logic sends a control signal through the TX timer to control the first dynamic bias circuit Bias1 and the second dynamic bias circuit Bias2 respectively, and output a bias current or voltage that increases or decreases in sequence with the increase of TX working time, thereby realizing a dynamic adjustment of the bias circuit compensation method and controlling the output power difference within 0.05dB, meeting the DEVM requirements of WiFi7.

[0075] Among them, the first dynamic bias circuit Bias1 and the second dynamic bias circuit Bias2 are shown in FIG18 , and an adjustable resistor R2 or other adjustable elements may be used to achieve dynamic adjustment of the output bias current or voltage.

[0076] It should be noted that, the first dynamic bias circuit Bias1 and the second dynamic bias circuit Bias2 can also be designed, according to specific circuit conditions, such that one of them is a bias circuit with a fixed output and the other is a bias circuit with a dynamic output.

[0077] From the analysis and description of the above embodiments, it can be seen that the RF front-end module for optimizing the dynamic error vector amplitude provided by the embodiments of the present invention adopts a technical solution of dynamic voltage compensation to dynamically compensate for the changes in output power caused by temperature changes during the PA working cycle, thereby ensuring that DEVM meets the requirements of WiFi7.

[0078] The RF front-end module for optimizing dynamic error vector amplitude provided by the embodiment of the present invention can be used in electronic devices as an important component of communication components. The electronic equipment referred to here refers to computer equipment that can be used in a mobile environment and supports multiple communication standards such as GSM, EDGE, CDMA, TD_SCDMA, WCDMA, TDD_LTE, FDD_LTE, NR, etc., including mobile phones, laptops, tablet computers, car computers, etc. In addition, the technical solution provided by the present invention is also applicable to other applications of radio frequency integrated circuits, such as communication base stations, intelligent connected vehicles, etc.

[0079] As shown in Figure 19, the electronic device includes at least a processor, a memory and a communication component, and may further include a sensor component, a power component, a multimedia component and an input / output interface according to actual needs. Among them, the memory, communication component, sensor component, power component, multimedia component and input / output interface are all connected to the processor. The memory can be a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, etc., and the processor can be a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processing (DSP) chip, etc. Other communication components, sensor components, power components, multimedia components, etc. can all be implemented using general components and are not specifically described here.

[0080] In summary, compared with the prior art, the RF front-end module with optimized dynamic error vector magnitude provided by the embodiments of the present invention dynamically compensates for changes in output power caused by temperature changes within the PA operating cycle by adopting a dynamic voltage compensation technical solution, ensuring that the DEVM meets the requirements of WiFi7. At the same time, it solves the problem of inconsistent temperature compensation requirements caused by different PA temperature changes under different packages or different layouts, or under different voltages and different TX duty cycles, thereby shortening the product development cycle. Therefore, the RF front-end module with optimized dynamic error vector magnitude provided by the embodiments of the present invention has the beneficial effects of ingenious and reasonable structural design, low design cost, and excellent circuit performance.

[0081] It should be noted that the above embodiments are only examples, the technical solutions of the various embodiments can be combined, and each unit circuit can be implemented using a corresponding circuit in the prior art, all of which are within the protection scope of the present invention.

[0082] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0083] The above describes in detail the RF front-end module and electronic device for optimizing dynamic error vector magnitude (DEM) provided by the present invention. However, any obvious modification to this invention without departing from its essence would constitute an infringement of the present invention's patent rights and would incur corresponding legal liability.

Claims

1. A radio frequency front-end module for optimizing dynamic error vector amplitude, characterized in that At least one transmission path is included; wherein each transmission path includes: A driving amplifier, used for gain amplifying the input RF signal, wherein the input end thereof is connected to the RF signal input end, and the output end thereof is connected to the input end of the power amplifier; A first bias circuit, used for providing a bias voltage for the driving amplifier, wherein an output terminal of the first bias circuit is connected to a bias terminal of the driving amplifier; A first dynamic power supply, used for providing a power supply voltage for the first bias circuit, and an output end of the first dynamic power supply is connected to a power supply end of the first bias circuit; A power amplifier, used for amplifying the power of the radio frequency signal, and an output end thereof is connected to the output end of the radio frequency signal; A second bias circuit, used for providing a bias voltage for the power amplifier, wherein an output end of the second bias circuit is connected to a bias end of the power amplifier; A second dynamic power supply, used for providing a power supply voltage for the second bias circuit, and an output end of the second dynamic power supply is connected to a power supply end of the second bias circuit; A logic circuit, used for generating a logic control signal to control the working state of a related unit according to a received baseband control signal; an input end of the logic circuit is connected to an input end of the baseband control signal, and an output end of the logic circuit is connected to a control end of a TX timer; TX timer, used to record TX working time; When the logic circuit receives a TX instruction, it controls the transmission path to enter the TX working mode, and the TX timer starts timing. When the first time, the second time, the third time...the nth time are reached respectively, at least one of the first dynamic power supply and the second dynamic power supply sequentially outputs a first voltage, a second voltage, a third voltage...the nth voltage, and provides them to the first bias circuit and / or the second bias circuit to dynamically compensate for the output power change caused by the circuit temperature change, wherein n is a positive integer.

2. The RF front-end module for optimizing DEVM according to claim 1, characterized in that: The output end of the TX timer is connected to the control end of the first dynamic power supply and the control end of the second dynamic power supply respectively.

3. The RF front-end module for optimizing dynamic error vector magnitude according to claim 2, characterized in that: When the output power decreases with the increase of TX working time, at least one of the first dynamic power supply and the second dynamic power supply outputs an increasing first voltage, a second voltage, a third voltage...the nth voltage in sequence at a first time, a second time, a third time...the nth time, and provides them to the first bias circuit and / or the second bias circuit.

4. The RF front-end module for optimizing dynamic error vector magnitude according to claim 2, characterized in that: When the output power increases with the increase of TX working time, at least one of the first dynamic power supply and the second dynamic power supply outputs a decreasing first voltage, a second voltage, a third voltage...the nth voltage in sequence at a first time, a second time, a third time...the nth time, and provides them to the first bias circuit and / or the second bias circuit.

5. The RF front-end module for optimizing dynamic error vector magnitude according to claim 1, characterized in that: The transmitting path also includes a voltage detection circuit, an input end of which is connected to a power source VDD; and an output end of which is respectively connected to the logic circuit and the TX timer.

6. The RF front-end module for optimizing dynamic error vector magnitude according to claim 5, characterized in that: When the voltage of the power supply VDD is higher than the first threshold, the output power decreases as the TX working time increases; the output voltage of at least one of the first dynamic power supply and the second dynamic power supply increases in sequence as the TX working time increases, and is provided to the first bias circuit and / or the second bias circuit; When the voltage of the power supply VDD is lower than the second threshold, the output power increases with the increase of TX working time; the output voltage of at least one of the first dynamic power supply and the second dynamic power supply decreases successively with the increase of TX working time, and is provided to the first bias circuit and / or the second bias circuit.

7. The RF front-end module for optimizing dynamic error vector magnitude according to claim 1, characterized in that: The transmission path also includes a TX duty cycle detection circuit, which is connected to the logic circuit and the TX timer respectively; and is used to detect the duty cycle of TX transmission in the TDD working mode.

8. The RF front-end module for optimizing dynamic error vector magnitude according to claim 7, characterized in that: When the TX duty cycle detected by the TX duty cycle detection circuit is lower than a third threshold, the output voltage of at least one of the first dynamic power supply and the second dynamic power supply increases or decreases in sequence with increasing TX working time, the greater the compensation amplitude; When the TX duty cycle detected by the TX duty cycle detection circuit is higher than a fourth threshold, the output voltage of at least one of the first dynamic power supply and the second dynamic power supply increases or decreases in sequence with increasing TX working time, and the compensation amplitude is smaller.

9. The RF front-end module for optimizing dynamic error vector magnitude according to claim 1, characterized in that: The transmitting path also includes a non-TX timer, which is connected to the logic circuit and the TX timer respectively, and is used to record the time of the non-TX working state.

10. The RF front-end module for optimizing dynamic error vector magnitude according to claim 9, characterized in that: When the time of the non-TX working state recorded by the non-TX timer is lower than the fifth threshold, the output voltage of at least one of the first dynamic power supply and the second dynamic power supply increases or decreases in sequence with the increase of the TX working time, and the compensation amplitude is smaller; When the time for which the non-TX working state is recorded by the non-TX timer is higher than the sixth threshold, the output voltage of at least one of the first dynamic power supply and the second dynamic power supply increases or decreases with increasing TX working time, and the compensation amplitude thereof increases.

11. The RF front-end module for optimizing dynamic error vector magnitude according to claim 1, characterized in that: The first bias circuit and the second bias circuit in the transmitting path respectively adopt a first dynamic bias circuit and a second dynamic bias circuit; The output end of the TX timer is connected to the control end of the first dynamic bias circuit and the control end of the second dynamic bias circuit respectively.

12. The RF front-end module for optimizing dynamic error vector magnitude according to claim 11, characterized in that: When the output power decreases or increases with the increase of the TX working time, the logic circuit sends a control signal through the TX timer to control at least one of the first dynamic bias circuit and the second dynamic bias circuit to output the output power as the TX working time increases. A bias current or voltage that increases or decreases sequentially with time.

13. An electronic device, characterized in that A radio frequency front-end module comprising the optimized dynamic error vector amplitude as claimed in any one of claims 1 to 12.

Images