Nitride semiconductor device

Abstract

This nitride semiconductor device includes: a conductive substrate having a substrate upper surface; a high-resistance layer; a nitride semiconductor layer formed on the high-resistance layer; a first electrode (source electrode) formed on the nitride semiconductor layer; and a via. The high-resistance layer is formed on the substrate upper surface, and has a higher resistance value than does the conductive substrate. The via is electrically connected to the first electrode (source electrode), is provided so as to pass through the nitride semiconductor layer and the high-resistance layer, and contacts the substrate upper surface.

Description

nitride semiconductor devices

[0001] The present invention relates to a nitride semiconductor device.

[0002] Currently, high electron mobility transistors (HEMTs) using group III nitride semiconductors (hereinafter sometimes simply referred to as "nitride semiconductors") such as gallium nitride (GaN) are being commercialized. HEMTs use two-dimensional electron gas (2DEG) formed near the interface of a semiconductor heterojunction as a conductive path (channel). Power devices using HEMTs are recognized as devices that enable lower on-resistance and higher speed / frequency operation compared to typical silicon (Si) power devices.

[0003] For example, a nitride semiconductor device described in Patent Document 1 includes a silicon substrate having an upper surface and a lower surface, an electron transit layer formed on the upper surface of the silicon substrate and composed of a gallium nitride (GaN) layer, and an electron supply layer formed on the electron transit layer and composed of an aluminum gallium nitride (AlGaN) layer. A 2DEG is formed in the electron transit layer near the heterojunction interface between the electron transit layer and the electron supply layer.

[0004] Patent No. 6877896

[0005] [Summary] The nitride semiconductor device of Patent Document 1 further includes a source electrode, a drain electrode, and a gate electrode formed on the electron supply layer, a backside electrode formed on the underside of the silicon substrate, and a via that penetrates the silicon substrate and connects the source electrode and the backside electrode. It is desirable to reduce the cost required for manufacturing nitride semiconductors with vias.

[0006] A nitride semiconductor device according to one aspect of the present disclosure includes a conductive substrate having a substrate upper surface, a high-resistance layer formed on the substrate upper surface and having a resistance higher than that of the conductive substrate, a nitride semiconductor layer formed on the high-resistance layer, a first electrode formed on the nitride semiconductor layer, and a via electrically connected to the first electrode, the via penetrating the nitride semiconductor layer and the high-resistance layer, and contacting the substrate upper surface.

[0007] A nitride semiconductor device according to one aspect of the present disclosure includes a substrate having a substrate upper surface and a substrate lower surface facing the opposite side to the substrate upper surface, a high-resistivity layer formed on the substrate upper surface of the substrate and having a resistance value higher than that of the substrate, a nitride semiconductor layer formed on the high-resistivity layer, a first electrode formed on the nitride semiconductor layer, a second electrode formed below the substrate lower surface of the substrate, and a via extending through the nitride semiconductor layer, the high-resistivity layer, and the substrate and electrically connecting the first electrode and the second electrode.

[0008] FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line 2-2 of FIG. 1. FIG. 3 is a schematic cross-sectional view showing an exemplary manufacturing process for the nitride semiconductor device according to the first embodiment. FIG. 4 is a schematic cross-sectional view showing a manufacturing process subsequent to the process shown in FIG. 3. FIG. 5 is a schematic cross-sectional view showing a manufacturing process subsequent to the process shown in FIG. 4. FIG. 6 is a schematic cross-sectional view showing a manufacturing process subsequent to the process shown in FIG. 5. FIG. 7 is a schematic cross-sectional view showing a manufacturing process subsequent to the process shown in FIG. 6. FIG. 8 is a schematic cross-sectional view showing a manufacturing process subsequent to the process shown in FIG. 7. FIG. 9 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to a second embodiment. FIG. 10 is a schematic cross-sectional view showing an exemplary manufacturing process for the nitride semiconductor device according to the second embodiment. FIG. 11 is a schematic cross-sectional view showing a manufacturing process subsequent to the process shown in FIG. 10. FIG. 12 is a schematic cross-sectional view showing a manufacturing process subsequent to the process shown in FIG. 11. FIG. 13 is a schematic cross-sectional view showing a manufacturing process subsequent to the process shown in FIG. 12. FIG. 14 is a schematic cross-sectional view showing a manufacturing process subsequent to the process shown in FIG. 13. FIG. 15 is a schematic cross-sectional view showing a manufacturing process of a modified example subsequent to the process shown in FIG. 3. Fig. 16 is a schematic cross-sectional view showing a manufacturing process of a modified example subsequent to the process shown in Fig. 15. Fig. 17 is a schematic cross-sectional view showing a manufacturing process of a modified example subsequent to the process shown in Fig. 16. Fig. 18 is a schematic cross-sectional view showing a manufacturing process of a modified example subsequent to the process shown in Fig. 17.

[0009] DETAILED DESCRIPTION Hereinafter, embodiments of nitride semiconductor devices according to the present disclosure will be described with reference to the accompanying drawings.

[0010] For simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0011] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0012] First Embodiment FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device 10 according to an embodiment. FIG. 2 is a schematic cross-sectional view of the nitride semiconductor device 10, taken along line 2-2 of FIG. 1. The term "plan view" used in the present disclosure refers to viewing the nitride semiconductor device 10 in the Z direction of the mutually orthogonal X, Y, and Z axes shown in FIGS. 1 and 2. For convenience, the +Z direction is defined as up, the −Z direction as down, the +X direction as right, and the −X direction as left in the nitride semiconductor device 10 shown in FIG. 1. Unless otherwise expressly specified, "plan view" refers to viewing the nitride semiconductor device 10 from above along the Z axis. Unless otherwise expressly specified, thickness refers to the dimension along the Z direction.

[0013] As an example, the nitride semiconductor device 10 may be a HEMT using GaN. Below, a cross-sectional structure of the nitride semiconductor device 10 will be described with reference to Fig. 2, and then a planar structure of the nitride semiconductor device 10 will be described with reference to Fig. 1.

[0014] 2 , the nitride semiconductor device 10 includes a conductive substrate 12, a high-resistance layer 13 formed on the conductive substrate 12, a buffer layer 14 formed on the high-resistance layer 13, and a nitride semiconductor layer 40 formed on the buffer layer 14. The buffer layer 14 and the nitride semiconductor layer 40 are epitaxially grown on an upper surface 13A of the high-resistance layer 13. The nitride semiconductor layer 40 includes an electron transit layer 16 formed on the buffer layer 14, and an electron supply layer 18 formed on the electron transit layer 16. Details of the conductive substrate 12 and the high-resistance layer 13 will be described later.

[0015] The buffer layer 14 is formed on the upper surface 13A of the high-resistivity layer 13. The buffer layer 14 may be located between the high-resistivity layer 13 and the electron transit layer 16. In one example, the buffer layer 14 may be made of any material that can facilitate epitaxial growth of the electron transit layer 16. The buffer layer 14 may include one or more nitride semiconductor layers. The thickness of the buffer layer 14 (when there are multiple buffer layers 14, the total thickness of the multiple buffer layers 14) is, for example, 50 nm or more and 1 μm or less. The buffer layer 14 may be omitted.

[0016] In one example, the buffer layer 14 may include at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having different aluminum (Al) compositions. For example, the buffer layer 14 may be composed of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure. To suppress leakage current in the buffer layer 14, impurities may be introduced into a portion of the buffer layer 14 to make the buffer layer 14 semi-insulating. In this case, the impurity may be, for example, carbon (C) or iron (Fe), and the impurity concentration may be, for example, 4×10 １６ cm －３ It can be more than that.

[0017] The electron transit layer 16 is made of a nitride semiconductor. The electron transit layer 16 is, for example, a GaN layer. The thickness of the electron transit layer 16 is, for example, 0.5 μm or more and 2 μm or less. In order to suppress leakage current in the electron transit layer 16, an impurity may be introduced into a part of the electron transit layer 16 to make the electron transit layer 16 semi-insulating except for the surface region. In this case, the impurity may be, for example, C, and the peak concentration of the impurity in the electron transit layer 16 may be, for example, 1×10 １９ cm －３ That's all.

[0018] The electron supply layer 18 is made of a nitride semiconductor having a larger band gap than the electron transit layer 16. The electron supply layer 18 is, for example, an AlGaN layer. In this case, the band gap increases as the Al composition increases, so the electron supply layer 18, which is an AlGaN layer, has a larger band gap than the electron transit layer 16, which is a GaN layer. In one example, the electron supply layer 18 is made of Al ｘ Ga １－ｘ The electron supply layer 18 is made of N, where x satisfies 0.1<x<0.4, and more preferably 0.2<x<0.3. The thickness of the electron supply layer 18 is, for example, not less than 5 nm and not more than 20 nm.

[0019] The electron transit layer 16 and the electron supply layer 18 are made of nitride semiconductors with different lattice constants. Therefore, the nitride semiconductor (e.g., GaN) that constitutes the electron transit layer 16 and the nitride semiconductor (e.g., AlGaN) that constitutes the electron supply layer 18 form a lattice-mismatched heterojunction. Due to spontaneous polarization in the electron transit layer 16 and the electron supply layer 18 and piezoelectric polarization caused by stress applied to the electron supply layer 18 near the heterojunction interface, the energy level of the conduction band of the electron transit layer 16 near the heterojunction interface is lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 20 spreads within the electron transit layer 16 near the heterojunction interface between the electron transit layer 16 and the electron supply layer 18 (e.g., within a range of several nanometers from the interface).

[0020] The nitride semiconductor device 10 further includes a gate layer 22 formed on the electron supply layer 18, a gate electrode 24 formed on the gate layer 22, and a passivation layer 26. The passivation layer 26 is formed on the electron supply layer 18, the gate layer 22, and the gate electrode 24, and includes a first opening 26A and a second opening 26B. The nitride semiconductor device 10 further includes a source electrode 28 in contact with the upper surface 18A of the electron supply layer 18 through the first opening 26A, a drain electrode 30 in contact with the upper surface 18A of the electron supply layer 18 through the second opening 26B, and a via 50. The via 50 will be described in detail later.

[0021] The gate layer 22 is located between the first opening 26A and the second opening 26B of the passivation layer 26 and is spaced apart from each of the first opening 26A and the second opening 26B. The gate layer 22 is located closer to the first opening 26A than to the second opening 26B. The thickness of the gate layer 22 is, for example, not less than 100 nm and not more than 200 nm.

[0022] The gate layer 22 has a band gap smaller than that of the electron supply layer 18 and is made of a nitride semiconductor containing acceptor-type impurities. The gate layer 22 can be made of any material having a band gap smaller than that of the electron supply layer 18, which is, for example, an AlGaN layer. In one example, the gate layer 22 is a GaN layer doped with acceptor-type impurities (a p-type GaN layer).

[0023] The acceptor-type impurities may include at least one of magnesium (Mg), zinc (Zn), and C. An example of the acceptor-type impurity is Mg. The maximum concentration of the acceptor-type impurity in the gate layer 22 is, for example, 1×10 １８ cm －３ or more, or 1 x 10 １９ cm －３ The maximum concentration of the acceptor-type impurity in the gate layer 22 is, for example, 1×10 ２０ cm －３ The following is the result.

[0024] As described above, the energy levels of the electron transit layer 16 and the electron supply layer 18 are raised by including acceptor-type impurities in the gate layer 22. Therefore, in the region immediately below the gate layer 22, the energy level of the conduction band of the electron transit layer 16 near the heterojunction interface between the electron transit layer 16 and the electron supply layer 18 is approximately the same as or higher than the Fermi level. Therefore, at zero bias when no voltage is applied to the gate electrode 24, no 2DEG 20 is formed in the region of the electron transit layer 16 immediately below the gate layer 22. On the other hand, 2DEG 20 is formed in the region of the electron transit layer 16 other than the region immediately below the gate layer 22.

[0025] In this way, the presence of the gate layer 22 doped with acceptor-type impurities causes the 2DEG 20 to disappear in the region directly below the gate layer 22. As a result, normally-off operation of the transistor is achieved. When an appropriate on-voltage is applied to the gate electrode 24, a channel is formed by the 2DEG 20 in the electron transit layer 16 in the region directly below the gate electrode 24, thereby establishing conduction between the source and drain.

[0026] The gate electrode 24 is composed of one or more metal layers. One example of the gate electrode 24 is a titanium nitride (TiN) layer. Alternatively, the gate electrode 24 may be composed of a first metal layer made of a material containing Ti and a second metal layer made of a material containing TiN and stacked on the first metal layer. The gate electrode 24 can form a Schottky junction with the gate layer 22. The gate electrode 24 can be formed in an area smaller than the gate layer 22 in a plan view. The thickness of the gate electrode 24 is, for example, 50 nm or more and 200 nm or less.

[0027] The passivation layer 26 is formed on the electron supply layer 18. It can also be said that the passivation layer 26 covers the upper surface 18A of the electron supply layer 18. The passivation layer 26 is made of, for example, silicon nitride (SiN), silicon dioxide (SiO ２ ), silicon oxynitride (SiON), alumina (Al ２ O ３The passivation layer 26 may be made of a material containing one of silicon nitride (SiN), aluminum nitride (AlN), and aluminum oxynitride (AlON). In one example, the passivation layer 26 is made of a material containing silicon nitride (SiN). The portion of the passivation layer 26 covering the gate layer 22 and the gate electrode 24 is formed along the surfaces of the gate layer 22 and the gate electrode 24, and therefore has an uneven surface. The passivation layer 26 has a thickness of, for example, 200 nm or less. Here, the thickness of the passivation layer 26 may be, for example, the thickness of the portion in contact with the electron supply layer 18 or the thickness of the portion in contact with the upper surface of the gate electrode 24.

[0028] The source electrode 28 and the drain electrode 30 are disposed in the X direction on the upper surface 18A of the electron supply layer 18, sandwiching the gate layer 22. The source electrode 28 and the drain electrode 30 may be formed of one or more metal layers. For example, the source electrode 28 and the drain electrode 30 may be formed of a combination of two or more metal layers selected from a group including a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer. At least a portion of the source electrode 28 is filled in the first opening 26A and makes ohmic contact with the 2DEG 20 directly below the electron supply layer 18 through the first opening 26A. Similarly, at least a portion of the drain electrode 30 is filled in the second opening 26B and makes ohmic contact with the 2DEG 20 directly below the electron supply layer 18 through the second opening 26B.

[0029] [Details of the Substrate and High-Resistance Layer] The conductive substrate 12 has a substrate upper surface 12A and a substrate lower surface 12B facing the opposite side to the substrate upper surface 12A. The resistance value of the conductive substrate 12 is, for example, 2×10 －２The resistivity is Ωcm or less. An example of the conductive substrate 12 is a silicon carbide (SiC) substrate. To achieve low resistance, the conductive substrate 12 may be doped with impurities. The impurities may be, for example, nitrogen (N). The conductive substrate 12 is preferably polycrystalline, i.e., a polycrystalline SiC substrate. Note that, instead of a SiC substrate, other semiconductor substrates such as a silicon (Si) substrate, a GaN substrate, or a sapphire substrate may also be used as the conductive substrate 12. Even in this case, the conductive substrate 12 may be doped with impurities or may be polycrystalline.

[0030] The thickness T1 of the conductive substrate 12 is, for example, 50 μm or more, preferably 100 μm or more, and for example, 500 μm or less, preferably 350 μm or less.

[0031] The high-resistance layer 13 has an upper surface 13A and a lower surface 13B facing the opposite side to the upper surface 13A. The lower surface 13B is the surface of the high-resistance layer 13 facing the conductive substrate 12 side. The high-resistance layer 13 is a layer for insulating between the conductive substrate 12 and the nitride semiconductor layer 40. The resistance value of the high-resistance layer 13 is higher than the resistance value of the conductive substrate 12. The resistance value of the high-resistance layer 13 is, for example, 1×10 ５ Ωcm or more. In one example where the buffer layer 14 is included, the resistance of the high-resistance layer 13 is higher than the resistance of the buffer layer 14 itself. In one example where the buffer layer 14 is included, the resistance of the high-resistance layer 13 is higher than the resistance of the entire buffer layer 14. In one example where the buffer layer 14 is not included, the resistance of the high-resistance layer 13 is higher than the resistance of the electron transit layer 16.

[0032] The high-resistance layer 13 can be formed of a semiconductor material such as Si, SiC, GaN, or sapphire. The high-resistance layer 13 may be irradiated with an electron beam to achieve high resistance. An example of the high-resistance layer 13 is a single crystal. For example, the high-resistance layer 13 is a single-crystal SiC layer. An example of the high-resistance layer 13 that is a single-crystal SiC layer is a hexagonal SiC layer having an upper surface 13A inclined at an off-angle of 2° to 6° with respect to the c-plane. In this disclosure, the term "c-plane" is used to refer to the (0001) plane of a hexagonal SiC crystal. The off-angle is preferably 3° to 5°, more preferably 3.5° to 4.5°.

[0033] It is also preferable that the high-resistance layer 13 has a thermal expansion coefficient close to that of the conductive substrate 12. For example, the difference between the thermal expansion coefficient of the conductive substrate 12 and the thermal expansion coefficient of the high-resistance layer 13 is 1×10 －６ (1 / ° C.) or less. In this case, the occurrence of warping due to the difference in the thermal expansion coefficient between the high-resistance layer 13 and the conductive substrate 12 can be suppressed.

[0034] To reduce the difference in thermal expansion coefficient, it is preferable to use a combination of the conductive substrate 12 and the high-resistance layer 13 made of the same material. Examples of such combinations include a SiC substrate and a SiC layer, and a GaN substrate and a GaN layer. One example of a combination of the conductive substrate 12 and the high-resistance layer 13 is a polycrystalline SiC substrate for the conductive substrate 12 and a single-crystal SiC layer for the high-resistance layer 13.

[0035] The thickness T2 of the high-resistance layer 13 is, for example, 100 μm or less, and preferably 20 μm or less. By reducing the thickness T2 of the high-resistance layer 13, the length L1 of the via 50, which will be described later, can be shortened. The thickness T2 of the high-resistance layer 13 is, for example, 3 μm or more. In one example, the thickness T2 of the high-resistance layer 13 is thinner than the thickness T1 of the conductive substrate 12. The thickness T2 of the high-resistance layer 13 may be thicker than the thickness T1 of the conductive substrate 12. In one example, the thickness T2 of the high-resistance layer 13 is thinner than the thickness of the buffer layer 14 (or the total thickness of the buffer layer 14 if the buffer layer 14 is made up of multiple layers). The thickness T2 of the high-resistance layer 13 may be thicker than the thickness of the buffer layer 14.

[0036] [Details of Via] The via 50 is electrically connected to the source electrode 28 and connects the source electrode 28 and the conductive substrate 12 in the Z direction. In this embodiment, the electrode corresponding to the first electrode is the source electrode 28. A source voltage is applied to the conductive substrate 12 through the source electrode 28 and the via 50.

[0037] The via 50 penetrates in the Z direction through the layers interposed between the source electrode 28 and the conductive substrate 12. More specifically, the via 50 penetrates in the Z direction through the high-resistance layer 13, the buffer layer 14, the electron transit layer 16, and the electron supply layer 18. A lower end 50B of the via 50 contacts the substrate upper surface 12A of the conductive substrate 12. An upper end 50A of the via 50 contacts the source electrode 28. The shape and size of the via 50 are not particularly limited and can be changed as desired. The number of vias 50 is also not particularly limited and may be one or more.

[0038] The length L1 of the via 50 is the total thickness (Z-direction dimension) of the layers interposed between the source electrode 28 and the conductive substrate 12. The via 50 may be made of one or more conductive materials. The conductive material is, for example, a metal material including one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. In one example, the via 50 is made of the same material as the source electrode 28. In this case, the via 50 and the source electrode 28 may be integrally formed, i.e., may have no joining surface between them.

[0039] [Planar Structure of Nitride Semiconductor Device] Next, the planar structure of the nitride semiconductor device 10 will be described with reference to Fig. 1. In Fig. 1, the passivation layer 26 and the source electrode 28 are not shown, and a first opening 26A and a second opening 26B of the passivation layer 26 are depicted by dashed lines.

[0040] The nitride semiconductor device 10 has, for example, active regions that contribute to transistor operation and inactive regions (not shown) that do not contribute to transistor operation. In one example, the active regions and inactive regions are arranged alternately in the Y direction.

[0041] In the active region of the nitride semiconductor device 10, the source electrode 28 (see FIG. 2), the gate electrode 24, and the drain electrode 30 are arranged adjacent to each other in the X direction on the electron supply layer 18 (see FIG. 2). A combination of the source electrode 28, the gate electrode 24, and the drain electrode 30 adjacent to each other in the X direction constitutes one HEMT cell 10HC. In the example of FIG. 1, two HEMT cells 10HC are arranged in the X direction in the active region. In practice, more HEMT cells 10HC may be arranged in each active region.

[0042] [Method of Manufacturing a Nitride Semiconductor Device] An exemplary method of manufacturing the nitride semiconductor device 10 will be described with reference to Figures 3 to 8. In Figures 3 to 8, components similar to those in Figure 2 are denoted by the same reference numerals.

[0043] 3 and 4, the manufacturing method of the nitride semiconductor device 10 includes a step of forming a conductive substrate 12 on the lower surface 13B of the high-resistance layer 13. As shown in Fig. 3, a flat plate-shaped member having a specific thickness and an upper surface 13A and a lower surface 13B is prepared as the high-resistance layer 13. The member is, for example, a single-crystal SiC substrate whose upper surface 13A is inclined at an off-angle of 2° to 6° with respect to the c-plane, and whose resistance is 1 × 10 ５ The conductive substrate 12 is, for example, a polycrystalline SiC substrate.

[0044] In one example, the conductive substrate 12 can be formed on the high-resistance layer 13 using a chemical vapor deposition (CVD) method. In this case, it is preferable to use a specific SiC layer formed by a specific process as the high-resistance layer 13 used in the manufacturing method of the nitride semiconductor device 10. Specifically, in the presence of a gaseous substance including an inert gas, a SiC film is formed on a layer containing one or both of graphene and hexagonal boron nitride on a substrate, and then the SiC film is peeled off from the substrate. The peeled SiC film is used as the high-resistance layer 13, and a SiC layer constituting the conductive substrate 12 is formed on the surface of the SiC film.

[0045] In another example, the conductive substrate 12 can be formed by bonding a semiconductor layer that will become the conductive substrate 12 to the lower surface 13B of the high-resistance layer 13. For example, the lower surface 13B of the high-resistance layer 13 is irradiated with a specific impurity in a vacuum, and the surface of the semiconductor layer that will become the conductive substrate 12 is irradiated with the specific impurity in a vacuum. Then, in the vacuum where the specific impurity has been irradiated, the lower surface 13B of the high-resistance layer 13 and the surface of the semiconductor layer are bonded, and then a heat treatment is performed. The specific impurity is an inactive impurity that does not generate carriers in the high-resistance layer 13 and the semiconductor layer. The heat treatment temperature can be determined depending on the materials that make up the high-resistance layer 13 and the semiconductor layer that will become the conductive substrate 12. For example, when the materials that make up the high-resistance layer 13 and the semiconductor layer that will become the conductive substrate 12 are both SiC, the heat treatment temperature is 1500°C or higher, for example, approximately 1700°C.

[0046] 5 , the method for manufacturing the nitride semiconductor device 10 includes the step of forming a buffer layer 14 and a nitride semiconductor layer 40 on the high-resistance layer 13. The buffer layer 14, and the electron transit layer 16 and electron supply layer 18 as the nitride semiconductor layer 40 are formed on the upper surface 13A of the high-resistance layer 13. The electron transit layer 16 is formed on the buffer layer 14, and the electron supply layer 18 is formed on the electron transit layer 16.

[0047] The buffer layer 14, the electron transit layer 16, and the electron supply layer 18 can be epitaxially grown on the high-resistance layer 13 by using a metal organic chemical vapor deposition (MOCVD) method. These layers are made of nitride semiconductors with relatively similar lattice constants, and therefore can be epitaxially grown continuously.

[0048] The buffer layer 14 is, for example, a multi-layer buffer layer in which an AlN layer (first buffer layer) is formed on the high-resistance layer 13, and then a graded AlGaN layer (second buffer layer) is formed on the AlN layer. The graded AlGaN layer is formed, for example, by stacking three AlGaN layers with Al compositions of 75%, 50%, and 25%, in that order from the side closest to the AlN layer.

[0049] The electron transit layer 16 and the electron supply layer 18 are formed by sequentially stacking them on the buffer layer 14. During the epitaxial growth of the electron transit layer 16 and the electron supply layer 18, a doping gas may be introduced into the growth chamber as needed. This allows the desired layer to be doped with an impurity. For example, during the epitaxial growth of the electron supply layer 18, Si is doped as an n-type impurity. This allows the electron supply layer 18 to be formed containing an n-type impurity.

[0050] 6 and 7 , the method for manufacturing the nitride semiconductor device 10 includes a step of forming a via 50 in the high-resistance layer 13, the buffer layer 14, and the nitride semiconductor layer 40. The step of forming the via 50 includes a step of forming a through-hole 51 that penetrates the high-resistance layer 13, the buffer layer 14, and the nitride semiconductor layer 40, and a step of filling the through-hole 51 with a conductive material.

[0051] As shown in FIG. 6 , the through-hole 51 penetrates the high-resistance layer 13, the buffer layer 14, and the nitride semiconductor layer 40, and is formed so as to open to the upper surface of the nitride semiconductor layer 40 (the upper surface 18A of the electron supply layer 18) and the lower surface 13B of the high-resistance layer 13. In one example, the through-hole 51 is formed by grinding the high-resistance layer 13, the buffer layer 14, and the nitride semiconductor layer 40. In another example, the through-hole 51 is formed by selectively removing parts of the high-resistance layer 13, the buffer layer 14, and the nitride semiconductor layer 40 by lithography and etching. The through-hole 51 is formed from the upper surface of the nitride semiconductor layer 40 (the upper surface 18A of the electron supply layer 18). The upper surface of the conductive substrate 12 is exposed through the through-hole 51. Next, as shown in FIG. 7 , a conductive material is filled in the through-hole 51 to form a via 50.

[0052] 8 , the method for manufacturing the nitride semiconductor device 10 includes the steps of forming a gate layer 22, a gate electrode 24, a passivation layer 26, a source electrode 28, and a drain electrode 30. In this embodiment, the step of forming the source electrode 28 is a step of forming a first electrode on the nitride semiconductor layer 40.

[0053] The gate layer 22 is formed by selectively removing a nitride semiconductor layer (not shown) formed on the electron supply layer 18 by lithography and etching. The nitride semiconductor layer can be epitaxially grown on the electron supply layer 18 by MOCVD. During the epitaxial growth of the nitride semiconductor layer, a doping gas is introduced into the growth chamber. For example, Mg is doped as an acceptor-type impurity during the epitaxial growth of the nitride semiconductor layer. This allows the gate layer 22 containing the acceptor-type impurity to be formed.

[0054] The gate electrode 24 is formed on the gate layer 22. In one example, the gate electrode 24 is formed by selectively removing a metal layer (not shown) formed on the nitride semiconductor layer 40 by lithography and etching.

[0055] The passivation layer 26 is formed on the electron supply layer 18, the gate layer 22, and the gate electrode 24. The passivation layer 26 is formed so as to cover a portion of the electron supply layer 18, the gate layer 22, and the gate electrode 24. In one example, the passivation layer 26 can be formed using a low-pressure chemical vapor deposition (LPCVD) method.

[0056] A first opening 26A exposing the electron supply layer 18 and the via 50 is formed in the passivation layer 26, and a second opening 26B exposing the electron supply layer 18 is formed. The first opening 26A and the second opening 26B are formed so that the gate layer 22 is located between the first opening 26A and the second opening 26B. The first opening 26A and the second opening 26B are formed by selectively removing a portion of the formed passivation layer 26 by lithography and etching.

[0057] The source electrode 28 is formed to contact the upper surface 18A of the electron supply layer 18 exposed in the first opening 26A of the passivation layer 26 and the upper end 50A of the via 50. The drain electrode 30 is formed to contact the upper surface 18A of the electron supply layer 18 exposed in the second opening 26B of the passivation layer 26. In one example, the source electrode 28 and the drain electrode 30 are formed by selectively removing, by lithography and etching, a metal layer (not shown) formed to cover the passivation layer 26. By undergoing the above steps, the nitride semiconductor device 10 can be obtained.

[0058] [Operation] Next, the operation of the nitride semiconductor device 10 of the first embodiment will be described. In the nitride semiconductor device 10, the conductive substrate 12 has a low resistance value and therefore functions as a back electrode to which a source voltage is applied through the source electrode 28 and the via 50. The high-resistance layer 13 functions as an insulating layer that insulates the conductive substrate 12 from the nitride semiconductor layer 40 and the HEMT formed using the nitride semiconductor layer 40. In this case, the via 50 does not need to have a shape that penetrates the conductive substrate 12, but only needs to have a shape that contacts the conductive substrate 12. Therefore, compared to a conventional configuration in which a back electrode is separately provided on the underside of the substrate, the length L1 of the via 50 can be shortened by the thickness of the conductive substrate 12. As a result of the shortened length L1 of the via 50, the amount of work required to form the via 50, the time required, and other costs can be reduced.

[0059] Furthermore, in the case of the nitride semiconductor device 10, the stress of the nitride semiconductor layer 40, particularly the force that tends to warp the nitride semiconductor device 10, can be borne by the conductive substrate 12 and the high-resistance layer 13. Therefore, even when the high-resistance layer 13 is formed thin in order to shorten the length L1 of the via 50, it is easy to ensure the strength to resist the stress of the nitride semiconductor layer 40.

[0060] [Effects] The nitride semiconductor device 10 of the first embodiment has the following effects. (1-1) The nitride semiconductor device 10 includes a conductive substrate 12 having a substrate upper surface 12A, a high-resistance layer 13, a nitride semiconductor layer 40 formed on the high-resistance layer 13, a first electrode (source electrode 28) formed on the nitride semiconductor layer 40, and a via 50. The high-resistance layer 13 is formed on the substrate upper surface 12A and has a higher resistance value than the conductive substrate 12. The via 50 is electrically connected to the first electrode (source electrode 28), penetrates the nitride semiconductor layer 40 and the high-resistance layer 13, and is in contact with the substrate upper surface 12A.

[0061] In this case, compared to a conventional configuration in which a back electrode is separately provided on the lower surface of the substrate, the length L1 of the via 50 can be shortened by the thickness of the conductive substrate 12. As a result of the shortened length L1 of the via 50, costs such as the amount of work and time required to form the via 50 can be reduced. In addition, the shortened length L1 of the via 50 reduces the contact area between the via 50 and the high-resistance layer 13 and the nitride semiconductor layer 40. This makes it possible to reduce the ground inductance of the via 50. As a result, an effect of reducing degradation of the nitride semiconductor device 10 can also be obtained.

[0062] (1-2) The difference between the thermal expansion coefficient of the conductive substrate 12 and the thermal expansion coefficient of the high resistance layer 13 is 1×10 －６ (1 / ° C.) or less. In this case, the occurrence of warping due to the difference in the thermal expansion coefficient between the high resistance layer 13 and the conductive substrate 12 can be suppressed.

[0063] (1-3) The thickness T2 of the high-resistance layer 13 is thinner than the thickness (T1) of the conductive substrate 12. In this case, the length of the via 50 that penetrates the high-resistance layer 13 in the thickness direction can be shortened. Therefore, the effect of (1-1) above can be obtained more significantly.

[0064] (1-4) The high-resistance layer 13 has an upper surface 13A facing the nitride semiconductor layer 40. The high-resistance layer 13 is a hexagonal single-crystal SiC layer. The upper surface 13A of the high-resistance layer 13 is inclined at an off-angle of 2° to 6° with respect to the c-plane. Because SiC substrates are generally expensive, the manufacturing cost of a nitride semiconductor device using a SiC substrate can be relatively high. Among SiC substrates, SiC substrates with an off-angle are available relatively inexpensively.

[0065] Second Embodiment The nitride semiconductor device 100 of the second embodiment differs from the first embodiment in the configurations of the substrate 120, the high-resistance layer 130, and the via 500. The nitride semiconductor device 100 of the second embodiment also includes a second electrode 60. The other configurations are similar to those of the first embodiment. Below, a description of the same components as those of the first embodiment will be omitted, and only components different from those of the first embodiment will be described.

[0066] 9, the substrate 120 has a substrate upper surface 120A and a substrate lower surface 120B facing the opposite side to the substrate upper surface 120A. The substrate 120 differs from the conductive substrate 12 of the first embodiment in terms of its conductivity and thickness, but is otherwise similar in configuration to the conductive substrate 12.

[0067] The substrate 120 may or may not be conductive. For example, the resistance value of the substrate 120 is 2×10 －２ It may be Ωcm or less, or 2×10 －２ The resistivity may exceed Ωcm. Examples of the substrate 120 include semiconductor substrates such as a Si substrate, a SiC substrate, a GaN substrate, and a sapphire substrate. The thickness T3 of the substrate 120 is, for example, 1 μm or more, and preferably 3 μm or more. The thickness T3 of the substrate 120 is, for example, 50 μm or less, and preferably 10 μm or less. By reducing the thickness T3 of the substrate 120, the length L2 of the via 500, which will be described later, can be shortened.

[0068] The high-resistance layer 130 has an upper surface 130A and a lower surface 130B facing the opposite side to the upper surface 130A. The lower surface 130B is the surface of the high-resistance layer 130 facing the substrate 120. The resistance value of the high-resistance layer 130 is higher than the resistance value of the substrate 120. The resistance value of the high-resistance layer 130 is, for example, 1×10 ５ Ωcm or more. In addition, when the buffer layer 14 is included, the resistance of the high resistance layer 130 is higher than the resistance of the buffer layer 14, for example. When the buffer layer 14 is made up of multiple layers, the resistance of the high resistance layer 130 is higher than the overall resistance of the multiple buffer layers 14. In the absence of the buffer layer 14, the resistance of the high resistance layer 130 is higher than the resistance of the electron transit layer 16, for example.

[0069] The thickness T4 of the high-resistance layer 130 is, for example, 3 μm or more, and preferably 5 μm or more. The thickness T4 of the high-resistance layer 130 is, for example, 100 μm or less, and preferably 20 μm or less. By reducing the thickness T4 of the high-resistance layer 130, the length L2 of the via 500, which will be described later, can be shortened. In one example, the thickness T4 of the high-resistance layer 130 is thicker than the thickness T3 of the substrate 120. The thickness T4 of the high-resistance layer 130 may be thinner than the thickness T3 of the substrate 120. In another example, the thickness T4 of the high-resistance layer 130 is thicker than the thickness of the buffer layer 14. The thickness T4 of the high-resistance layer 130 may be thinner than the thickness of the buffer layer 14.

[0070] The sum of the thickness T3 of the substrate 120 and the thickness T4 of the high-resistance layer 130 is, for example, 4 μm or more, and preferably 8 μm or more. The sum of the thickness T3 of the substrate 120 and the thickness T4 of the high-resistance layer 130 is, for example, 150 μm or less, and preferably 30 μm or less. The other configuration of the high-resistance layer 130 is the same as that of the high-resistance layer 13 of the first embodiment.

[0071] The second electrode 60 is formed on the lower surface 120B of the substrate 120. The second electrode 60 has an upper surface 60A and a lower surface 60B facing the opposite side to the upper surface 60A. The upper surface 60A of the second electrode 60 faces the substrate 120. The second electrode 60 is electrically connected to the source electrode 28 through a via 500, which will be described later.

[0072] The second electrode 60 may be composed of one or more metal layers. For example, the second electrode 60 may be composed of a combination of two or more metal layers selected from the group including a Ti layer, a TiN layer, an Au layer, an Al layer, an AlSiCu layer, and an AlCu layer. The thickness of the second electrode 60 is, for example, 3 μm or more and 50 μm or less.

[0073] The via 500 is electrically connected to the source electrode 28 and also connects the source electrode 28 and the second electrode 60 in the Z direction. A source voltage is applied to the second electrode 60 through the source electrode 28 and the via 50. The via 500 penetrates the layer interposed between the source electrode 28 and the second electrode 60 in the Z direction.

[0074] More specifically, the via 500 penetrates the substrate 120, the high-resistance layer 130, the buffer layer 14, the electron transit layer 16, and the electron supply layer 18 in the Z direction. A lower end 500B of the via 500 contacts the upper surface 60A of the second electrode 60. An upper end 500A of the via 500 contacts the source electrode 28. The shape and size of the via 500 are not particularly limited and can be changed as desired. The number of vias 500 is also not particularly limited and may be one or more.

[0075] The length L2 of the via 500 is the total thickness (Z-direction dimension) of the layers interposed between the source electrode 28 and the second electrode 60. The material constituting the via 500 is similar to that of the via 50 in the first embodiment. An example of the via 500 is made of the same material as one or both of the source electrode 28 and the second electrode 60. In this case, the via 500 may be formed integrally with one or both of the source electrode 28 and the second electrode 60, which are made of the same material, i.e., there may be no joining surface between them.

[0076] 10 to 14, an exemplary method for manufacturing the nitride semiconductor device 100 will be described. In FIGS. 10 to 14, components similar to those in FIG. 9 are denoted by the same reference numerals.

[0077] The method for manufacturing the nitride semiconductor device 100 includes a step of forming a buffer layer 14 and a nitride semiconductor layer 40 on the high-resistance layer 130. This step is the same as that in the first embodiment, except that the high-resistance layer 13 is changed to the high-resistance layer 130.

[0078] 10 , the method for manufacturing the nitride semiconductor device 100 includes a step of forming the substrate 120 on the lower surface 130B of the high-resistance layer 130. The method for forming the substrate 120 is the same as the method for forming the conductive substrate 12 in the first embodiment. Note that, since the thickness of the substrate 120 can be easily adjusted, it is preferable to form the substrate 120 by film formation using a CVD method.

[0079] 11 and 12 , the method for manufacturing the nitride semiconductor device 100 includes a step of forming a via 500 in the substrate 120, the high-resistance layer 130, the buffer layer 14, and the nitride semiconductor layer 40. The step of forming the via 500 includes a step of forming a through-hole 510 that penetrates the substrate 120, the high-resistance layer 130, the buffer layer 14, and the nitride semiconductor layer 40, and a step of filling the through-hole 510 with a conductive material.

[0080] 11 , the through-hole 510 penetrates the substrate 120, the high-resistance layer 130, the buffer layer 14, and the nitride semiconductor layer 40, and is formed so as to open to the upper surface of the nitride semiconductor layer 40 (the upper surface 18A of the electron supply layer 18) and the lower surface 120B of the substrate 120. In one example, the through-hole 510 is formed by grinding the substrate 120, the high-resistance layer 130, the buffer layer 14, and the nitride semiconductor layer 40. In another example, the through-hole 510 is formed by selectively removing parts of the substrate 120, the high-resistance layer 130, the buffer layer 14, and the nitride semiconductor layer 40 by lithography and etching. Note that the through-hole 510 may be formed from the lower surface 120B side of the substrate 120, or from the upper surface of the nitride semiconductor layer 40 (the upper surface 18A of the electron supply layer 18). Next, as shown in FIG. 12, a via 500 is formed by filling the through hole 510 with a conductive material.

[0081] 13 , the method for manufacturing the nitride semiconductor device 100 includes a step of forming the second electrode 60 on the substrate lower surface 120B of the substrate 120. In one example, the second electrode 60 can be formed by forming a metal layer that will become the second electrode 60 on the substrate lower surface 120B of the substrate 120.

[0082] 14 , the method for manufacturing the nitride semiconductor device 100 includes the steps of forming a gate layer 22, a gate electrode 24, a passivation layer 26, a source electrode 28, and a drain electrode 30. Each of these steps is the same as in the first embodiment. By going through the above steps, the nitride semiconductor device 100 can be obtained.

[0083] [Function] Next, the function of the nitride semiconductor device 100 of the second embodiment will be described. In the nitride semiconductor device 100, the substrate 120 and the high-resistance layer 130 are interposed between the nitride semiconductor layer 40 and the second electrode 60 connected to the source electrode 28 through the via 500. The via 500 is formed to penetrate both the substrate 120 and the high-resistance layer 130. In this case, compared to a conventional configuration in which only a substrate with a high resistance value is interposed between the second electrode 60 and the nitride semiconductor layer 40, the thickness of the layer interposed between the second electrode 60 and the nitride semiconductor layer 40 (hereinafter referred to as the interlayer thickness) can be easily adjusted.

[0084] That is, in the case of a conventional configuration in which only a substrate with a high resistance value is interposed between the second electrode 60 and the nitride semiconductor layer 40, a substrate thicker than the specified interlayer thickness is used to form the nitride semiconductor layer 40 and a HEMT configured using the nitride semiconductor layer 40. Thereafter, an operation of cutting the substrate is performed so that the specified interlayer thickness is obtained. Therefore, the interlayer thickness is adjusted by the operation of cutting the substrate.

[0085] In contrast, in the case of the nitride semiconductor device 100, a substrate 120 having a second specified thickness is bonded to the lower surface 130B of the high-resistance layer 130 having the first specified thickness, or the substrate 120 is formed by film deposition up to the second specified thickness. Therefore, the interlayer thickness (first specified thickness + second specified thickness) is adjusted by the operation of newly forming the substrate 120. Adjusting the interlayer thickness by the operation of newly forming the substrate 120 requires less work and shorter work time than adjusting the interlayer thickness by cutting the substrate. As a result, the cost required for manufacturing the nitride semiconductor device 100 having the via 500 can be reduced.

[0086] [Effects] The nitride semiconductor device 100 of the second embodiment has the same effects as those (1-2) and (1-3) above. Furthermore, the nitride semiconductor device 100 of the second embodiment has the following effects.

[0087] (2-1) The nitride semiconductor device 100 includes a substrate 120 having a substrate upper surface 120A and a substrate lower surface 120B, a high-resistance layer 130, a nitride semiconductor layer 40 formed on the high-resistance layer 130, a source electrode 28 formed on the nitride semiconductor layer 40, a second electrode 60 formed below the substrate lower surface 120B of the substrate 120, and a via 500. The high-resistance layer 130 is formed on the substrate upper surface 120A and has a higher resistance value than the substrate 120. The via 500 is provided to penetrate the nitride semiconductor layer 40, the high-resistance layer 130, and the substrate 120, and electrically connects the source electrode 28 and the second electrode 60. In this case, compared to a conventional configuration in which only a high-resistance substrate is interposed between the second electrode 60 and the nitride semiconductor layer 40, the cost required to adjust the thickness (interlayer thickness) of the layer interposed between the second electrode 60 and the nitride semiconductor layer 40 can be reduced.

[0088] (2-2) The thickness T4 of the high-resistance layer 130 is greater than the thickness T3 of the substrate 120. In this case, the time required for the process of forming the substrate 120 by film deposition on the lower surface 130B of the high-resistance layer 130 can be further shortened. Therefore, the effect of (2-1) above can be obtained more significantly.

[0089] <Modifications> The above-described embodiments can be modified, for example, as follows. The above-described embodiments and the following modifications can be combined with each other as long as no technical contradiction occurs. In the following modifications, parts common to the above-described embodiments will be assigned the same reference numerals as in the above-described embodiments, and their description will be omitted.

[0090] In the nitride semiconductor device 10 of the first embodiment, the first electrode connected to the conductive substrate 12 through the via 50 is not limited to the source electrode 28. For example, the via 50 may be configured to electrically connect the drain electrode 30 and the conductive substrate 12. In this case, the first electrode is the drain electrode 30. Furthermore, in this case, a drain voltage is applied to the conductive substrate 12 through the drain electrode 30 and the via 50. The same applies to the via 500 of the nitride semiconductor device 100 of the second embodiment.

[0091] The nitride semiconductor device 10 of the first embodiment may be a normally-on type that does not have a gate layer 22. The same applies to the nitride semiconductor device 100 of the second embodiment. The conductive substrate 12 of the nitride semiconductor device 10 of the first embodiment may be a metal substrate instead of a semiconductor substrate. In this case, the conductive substrate 12 is, for example, a Cu substrate, a molybdenum (Mo) substrate, a tantalum (Ta) substrate, a Ti substrate, a niobium (Nb) substrate, or a compound substrate including one or more of these substrates.

[0092] In the method for manufacturing the nitride semiconductor device 10 of the first embodiment, the order of the steps is not limited to the order described in the embodiment and can be changed as desired. As an example, the nitride semiconductor device 10 can be manufactured in the order shown in FIGS. 15 to 18.

[0093] 15 shows a step subsequent to that shown in Fig. 3 , in which a buffer layer 14 and a nitride semiconductor layer 40 are formed on the high-resistance layer 13. As shown in Fig. 15 , the buffer layer 14, and the electron transit layer 16 and the electron supply layer 18 as the nitride semiconductor layer 40 are formed on the upper surface 13A of the high-resistance layer 13.

[0094] 16 and 17 show a step subsequent to that shown in Fig. 15 , in which a via 50 is formed. As shown in Fig. 16 , a through hole 51 is formed penetrating the high-resistance layer 13, the buffer layer 14, and the nitride semiconductor layer 40. In this case, the through hole 51 may be formed from the lower surface 13B side of the high-resistance layer 13, or from the upper surface (upper surface 18A of the electron supply layer 18) side of the nitride semiconductor layer 40. Next, as shown in Fig. 17 , a conductive material is embedded in the through hole 51 to form the via 50.

[0095] 18 shows a step subsequent to FIG. 17 , in which a conductive substrate 12 is formed on the lower surface 13B of the high-resistance layer 13. After the conductive substrate 12 is formed, as shown in FIG. 8 , the steps of forming a gate layer 22, a gate electrode 24, a passivation layer 26, a source electrode 28, and a drain electrode 30 are performed. The step of forming the conductive substrate 12 may be performed after the steps of forming the gate layer 22, the gate electrode 24, the passivation layer 26, the source electrode 28, and the drain electrode 30. When the conductive substrate 12 is a polycrystalline SiC substrate, it is preferable to form the buffer layer 14 and the nitride semiconductor layer 40 after forming the conductive substrate 12, as described in the above embodiment. This allows the conductive substrate 12, which is a polycrystalline SiC substrate, to be easily formed.

[0096] In the manufacturing method of the nitride semiconductor device 10 of the first embodiment, if the material constituting the via 50 is the same as the material constituting the source electrode 28, the process of filling the through hole 51 with a conductive material and the process of filling the source electrode 28 may be performed as a single process.

[0097] In the manufacturing method of the nitride semiconductor device 100 according to the second embodiment, the order of the steps may be changed. For example, the step of forming the via 500 may be performed after the step of forming the second electrode 60. Furthermore, the step of forming the second electrode 60 may be performed after the steps of forming the gate layer 22, the gate electrode 24, the passivation layer 26, the source electrode 28, and the drain electrode 30.

[0098] In the method for manufacturing the nitride semiconductor device 100 according to the second embodiment, if the material constituting the via 500 is the same as the material constituting the source electrode 28, the step of filling the through hole 510 with a conductive material and the step of forming the source electrode 28 may be performed as a single process. Furthermore, if the material constituting the via 500 is the same as the material constituting the second electrode 60, the step of filling the through hole 510 with a conductive material and the step of forming the second electrode 60 may be performed as a single process.

[0099] In the above embodiments, the nitride semiconductor devices 10 and 100 are configured as nitride semiconductor HEMTs. However, the nitride semiconductor devices are not limited to nitride semiconductor HEMTs and may be configured as nitride semiconductor diodes.

[0100] The term "on" as used in this disclosure includes both the meanings of "on" and "above," unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0101] The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" in the Z direction described herein being "up" and "down" in the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0102] Terms such as "first," "second," and "third" in this disclosure are used merely to distinguish between objects and are not used to rank the objects. In this specification, "at least one of A and B" should be understood to mean "A only, or B only, or both A and B." <Notes> The technical ideas that can be grasped from this disclosure are described below. Note that, for the purpose of aiding understanding and not for the purpose of limitation, the components described in the notes are given the reference symbols of the corresponding components in the embodiments. The reference symbols are shown as examples to aid understanding, and the components described in each note should not be limited to the components indicated by the reference symbols.

[0103] [Supplementary Note 1] A nitride semiconductor device (10) comprising: a conductive substrate (12) having a substrate upper surface (12A); a high-resistivity layer (13) formed on the substrate upper surface (12A) and having a resistance value higher than that of the conductive substrate (12); a nitride semiconductor layer (40) formed on the high-resistivity layer (13); a first electrode (28) formed on the nitride semiconductor layer (40); and a via (50) electrically connected to the first electrode (28), provided to penetrate the nitride semiconductor layer (40) and the high-resistivity layer (13) and in contact with the substrate upper surface (12A).

[0104] [Supplementary Note 2] The nitride semiconductor device (10) according to Supplementary Note 1, wherein the conductive substrate (12) is a semiconductor substrate.

[0105] [Appendix 3] The difference between the thermal expansion coefficient of the conductive substrate (12) and the thermal expansion coefficient of the high resistance layer (13) is 1×10 －６ (1 / °C) or less.

[0106] [Appendix 4] The nitride semiconductor device (10) according to any one of Appendices 1 to 3, wherein the conductive substrate (12) is a SiC substrate, and the high resistance layer (13) is a SiC layer.

[0107] [Appendix 5] The nitride semiconductor device (10) according to any one of Appendices 1 to 4, wherein the high resistance layer (13) is thinner than the conductive substrate (12).

[0108] [Appendix 6] The nitride semiconductor device (10) according to any one of Appendices 1 to 5, further comprising a buffer layer (14) provided between the high-resistance layer (13) and the nitride semiconductor layer (40), wherein the high-resistance layer (13) has a higher resistance than the buffer layer (14).

[0109] [Note 7] The resistance value of the conductive substrate (12) is 2×10 －２ The nitride semiconductor device (10) according to any one of appendices 1 to 6, wherein the resistivity is Ωcm or less.

[0110] [Note 8] The resistance value of the high resistance layer (13) is 1×10 ５ The nitride semiconductor device (10) according to any one of appendices 1 to 7, wherein the resistivity is Ωcm or more.

[0111] [Supplementary Note 9] A nitride semiconductor device (100) comprising: a substrate (120) having a substrate upper surface (120A) and a substrate lower surface (120B) facing the opposite side to the substrate upper surface (120A); a high-resistivity layer (130) formed on the substrate upper surface (120A) of the substrate (120) and having a resistance value higher than that of the substrate (120); a nitride semiconductor layer (40) formed on the high-resistivity layer (130); a first electrode (28) formed on the nitride semiconductor layer (40); a second electrode (60) formed below the substrate lower surface (120B) of the substrate (120); and a via (500) provided through the nitride semiconductor layer (40), the high-resistivity layer (130), and the substrate (120) and electrically connecting the first electrode (28) and the second electrode (60).

[0112] [Supplementary Note 10] The difference between the thermal expansion coefficient of the substrate (120) and the thermal expansion coefficient of the high resistance layer (130) is 1×10 －６ (1 / °C) or less.

[0113] [Supplementary Note 11] The nitride semiconductor device (100) according to Supplementary Note 9 or Supplementary Note 10, wherein the substrate (120) is a SiC substrate, and the high resistance layer (130) is a SiC layer.

[0114] [Supplementary Note 12] The nitride semiconductor device (100) according to any one of Supplementary Notes 9 to 11, wherein the high resistance layer (130) is thicker than the substrate (120).

[0115] [Appendix 13] The nitride semiconductor device (100) according to any one of Appendices 9 to 12, further comprising a buffer layer (14) provided between the high-resistance layer (130) and the nitride semiconductor layer (40), wherein the high-resistance layer (130) has a higher resistance than the buffer layer (14).

[0116] [Supplementary Note 14] The resistance value of the high resistance layer (130) is 1×10 ５ The nitride semiconductor device (100) according to any one of appendices 9 to 13, wherein the resistivity is Ωcm or more.

[0117] [Appendix 15] The nitride semiconductor device (10, 100) according to any one of Appendices 1 to 14, wherein the high-resistance layer (13, 130) has an upper surface (13A, 130A) facing the nitride semiconductor layer (40), the high-resistance layer (13, 130) is a hexagonal single-crystal SiC layer, and the upper surface (13A, 130A) of the high-resistance layer (13, 130) is inclined at an off-angle of 2° to 6° with respect to a c-plane.

[0118] [Supplementary Note 16] The nitride semiconductor device (10, 100) according to any one of Supplementary Notes 1 to 15, wherein the nitride semiconductor layer (40) includes: an electron transit layer (16) made of a nitride semiconductor; an electron supply layer (18) formed on the electron transit layer (16) and made of a nitride semiconductor having a larger band gap than the electron transit layer (16); and a gate electrode (24), a source electrode (28), and a drain electrode (30) formed on the electron supply layer (18), and the via (50, 500) is electrically connected to the source electrode (28) as the first electrode.

[0119] [Appendix 17] A method for manufacturing a nitride semiconductor device (10) according to any one of Appendices 1 to 8, comprising: forming the nitride semiconductor layer (40) on an upper surface (13A) of the high-resistivity layer (13); forming the via (50) in the high-resistivity layer (13) and the nitride semiconductor layer (40); forming the conductive substrate (12) on a lower surface (13B) of the high-resistivity layer (13); and forming the first electrode (28) on the nitride semiconductor layer (40).

[0120] [Appendix 18] A method for manufacturing a nitride semiconductor device (100) according to any one of Appendices 9 to 14, comprising: forming the nitride semiconductor layer (40) on an upper surface (130A) of the high-resistivity layer (130); forming the substrate (120) on a lower surface (130B) of the high-resistivity layer (130); forming the via (500) in the substrate (120), the high-resistivity layer (130), and the nitride semiconductor layer (40); forming the second electrode (60) on a substrate lower surface (120B) of the substrate (120); and forming the first electrode (28) on the nitride semiconductor layer (40).

[0121] L1, L2...lengths T1 to T4...thicknesses 10...nitride semiconductor device 10HC...HEMT cell 12...conductive substrate 12A...substrate upper surface 12B...substrate lower surface 13...high resistance layer 13A...upper surface 13B...lower surface 14...buffer layer 16...electron transit layer 18...electron supply layer 18A...upper surface 20...two-dimensional electron gas (2DEG) 22...gate layer 24...gate electrode 26...passivation layer 26A...first opening 26B...second opening 28...source electrode 30...drain electrode 40...nitride semiconductor layer 50...via 50A...upper end 50B...lower end 51...through hole 60...second electrode 60A...upper surface 60B...lower surface 100...nitride semiconductor device 120...substrate 120A...substrate upper surface 120B...Bottom surface of substrate 130...High resistance layer 130A...Top surface 130B...Bottom surface 500...Via 500A...Top end 500B...Bottom end 510...Through hole

Claims

1. A nitride semiconductor device comprising: a conductive substrate having a substrate upper surface; a high-resistance layer formed on the substrate upper surface and having a higher resistance than the conductive substrate; a nitride semiconductor layer formed on the high-resistance layer; a first electrode formed on the nitride semiconductor layer; and a via electrically connected to the first electrode, the via penetrating the nitride semiconductor layer and the high-resistance layer and in contact with the substrate upper surface.

2. The nitride semiconductor device according to claim 1, wherein said conductive substrate is a semiconductor substrate.

3. The difference between the thermal expansion coefficient of the conductive substrate and the thermal expansion coefficient of the high resistance layer is 1×10 －６ 3. The nitride semiconductor device according to claim 1, wherein the temperature is 1 / ° C. or less.

4. The nitride semiconductor device according to any one of claims 1 to 3, wherein the conductive substrate is a SiC substrate, and the high-resistance layer is a SiC layer.

5. The nitride semiconductor device according to claim 1, wherein the high resistance layer is thinner than the conductive substrate.

6. The nitride semiconductor device according to any one of claims 1 to 5, further comprising a buffer layer provided between said high resistance layer and said nitride semiconductor layer, said high resistance layer having a resistance value higher than that of said buffer layer.

7. The resistance value of the conductive substrate is 2×10 －２ The nitride semiconductor device according to claim 1, wherein the resistivity is Ωcm or less.

8. The resistance value of the high resistance layer is 1×10 ５ The nitride semiconductor device according to claim 1, wherein the resistivity is Ωcm or more.

9. A nitride semiconductor device comprising: a substrate having a substrate upper surface and a substrate lower surface facing opposite to the substrate upper surface; a high-resistance layer formed on the substrate upper surface of the substrate and having a resistance higher than that of the substrate; a nitride semiconductor layer formed on the high-resistance layer; a first electrode formed on the nitride semiconductor layer; a second electrode formed below the substrate lower surface of the substrate; and a via that penetrates the nitride semiconductor layer, the high-resistance layer, and the substrate and electrically connects the first electrode and the second electrode.

10. The difference between the thermal expansion coefficient of the substrate and the thermal expansion coefficient of the high resistance layer is 1×10 －６ 10. The nitride semiconductor device according to claim 9, wherein the temperature is 1 / ° C. or less.

11. The nitride semiconductor device according to claim 9 or 10, wherein the substrate is a SiC substrate, and the high-resistance layer is a SiC layer.

12. The nitride semiconductor device according to claim 9, wherein the high resistance layer is thicker than the substrate.

13. The nitride semiconductor device according to any one of claims 9 to 12, further comprising a buffer layer provided between said high resistance layer and said nitride semiconductor layer, said high resistance layer having a resistance value higher than that of said buffer layer.

14. The resistance value of the high resistance layer is 1×10 ５ The nitride semiconductor device according to any one of claims 9 to 13, wherein the resistivity is Ωcm or more.

15. The nitride semiconductor device according to any one of claims 1 to 14, wherein the high-resistance layer has an upper surface facing the nitride semiconductor layer, the high-resistance layer is a hexagonal single crystal SiC layer, and the upper surface of the high-resistance layer is inclined at an off angle of 2° or more and 6° or less with respect to a c-plane.

16. The nitride semiconductor device according to any one of claims 1 to 15, wherein the nitride semiconductor layer includes: an electron transit layer made of a nitride semiconductor; an electron supply layer formed on the electron transit layer and made of a nitride semiconductor having a larger band gap than the electron transit layer; and a gate electrode, a source electrode, and a drain electrode formed on the electron supply layer; and the via is electrically connected to the source electrode serving as the first electrode.

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