Drive circuit and operation method

Abstract

A drive circuit (1) drives a transistor having: a first terminal which is a gate or a base; a second terminal which is a source or an emitter; and a third terminal which is a drain or a collector. The drive circuit comprises: an isolation pulse transformer (T1); a full-wave rectifier circuit (21) connected to a secondary winding (L2) of the pulse transformer (T1); and a sink circuit (31) connected between the full-wave rectifier circuit (21) and the transistor, and connected to the first terminal and the second terminal, for sinking current from the first terminal when the transistor turns off. A signal input into a terminal (t1) on one end of a primary winding (L1) of the pulse transformer (T1) and a signal input into a terminal (t2) on the other end thereof have a phase difference.

Description

Driving circuit and operating method

[0001] The present disclosure relates to a driving circuit for driving a transistor.

[0002] Patent Document 1 discloses a drive circuit using a pulse transformer.

[0003] Patent No. 5930560

[0004] However, in the drive circuit disclosed as a conventional example in Fig. 11 of Patent Document 1, the pulse transformer becomes biased, requiring a reset period for the transformer, making it impossible to output a high-duty pulse. Also, in the drive circuit disclosed as a proposed example in Fig. 2 of Patent Document 1, biased magnetization of the transformer does not occur and no reset period is required, but the secondary side circuit is half-wave rectified, so only pulses with a duty of 50% or less can be output.

[0005] Therefore, the present disclosure provides a drive circuit and the like that can achieve a duty ratio greater than 50% without causing bias magnetism in the transformer and further prevent erroneous firing of the main bridge circuit.

[0006] The drive circuit according to the present disclosure is a drive circuit for driving a transistor having a first terminal which is a gate or base, a second terminal which is a source or emitter, and a third terminal which is a drain or collector, and includes an isolated pulse transformer, a full-wave rectifier circuit connected to a secondary winding of the pulse transformer, and a draw-out circuit connected between the full-wave rectifier circuit and the transistor, connected to the first terminal and the second terminal, and for drawing current from the first terminal when the transistor is turned off, wherein there is a phase difference between a signal input to one terminal of the primary winding of the pulse transformer and a signal input to the other terminal.

[0007] An operating method according to the present disclosure is a method for operating a drive circuit for driving a transistor having a first terminal which is a gate or base, a second terminal which is a source or emitter, and a third terminal which is a drain or collector, and includes the steps of inputting signals having a phase difference to one terminal and the other terminal of a primary winding of an isolated pulse transformer, full-wave rectifying a signal output from a secondary winding of the pulse transformer, outputting the full-wave rectified signal to the first terminal, and drawing current from the first terminal when the transistor is turned off.

[0008] These comprehensive or specific aspects may be realized as a system, a method, an integrated circuit, a computer program, or a computer-readable recording medium such as a CD-ROM, or may be realized as any combination of a system, a method, an integrated circuit, a computer program, and a recording medium.

[0009] According to a drive circuit and the like according to an aspect of the present disclosure, a duty ratio greater than 50% can be achieved without causing bias magnetization in the transformer, and further, erroneous firing of the main bridge circuit can be prevented.

[0010] FIG. 1 is a circuit diagram showing an example of a drive circuit according to a first embodiment. FIG. 2 is a diagram explaining that a duty ratio of 5% can be realized. FIG. 3 is a diagram explaining that a duty ratio of 50% can be realized. FIG. 4 is a diagram explaining that a duty ratio of 95% can be realized. FIG. 5 is a diagram showing an example of application of the drive circuit according to the first embodiment to a main bridge circuit. FIG. 6 is a diagram explaining the operation of the drive circuit according to the first embodiment. FIG. 7 is a diagram explaining the operation of the drive circuit according to the first embodiment when an FET is turned off. FIG. 8 is a diagram explaining the operation of the drive circuit according to the first embodiment when an FET is turned on. FIG. 9 is a circuit diagram showing an example of a drive circuit according to a second embodiment. FIG. 10 is a circuit diagram showing an example of a drive circuit according to a third embodiment. FIG. 11 is a circuit diagram showing an example of a drive circuit according to a fourth embodiment. FIG. 12 is a circuit diagram showing an example of a drive circuit according to a fifth embodiment. FIG. 13 is a circuit diagram showing an example of a drive circuit according to a sixth embodiment. FIG. 14 is a flowchart showing an example of an operation method according to other embodiments.

[0011] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0012] The embodiments described below are all comprehensive or specific examples, and the numerical values, shapes, materials, components, arrangement and connection of the components, steps, and order of steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure.

[0013] First Embodiment A drive circuit according to a first embodiment will be described below.

[0014] FIG. 1 is a circuit diagram showing an example of a drive circuit 1 according to a first embodiment.

[0015] The drive circuit 1 is a circuit for driving a transistor having a first terminal which is a gate or a base, a second terminal which is a source or an emitter, and a third terminal which is a drain or a collector. The transistor may be, for example, a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a GaN FET, or a bipolar transistor. In the following description, the transistor driven by the drive circuit 1 is referred to as an FET, with the first terminal being the gate, the second terminal being the source, and the third terminal being the drain. In this case, the inter-terminal voltage between the first terminal and the second terminal is the gate-source voltage of the FET, and the voltage at the second terminal is the source voltage of the FET.

[0016] If the transistor driven by the drive circuit 1 is an IGBT, then in the following description, "FET" can be replaced with "IGBT," "FET source" can be replaced with "IGBT emitter," and "FET drain" can be replaced with "IGBT collector." Furthermore, "FET gate-source voltage" can be replaced with "IGBT gate-emitter voltage," and "FET source voltage" can be replaced with "IGBT source voltage."

[0017] Furthermore, when the transistor driven by the drive circuit 1 is a bipolar transistor, the term "FET" in the following description can be replaced with "bipolar transistor," the term "gate of the FET" can be replaced with "base of the bipolar transistor," the term "source of the FET" can be replaced with "emitter of the bipolar transistor," and the term "drain of the FET" can be replaced with "collector of the bipolar transistor." Furthermore, the term "gate-source voltage of the FET" can be replaced with "base-emitter voltage of the bipolar transistor," and the term "source voltage of the FET" can be replaced with "emitter voltage of the bipolar transistor."

[0018] 1 is connected to the gate of the FET, and the terminal t6 is connected to the source of the FET, so that the driving circuit 1 can control the on and off of the FET.

[0019] The drive circuit 1 includes a power supply Bat, a phase control circuit 10, a pulse transformer T1, a resistor R10, a capacitor C10, a full-wave rectifier circuit 21, and a pull-out circuit 31. The capacitor Cgs in Fig. 1 represents the gate-source capacitance of the FET connected to terminals t5 and t6.

[0020] The pulse transformer T1 is an isolated pulse transformer having an isolated primary winding L1 and a secondary winding L2. For example, a photocoupler may be used as a method for transmitting signals while isolating the primary and secondary sides, but this method requires a separate isolated power supply. On the other hand, the pulse transformer T1 can transmit both the power and signals for driving the FET while isolating the primary and secondary sides.

[0021] A signal Vin1 input to a terminal t1 at one end of the primary winding L1 of the pulse transformer T1 and a signal Vin2 input to a terminal t2 at the other end have a phase difference. For example, a phase control circuit 10 can impart a phase difference between the signal Vin1 input to the terminal t1 and the signal Vin2 input to the terminal t2. The signals Vin1 and Vin2 are each a pulse signal, and these pulse signals are generated by the voltage Vcc of the power supply Bat.

[0022] For example, in state A where signal Vin1 is a high signal and signal Vin2 is a high signal, voltage VT1 is not generated in primary winding L1, and therefore voltage VT2 is not generated in secondary winding L2 either.

[0023] For example, in state B where signal Vin1 is a high signal and signal Vin2 is a low signal, a voltage VT1 having the polarity shown in Fig. 1 is generated in primary winding L1, which in turn generates a voltage VT2 having the polarity shown in Fig. 1 in secondary winding L2.

[0024] For example, in state C where the signal Vin1 is a low signal and the signal Vin2 is a low signal, the voltage VT1 is not generated in the primary winding L1, and therefore the voltage VT2 is not generated in the secondary winding L2 either.

[0025] For example, in state D when signal Vin1 is a low signal and signal Vin2 is a high signal, a voltage VT1 having a polarity opposite to that shown in Fig. 1 is generated in primary winding L1. As a result, in state D, a voltage VT2 having a polarity opposite to that shown in Fig. 1 is generated in secondary winding L2.

[0026] The full-wave rectifier circuit 21 is connected to the secondary winding L2 of the pulse transformer T1. In FIG. 1 , the full-wave rectifier circuit 21 is connected to the secondary winding L2 via an RC circuit consisting of a resistor R10 and a capacitor C10. For example, the RC circuit consisting of the resistor R10 and the capacitor C10 is a circuit for suppressing ringing caused by the leakage inductance of the pulse transformer T1. The drive circuit 1 does not necessarily need to include the resistor R10 and the capacitor C10; a resistor R5 (described later) may also perform this function. Because this RC circuit may or may not be provided, hereinafter, the phrase "connected to terminal t3" includes the case where the full-wave rectifier circuit 21 is connected to terminal t3 via such an RC circuit.

[0027] For example, the full-wave rectifier circuit 21 includes two switches Q1 and Q2 connected in series to form a full-bridge circuit, and two diodes D3 and D4 connected in series to form the full-bridge circuit. A node between the two switches Q1 and Q2 is connected to a terminal t3 at one end of a secondary winding L2 of a pulse transformer T1. A node between the two diodes D3 and D4 is connected to a terminal t4 at the other end of the secondary winding L2 of the pulse transformer T1.

[0028] The switch Q1 is, for example, a P-channel MOSFET. The drain of the switch Q1 is connected to the drain of the switch Q2 and the terminal t3, and the source of the switch Q1 is connected to the cathode of the diode D3 and the extraction circuit 31. The gate of the switch Q1 is connected to the node between the two diodes D3 and D4. FIG. 1 shows a parasitic diode of the switch Q1, and in the equivalent circuit, the anode of the diode is connected to the drain of the switch Q1 and the cathode is connected to the source of the switch Q1.

[0029] The switch Q2 is, for example, an N-channel MOSFET. The drain of the switch Q2 is connected to the drain of the switch Q1 and terminal t3, and the source of the switch Q2 is connected to terminal t6. The gate of the switch Q2 is connected to the node between the two diodes D3 and D4. FIG. 1 shows a parasitic diode of the switch Q2, and in the equivalent circuit, the anode of the diode is connected to the source of the switch Q2 and the cathode is connected to the drain of the switch Q2.

[0030] The anode of the diode D3 is connected to the cathode of the diode D4, the gates of the switches Q1 and Q2, and the terminal t4, and the cathode of the diode D3 is connected to the source of the switch Q1 and the extraction circuit 31.

[0031] The anode of diode D4 is connected to terminal t6, and the cathode of diode D4 is connected to the anode of diode D3, the gates of switches Q1 and Q2, and terminal t4.

[0032] The terminals t3 and t4 may be interchanged. Specifically, the terminal t4 may be connected to the source of the switch Q1 and the drain of the switch Q2, and the terminal t3 may be connected to the gate of the switch Q1, the gate of the switch Q2, the anode of the diode D3, and the cathode of the diode D4.

[0033] The full-wave rectifier circuit 21 full-wave rectifies the voltage generated in the secondary winding L2 and outputs the result to the gate of the FET. FIG. 1 shows a voltage Vo2 as the output voltage of the full-wave rectifier circuit 21. The secondary winding L2 generates voltages of different polarities in State B, where a high signal is input to terminal t1 and a low signal is input to terminal t2, and State D, where a low signal is input to terminal t1 and a high signal is input to terminal t2. However, because the full-wave rectifier circuit 21 is connected to the secondary winding L2, the full-wave rectifier circuit 21 can output a voltage Vo2 corresponding to the absolute value of the voltage generated in the secondary winding L2 regardless of the polarity of the voltage generated in the secondary winding L2 (in other words, in either State B or State D). Therefore, the drive circuit 1 can apply a voltage Vgs corresponding to the voltage Vo2 to the FET connected between terminals t5 and t6.

[0034] The extraction circuit 31 is connected between the full-wave rectifier circuit 21 and the FET, and is also connected to the gate and source of the FET, and is a circuit for extracting current from the gate of the FET when the FET is turned off. The operation of the extraction circuit 31 will be described in detail later.

[0035] The pull-out circuit 31 includes, for example, resistors R5, R6, R7, R8, and R9 and switches Q5, Q6, and Q7. The resistor R5 is an example of a first circuit that generates a voltage difference between the output voltage of the full-wave rectifier circuit 21 and the gate-source voltage of the FET. The resistors R6, R7, R8, and R9 and the switches Q5, Q6, and Q7 are an example of a second circuit that brings the output voltage of the full-wave rectifier circuit 21 or the gate-source voltage of the FET closer to the source voltage of the FET (the voltage at terminal t6: for example, 0 V) ​​based on the output voltage of the full-wave rectifier circuit 21 (voltage Vo2), the gate-source voltage of the FET (voltage Vgs), or the voltage difference between the output voltage of the full-wave rectifier circuit 21 and the gate-source voltage of the FET.

[0036] Here, bringing the output voltage of the full-wave rectifier circuit 21 closer to the source voltage of the FET means bringing both output terminals of the full-wave rectifier circuit 21 into conduction with a switch and connecting the source of the FET with both output terminals of the full-wave rectifier circuit 21 at low impedance. Similarly, bringing the gate-source voltage of the FET closer to the source voltage of the FET means bringing the gate-source of the FET into conduction with a switch and connecting the source and gate of the FET at low impedance.

[0037] For example, in the first embodiment, resistors R6, R7, R8, and R9 and switches Q5, Q6, and Q7 (second circuit) bring the output voltage of full-wave rectifier circuit 21 or the gate-source voltage of FET closer to the source voltage of FET based on the voltage difference between the output voltage of full-wave rectifier circuit 21 and the gate-source voltage of FET. Specifically, assuming that the gate-source voltage of FET is Vgs, the output voltage of full-wave rectifier circuit 21 is Vo2, a first threshold voltage set for the second circuit is Vth1 (e.g., 0 V or higher), and the source voltage of FET is Vs, the second circuit brings Vo2 or Vgs closer to Vs when Vgs-Vo2>Vth1 (in other words, when Vgs-Vo2 exceeds Vth1).

[0038] The switch Q5 is, for example, a PNP transistor. The base of the switch Q5 is connected to one end of a resistor R5, one end of a resistor R6, the source of the switch Q1, and the cathode of a diode D3. The collector of the switch Q5 is connected to one end of a resistor R8. The emitter of the switch Q5 is connected to the other end of the resistor R5, one end of a resistor R7, and a terminal t5. The voltage VEB5 shown in FIG. 1 is the emitter-base voltage of the switch Q5.

[0039] The switch Q6 is, for example, an NPN transistor. The base of the switch Q6 is connected to the base of the switch Q7, the other end of the resistor R8, and one end of the resistor R9. The collector of the switch Q6 is connected to the other end of the resistor R6. The emitter of the switch Q6 is connected to the terminal t6.

[0040] The switch Q7 is, for example, an NPN transistor. The base of the switch Q7 is connected to the base of the switch Q6, the other end of the resistor R8, and one end of the resistor R9. The collector of the switch Q7 is connected to the other end of the resistor R7. The emitter of the switch Q7 is connected to the terminal t6. The voltage VBE7 shown in FIG. 1 is the base-emitter voltage of the switch Q7.

[0041] One end of the resistor R5 is connected to one end of the resistor R6, the base of the switch Q5, the source of the switch Q1 and the cathode of the diode D3, and the other end is connected to the emitter of the switch Q5, one end of the resistor R7 and the terminal t5.

[0042] One end of the resistor R6 is connected to one end of the resistor R5, the base of the switch Q5, the source of the switch Q1 and the cathode of the diode D3, and the other end is connected to the collector of the switch Q6.

[0043] One end of the resistor R7 is connected to the other end of the resistor R5, the emitter of the switch Q5, and the terminal t5, and the other end is connected to the collector of the switch Q7. The current Irg_dn shown in FIG.

[0044] One end of the resistor R8 is connected to the collector of the switch Q5, and the other end is connected to the base of the switch Q6, the base of the switch Q7, and one end of the resistor R9.

[0045] One end of the resistor R9 is connected to the other end of the resistor R8, the base of the switch Q6, and the base of the switch Q7, and the other end is connected to the terminal t6.

[0046] Capacitor Cgs refers to the gate-source capacitance of the FET connected to terminals t5 and t6. The voltage Vgs generated across capacitor Cgs is the gate-source voltage of the FET. The current Ig shown in Figure 1 is the current flowing through capacitor Cgs. In other words, it is the current flowing through the gate of the FET, and the direction in which charge is drawn is positive.

[0047] Next, the duty ratio of the FET switching that can be realized by the drive circuit 1 will be described with reference to FIGS. 2A to 2C.

[0048] FIG. 2A is a diagram for explaining that a duty ratio of 5% can be achieved.

[0049] FIG. 2B is a diagram for explaining that a duty ratio of 50% can be realized.

[0050] FIG. 2C is a diagram for explaining that a duty ratio of 95% can be achieved.

[0051] 2A to 2C show, from the top to the bottom, time waveforms of signals Vin1 and Vin2, voltage VT1 and current IT1, voltage VT2 and current IT2, voltage Vgs and current Ig, and voltages VEB5 and VBE7.

[0052] For example, by adjusting the phase difference between the signal Vin1 input to the terminal t1 and the signal Vin2 input to the terminal t2, it is possible to shorten the period during which the signal Vin1 is a High signal and the signal Vin2 is a Low signal, and the period during which the signal Vin1 is a Low signal and the signal Vin2 is a High signal, as shown in Fig. 2A. As a result, whether a positive voltage or a negative voltage is generated as the voltage VT2, the full-wave rectifier circuit 21 can generate the voltage Vgs during the above period, and it is possible to achieve, for example, a 5% duty cycle for the FET switching.

[0053] For example, by adjusting the phase difference between the signal Vin1 input to the terminal t1 and the signal Vin2 input to the terminal t2, it is possible to lengthen to some extent the period during which the signal Vin1 is a High signal and the signal Vin2 is a Low signal, and the period during which the signal Vin1 is a Low signal and the signal Vin2 is a High signal, as shown in Fig. 2B. As a result, whether a positive voltage or a negative voltage is generated as the voltage VT2, the full-wave rectifier circuit 21 can generate the voltage Vgs during the above period, thereby achieving, for example, a 50% duty cycle for the FET switching.

[0054] For example, by adjusting the phase difference between the signal Vin1 input to the terminal t1 and the signal Vin2 input to the terminal t2, the period during which the signal Vin1 is a High signal and the signal Vin2 is a Low signal, and the period during which the signal Vin1 is a Low signal and the signal Vin2 is a High signal, can be lengthened, as shown in Fig. 2C. As a result, whether a positive voltage or a negative voltage is generated as the voltage VT2, the full-wave rectifier circuit 21 can generate the voltage Vgs during the above period, and a switching duty ratio of 95%, for example, can be achieved for the FET.

[0055] For example, if the full-wave rectifier circuit 21 is not provided and the voltage Vgs can be generated only when a positive voltage or a negative voltage is generated as the voltage VT2, the duty ratio in FIG. 2C would be 47.5%. In this case, even if the period during which the signal Vin1 is a high signal and the signal Vin2 is a low signal, or the period during which the signal Vin1 is a low signal and the signal Vin2 is a high signal, is made as long as possible, the duty ratio can only be up to 50%. On the other hand, because the drive circuit 1 is provided with the full-wave rectifier circuit 21, a duty ratio greater than 50%, for example, a duty ratio between 5% and 95%, can be realized.

[0056] Here, the reason why biased magnetization does not occur in the drive circuit 1 will be explained with reference to FIG. 2B.

[0057] Current IT1 is stagnant (i.e., the current does not change) in states A and C. Current IT1 also rises in state B and falls in state D. Because the periods of state B and state D are equal, current IT1 returns to its original current value in one cycle. Therefore, biased magnetization does not occur in drive circuit 1.

[0058] Next, the operation of the drive circuit 1 when it is applied to a main bridge circuit will be described.

[0059] 3 is a diagram showing an example of application of the drive circuit 1 according to the first embodiment to a main bridge circuit. In FIG. 3, switches MH and ML are shown as the main bridge circuit, and the drive circuit 1 is connected to each of the switches MH and ML. In other words, the switches MH and ML are connected between the terminals t5 and t6 of the drive circuit 1, and are an example of an FET driven by the drive circuit 1.

[0060] The switch MH is, for example, an N-channel MOSFET. The drain of the switch MH is connected to the power supply voltage Vbus. The source of the switch MH is connected to terminal t6 of the drive circuit 1 shown in the upper part of FIG. 3 , the drain of the switch ML, and a component (e.g., a transformer or an inductor) provided on the output side of the main bridge circuit. The gate of the switch MH is connected to terminal t5 of the drive circuit 1 shown in the upper part of FIG. 3 . FIG. 3 also shows a parasitic diode of the switch MH, and in an equivalent circuit, the anode of the diode is connected to the source of the switch MH and the cathode is connected to the drain of the switch MH.

[0061] The switch ML is, for example, an N-channel MOSFET. The drain of the switch ML is connected to the source of the switch MH and a component (e.g., a transformer or an inductor) provided on the output side of the main bridge circuit. The source of the switch ML is connected to terminal t6 of the drive circuit 1 shown in the lower part of FIG. 3 and the ground terminal of the main bridge circuit. The gate of the switch ML is connected to terminal t5 of the drive circuit 1 shown in the lower part of FIG. 3. FIG. 3 also shows the parasitic diode of the switch ML, and in the equivalent circuit, the anode of the diode is connected to the source of the switch ML and the cathode is connected to the drain of the switch ML. FIG. 3 also shows the parasitic capacitance Cgd between the drain and gate of the switch ML. The voltage Vgs shown in FIG. 3 is the gate-source voltage of the switch ML and corresponds to the voltage Vgs shown in FIG. 1. The voltage Vds shown in FIG. 3 is the drain-source voltage of the switch ML.

[0062] The current Idg shown in FIG. 3 is a current that flows into the gate of the switch ML and further into the terminal t5 of the drive circuit 1 on the lower side of FIG. 3 via the parasitic capacitance Cgd.

[0063] FIG. 4 is a diagram for explaining the operation of the drive circuit 1 (specifically, the drive circuit 1 of the switch ML) according to the first embodiment.

[0064] FIG. 4 shows, from the top to the bottom, the time waveforms of signals Vin1 and Vin2, voltage VT2 and current IT2, voltage Vds, voltage Vgs, voltage Vo2 and current Ig, and voltages VEB5 and VBE7.

[0065] In period (1) shown in Fig. 4, signal Vin1 is a low signal and signal Vin2 is a low signal, voltages VT1 and VT2 are 0 V, and voltage Vgs is 0 V. In period (2) shown in Fig. 4, signal Vin1 is a high signal and signal Vin2 is a low signal, voltages VT1 and VT2 are Vcc (e.g., 15 V), and voltage Vgs is Vcc. In period (3) shown in Fig. 4, signal Vin1 is a high signal and signal Vin2 is a high signal, voltages VT1 and VT2 are 0 V, and voltage Vgs is 0 V. In period (4) shown in Fig. 4, signal Vin1 is a low signal and signal Vin2 is a high signal, voltages VT1 and VT2 are −Vcc (e.g., −15 V), and voltage Vgs is Vcc. When the voltage Vo2 is Vcc, the switch Q5 is turned off, and the switches Q6 and Q7 are also turned off.

[0066] 4, the operation of the main bridge circuit (switches MH and ML) driven by the drive circuit 1 will be described. The switches MH and ML are provided with a dead time during which they are both in the off state, and are controlled so that outside the dead time, when the switch MH is in the on state, the switch ML is in the off state, and when the switch MH is in the off state, the switch ML is in the on state.

[0067] In periods (1) and (3), the voltage Vgs of the switch ML is 0 V, so the voltage Vds of the switch ML is the voltage Vbus. In addition, in periods (2) and (4), the voltage Vgs of the switch ML is Vcc, so the voltage Vds of the switch ML is 0 V.

[0068] When transitioning from period (2) to period (3), the voltage Vgs of switch ML becomes 0 V, turning switch ML off. After switch ML is turned off, switch MH turns on, causing the voltage Vds of switch ML to rise. At this time, current Idg flows toward the gate of switch ML via parasitic capacitance Cgd. Current Idg then flows into drive circuit 1 (shown at the bottom of FIG. 3 ), through terminal t5, switch Q7, and terminal t6. If the impedance between terminals t5 and t6 is high, a high voltage is generated between the gate and source of switch ML, which could result in erroneous firing of switch ML.

[0069] For this reason, it is necessary to sufficiently reduce the impedance between the terminals t5 and t6. In particular, if the switch Q7 is not sufficiently turned on, the impedance between the terminals t5 and t6 becomes high, increasing the possibility of erroneous firing of the switch ML.

[0070] The pull-out circuit 31 has a function of suppressing erroneous firing of the switch ML, in other words, a function of pulling out the current Idg through a low-impedance path by turning on the switch Q7 sufficiently. Here, the operation of the drive circuit 1, and in particular the operation of the pull-out circuit 31, will be described with reference to FIGS.

[0071] FIG. 5 is a diagram for explaining the operation of the drive circuit 1 (specifically, the drive circuit 1 for the switch ML) according to the first embodiment when the FET (switch ML) is turned off.

[0072] FIG. 6 is a diagram for explaining the operation of the drive circuit 1 (specifically, the drive circuit 1 for the switch ML) according to the first embodiment when the FET (switch ML) is turned on.

[0073] 5 and 6 show, from the top, the time waveforms of signals Vin1 and Vin2, voltage VT2 and current IT2, voltages Vds, voltages Vgs, Vo2, currents Ig and Irg_dn, and voltages VEB5 and VBE7.

[0074] 5, the signal Vin1 is a low signal, the signal Vin2 is a high signal, and the voltage VT2 is −Vcc. At this time, the switch Q1 is in the off state and the switch Q2 is in the on state, so the path through the switch Q2, the secondary winding L2, and the diode D3 is conductive. As a result, the voltage Vgs becomes Vcc.

[0075] During period (6) shown in FIG. 5 , signal Vin2 switches from a high signal to a low signal, and voltage VT2 changes from −Vcc to 0 V. Because switch Q2 is on, the gate voltage of switch Q1 drops, turning switch Q1 on. That is, during period (7) shown in FIG. 5 , switches Q1 and Q2 are on, and voltage Vo2 drops rapidly. In this way, switches Q1 and Q2 are on when switch ML turns off (specifically, when the maximum voltage at terminal t3 becomes smaller than voltage Vo2 or when the minimum voltage at terminal t4 becomes larger than 0 V), thereby shorting voltage Vo2 of full-wave rectifier circuit 21 to the source terminal (terminal t6) of switch ML and reliably preventing erroneous firing of switch ML.

[0076] Because voltage Vgs is maintained between the gate and source of switch ML, current flows from terminal t5 of resistor R5 to full-wave rectifier circuit 21, causing voltage VEB5 of switch Q5 to exceed voltage Vbe.th (e.g., 0.6 V), turning switch Q5 on. Furthermore, voltage VBE7 of switch Q7 exceeds voltage Vbe.th, turning switch Q7 on. Switch Q6 also turns on, similarly to switch Q7. Turning on switches Q6 and Q7 promotes a decrease in voltage Vo2, thus achieving a latching effect. Note that, to maintain switch Q5 in the on state, it is preferable to decrease voltage Vo2 faster than voltage Vgs. Furthermore, switch Q6 may be omitted if a capacitor is provided between the base and emitter of switch Q7 so that voltage VBE7 of switch Q7 can be maintained above voltage Vbe.th once switch Q5 is turned on.

[0077] If switches Q6 and Q7 were not provided, voltage Vo2 could only be reduced to a voltage equivalent to the voltage Vgs.th of switches Q1 and Q2 (i.e., a voltage of Vgs.th×2). However, by providing switches Q6 and Q7, voltage Vo2 can be reduced to 0 V.

[0078] During period (8) shown in Figure 5, switch MH turns on, causing voltage Vds across switch ML to rise and current Idg to flow into drive circuit 1. At this time, voltage VBE7 across switch Q7 is sufficiently higher than voltage Vbe.th, maintaining switch Q7 in the on state. This allows switch Q7 to maintain a low impedance between terminals t5 and t6, preventing false firing of switch ML. The rate at which voltage VBE7 drops can be determined by the magnitude of resistor R9.

[0079] When the voltage VT2 changes from Vcc to 0V and the switch ML is turned off, erroneous firing of the switch ML can be prevented in the same way as when the voltage VT2 changes from -Vcc to 0V and the switch ML is turned off.

[0080] Furthermore, because the base-emitter voltage of switch Q6 is equal to voltage VBE7, switch Q6 can remain on, and current Idg flows through resistors R5 and R6 to switch Q6. At this time, a voltage is applied across the base and emitter of switch Q5, and when switch Q5 is turned on, it operates in the direction in which a voltage is applied across the base and emitter of switch Q6, so switch Q7 may not be provided depending on the magnitude of current Idg or the setting of resistor R5.

[0081] 6, the signal Vin1 is a low signal, the signal Vin2 is a low signal, and the voltage VT2 is 0 V. At this time, the switch Q1 is in the off state, and the switch Q2 is in the off state, so the voltages Vo2 and Vgs are 0 V.

[0082] 6, signal Vin1 switches from a low signal to a high signal, and voltage VT2 rises from 0 V to Vcc. Even when switches Q1 and Q2 are off, full-wave rectification can be performed by the body diodes of switches Q1 and Q2, so voltage Vo2 rises along with voltage VT2. The path through diode D4, secondary winding L2, and switch Q1 becomes conductive, and voltage VT2 is applied between the gate and source of switch Q1, turning switch Q1 on.

[0083] When voltage Vo2 rises, current flows from the full-wave rectifier circuit 21 side of resistor R5 to terminal t5 side, so as to raise voltage Vgs of switch ML. As a result, voltage VEB5 of switch Q5 is firmly in the OFF state. Because switch Q5 is in the OFF state, switches Q6 and Q7 cannot be turned on.

[0084] As explained in FIG. 5, the switches Q5, Q6 and Q7 are circuits for drawing out the current Idg, but as explained in FIG. 6, they are automatically turned off when the voltage Vgs rises.

[0085] As described above, there is a phase difference between signal Vin1 input to terminal t1 of primary winding L1 of pulse transformer T1 and signal Vin2 input to terminal t2, and full-wave rectifier circuit 21 is connected to secondary winding L2, so a duty ratio greater than 50% can be achieved without causing bias magnetism in the transformer. Furthermore, full-wave rectifier circuit 21 and extraction circuit 31 can reduce the impedance between terminals t5 and t6, preventing false firing of the main bridge circuit.

[0086] Specifically, due to the phase difference, the primary winding L1 can be in one of three states: state A where a high signal is input to the terminal t1 and a high signal is input to the terminal t2, state B where a high signal is input to the terminal t1 and a low signal is input to the terminal t2, state C where a low signal is input to the terminal t1 and a low signal is input to the terminal t2, and state D where a low signal is input to the terminal t1 and a high signal is input to the terminal t2. Voltages of different polarities are generated in the secondary winding L2 in states B and D, but because the full-wave rectifier circuit 21 is connected to the secondary winding L2, the drive circuit 1 can apply a voltage to the switch ML regardless of the polarity of the voltage generated in the secondary winding L2 (in other words, regardless of whether the state is B or D). For example, if a voltage can be applied to the switch ML only in states B and D among states A, B, C, and D, a maximum duty ratio of only 50% can be realized, but if a voltage can be applied to the switch ML in both states B and D among states A, B, C, and D, various duty ratios can be realized, and therefore a duty ratio greater than 50% can be realized.

[0087] When the switch ML is turned off, a current Idg generated by the parasitic capacitance Cgd of the switch ML flows from the gate of the switch ML into the drive circuit 1, which may result in erroneous firing of the switch ML. In contrast, the drive circuit 1 is provided with an extraction circuit 31 for extracting the current Idg from the gate of the switch ML when the switch ML is turned off, which prevents erroneous firing of the switch ML and enables high-speed turn-off and turn-on.

[0088] For example, by using the extraction circuit 31, it is possible to make the voltage Vo2 or Vgs approach the source voltage of the switch ML (the voltage at the terminal t6: for example, 0 V), thereby preventing erroneous firing of the switch ML. For example, when Vgs-Vo2 exceeds Vth1, that is, when the absolute value of the voltage generated in the secondary winding L2 becomes small and the switch ML turns off, it is possible to prevent erroneous firing of the switch ML.

[0089] Second Embodiment Next, a drive circuit according to a second embodiment will be described.

[0090] FIG. 7 is a circuit diagram showing an example of a drive circuit 2 according to the second embodiment.

[0091] The drive circuit 2 differs from the drive circuit 1 according to the first embodiment in that it includes a full-wave rectifier circuit 22 instead of the full-wave rectifier circuit 21 and a pull-out circuit 32 instead of the pull-out circuit 31. The other points are the same as those in the first embodiment, and therefore a description thereof will be omitted.

[0092] The full-wave rectifier circuit 22 is connected to the secondary winding L2 of the pulse transformer T1. Although Fig. 7 shows an example in which the full-wave rectifier circuit 22 is connected to the secondary winding L2 via an RC circuit made up of a resistor R10 and a capacitor C10, this RC circuit may not be provided, as in the first embodiment.

[0093] For example, the full-wave rectifier circuit 22 includes two diodes D1 and D2 connected in series to form a full-bridge circuit, and two diodes D3 and D4 connected in series to form the full-bridge circuit. The node between the two diodes D1 and D2 is connected to a terminal t3 at one end of a secondary winding L2 of a pulse transformer T1. The node between the two diodes D3 and D4 is connected to a terminal t4 at the other end of the secondary winding L2 of the pulse transformer T1. The full-wave rectifier circuit 22 also includes a resistor R4 connected in parallel with the diode D4.

[0094] The anode of the diode D1 is connected to the cathode of the diode D2, the terminal t3, and the extraction circuit 32. The cathode of the diode D1 is connected to the cathode of the diode D3 and the extraction circuit 32.

[0095] The anode of the diode D2 is connected to the terminal t6, and the cathode of the diode D2 is connected to the anode of the diode D1, the terminal t3, and the extraction circuit 32.

[0096] The anode of the diode D3 is connected to the cathode of the diode D4, the terminal t4, and the extraction circuit 32. The cathode of the diode D3 is connected to the cathode of the diode D1 and the extraction circuit 32.

[0097] The anode of the diode D4 is connected to the terminal t6, and the cathode of the diode D4 is connected to the anode of the diode D3, the terminal t4, and the extraction circuit 32.

[0098] The full-wave rectifier circuit 22 full-wave rectifies the voltage generated in the secondary winding L2 and outputs the result to the gate of the FET. FIG. 7 shows a voltage Vo2 as the output voltage of the full-wave rectifier circuit 22. The secondary winding L2 generates voltages of different polarities in State B, where a high signal is input to terminal t1 and a low signal is input to terminal t2, and State D, where a low signal is input to terminal t1 and a high signal is input to terminal t2. However, because the full-wave rectifier circuit 22 is connected to the secondary winding L2, the full-wave rectifier circuit 22 can output a voltage Vo2 corresponding to the absolute value of the voltage generated in the secondary winding L2 regardless of the polarity of the voltage generated in the secondary winding L2 (in other words, in either State B or State D). Therefore, the drive circuit 2 can apply a voltage Vgs corresponding to the voltage Vo2 to the FET connected between terminals t5 and t6.

[0099] The extraction circuit 32 is a circuit for extracting current from the gate of the FET when the FET is turned off. The operation of the extraction circuit 32 will be described in detail later.

[0100] The pull-out circuit 32 includes, for example, resistors R11, R12, R13, R14, and R15, switches Q8 and Q9, and diodes D5 and D6. Resistor R12 is an example of a first circuit that generates a voltage difference between the output voltage of the full-wave rectifier circuit 22 and the gate-source voltage of the FET. Resistors R13, R14, and R15 and switches Q8 and Q9 are an example of a second circuit that adjusts the output voltage of the full-wave rectifier circuit 22 or the gate-source voltage of the FET to the source voltage of the FET (the voltage at terminal t6: e.g., 0 V) ​​based on the output voltage of the full-wave rectifier circuit 22, the gate-source voltage of the FET, or the voltage difference between the output voltage of the full-wave rectifier circuit 22 and the gate-source voltage of the FET. Diodes D5 and D6 and resistor R11 are an example of a third circuit. If the output voltage of the full-wave rectifier circuit 22 is Vo2, the threshold voltage set for the third circuit is Vth2 (for example, 0 V or higher), the source voltage of the FET is Vs, and the value obtained by subtracting Vs from the higher of the voltages at one terminal and the other terminal of the secondary winding of the pulse transformer T1 (i.e., the voltage based on the source voltage of the FET), the third circuit causes the second circuit to bring Vo2 closer to Vs when Vo2-VT2>Vth2 (in other words, when Vo2-VT2 exceeds Vth2).

[0101] Here, bringing the output voltage of the full-wave rectifier circuit 22 closer to the source voltage of the FET means making the two output terminals of the full-wave rectifier circuit 22 conductive with a switch and connecting the source of the FET and both output terminals of the full-wave rectifier circuit 22 with low impedance.

[0102] For example, in the second embodiment, resistors R13, R14, and R15 and switches Q8 and Q9 bring the output voltage of full-wave rectifier circuit 22 or the gate-source voltage of the FET closer to the source voltage of the FET based on the voltage difference between the output voltage of full-wave rectifier circuit 22 and the gate-source voltage of the FET. Specifically, when the gate-source voltage of the FET is greater than the output voltage of full-wave rectifier circuit 22, resistors R13, R14, and R15 and switches Q8 and Q9 bring the output voltage of full-wave rectifier circuit 22 or the gate-source voltage of the FET closer to the source voltage of the FET.

[0103] The switch Q8 is, for example, a PNP transistor. The base of the switch Q8 is connected to one end of a resistor R11, the cathode of a diode D5, and the cathode of a diode D6. The collector of the switch Q8 is connected to one end of a resistor R13. The emitter of the switch Q8 is connected to one end of a resistor R12, one end of a resistor R14, the base of the switch Q9, the cathode of a diode D1, and the cathode of a diode D3.

[0104] The switch Q9 is, for example, a PNP transistor. The base of the switch Q9 is connected to the emitter of the switch Q8, one end of the resistor R12, one end of the resistor R14, the cathode of the diode D1, and the cathode of the diode D3. The collector of the switch Q9 is connected to the other end of the resistor R12 and the terminal t5. The emitter of the switch Q9 is connected to one end of the resistor R15.

[0105] The anode of diode D5 is connected to the anode of diode D1, the cathode of diode D2, and terminal t3. The cathode of diode D5 is connected to the cathode of diode D6, the base of switch Q8, and one end of resistor R11.

[0106] The anode of diode D6 is connected to the anode of diode D3, the cathode of diode D4, the other end of resistor R11, and terminal t4, and the cathode of diode D6 is connected to the cathode of diode D5, the base of switch Q8, and one end of resistor R11.

[0107] Resistor R11 is connected in parallel with diode D6.

[0108] One end of the resistor R12 is connected to the emitter of the switch Q8, the base of the switch Q9, one end of the resistor R14, the cathode of the diode D1 and the cathode of the diode D3, and the other end is connected to the emitter of the switch Q9 and the terminal t5.

[0109] One end of the resistor R13 is connected to the collector of the switch Q8, and the other end is connected to the terminal t6.

[0110] One end of the resistor R14 is connected to the base of the switch Q9, the emitter of the switch Q8, one end of the resistor R12, the cathode of the diode D1 and the cathode of the diode D3, and the other end is connected to the terminal t6.

[0111] One end of the resistor R15 is connected to the collector of the switch Q9, and the other end is connected to the terminal t6.

[0112] As with the drive circuit 1, the drive circuit 2 can also achieve a duty ratio greater than 50%.

[0113] Next, an operation of the drive circuit 2 for the switch ML when the switch ML is turned off will be described when the drive circuit 2 is applied to the main bridge circuit shown in Fig. 3. The switch ML is an example of an FET driven by the drive circuit 2.

[0114] When the switch ML turns off, for example, the voltage VT2 changes from -Vcc to 0 V. The voltage VT2 across the secondary winding L2 is pulled down by the resistor R4, and approaches the voltage at the terminal t6 (the source voltage of the switch ML). Furthermore, the base of the switch Q8 is pulled down toward the resistor R4 by the resistor R11, and the base of the switch Q8 approaches the voltage at the terminal t6. As the voltage VT2 changes to 0 V, the switch Q8 turns on.

[0115] When switch Q8 is turned on, voltage Vo2 drops, and current flows through a path that passes through terminal t5, resistor R12, switch Q8, resistor R13, and terminal t6, allowing current Idg to be drawn from the gate of switch ML via a low-impedance path. Furthermore, current flows from terminal t5 of resistor R12 to full-wave rectifier circuit 22, turning on switch Q9, allowing current Idg to be drawn from the gate of switch ML at high speed. This prevents erroneous firing of switch ML.

[0116] When the voltage VT2 changes from Vcc to 0V and the switch ML is turned off, erroneous firing of the switch ML can be prevented in the same way as when the voltage VT2 changes from -Vcc to 0V and the switch ML is turned off.

[0117] When the voltage VT2 is Vcc and the switch ML is in the ON state, a current flows through the diode D1, so that the base of the switch Q8 goes to a high level and the switch Q8 is in the OFF state.

[0118] In this way, the extraction circuit 32 can bring the voltage Vo2 or Vgs closer to the source voltage of the switch ML (the voltage at the terminal t6), thereby preventing erroneous firing of the switch ML. For example, when the voltage Vgs is greater than the voltage Vo2, that is, when the absolute value of the voltage generated in the secondary winding L2 becomes small and the switch ML is turned off, erroneous firing of the switch ML can be prevented. Note that, in order to speed up the turn-on of the switch Q8, the resistance values ​​of the resistors R4 and R11 must be small, which increases the bias power.

[0119] Third Embodiment Next, a drive circuit according to a third embodiment will be described.

[0120] FIG. 8 is a circuit diagram showing an example of a drive circuit 3 according to the third embodiment.

[0121] The drive circuit 3 differs from the drive circuit 2 according to the second embodiment in that it includes a full-wave rectifier circuit 23 instead of the full-wave rectifier circuit 22, and a pull-out circuit 33 instead of the pull-out circuit 32. The other points are the same as those in the second embodiment, and therefore a description thereof will be omitted.

[0122] The full-wave rectifier circuit 23 differs from the full-wave rectifier circuit 22 according to the second embodiment in that it includes a resistor R1 instead of the resistor R4. Since the other points are the same as those in the second embodiment, the description thereof will be omitted. The resistor R4 is connected in parallel with the diode D1.

[0123] The pull-out circuit 33 differs from the pull-out circuit 32 according to the second embodiment in that it includes a switch Q10, diodes D7 and D8, and resistors R16 and R17 instead of a switch Q8, diodes D5 and D6, and resistors R11 and R13. Since the other points are the same as those in the second embodiment, a description thereof will be omitted.

[0124] Resistor R12 is an example of a first circuit that generates a voltage difference between the output voltage of full-wave rectifier circuit 23 and the gate-source voltage of the FET. Resistors R14, R15, and R17 and switches Q9 and Q10 are an example of a second circuit that brings the output voltage of full-wave rectifier circuit 23 or the gate-source voltage of the FET closer to the source voltage of the FET (the voltage at terminal t6: e.g., 0 V) ​​based on the output voltage of full-wave rectifier circuit 23, the gate-source voltage of the FET, or the voltage difference between the output voltage of full-wave rectifier circuit 23 and the gate-source voltage of the FET. Diodes D7 and D8 and resistor R16 are an example of a fourth circuit. If the output voltage of the full-wave rectifier circuit 23 is Vo2, the threshold voltage set for the fourth circuit is Vth3 (for example, 0 V or higher), the source voltage of the FET is Vs, and the value obtained by subtracting Vs from the lower of the voltages at one terminal and the other terminal of the secondary winding of the pulse transformer T1 (i.e., the voltage based on the source voltage of the FET) is VT2', the fourth circuit causes the second circuit to bring Vo2 closer to Vs when VT2' > Vth3 (in other words, when VT2' exceeds Vth3).

[0125] Here, bringing the output voltage of the full-wave rectifier circuit 23 closer to the source voltage of the FET means making the two output terminals of the full-wave rectifier circuit 23 conductive with a switch and connecting the source of the FET and both output terminals of the full-wave rectifier circuit 23 with low impedance.

[0126] For example, in the third embodiment, resistors R14, R15, and R17 and switches Q9 and Q10 bring the output voltage of full-wave rectifier circuit 23 or the gate-source voltage of the FET closer to the source voltage of the FET based on the voltage difference between the output voltage of full-wave rectifier circuit 23 and the gate-source voltage of the FET. Specifically, when the gate-source voltage of the FET is larger than the output voltage of full-wave rectifier circuit 23, resistors R14, R15, and R17 and switches Q9 and Q10 bring the output voltage of full-wave rectifier circuit 23 or the gate-source voltage of the FET closer to the source voltage of the FET.

[0127] The switch Q10 is, for example, an NPN transistor. The base of the switch Q10 is connected to one end of a resistor R16, the anode of a diode D7, and the anode of a diode D8. The collector of the switch Q10 is connected to one end of a resistor R17. The emitter of the switch Q10 is connected to a terminal t6.

[0128] The anode of diode D7 is connected to the anode of diode D8, the base of switch Q10, and one end of resistor R16. The cathode of diode D7 is connected to the anode of diode D1, the cathode of diode D2, the other end of resistor R16, and terminal t3.

[0129] The anode of diode D8 is connected to the anode of diode D7, the base of switch Q10, and one end of resistor R16. The cathode of diode D8 is connected to the anode of diode D3, the cathode of diode D4, and terminal t4.

[0130] Resistor R16 is connected in parallel with diode D7.

[0131] One end of the resistor R17 is connected to the collector of the switch Q10, and the other end is connected to one end of the resistor R12, one end of the resistor R14, the base of the switch Q9, the cathode of the diode D1, and the cathode of the diode D3.

[0132] As with the drive circuits 1 and 2, the drive circuit 3 can also achieve a duty ratio greater than 50%.

[0133] 3, the operation of drive circuit 3 for switch ML when switch ML is turned off is basically the same as that of drive circuit 2, and therefore will not be described here. In the third embodiment, the bridge circuit is pulled up to the high side. Furthermore, when voltage VT2 is Vcc and switch ML is on, current flows through diode D4, so the base of switch Q10 goes low, and switch Q10 is turned off.

[0134] In this way, the extraction circuit 33 can bring the voltage Vo2 or Vgs closer to the source voltage of the switch ML (the voltage at the terminal t6), thereby preventing erroneous firing of the switch ML. For example, when the voltage Vgs is greater than the voltage Vo2, that is, when the absolute value of the voltage generated in the secondary winding L2 becomes small and the switch ML is turned off, erroneous firing of the switch ML can be prevented. Note that, in order to speed up the turn-on of the switch Q10, the resistance values ​​of the resistors R1 and R16 must be small, which increases the bias power.

[0135] Fourth Embodiment Next, a drive circuit according to a fourth embodiment will be described.

[0136] FIG. 9 is a circuit diagram showing an example of the drive circuit 4 according to the fourth embodiment.

[0137] The drive circuit 4 differs from the drive circuit 1 according to the first embodiment in that it includes a full-wave rectifier circuit 24 instead of the full-wave rectifier circuit 21, a pull-out circuit 34 instead of the pull-out circuit 31, and does not include the resistor R10 and the capacitor C10. Since the other points are the same as those in the first embodiment, a description thereof will be omitted. Note that the drive circuit 4 may also include the resistor R10 and the capacitor C10.

[0138] The full-wave rectifier circuit 24 is connected to the secondary winding L2 of the pulse transformer T1. For example, the full-wave rectifier circuit 24 includes two diodes D1 and D2 connected in series to form a full-bridge circuit, and two diodes D3 and D4 connected in series to form the full-bridge circuit. The node between the two diodes D1 and D2 is connected to a terminal t3 at one end of the secondary winding L2 of the pulse transformer T1. The node between the two diodes D3 and D4 is connected to a terminal t4 at the other end of the secondary winding L2 of the pulse transformer T1.

[0139] The anode of the diode D1 is connected to the cathode of the diode D2 and the terminal t3, and the cathode of the diode D1 is connected to the cathode of the diode D3 and the extraction circuit 34.

[0140] The anode of diode D2 is connected to terminal t6, and the cathode of diode D2 is connected to the anode of diode D1 and terminal t3.

[0141] The anode of the diode D3 is connected to the cathode of the diode D4 and the terminal t4, and the cathode of the diode D3 is connected to the cathode of the diode D1 and the extraction circuit 34.

[0142] The anode of diode D4 is connected to terminal t6, and the cathode of diode D4 is connected to the anode of diode D3 and terminal t4.

[0143] The full-wave rectifier circuit 24 full-wave rectifies the voltage generated in the secondary winding L2 and outputs the result to the gate of the FET. FIG. 9 shows a voltage Vo2 as the output voltage of the full-wave rectifier circuit 24. The secondary winding L2 generates voltages of different polarities in State B, where a high signal is input to terminal t1 and a low signal is input to terminal t2, and State D, where a low signal is input to terminal t1 and a high signal is input to terminal t2. However, because the full-wave rectifier circuit 24 is connected to the secondary winding L2, the full-wave rectifier circuit 24 can output a voltage Vo2 corresponding to the absolute value of the voltage generated in the secondary winding L2 regardless of the polarity of the voltage generated in the secondary winding L2 (in other words, in either State B or State D). Therefore, the drive circuit 4 can apply a voltage Vgs corresponding to the voltage Vo2 to the FET connected between terminals t5 and t6.

[0144] The extraction circuit 34 is a circuit for extracting current from the gate of the FET when the FET is turned off. The operation of the extraction circuit 34 will be described in detail later.

[0145] The extraction circuit 34 includes, for example, resistors R18, R19, R20, R21, and R22, switches Q11 and Q12, a diode D9, and a capacitor C1. The resistor R18 and the diode D9 are an example of a first circuit that generates a voltage difference between the output voltage of the full-wave rectifier circuit 24 and the gate-source voltage of the FET. The resistors R19, R20, R21, and R22, the switches Q11 and Q12, and the capacitor C1 are an example of a second circuit that brings the output voltage of the full-wave rectifier circuit 24 or the gate-source voltage of the FET closer to the source voltage of the FET (the voltage at terminal t6: for example, 0 V) ​​based on the output voltage of the full-wave rectifier circuit 24, the gate-source voltage of the FET, or the voltage difference between the output voltage of the full-wave rectifier circuit 24 and the gate-source voltage of the FET.

[0146] Here, bringing the output voltage of the full-wave rectifier circuit 24 closer to the source voltage of the FET means making the two output terminals of the full-wave rectifier circuit 24 conductive with a switch and connecting the source of the FET and both output terminals of the full-wave rectifier circuit 24 with low impedance.

[0147] For example, in the fourth embodiment, resistors R19, R20, R21, and R22, switches Q11 and Q12, and capacitor C1 bring the output voltage of full-wave rectifier circuit 24 or the gate-source voltage of the FET closer to the source voltage of the FET based on the output voltage of full-wave rectifier circuit 24 or the gate-source voltage of the FET. Specifically, when the output voltage of full-wave rectifier circuit 24 is smaller than a predetermined value and the gate-source voltage of the FET is greater than a predetermined value, resistors R19, R20, R21, and R22, switches Q11 and Q12, and capacitor C1 bring the gate-source voltage of the FET closer to the source voltage of the FET. The predetermined value is not particularly limited as long as it is a value that can determine whether the output voltage of full-wave rectifier circuit 24 and the gate-source voltage of the FET are at a high level or a low level.

[0148] One end of the resistor R18 is connected to one end of the resistor R19, the cathode of the diode D1, and the cathode of the diode D3, and the other end is connected to the anode of the diode D9.

[0149] One end of the resistor R19 is connected to one end of the resistor R18, the cathode of the diode D1, and the cathode of the diode D3, and the other end is connected to one end of the resistor R20 and the base of the switch Q11.

[0150] One end of the resistor R20 is connected to the other end of the resistor R19 and the base of the switch Q11, and the other end is connected to the terminal t6.

[0151] One end of the resistor R21 is connected to one end of the resistor R22, the cathode of the diode D9, and the terminal t5, and the other end is connected to the collector of the switch Q11, the base of the switch Q12, and one end of the capacitor C1.

[0152] One end of the resistor R22 is connected to one end of the resistor R21, the cathode of the diode D9, and the terminal t5, and the other end is connected to the collector of the switch Q12.

[0153] The capacitor C1 has one end connected to the other end of the resistor R21, the collector of the switch Q11, and the base of the switch Q12, and the other end connected to the terminal t6.

[0154] The anode of the diode D9 is connected to the other end of the resistor R18, and the cathode of the diode D9 is connected to one end of the resistor R21, one end of the resistor R22, and the terminal t5.

[0155] The switch Q11 is, for example, an NPN transistor. The base of the switch Q11 is connected to the other end of the resistor R19 and one end of the resistor R20. The collector of the switch Q11 is connected to the other end of the resistor R21, one end of the capacitor C1, and the base of the switch Q12. The emitter of the switch Q11 is connected to the terminal t6.

[0156] The switch Q12 is, for example, an NPN transistor. The base of the switch Q12 is connected to the other end of the resistor R21, one end of the capacitor C1, and the collector of the switch Q11. The collector of the switch Q12 is connected to the other end of the resistor R22. The emitter of the switch Q12 is connected to the terminal t6.

[0157] As with the drive circuits 1 to 3, the drive circuit 4 can also achieve a duty ratio greater than 50%.

[0158] Next, an operation of the drive circuit 4 for the switch ML when the switch ML is turned off will be described when the drive circuit 4 is applied to the main bridge circuit shown in Fig. 3. The switch ML is an example of an FET driven by the drive circuit 4.

[0159] When the switch ML is turned off, for example, the voltage VT2 changes from −Vcc to 0 V. Accordingly, the voltage Vo2 is reduced by the resistors R19 and R20. Note that a diode D9 is provided to prevent the voltage Vo2 from being affected by the voltage Vgs of the capacitor Cgs at this time.

[0160] When switch Q11 turns off due to a drop in voltage Vo2, switch Q12 turns on, and current Idg is rapidly drawn through a low-impedance path, preventing erroneous firing of switch ML. By maintaining the base-emitter voltage of switch Q12 at a constant level or higher using capacitor C1, erroneous firing of switch ML can also be prevented. Similarly to when voltage VT2 changes from Vcc to 0 V to turn switch ML off, erroneous firing of switch ML can also be prevented.

[0161] In this way, the extraction circuit 34 can bring the voltage Vo2 or Vgs closer to the source voltage of the switch ML (the voltage at the terminal t6), thereby preventing erroneous firing of the switch ML. For example, when the voltage Vo2 is smaller than a predetermined value and the voltage Vgs is larger than a predetermined value, that is, when the absolute value of the voltage generated in the secondary winding L2 becomes small and the switch ML turns off, erroneous firing of the switch ML can be prevented. Note that, in order to speed up the turn-off of the switch Q11, the resistance values ​​of the resistors R19 and R20 must be small, which increases the bias power.

[0162] Fifth Embodiment Next, a drive circuit according to a fifth embodiment will be described.

[0163] FIG. 10 is a circuit diagram showing an example of a drive circuit 5 according to the fifth embodiment.

[0164] The drive circuit 5 differs from the drive circuit 4 according to the fourth embodiment in that it includes an extraction circuit 35 instead of the extraction circuit 34. The other points are the same as those in the fourth embodiment, and therefore a description thereof will be omitted.

[0165] The pull-out circuit 35 is a circuit for pulling out current from the gate of the FET when the FET is turned off. The operation of the pull-out circuit 35 will be described in detail later.

[0166] The pull-out circuit 35 includes, for example, resistors R23, R24, R25, and R26, a switch Q13, and a diode D10. The resistor R23 and the diode D10 are an example of a first circuit that generates a voltage difference between the output voltage of the full-wave rectifier circuit 24 and the gate-source voltage of the FET. The resistors R24, R25, and R26 and the switch Q13 are an example of a second circuit that brings the output voltage of the full-wave rectifier circuit 24 or the gate-source voltage of the FET closer to the source voltage of the FET (the voltage at terminal t6: for example, 0 V) ​​based on the output voltage of the full-wave rectifier circuit 24, the gate-source voltage of the FET, or the voltage difference between the output voltage of the full-wave rectifier circuit 24 and the gate-source voltage of the FET.

[0167] For example, in the fifth embodiment, resistors R24, R25, and R26 and switch Q13 bring the output voltage of full-wave rectifier circuit 24 or the gate-source voltage of the FET closer to the source voltage of the FET based on the voltage difference between the output voltage of full-wave rectifier circuit 24 and the gate-source voltage of the FET. Specifically, when the gate-source voltage of the FET is larger than the output voltage of full-wave rectifier circuit 24, resistors R24, R25, and R26 and switch Q13 bring the output voltage of full-wave rectifier circuit 24 or the gate-source voltage of the FET closer to the source voltage of the FET.

[0168] The resistor R23 has one end connected to one end of the resistor R24, the cathode of the diode D1, and the cathode of the diode D3, and the other end connected to the anode of the diode D10.

[0169] One end of the resistor R24 ​​is connected to one end of the resistor R23, the cathode of the diode D1, and the cathode of the diode D3, and the other end is connected to one end of the resistor R25 and the base of the switch Q13.

[0170] One end of the resistor R25 is connected to the other end of the resistor R24 ​​and the base of the switch Q13, and the other end is connected to the terminal t6.

[0171] One end of the resistor R26 is connected to the collector of the switch Q13, and the other end is connected to the terminal t6.

[0172] The anode of the diode D10 is connected to the other end of the resistor R23, and the cathode of the diode D10 is connected to the emitter of the switch Q13 and the terminal t5.

[0173] The switch Q13 is, for example, a PNP transistor. The base of the switch Q13 is connected to the other end of the resistor R24 ​​and one end of the resistor R25. The collector of the switch Q13 is connected to one end of the resistor R26. The emitter of the switch Q13 is connected to the cathode of the diode D10 and the terminal t5.

[0174] As with the drive circuits 1 to 4, the drive circuit 5 can also achieve a duty ratio greater than 50%.

[0175] Next, an operation of the drive circuit 5 for the switch ML when the switch ML is turned off will be described when the drive circuit 5 is applied to the main bridge circuit shown in Fig. 3. The switch ML is an example of an FET driven by the drive circuit 5.

[0176] When the switch ML is turned off, for example, the voltage VT2 changes from −Vcc to 0 V. Accordingly, the voltage Vo2 is reduced by the resistors R24 and R25. Note that the diode D10 is provided to prevent the voltage Vo2 from being affected by the voltage Vgs of the capacitor Cgs at this time.

[0177] When the switch Q13 is turned on due to a drop in the voltage Vo2, the current Idg is drawn out at high speed via a low-impedance path, preventing erroneous firing of the switch ML. Note that when the voltage VT2 changes from Vcc to 0 V to turn off the switch ML, erroneous firing of the switch ML can also be prevented, just as when the voltage VT2 changes from −Vcc to 0 V to turn off the switch ML.

[0178] In this way, the extraction circuit 35 can bring the voltage Vo2 or Vgs closer to the source voltage of the switch ML (the voltage at the terminal t6), thereby preventing erroneous firing of the switch ML. For example, when the voltage Vgs is greater than the voltage Vo2, that is, when the absolute value of the voltage generated in the secondary winding L2 becomes small and the switch ML turns off, erroneous firing of the switch ML can be prevented. Note that, to speed up the turn-on of the switch Q13, the resistance values ​​of the resistors R24 and R25 must be small, which increases the bias power. Furthermore, the resistance value of the resistor R24 ​​must be set to a value that prevents the switch Q13 from turning on when the voltage Vgs is high.

[0179] Sixth Embodiment Next, a drive circuit according to a sixth embodiment will be described.

[0180] FIG. 11 is a circuit diagram showing an example of a drive circuit 6 according to the sixth embodiment.

[0181] The drive circuit 6 differs from the drive circuit 4 according to the fourth embodiment in that it includes an extraction circuit 36 ​​instead of the extraction circuit 34. The other points are the same as those in the fourth embodiment, and therefore a description thereof will be omitted.

[0182] The extraction circuit 36 ​​differs from the extraction circuit 31 according to the first embodiment in that it further includes a resistor R27, a capacitor C2, and a diode D11. The other points are the same as those in the first embodiment, and therefore description thereof will be omitted.

[0183] Resistor R5 and diode D11 are an example of a first circuit that generates a voltage difference between the output voltage of full-wave rectifier circuit 24 and the gate-source voltage of the FET. Resistors R6, R7, R8, R9, and R27, capacitor C2, and switches Q5, Q6, and Q7 are an example of a second circuit that brings the output voltage of full-wave rectifier circuit 24 or the gate-source voltage of the FET closer to the source voltage of the FET (the voltage at terminal t6: for example, 0 V) ​​based on the output voltage of full-wave rectifier circuit 24, the gate-source voltage of the FET, or the voltage difference between the output voltage of full-wave rectifier circuit 24 and the gate-source voltage of the FET.

[0184] For example, in the sixth embodiment, resistors R6, R7, R8, R9, and R27, capacitor C2, and switches Q5, Q6, and Q7 bring the output voltage of full-wave rectifier circuit 24 or the gate-source voltage of the FET closer to the source voltage of the FET based on the voltage difference between the output voltage of full-wave rectifier circuit 24 and the gate-source voltage of the FET. Specifically, when the gate-source voltage of the FET is larger than the output voltage of full-wave rectifier circuit 24, resistors R6, R7, R8, R9, and R27, capacitor C2, and switches Q5, Q6, and Q7 bring the output voltage of full-wave rectifier circuit 24 or the gate-source voltage of the FET closer to the source voltage of the FET.

[0185] One end of the resistor R27 is connected to one end of the resistor R5, one end of the resistor R6, the base of the switch Q5, the cathode of the diode D1 and the cathode of the diode D3, and the other end is connected to the terminal t6.

[0186] The capacitor C2 has one end connected to the other end of the resistor R8, one end of the resistor R9, the base of the switch Q6, and the base of the switch Q7, and the other end connected to the terminal t6.

[0187] The anode of the diode D11 is connected to the other end of the resistor R5, and the cathode of the diode D11 is connected to the emitter of the switch Q5, one end of the resistor R7, and the terminal t5.

[0188] As in the first to fifth embodiments, the drive circuit 6 can also achieve a duty ratio greater than 50%.

[0189] Next, an operation of the drive circuit 6 for the switch ML when the switch ML is turned off will be described when the drive circuit 6 is applied to the main bridge circuit shown in Fig. 3. The switch ML is an example of an FET driven by the drive circuit 6.

[0190] When the switch ML is turned off, for example, the voltage VT2 changes from −Vcc to 0 V. Accordingly, the voltage Vo2 is reduced by the resistor R27. Note that the diode D11 is provided to prevent the voltage Vo2 from being affected by the voltage Vgs of the capacitor Cgs at this time.

[0191] When switch Q5 turns on due to a drop in voltage Vo2, switches Q6 and Q7 turn on, current Idg is rapidly drawn through a low-impedance path, and voltage Vo2 rapidly drops. This prevents erroneous firing of switch ML. Incidentally, when switch ML is turned off due to a change in voltage VT2 from Vcc to 0 V, erroneous firing of switch ML can also be prevented, just as when switch ML is turned off due to a change in voltage VT2 from −Vcc to 0 V.

[0192] In this way, the pull-out circuit 36 ​​can prevent erroneous firing of the switch ML, as in the first to fifth embodiments. In order to speed up the turn-on of the switch Q5, the resistance value of the resistor R27 must be reduced, which increases the bias power.

[0193] (Other Embodiments) As described above, the embodiments have been described as examples of the technology according to the present disclosure. However, the technology according to the present disclosure is not limited to these, and can be applied to embodiments in which modifications, substitutions, additions, omissions, etc. are made as appropriate. For example, the following modifications are also included in one embodiment of the present disclosure.

[0194] For example, the first circuit in the first to sixth embodiments may be configured with a resistor as in the first to third embodiments, or may be configured with a series circuit of a resistor and a diode as in the fourth to sixth embodiments, or may be configured with a diode. In other words, the first circuit is a circuit made up of a resistor, a diode, or a series circuit of a resistor and a diode.

[0195] For example, a capacitor may be provided between the base and emitter of the switch Q7 in the first embodiment.

[0196] For example, the capacitor C1 does not need to be provided between the base and emitter of the switch Q12 in the fourth embodiment.

[0197] For example, the capacitor C2 may not be provided between the base and emitter of the switch Q7 in the sixth embodiment.

[0198] For example, the resistors R6, R7, R8, and R9 and the switches Q5, Q6, and Q7 in the first embodiment may be replaced with the resistors R19, R20, R21, and R22 and the switches Q11 and Q12 in the fourth embodiment, and further, a capacitor C1 may be provided.

[0199] For example, the switch Q9 and the resistors R14 and R15 in the second and third embodiments may be replaced with the resistors R19, R20, R21 and R22 and the switches Q11 and Q12 in the fourth embodiment, and further, a capacitor C1 may be provided.

[0200] For example, the present disclosure can be realized not only as a drive circuit, but also as an operating method of a drive circuit.

[0201] FIG. 12 is a flowchart illustrating an example of a method of operation according to another embodiment.

[0202] As shown in FIG. 12 , a method of operating a drive circuit for driving a transistor having a first terminal which is a gate or a base, a second terminal which is a source or an emitter, and a third terminal which is a drain or a collector includes the steps of inputting signals having a phase difference to one terminal and the other terminal of a primary winding of an isolated pulse transformer (step S11), full-wave rectifying the signal output from the secondary winding of the pulse transformer (step S12), outputting the full-wave rectified signal to the first terminal (step S13), and drawing current from the first terminal when the transistor is turned off (step S14).

[0203] For example, the present disclosure can be realized as a program for causing a computer (processor) to execute steps included in the operating method. Furthermore, the present disclosure can be realized as a non-transitory computer-readable recording medium, such as a CD-ROM, on which the program is recorded.

[0204] For example, when the present disclosure is realized as a program (software), each step is performed by running the program using hardware resources such as a computer's CPU, memory, input / output circuits, etc. In other words, each step is performed by the CPU acquiring data from memory or input / output circuits, etc., performing calculations, and outputting the calculation results to memory or input / output circuits, etc.

[0205] In the above-described embodiments, each component included in the drive circuit may be configured with dedicated hardware, or may be realized by executing a software program suitable for each component. Each component may be realized by a program execution unit such as a CPU or processor reading and executing a software program recorded on a recording medium such as a hard disk or semiconductor memory.

[0206] Some or all of the functions of the drive circuits according to the above embodiments are typically realized as an LSI, which is an integrated circuit. These may be individually integrated into single chips, or some or all of them may be integrated into a single chip. Furthermore, the integrated circuit is not limited to an LSI, and may be realized using a dedicated circuit or a general-purpose processor. It is also possible to use an FPGA (Field Programmable Gate Array) that can be programmed after LSI manufacturing, or a reconfigurable processor that can reconfigure the connections and settings of circuit cells within the LSI.

[0207] Furthermore, if an integrated circuit technology that can replace LSI emerges due to advances in semiconductor technology or other derivative technologies, it is natural that each component included in the drive circuit may be integrated using that technology.

[0208] In addition, this disclosure also includes forms obtained by making various modifications to the embodiments that a person skilled in the art would think of, and forms realized by arbitrarily combining the components and functions in each embodiment within the scope of the present disclosure.

[0209] (Additional Notes) The above description of the embodiments discloses the following techniques.

[0210] (Technology 1) A drive circuit for driving a transistor having a first terminal which is a gate or a base, a second terminal which is a source or an emitter, and a third terminal which is a drain or a collector, the drive circuit comprising: an isolated pulse transformer; a full-wave rectifier circuit connected to a secondary winding of the pulse transformer; and an extraction circuit connected between the full-wave rectifier circuit and the transistor, and connected to the first terminal and the second terminal, for extracting current from the first terminal when the transistor is turned off, wherein there is a phase difference between a signal input to a terminal at one end of the primary winding of the pulse transformer and a signal input to a terminal at the other end.

[0211] This allows a phase difference between the signal input to one terminal of the primary winding of the pulse transformer and the signal input to the other terminal, and a full-wave rectifier circuit is connected to the secondary winding, so that a duty ratio of greater than 50% can be achieved without causing bias magnetism in the transformer. Furthermore, the full-wave rectifier circuit and the extraction circuit can prevent false ignition of the main bridge circuit.

[0212] Specifically, due to the phase difference, the primary winding can be in one of three states: state A, in which a high signal is input to one terminal and a high signal is input to the other terminal; state B, in which a high signal is input to one terminal and a low signal is input to the other terminal; state C, in which a low signal is input to one terminal and a low signal is input to the other terminal; and state D, in which a low signal is input to one terminal and a high signal is input to the other terminal. In states B and D, voltages of different polarities are generated in the secondary winding, but because a full-wave rectifier circuit is connected to the secondary winding, the drive circuit can apply a voltage to the transistor regardless of the polarity of the voltage generated in the secondary winding (in other words, in either state B or D). For example, if a voltage can be applied to a transistor only in states B and D among states A, B, C, and D, a maximum duty ratio of only 50% can be realized, but if a voltage can be applied to a transistor in both states B and D among states A, B, C, and D, various duty ratios can be realized, and therefore a duty ratio greater than 50% can be realized.

[0213] Depending on the configuration of a circuit that includes a transistor driven by a drive circuit, when the transistor is turned off, current generated by the parasitic capacitance of the transistor may flow from the gate of the transistor into the drive circuit, which may cause the transistor to erroneously fire. In contrast, in the present disclosure, a drain circuit is provided to drain current from the gate of the transistor when the transistor is turned off, which prevents erroneous firing of the transistor and enables high-speed turn-off and turn-on.

[0214] (Technology 2) The drive circuit according to Technology 1, wherein the extraction circuit includes: a first circuit that generates a voltage difference between the output voltage of the full-wave rectifier circuit and a terminal-to-terminal voltage between the first terminal and the second terminal; and a second circuit that brings the output voltage or the terminal-to-terminal voltage of the full-wave rectifier circuit closer to the voltage of the second terminal based on the output voltage, the terminal-to-terminal voltage, or the voltage difference of the full-wave rectifier circuit.

[0215] According to this, the output voltage of the full-wave rectifier circuit or the voltage between the terminals can be made to approach the voltage at the second terminal of the transistor by the extraction circuit, thereby preventing erroneous firing of the transistor.

[0216] (Technology 3) A drive circuit according to Technology 2, in which, when the inter-terminal voltage is Vgs, the output voltage of the full-wave rectifier circuit is Vo2, a first threshold voltage set for the second circuit is Vth1, and the voltage of the second terminal is Vs, the second circuit brings Vo2 or Vgs closer to Vs when Vgs-Vo2>Vth1.

[0217] This makes it possible to prevent erroneous firing of the transistor when Vgs-Vo2 exceeds Vth1, that is, when the absolute value of the voltage generated in the secondary winding becomes small and the transistor turns off.

[0218] (Technology 4) The drive circuit according to Technology 2, wherein the second circuit brings the inter-terminal voltage closer to the voltage of the second terminal when the output voltage of the full-wave rectifier circuit is smaller than a predetermined value and the inter-terminal voltage is larger than the predetermined value.

[0219] This makes it possible to prevent erroneous firing of the transistor when the output voltage of the full-wave rectifier circuit is smaller than a predetermined value and the voltage between the terminals is larger than a predetermined value, that is, when the absolute value of the voltage generated in the secondary winding becomes small and the transistor turns off.

[0220] (Technology 5) The drive circuit according to any one of Technologies 2 to 4, wherein the extraction circuit further includes a third circuit, and when Vo2 - VT2 > Vth2, the third circuit causes the second circuit to bring Vo2 closer to Vs, where Vo2 is the output voltage of the full-wave rectifier circuit, Vth2 is a threshold voltage set for the third circuit, Vs is the voltage of the second terminal, and VT2 is a value obtained by subtracting Vs from the higher of the voltages at the terminal at one end and the terminal at the other end of the secondary winding of the pulse transformer.

[0221] According to this, by monitoring the voltage at both ends of the terminals of the secondary winding of the pulse transformer and comparing it with the output voltage of the full-wave rectifier circuit, the operation of the extraction circuit can be started according to the voltage at both ends of the terminals of the secondary winding of the pulse transformer.

[0222] (Technology 6) The drive circuit according to Technology 2, further comprising a fourth circuit, wherein when the output voltage of the full-wave rectifier circuit is Vo2, a threshold voltage set for the fourth circuit is Vth3, the voltage of the second terminal is Vs, and a value obtained by subtracting Vs from the lower of the voltages at one terminal and the other terminal of the secondary winding of the pulse transformer is VT2', the fourth circuit causes the second circuit to bring Vo2 closer to Vs when VT2'>Vth3.

[0223] According to this, by monitoring the voltage at both ends of the terminals of the secondary winding of the pulse transformer and comparing it with the output voltage of the full-wave rectifier circuit, the operation of the extraction circuit can be started according to the voltage at both ends of the terminals of the secondary winding of the pulse transformer.

[0224] (Technology 7) The drive circuit according to any one of Technologies 2 to 6, wherein the first circuit is a circuit consisting of a resistor, a diode, or a series circuit of a resistor and a diode.

[0225] In this way, the first circuit can be realized.

[0226] (Technology 8) A drive circuit according to any one of technologies 1 to 7, wherein the full-wave rectifier circuit includes two switches connected in series to form a full-bridge circuit, and a node between the two switches is connected to one terminal of a secondary winding of the pulse transformer.

[0227] In this way, the full-wave rectifier circuit may include two switches.

[0228] (Technology 9) The drive circuit according to Technology 8, wherein the two switches are turned on when the transistor is turned off.

[0229] This allows the two switches to be turned on when the transistor is turned off, making it possible to bring the output voltage of the full-wave rectifier circuit closer to the voltage at the second terminal of the transistor, thereby reliably preventing false firing of the transistor.

[0230] (Technology 10) A method for operating a drive circuit for driving a transistor having a first terminal which is a gate or a base, a second terminal which is a source or an emitter, and a third terminal which is a drain or a collector, the method comprising: inputting signals having a phase difference to one terminal and the other terminal of a primary winding of an isolated pulse transformer; full-wave rectifying a signal output from a secondary winding of the pulse transformer; outputting the full-wave rectified signal to the first terminal; and drawing current from the first terminal when the transistor is turned off.

[0231] This makes it possible to provide an operating method that can realize a duty ratio greater than 50% without causing asymmetric magnetism in the transformer and that can prevent erroneous firing of the main bridge circuit.

[0232] The present disclosure is applicable to drive circuits for driving transistors such as MOSFETs, GaN FETs or IGBTs.

[0233] 1, 2, 3, 4, 5, 6 Drive circuit 10 Phase control circuit 21, 22, 23, 24 Full-wave rectifier circuit 31, 32, 33, 34, 35, 36 Extraction circuit Bat Power supply C1, C2, C10, Cgs Capacitor Cgd Parasitic capacitance D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11 Diode L1 Primary winding L2 Secondary winding MH, ML, Q1, Q2, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13 Switch R1, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27 Resistor T1 Pulse transformer t1, t2, t3, t4, t5, t6 terminals

Claims

1. A drive circuit for driving a transistor having a first terminal which is a gate or base, a second terminal which is a source or emitter, and a third terminal which is a drain or collector, comprising: an isolated pulse transformer; a full-wave rectifier circuit connected to a secondary winding of the pulse transformer; and a pull-out circuit connected between the full-wave rectifier circuit and the transistor, connected to the first terminal and the second terminal, for pulling out current from the first terminal when the transistor is turned off, wherein there is a phase difference between a signal input to one terminal of the primary winding of the pulse transformer and a signal input to the other terminal.

2. The drive circuit of claim 1, wherein the extraction circuit comprises: a first circuit that generates a voltage difference between the output voltage of the full-wave rectifier circuit and a terminal-to-terminal voltage between the first terminal and the second terminal; and a second circuit that brings the output voltage or the terminal-to-terminal voltage of the full-wave rectifier circuit closer to the voltage of the second terminal based on the output voltage, the terminal-to-terminal voltage, or the voltage difference of the full-wave rectifier circuit.

3. The drive circuit of claim 2, wherein, when the inter-terminal voltage is Vgs, the output voltage of the full-wave rectifier circuit is Vo2, a first threshold voltage set for the second circuit is Vth1, and the voltage of the second terminal is Vs, the second circuit brings Vo2 or Vgs closer to Vs when Vgs-Vo2>Vth1.

4. The drive circuit according to claim 2, wherein the second circuit brings the inter-terminal voltage closer to the voltage at the second terminal when the output voltage of the full-wave rectifier circuit is smaller than a predetermined value and the inter-terminal voltage is larger than the predetermined value.

5. The drive circuit according to claim 2, wherein the extraction circuit further comprises a third circuit, wherein, when Vo2 - VT2 > Vth2, the output voltage of the full-wave rectifier circuit is Vo2, a threshold voltage set for the third circuit is Vth2, the voltage of the second terminal is Vs, and a value obtained by subtracting Vs from the higher of the voltages at the one terminal and the other terminal of the secondary winding of the pulse transformer is VT2, the third circuit causes the second circuit to bring Vo2 closer to Vs when Vo2 - VT2 > Vth2.

6. The drive circuit according to claim 2, wherein the extraction circuit further comprises a fourth circuit, wherein, when VT2'>Vth3, the output voltage of the full-wave rectifier circuit is Vo2, a threshold voltage set for the fourth circuit is Vth3, the voltage of the second terminal is Vs, and a value obtained by subtracting Vs from the lower of the voltages at the one terminal and the other terminal of the secondary winding of the pulse transformer is VT2', the fourth circuit causes the second circuit to bring Vo2 closer to Vs.

7. The drive circuit according to claim 2, wherein the first circuit is a circuit made up of a resistor, a diode, or a series circuit of a resistor and a diode.

8. The drive circuit according to any one of claims 1 to 7, wherein the full-wave rectifier circuit includes two switches connected in series to form a full-bridge circuit, and a node between the two switches is connected to a terminal at one end of a secondary winding of the pulse transformer.

9. The drive circuit according to claim 8, wherein the two switches are in an on state when the transistor is turned off.

10. A method of operating a drive circuit for driving a transistor having a first terminal which is a gate or base, a second terminal which is a source or emitter, and a third terminal which is a drain or collector, comprising the steps of: inputting signals having a phase difference to one end terminal and the other end terminal of a primary winding of an isolated pulse transformer; full-wave rectifying a signal output from a secondary winding of the pulse transformer; outputting the full-wave rectified signal to the first terminal; and drawing current from the first terminal when the transistor is turned off.

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