Circuit board

Abstract

A circuit board (10) is provided with: a multilayer circuit in which an insulating layer (41) and wiring layers are alternately stacked; and a pad (21) disposed on an upper layer of the multilayer circuit and forming a bonding part (13a) for electrical connection between the pad and end parts (11c, 11a) of an electronic component (11). The wiring layers include a first wiring layer (22) and a second wiring layer (23), and the insulating layer has vias, the vias including a first via (31a) that electrically connects the pad and the first wiring layer, and a second via (31b) that electrically connects the first wiring layer and the second wiring layer. The pad includes a first pad (21a) connected to the first via, and a second pad (21b) not connected to the first via. The first via is disposed in a position overlapping the bonding part on the first pad in the stacking direction, and the second via is provided in a position spaced apart from a position on one end part (11c) side of the electronic component close to at least the position of the first via, toward a position on the other end part (11a) side of the electronic component.

Description

circuit board

[0001] The present invention relates to a circuit board.

[0002] In order to meet the demand for autonomous driving of vehicles, on-board control devices are required to be miniaturized in order to achieve high-density packaging. Furthermore, along with miniaturization, reliability of the joints of the control devices is also required. For example, Patent Literature 1 discloses a circuit board in which vias other than the first via are shifted in a planar direction to improve the connection reliability of the joints.

[0003] Japanese Patent Application Laid-Open No. 2005-123332

[0004] The technology described in Patent Document 1 does not take into consideration the inward shift in the longitudinal direction to achieve miniaturization, nor the amount of shift in the stacking direction to prevent overlapping, which also improves the reliability of other solder joints, and therefore the wiring area expands, resulting in the problem of being unable to accommodate miniaturization.

[0005] a first via electrically connecting the pad to the first wiring layer and a second via electrically connecting the first wiring layer to the second wiring layer; a first pad connected to the first via and a second pad not connected to the first via; the first via is positioned in a stacking direction so as to overlap the joint on the first pad; and the second via is positioned at a position away from a position on one end of the electronic component that is closer to the position of the first via, the second via being positioned further away from a position on the other end of the electronic component than a position on one end of the electronic component that is closer to the position of the first via.

[0006] According to the present invention, it is possible to provide a circuit board that achieves both improved reliability of solder joints and miniaturization.

[0007] 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention; 2 is a plan view of a circuit board according to an embodiment of the present invention; 3 is a first modification of FIG. 2;

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The following description and drawings are examples for explaining the present invention, and some omissions and simplifications have been made as appropriate for clarity of explanation. The present invention can be implemented in various other forms. Unless otherwise specified, each component may be singular or plural.

[0009] In order to facilitate understanding of the invention, the position, size, shape, range, etc. of each component shown in the drawings may not represent the actual position, size, shape, range, etc. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings.

[0010] (First embodiment of the present invention and overall configuration) (FIGS. 1 and 2) The electronic control device 1 has a circuit board 10 formed by a multilayer circuit and an electronic component 11 electrically connected to the circuit board 10. The circuit board 10 has a multilayer circuit in which insulating layers 41 and wiring layers are alternately stacked. The wiring layers include a first wiring layer 22 and a second wiring layer 23. Note that while FIG. 1 omits explanation of the third wiring layer and below, a configuration in which a wiring layer and a core layer are formed below the third wiring layer may also be used. Pads 21a and 21b that electrically connect to the ends of the electronic component 11 are provided on the surface of the circuit board 10.

[0011] Each insulating layer 41 may be, for example, a glass epoxy substrate made of woven glass fiber and impregnated with epoxy resin, and each wiring layer may be, for example, a wiring pattern made of copper foil formed on the surface of the insulating layer 41, and is formed through a well-known process.

[0012] Pads 21a and 21b are made of, for example, copper foil formed on one surface of insulating layer 41, and electronic component 11 is joined to the upper surface thereof using a joining material 13 such as solder by a well-known method. Electrodes 12 formed on ends 11a and 11c of electronic component 11 are solder-joined to the upper surfaces of pads 21a and 21b via solder fillets of joining material 13. Note that electrodes 12 of electronic component 11 need only be formed on the bottom and side surfaces of at least ends 11a and 11c of electronic component 11.

[0013] The circuit board 10 has a first via 31a, a second via 31b, a third via 32a, and a fourth via 32b between each insulating layer 41 and the wiring layers 22, 23. The first via 31a and the third via 32a electrically connect the first wiring layer 22 to the pads 21a, 21b. The second via 31b and the fourth via 32b electrically connect the first wiring layer 22 to the second wiring layer 23. The first pad 21a is electrically connected directly or indirectly to the first via 31a and the second via 31b. The second pad 21b is electrically connected directly or indirectly to the third via 32a and the fourth via 32b.

[0014] The first via 31a electrically connects the first pad 21a and the first wiring layer 22. The second via 31b electrically connects the first wiring layer 22 and the second wiring layer 23. The third via 32a electrically connects the second pad 21b and the first wiring layer 22. The fourth via 32b electrically connects the first wiring layer 22 and the second wiring layer 23. Note that the reference numerals of the vias connecting the second wiring layer 23 and the third wiring layer are not shown, but in FIG. 1 , this via is located at a position overlapping the second via 31b or the fourth via 32b in the stacking direction.

[0015] The ends 11a and 11c of the electronic component 11 are electrically connected to the pads 21a and 21b via the electronic component electrodes 12 and the bonding material 13, and the bonding portions 13a are provided at the connection portions. In FIG. 1, the bonding portions 13a are provided between the pads 21a and 21b and the bonding material 13.

[0016] The first pad 21a is disposed on the first via 31a. The first via 31a is located approximately in the center of the first pad 21a, and is disposed in a position overlapping in the stacking direction with the electrodes on the bottom and side surfaces of the end 11c of the electronic component 11. The second via 31b is provided at a position farther toward the other end 11a of the electronic component 11 than a position on the one end 11c of the electronic component 11 that is at least closest to the position of the first via 31a.

[0017] The third via 32a electrically connected to the second pad 21b is provided at a position away from the center position of the bonding portion 13a on the second pad 21b and does not overlap with the bonding portion 13a on the second pad in the stacking direction.

[0018] The direction in which the second via 31b is moved away from the position of the first via 31a is the same as the direction in which the third via 32a is moved away from the position of the bonding portion 13a on the second pad 21b. Note that the distances (movement amounts) by which the second via 31b and the third via 32a are moved away from their respective reference positions are not necessarily the same.

[0019] In this way, by moving the second via 31b to a position farther away from the one end 11c of the electronic component 11, which is closer to the position of the first via 31a, toward the other end 11a of the electronic component 11, the wiring area on the circuit board 10 can be reduced, and the electronic control device 1 can be made smaller.

[0020] The linear expansion coefficient of the vias and pads (both made of copper) is 16.8×10-6 / K, and the linear expansion coefficient of the insulating layer 120 (glass epoxy resin) is 40.0×10-6 / K. Therefore, when the temperature of the insulating layer 41, pads, and vias of the circuit board 10 rises in the thickness direction of the circuit board 10 (the direction perpendicular to the board surface), the pads and vias shrink relative to the insulating layer 120, causing tensile stress in the solder fillets of the bonding material 13 located above the pads. Furthermore, if the temperature of the circuit board 10 repeatedly rises and falls, the solder fillets may gradually fatigue, resulting in cracks in the solder fillets.

[0021] For example, in a conventional configuration in which the first via 31a and the second via 31b are arranged overlapping in the thickness direction of the circuit board 10, the thermal expansion coefficients of the insulating layer 41 of the circuit board 10 and the vias are different, and as the temperature changes, the first via 31a and the second via 31b, which have a smaller thermal expansion coefficient, cannot follow the deformation of the insulating layer 41, which has a larger thermal expansion coefficient, and as a result, the first pad 21a is deformed in an up and down direction, which increases the strain of the solder joint 13a on the first pad 21a and reduces the joint reliability.

[0022] In contrast, the second via 31b of the circuit board 10 in one embodiment of the present invention is provided at a position farther toward the other end of the electronic component 11 than the position of one end of the electronic component 11 that is closer to the position of the first via 31a. This prevents or reduces the placement of a member (via) with a low thermal expansion coefficient at a position that overlaps with the first pad 21a in the thickness direction of the circuit board 10, and reduces the force that pulls the first pad 21a up and down by the first via 31a and the second via 31b, thereby improving the reliability of the solder joint 13a in the first pad 21a.

[0023] The second via 31b is provided at a position that does not overlap with the bonding portion 13a on the second pad 21b in the stacking direction. Also, as described above, the third via 32a electrically connected to the second pad 21b is provided at a position that does not overlap with the bonding portion 13a on the second pad 21b in the stacking direction.

[0024] By doing this, tilting of the electronic component 11 due to a via with a small thermal expansion coefficient deforming the second pad 21b in the vertical direction during temperature changes, which previously occurred when the solder joint 13a of the second via 31b and the second pad 21b overlapped in the stacking direction, or when the solder joint 13a of the third via 32a and the second pad 21b overlapped in the stacking direction, can be prevented, and a decrease in solder joint reliability on the other end 11a side can be suppressed, thereby improving solder joint reliability.

[0025] Here, the electronic component 11 can be, for example, a chip component such as a chip resistor or a chip capacitor as an EC. Regarding the size of each component described in the present invention, for example, the electronic component 11 has a longitudinal length of 0.6 mm, a height of 0.23 mm, and a lateral length of 0.3 mm, the longitudinal and lateral lengths of the first pad are 0.35 mm, the longitudinal length of the second pad is 0.76 mm, and the lateral length is 0.35 mm, and the via diameter is 0.1 mm, but the sizes are not limited to these.

[0026] In recent years, electronic components have been miniaturized to improve packaging density on circuit boards. When the electronic component 11 is miniaturized, shifting the second via 31b away from the electronic component 11 (starting from one end of the electronic component 11 near the first pad 21a and moving away from the other end of the electronic component 11) to improve the reliability of the solder joint 13a of the first pad 21a would result in an expansion of the wiring area, making it impossible to meet the demand for miniaturization. On the other hand, when the electronic component 11 is miniaturized, the reliability of the solder joint 13a of other pads (e.g., the second pad 21b) may be reduced depending on the shift direction and amount of the shift of the second via 31b, which imposes restrictions on the shift direction and amount of the shift of the second via 31b. For example, if the second via 31b is shifted in the short-side direction of the electronic component 11, the electronic component 11 will tilt in the shift direction of the second via 31b, reducing the reliability of the solder joint 13a.

[0027] Therefore, in one embodiment of the present invention, the circuit board 10 has the second via 31b located further toward the other end of the electronic component 11 than the position of the first via 31a at one end of the electronic component 11, and also located at a position that does not overlap with the joint 13a on the second pad 21b in the stacking direction.This makes it possible to improve the reliability of the solder joint 13a while preventing the wiring area from expanding even when the electronic component 11 is made smaller.

[0028] (First Modification) (FIG. 3) The second via 31b is provided at a position away from the position of the first via 31a along the longitudinal direction of the electronic component 11. The fourth via 32b is provided at a position away from the position of the third via 32a toward the arrangement position of the electronic component 11. This reduces deformation of the second pad 21b that occurs when the third via 32a and the fourth via 32b overlap, and further improves the reliability of the bonding portion 13a.

[0029] (Second variant) (Figure 4) The configuration shown in Figure 3, for example, by arranging the second wiring layer 23 to which the second via 31b is connected and the second wiring layer 23 to which the fourth via 32b is connected close to each other along the longitudinal direction of the electronic component 11 and offsetting them in the short direction of the electronic component 11 so that they do not overlap, not only can the reliability of the joint 13a be improved but also the electronic control device 1 can be further miniaturized in the longitudinal direction of the electronic component 11.

[0030] (Third Modification) (FIG. 5) In the circuit board 10 described above, a via provided further below the second wiring layer 23 will be described. The second wiring layer 23 and the third wiring layer 24 are electrically connected by the fifth via 31c and the sixth via 32c. The fifth via 31c is provided so as to overlap the second via 31b in the stacking direction. The sixth via 32c does not overlap the fourth via 32b in the stacking direction. In other words, of the third via 32a, the fourth via 32b, and the sixth via 32c that directly or indirectly connect to the second pad 21b, only the fourth via 32b is provided at a position away from the third via 32a and the sixth via 32c toward the position where the electronic component 11 is disposed. This reduces deformation of the second pad 21b and improves the reliability of the solder joint 13a.

[0031] According to the embodiment of the present invention described above, the following advantageous effects are achieved.

[0032] (1) A circuit board 10 electrically connected to an electronic component 11 includes a multilayer circuit in which insulating layers 41 and wiring layers are alternately stacked, and a pad 21 disposed on the surface of the multilayer circuit and electrically connected to an end of the electronic component 11 by forming a joint 13a with the end of the electronic component 11. The wiring layer includes a first wiring layer 22 and a second wiring layer 23, the insulating layer 41 includes vias, the vias including a first via 31a electrically connecting the pad 21 to the first wiring layer 22 and a second via 31b electrically connecting the first wiring layer 22 to the second wiring layer 23, and the pad 21 includes a first pad 21a connected to the first via 31a and a second pad 21b not connected to the first via 31a. The first via 31a is disposed in a position overlapping the bonding portion 13a on the first pad 21a in the stacking direction, and the second via 31b is provided in a position that is farther away from a position on one end side of the electronic component 11 that is closer to the position of at least the first via 31a, toward a position on the other end side of the electronic component 11. In this way, it is possible to provide a circuit board 10 that achieves both improved reliability of the solder bonding portion 13a and miniaturization.

[0033] (2) The first vias 31a are arranged in positions that overlap in the stacking direction with the electrodes 12 on the bottom and side surfaces of the end portions of the electronic components 11. This arrangement makes it possible to provide a circuit board 10 that achieves both improved reliability of the solder joints 13a and miniaturization.

[0034] (3) The second via 31b does not overlap the bonding portion 13a on the second pad 21b in the stacking direction, which improves the reliability of the solder joint.

[0035] (4) The second via 31b is provided at a position away from the first via 31a along the longitudinal direction of the electronic component 11. This can improve the reliability of the solder joint.

[0036] (5) The vias include a third via 32a electrically connected to the second pad 21b, and the third via 32a does not overlap the bonding portion 13a of the second pad 21b in the stacking direction, thereby improving the reliability of the solder joint.

[0037] (6) The vias include a third via 32a electrically connected to the second pad 21b, and the third via 32a does not overlap the bonding portion 13a of the second pad 21b in the stacking direction, and the direction in which the second via 31b is spaced apart from the position of the first via 31a and the direction in which the third via 32a is spaced apart from the position of the bonding portion 13a on the second pad 21b are the same. This can improve the reliability of the solder joint.

[0038] (7) The vias include a third via 32a that electrically connects the second pad 21b and the first wiring layer 22, and a fourth via 32b that electrically connects the first wiring layer 22 and the second wiring layer 23, the third via 32a does not overlap the bonding portion 13a of the second pad 21b in the stacking direction, and the fourth via 32b is provided at a position away from the position of the third via 32a toward the position of the electronic component 11. This can improve the reliability of the solder joint.

[0039] The present invention is not limited to the above-described embodiments, and various modifications and combinations of other configurations are possible without departing from the spirit of the present invention. Furthermore, the present invention is not limited to those having all of the configurations described in the above-described embodiments, and includes those in which some of the configurations are omitted.

[0040] REFERENCE SIGNS LIST 1 Electronic control device 10 Circuit board 11 Electronic component 11a Outer end (second pad side) 11c Outer end (first pad side) 12 Electronic component electrode portion 13 Bonding material 13a Bonding portion 21 Pad 21a First pad 21b Second pad 22 First wiring layer 23 Second wiring layer 24 Third wiring layer 31a First via 31b Second via 32a Third via 32b Fourth via 33 Fifth via 41 Insulating layer

Claims

1. A circuit board for electrically connecting to an electronic component, comprising: a multilayer circuit in which insulating layers and wiring layers are alternately stacked; and a pad arranged on a surface of the multilayer circuit and forming a joint between an end of the electronic component and electrically connecting the end of the electronic component, wherein the wiring layer has a first wiring layer and a second wiring layer, the insulating layer has a via, wherein the via has a first via electrically connecting the pad and the first wiring layer and a second via electrically connecting the first wiring layer and the second wiring layer, the pad has a first pad connected to the first via and a second pad not connected to the first via, the first via is arranged at a position overlapping the joint on the first pad in the stacking direction, and the second via is provided at a position away from a position on one end of the electronic component that is at least closer to the position of the first via, toward the other end of the electronic component.

2. A circuit board according to claim 1, wherein the first via is arranged at a position overlapping with electrodes on the bottom and side of the end of the electronic component in the stacking direction.

3. A circuit board as described in claim 1, wherein the second via does not overlap the bonding portion on the second pad in the stacking direction.

4. A circuit board according to claim 1, wherein the second via is provided at a position spaced apart from the position of the first via along the longitudinal direction of the electronic component.

5. A circuit board according to claim 1, wherein the vias include a third via electrically connecting to the second pad, and the third via does not overlap the bonding portion of the second pad in the stacking direction.

6. A circuit board as described in claim 1, wherein the vias include a third via electrically connected to the second pad, the third via does not overlap with the joint portion of the second pad in the stacking direction, and the direction in which the second via is positioned away from the position of the first via is the same as the direction in which the third via is positioned away from the position of the joint portion on the second pad.

7. A circuit board as described in claim 1, wherein the vias include a third via electrically connecting the second pad and the first wiring layer, and a fourth via electrically connecting the first wiring layer and the second wiring layer, the third via does not overlap the joint portion of the second pad in the stacking direction, and the fourth via is provided at a position away from the position of the third via toward the position of the electronic component.

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