Intelligent power module, electronic device, and control method for intelligent power module

Abstract

Provided are an intelligent power module, an electronic device, and a control method for an intelligent power module. The intelligent power module comprises a signal input terminal, a power switch device and a first integrated circuit. The first integrated circuit comprises a first detection circuit and a first switching circuit, wherein the first detection circuit is configured to receive a PWM signal, and detect a current change region according to the PWM signal, and the current change region comprises a first current region and a second current region; and the first switching circuit is configured to: receive a first detection result and the PWM signal; switch a gate resistor to a first resistance mode when the first detection result indicates the first current region; or switch the gate resistor to a second resistance mode when the first detection result indicates the second current region.

Description

Intelligent power module, electronic device, and control method of intelligent power module

[0001] This application claims priority to Chinese patent application No. 202311113630.5 filed on August 30, 2023; priority to Chinese patent application No. 202310948246.0 filed on July 28, 2023; and priority to Chinese patent application No. 202310944702.4 filed on July 28, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of power semiconductor technology, and in particular to an intelligent power module, an electronic device, and a control method for the intelligent power module. Background Art

[0003] Intelligent Power Modules (IPMs), as power switching devices, are commonly used in three-phase inverter circuits for electronic products such as household appliances (such as variable-frequency air conditioners), industrial machinery, and automotive products. Furthermore, IPMs can be applied to a wide range of electronic products.

[0004] Summary of the Invention

[0005] On the one hand, an intelligent power module is provided. The intelligent power module includes a signal input terminal, a power switching device, and a first integrated circuit. The signal input terminal is configured to receive a pulse width modulation (PWM) signal input by an external controller. The first integrated circuit includes a first detection circuit and a first switching circuit. The first detection circuit is electrically connected to the signal input terminal and is configured to receive the PWM signal transmitted by the signal input terminal and detect a current change region based on the PWM signal. The current change region includes a first current region within a preset threshold range or a second current region outside the preset threshold range. The first switching circuit is electrically connected to the signal input terminal, the first detection circuit, and the power switch device, respectively, and is configured to: receive a first detection result of the first detection circuit and the PWM signal transmitted by the signal input terminal; when the first detection result is in the first current range, switch the gate resistor to a first resistance mode, and control the power switch device to be turned on or off according to the PWM signal in the first resistance mode; or, when the first detection result is in the second current range, switch the gate resistor to a second resistance mode, and control the power switch device to be turned on or off according to the PWM signal in the second resistance mode. The resistance value of the gate resistor in the first resistance mode is greater than the resistance value of the gate resistor in the second resistance mode.

[0006] In some embodiments, the intelligent power module further includes a signal output terminal, and the signal input terminal is further configured to transmit an interface (I / F) signal. The first integrated circuit includes a second detection circuit, a second switching circuit, an interface control circuit, an interface execution circuit, and a PWM signal input circuit. The second detection circuit is electrically connected to the signal output terminal and configured to detect the level signal at the signal output terminal and transmit a second detection result to the second switching circuit. The second switching circuit is electrically connected to the second detection circuit and the signal input terminal, respectively, and is configured to: switch connection to the interface control circuit or the PWM signal input circuit based on the second detection result; and receive the I / F signal or the PWM signal transmitted through the signal input terminal and transmit the I / F signal to the interface control circuit or the PWM signal to the PWM signal input circuit. The interface control circuit is electrically connected to the second switching circuit and the interface execution circuit, respectively, and is configured to, upon receiving the I / F signal, control the interface execution circuit to perform corresponding processing based on the I / F signal. The interface execution circuit is configured to perform corresponding processing based on the I / F signal. The PWM signal input circuit is electrically connected to the second switching circuit and the power switching device respectively, and is configured to control the power switching device to be turned on or off when receiving the PWM signal.

[0007] In some embodiments, the interface execution circuit includes at least one of a first subcircuit, a second subcircuit, or a third subcircuit. The first subcircuit is configured to switch the gate resistor according to a gate resistor switching signal. The second subcircuit is configured to set a threshold corresponding to a protection function of a protection circuit according to a circuit protection setting signal, wherein the protection function of the protection circuit includes at least one of overheat protection, overcurrent protection, or undervoltage protection. The third subcircuit is configured to detect temperature information of the intelligent power module according to a temperature monitoring signal.

[0008] In some embodiments, the intelligent power module further includes a signal output terminal. The signal input terminal is further configured to transmit an I / F signal, wherein the I / F signal is configured to request product information of the intelligent power module. The product information includes at least one of manufacturing information, circuit information, or test information of the intelligent power module. The first integrated circuit includes a second detection circuit, a second switching circuit, a storage circuit, and a PWM signal input circuit. The second detection circuit is electrically connected to the signal output terminal and is configured to detect the level signal of the signal output terminal and transmit a second detection result to the second switching circuit. The second switching circuit is electrically connected to the second detection circuit and the signal input terminal, respectively. The second switching circuit is configured to: switch connection to the storage circuit or the PWM signal input circuit based on the second detection result; and receive the I / F signal or the PWM signal transmitted through the signal input terminal and transmit the I / F signal to the storage circuit or transmit the PWM signal to the PWM signal input circuit. The storage circuit is electrically connected to the second switching circuit and is configured to store product information of the intelligent power module, read the corresponding product information according to the I / F signal, and transmit the product information to the external controller in the form of the I / F signal through the signal input terminal. The PWM signal input circuit is electrically connected to the second switching circuit and the power switching device, respectively, and is configured to control the power switching device to be turned on or off when receiving the PWM signal.

[0009] In some embodiments, the first integrated circuit further includes a protection circuit. The protection circuit is electrically connected to the signal output terminal and configured to output a circuit protection signal to the signal output terminal. The second detection circuit is also connected to the protection circuit and configured to transmit the second detection result to the second switching circuit when the protection circuit does not transmit the circuit protection signal.

[0010] In some embodiments, the protection circuit includes a switching transistor. The switching transistor is configured to be turned on upon receiving the circuit protection signal and output the circuit protection signal to the signal output terminal, so that the signal output terminal is in a low-level state, so that the external controller controls the intelligent power module according to the low-level signal of the signal output terminal to protect the circuit.

[0011] In some embodiments, the intelligent power module further includes a pull-up resistor and a power supply. The signal output terminal is connected to one end of the pull-up resistor, and the other end of the pull-up resistor is connected to the power supply, so that when the signal output terminal does not receive the circuit protection signal output by the protection circuit, the signal output terminal is in a high-level state corresponding to the pull-up resistor, so that the external controller controls the high-level state of the signal output terminal to a low-level state. The second switching circuit is further configured to: when the protection circuit does not output the circuit protection signal, when the second detection result is a low-level signal, switch to connect to the interface control circuit or the storage circuit; or, when the second detection result is a high-level signal, switch to connect to the PWM signal input circuit.

[0012] In some embodiments, the I / F signal includes a clock (CLK) signal, a digital input (DI) signal, and a digital output (DO) signal. The signal input terminal includes a U-phase signal input terminal, a V-phase signal input terminal, and a W-phase signal input terminal. The U-phase signal input terminal is configured to receive a U-phase signal or a CLK signal transmitted by the external controller. The V-phase signal input terminal is configured to receive a V-phase signal or transmit a DO signal to the external controller. The W-phase signal input terminal is configured to receive a W-phase signal or a DI signal transmitted by the external controller.

[0013] In some embodiments, the intelligent power module further includes a second integrated circuit. The first integrated circuit and the second integrated circuit are assembled using a lead frame. A power ground terminal of the second integrated circuit is connected to a power ground terminal of the first integrated circuit. The first integrated circuit is a low-voltage integrated circuit, and the second integrated circuit is a high-voltage integrated circuit.

[0014] In another aspect, an electronic device is provided. The electronic device includes the above-mentioned intelligent power module and an external controller. The external controller is electrically connected to the intelligent power module and configured to transmit a PWM signal or an I / F signal to the intelligent power module.

[0015] In another aspect, a control method for an intelligent power module is provided. The intelligent power module includes a signal input terminal, a power switching device, and a first integrated circuit. The signal input terminal is configured to receive a PWM signal input by an external controller. The first integrated circuit includes a first detection circuit and a first switching circuit. The first detection circuit is electrically connected to the signal input terminal. The first switching circuit is electrically connected to the signal input terminal, the first detection circuit, and the power switching device, respectively. The method includes: a first detection circuit receiving a PWM signal transmitted from the external controller to the intelligent power module via the signal input terminal, and detecting a current variation region based on the PWM signal; the current variation region including a first current region within a preset threshold range and a second current region outside the preset threshold range; a first switching circuit receiving a first detection result of the first detection circuit and a PWM signal transmitted from the external controller to the intelligent power module via the signal input terminal; when the first detection result is within the first current range, switching the gate resistor to a first resistance mode, and controlling the power switch device to be turned on or off according to the PWM signal in the first resistance mode; or, when the first detection result is within the second current range, switching the gate resistor to a second resistance mode, and controlling the power switch device to be turned on or off according to the PWM signal in the second resistance mode. The resistance value of the gate resistor in the first resistance mode is greater than the resistance value of the gate resistor in the second resistance mode.

[0016] In yet another aspect, a control method for an intelligent power module is provided. The method is applied to an external controller and includes: transmitting an I / F signal or a PWM signal to a signal input terminal of the intelligent power module; the I / F signal is configured to control an I / F execution circuit of the intelligent power module to perform corresponding processing on the I / F signal; and the PWM signal is configured to control the on / off switching of a power switching device.

[0017] In yet another aspect, a control method for an intelligent power module is provided. The method is applied to an external controller and includes: transmitting an I / F signal to a signal input terminal of the intelligent power module, the I / F signal configured to request product information of the intelligent power module, the product information including at least one of manufacturing information, circuit information, or test information of the intelligent power module; and receiving the product information read by a storage circuit of the intelligent power module based on the I / F signal and transmitted via the signal input terminal in the form of the I / F signal.

[0018] In some embodiments, the method further includes: before transmitting the I / F signal to the signal input terminal, when the signal output terminal of the intelligent power module is in a high level state, controlling the high level state of the signal output terminal to a low level state. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] FIG1 is a structural diagram of an intelligent power module according to some embodiments;

[0020] FIG2 is a graph showing collector current variation over time according to some embodiments;

[0021] FIG3 is a graph showing the voltage between the collector and the emitter changing with time according to some embodiments;

[0022] FIG4 is a graph showing power consumption of a power switch device over time according to some embodiments;

[0023] FIG5 is a waveform diagram of a collector current change rate according to some embodiments;

[0024] FIG6 is another waveform diagram of the collector current change rate according to some embodiments;

[0025] FIG7 is a waveform diagram of a voltage change rate between a collector and an emitter according to some embodiments;

[0026] FIG8 is another waveform diagram of the voltage change rate between the collector and the emitter according to some embodiments;

[0027] FIG9 is a schematic diagram illustrating noise generation of electromagnetic interference according to some embodiments;

[0028] FIG10 is a graph showing the rate of change of collector-emitter voltage as collector current varies according to some embodiments;

[0029] FIG11 is a graph showing the rate of change of collector-emitter voltage as gate resistance varies according to some embodiments;

[0030] FIG12 is a structural diagram of another intelligent power module according to some embodiments;

[0031] FIG13 is a structural diagram of another intelligent power module according to some embodiments;

[0032] FIG14 is a schematic diagram of obtaining interphase voltages of multiple phase signals based on interphase signals according to some embodiments;

[0033] FIG15 is a block diagram of a comparison circuit according to some embodiments;

[0034] FIG16 is a block diagram of a logic circuit according to some embodiments;

[0035] FIG17 is a structural diagram of a first switching circuit according to some embodiments;

[0036] FIG18 is another structural diagram of a first switching circuit according to some embodiments;

[0037] FIG19 is a structural diagram of another intelligent power module according to some embodiments;

[0038] FIG20 is a structural diagram of another intelligent power module according to some embodiments;

[0039] FIG21 is a structural diagram of another intelligent power module according to some embodiments;

[0040] FIG22 is a structural diagram of another intelligent power module according to some embodiments;

[0041] FIG23 is a timing diagram of an intelligent power module according to some embodiments;

[0042] FIG24 is another timing diagram of an intelligent power module according to some embodiments;

[0043] FIG25 is a structural diagram of another intelligent power module according to some embodiments;

[0044] FIG26 is a structural diagram of another intelligent power module according to some embodiments;

[0045] FIG27 is a structural diagram of another intelligent power module according to some embodiments;

[0046] FIG28 is a structural diagram of yet another intelligent power module according to some embodiments;

[0047] FIG29A is a structural diagram of another intelligent power module according to some embodiments;

[0048] FIG29B is a structural diagram of yet another intelligent power module according to some embodiments;

[0049] FIG29C is a structural diagram of yet another intelligent power module according to some embodiments;

[0050] FIG30 is a structural diagram of an electronic device according to some embodiments;

[0051] FIG31 is a block diagram of another electronic device according to some embodiments;

[0052] FIG32 is a flow chart of a method for controlling an intelligent power module according to some embodiments;

[0053] FIG33 is a flow chart of another method for controlling an intelligent power module according to some embodiments;

[0054] FIG34 is a flowchart of another method for controlling an intelligent power module according to some embodiments;

[0055] FIG35 is a flowchart of another method for controlling an intelligent power module according to some embodiments;

[0056] FIG36 is a flowchart of another method for controlling an intelligent power module according to some embodiments;

[0057] FIG37 is a flowchart of yet another method for controlling an intelligent power module according to some embodiments. DETAILED DESCRIPTION

[0058] The following will be combined with the accompanying drawings to clearly and completely describe some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0059] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0060] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of some embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0061] When describing some embodiments, the word "connected" and its derivatives may be used. The term "connected" should be understood broadly. For example, "connected" can mean fixed, removable, or integrated; it can be directly connected or indirectly connected through an intermediary. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0062] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0063] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0064] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0065] As used herein, "parallel," "perpendicular," and "equal" include the stated conditions and conditions approximating the stated conditions within an acceptable range of deviation as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0066] Typically, an Intelligent Power Module (IPM) consists of an insulated gate bipolar transistor (IGBT) with high switching speed and low power consumption, a gate driver, and a protection circuit. In a three-phase inverter circuit, the IPM serves as an interface with the outside world, including signal input terminals for pulse width modulation (PWM) to drive the motor and signal output terminals for transmitting protection actions. An external controller (such as a microcontroller unit (MCU)) can use the signal input terminals to input PWM signals to the IPM to control the conduction of the IGBT.

[0067] Users generally demand low-loss IPMs. The loss of an IPM is proportional to its switching speed. For example, the faster the IPM's switching speed, the lower the IPM's loss, but the IPM's electromagnetic interference (EMI) noise level also increases. Current low-loss IPMs are noisy and cannot meet these requirements. In this case, users are forced to choose a low-noise IPM with higher loss, resulting in poor IPM performance.

[0068] To address the above issues, some embodiments of the present disclosure provide an intelligent power module that provides a first detection circuit and a first switching circuit to switch between different gate resistors, thereby achieving low-loss requirements for different applications without generating significant noise.

[0069] FIG1 is a block diagram of an intelligent power module (IPM) according to some embodiments. The IPM 100 can be applied to a three-phase inverter circuit. As shown in FIG1 , the IPM 100 includes a signal input terminal 110 , a first integrated circuit (IC) 120 , and a power switch device 130 .

[0070] The input end of the signal input terminal 110 is connected to an external controller (such as an MCU), and the output end is electrically connected to the first detection circuit 121 and the first switching circuit 122, and is configured to receive a PWM signal output by the external controller. The signal input terminal 110 may include the original signal input terminal of the IPM 100. For example, the signal input terminal 110 includes at least one of a U-phase signal input terminal, a V-phase signal input terminal, or a W-phase signal input terminal. The PWM signal may correspond to at least one of a U-phase signal, a V-phase signal, or a W-phase signal. In combination with the U-phase signal, the V-phase signal, and the W-phase signal, noise reduction processing and low-loss processing can be performed during the driving process of the power switching device 130. Here, the U-phase signal, the V-phase signal, and the W-phase signal are signals input to the U-phase signal input terminal, the V-phase signal input terminal, and the W-phase signal input terminal, respectively.

[0071] In addition, the external controller may be a controller in a product (e.g., an air conditioner or a washing machine) that controls the product, and the controller is located outside the IPM 100. Therefore, the controller may be referred to as an external controller. The external controller may be a processor. Of course, the external controller may also include a central processing unit (CPU), a microcontroller, or an application-specific integrated circuit (ASIC), and may be configured to perform the corresponding operations described in the external controller when the processor executes a program stored in a non-transitory computer-readable medium coupled to the external controller. Some embodiments of the present disclosure are mainly described by taking the external controller including a microcontroller as an example. Of course, the present disclosure is not limited to this.

[0072] In some embodiments, the signal input terminal 110 may also include a terminal newly added to the IPM 100 for measuring the current variation region. It is understood that those skilled in the art may develop the IPM 100 in combination with practical applications and related technologies, and may add a signal input terminal specifically for detecting the current variation region in addition to the signal input terminal 110.

[0073] The first integrated circuit 120 includes a first detection circuit 121 and a first switching circuit 122. The first detection circuit 121 is configured to receive a PWM signal transmitted from the signal input terminal 110 and detect a current variation region based on the PWM signal. The current variation region includes a first current region within a preset threshold range and a second current region outside the preset threshold range. For example, the first current region is a low current region, the second current region is a high current region, and the current value within the first circuit region is smaller than the current value in the second current region.

[0074] In some embodiments, the first detection circuit 121 may be a current detection circuit. For example, the first detection circuit 121 may be a transistor current detection circuit to detect whether the current that varies with time is in the second current region or the first current region.

[0075] In some embodiments, the first detection circuit 121 may also employ a comparison circuit 1211 and a logic circuit 1212. This avoids mutual interference between signals of different phases in the IPM 100, improves the accuracy of current detection, and thereby achieves the noise reduction and loss reduction functions of the IPM 100. The detailed process can be found later. It should be noted that those skilled in the art can predetermine the second current region and the first current region in combination with practical applications and related technologies. For example, by experimentally determining in which current variation region the IPM has the greatest loss, the current variation region is determined as the second current region, and conversely, the current variation region is determined as the first current region.

[0076] The first switching circuit 122 is electrically connected to the first detection circuit 121 and the power switch device 130, respectively, and is configured to receive the first detection result of the first detection circuit 121 and the PWM signal transmitted from the signal input terminal 110. When the first detection result is in the first current region, the first switching circuit 122 switches the gate resistance to the first resistance mode and controls the power switch device 130 to be turned on or off according to the PWM signal in the first resistance mode. Alternatively, when the first detection result is in the second current region, the first switching circuit 122 switches the gate resistance to the second resistance mode and controls the power switch device 130 to be turned on or off according to the PWM signal in the second resistance mode. Here, the first detection result of the first detection circuit 121 indicates whether the current variation region is the first current region or the second current region.

[0077] The first switching circuit 122 may include two circuits with different gate resistance values, corresponding to a first resistance mode and a second resistance mode, respectively. Furthermore, the gate resistance in the first resistance mode is greater than the gate resistance in the second resistance mode. Here, the gate resistance can be understood as the resistance of the drive circuit that controls the on / off switching of the power switch 130. For example, if the power switch 130 is an IGBT, the gate resistance is the resistance of the circuit connected to the gate of the IGBT.

[0078] When the current change region is a low current (constant current) region, the rate of change of the voltage or current is high, which is prone to noise. In this case, by switching to the first resistance mode, the resistance of the gate resistor can be increased, the switching speed of the power switch device 130 can be reduced, and thus the noise can be reduced. When the current change region is a second current region, the rate of change of the voltage or current is low, which is not prone to noise. In this case, by switching to the second resistance mode, the resistance of the gate resistor can be reduced, the switching speed of the power switch device 130 can be increased, and thus the loss can be reduced.

[0079] It should be noted that three, four or more resistance modes may be set in the IPM 100 to further refine the resistance values ​​of the gate resistors in the multiple resistance modes, thereby adapting to various application scenarios of the IPM 100 .

[0080] In some embodiments, one or more resistors can be added to the original gate resistor of the IPM 100 to form a new gate resistor. Furthermore, by connecting corresponding switches in parallel across the added resistors, switching between different resistance modes can be achieved. This can reduce the development cost of the IPM 100. The detailed process is described below.

[0081] In some embodiments, the first integrated circuit 120 may be a low voltage integrated circuit (LVIC). It is understood that ICs can be divided into two types, low voltage integrated circuits and high voltage integrated circuits (HVIC), depending on their operating voltage. Of course, in some embodiments, the first integrated circuit 120 may also be a high voltage integrated circuit.

[0082] The power switching device 130 can be an insulated gate bipolar transistor with high switching speed and low power. In the case where the IPM 100 includes U, V, and W phase signal input terminals, the IPM 100 can include multiple IGBTs corresponding to multiple phase signals (i.e., U, V, and W phase signals). For example, the IPM 100 includes three power switching devices 130, and the three power switching devices 130 correspond to the U, V, and W phase signal input terminals respectively. Of course, the IPM 100 can also include two, four, or more power switching devices 130. Some embodiments of the present disclosure are mainly described by taking the first integrated circuit 120 as a low-voltage integrated circuit and the first integrated circuit 120 corresponding to three IGBTs as an example.

[0083] In some embodiments of the present disclosure, by providing a first detection circuit 121 and a first switching circuit 122, a gate resistor switching function can be implemented for IPM 100. Furthermore, by distinguishing between a first current region and a second current region, the gate resistor can be switched to control the switching speed of power switch device 130, thereby achieving noise reduction in the first current region and power reduction in the second current region. This, in turn, allows for the provision of an IPM with appropriate noise and power consumption for different applications, thereby improving the performance of IPM 100. Furthermore, since the gate resistor value is increased only in the first current region, the loss of IPM 100 is minimally affected, thereby preventing increased loss in IPM 100 while suppressing EMI noise.

[0084] Furthermore, the output characteristics of an IPM are largely determined during the IPM design phase based on the application specifications, making it difficult for current IPMs to simultaneously meet low-loss and low-noise requirements. However, some embodiments of the present disclosure achieve low loss in the primary current range and adjust the IPM to a less noisy region by detecting current variations, thereby meeting both low-loss and low-noise requirements and effectively improving the performance of the IPM 100.

[0085] The principle of using different resistance modes for different current change regions in some embodiments of the present disclosure will be described below with reference to FIG. 2 to FIG. 11 .

[0086] It is understood that the IPM loss is the power consumption generated by the power switch 130 at the moment of turning on and off. This power consumption is mainly calculated from the pulses consumed between the on and off times of the power switch 130. Therefore, the estimated value of the power consumption can be obtained by integrating the product of the collector current and the voltage between the collector and emitter within a switching cycle.

[0087] 2 to 4 are schematic diagrams showing how the power consumption of the power switch device 130 changes over time.

[0088] As shown in Figures 2 to 4, Ic(t) represents the collector current within a switching cycle, Vce(t) represents the voltage between the collector and the emitter within a switching cycle, Vds(t) represents the base voltage within a switching cycle, and VDD represents the power supply voltage. It can be seen from Figures 2 to 4 that the larger the current, the greater the impact of the current on the loss. Therefore, noise reduction in the first current region also has a smaller impact on the loss of the power switching device 130. Here, the estimated value of power consumption can be obtained by the following formula: Eloss = ∫W(t)dt; (1) W(t) = Ic(t) × Vce(t). (2)

[0089] Here, Eloss represents the IPM loss, and W(t) represents the power in one switching cycle.

[0090] Figures 5 to 8 show waveforms of the collector current Ic and the voltage Vce between the collector and emitter when the power switch device 130 is turned on and off, respectively. As shown in Figures 5 to 8, the greater the rate of change of the voltage between the collector and emitter (dVce / dt) or the rate of change of the collector current (dIc / dt), the more likely it is to generate noise, and the smaller the rate of change of the voltage between the collector and emitter or the rate of change of the collector current, the smaller the noise. As can be understood, as shown in Figure 9, the changes in the voltage or current of the power switch device 130 when it is turned on and off can easily cause parasitic inductance (Parasitic Inductance) and parasitic capacitance (Parasitic Capacitance) to generate noise.

[0091] Figure 10 is a graph showing the rate of change of the voltage between the collector and the emitter as the collector current changes. Figure 11 is a graph showing the rate of change of the voltage between the collector and the emitter as the gate resistance changes.

[0092] As shown in Figure 10, the rate of change of the collector-emitter voltage dVce / dt is defined as the first voltage rate of change when the collector current is less than or equal to 40A; the rate of change of the collector-emitter voltage dVce / dt is defined as the second voltage rate of change when the collector current is greater than or equal to 40A. The first voltage rate of change is greater than the second voltage rate of change. In other words, noise is more likely to be generated when the collector current is less than or equal to 40A. As shown in Figure 11, the rate of change of the collector-emitter voltage dVce / dt is defined as the third voltage rate of change when the gate resistor value is less than or equal to 4Ω; the rate of change of the collector-emitter voltage dVce / dt is defined as the fourth voltage rate of change when the gate resistor value is greater than or equal to 4Ω. The third voltage rate of change is greater than the fourth voltage rate of change. Furthermore, when the gate resistor value is greater than or equal to 4Ω, especially 8Ω, the rate of change of the collector-emitter voltage dVce / dt approaches zero (i.e., the curve corresponding to the voltage rate of change is flat).

[0093] Therefore, when the collector current is less than or equal to 40A, if the corresponding gate resistor is controlled to be greater than or equal to 8Ω, noise can be reduced. When the collector current is greater than or equal to 40A, the voltage change rate has less impact on noise, and the gate resistor can be controlled to be roughly constant (for example, the gate resistor is roughly equal to 4Ω), thereby reducing losses. In this way, some embodiments of the present disclosure can achieve noise reduction and low loss functions of the IPM by adopting the above method.

[0094] It should be noted that the first current region can be understood as the current region corresponding to a small PWM signal duty cycle and a fast IGBT switching speed. In this case, the IPM 100 has high voltage and current change rates and is prone to noise generation. The second current region can be understood as the current region corresponding to a large PWM signal duty cycle and a slow IGBT switching speed. In this case, the IPM 100 has low voltage and current change rates and is less noisy.

[0095] In some embodiments, as shown in Figures 12 and 13, the first integrated circuit 120 further includes a buffer circuit 123. The input end of the buffer circuit 123 is electrically connected to the signal input terminal 110, and the output end of the buffer circuit 123 is connected to the first detection circuit 121 and the first switching circuit 122, respectively. The buffer circuit 123 is configured to receive the PWM signal transmitted from the signal input terminal 110 and buffer the PWM signal to transmit the PWM signal to the first detection circuit 121 and the first switching circuit 122, respectively.

[0096] Since the first detection circuit 121 needs to use a PWM signal to detect the current change area, and the first switching circuit 122 needs to use a PWM signal to drive the gate resistor, therefore, by adding a buffer circuit 123 to buffer the PWM signal, the reliability of the PWM signal can be improved, thereby further improving the reliability of the first switching circuit 122, and solving the capacitance load problem that may occur in signal transmission.

[0097] FIG13 shows a structure of a first detection circuit 121. N Phase signal input terminal, V N Phase signal input terminal and W N The phase signal input terminals are the U-phase signal input terminal, the V-phase signal input terminal, and the W-phase signal input terminal included in the signal input terminal 110 . As shown in FIG13 , the first detection circuit 121 includes a comparison circuit 1211 and a logic circuit 1212 .

[0098] Comparison circuit 1211 is configured to compare any two of the U-phase, V-phase, and W-phase signals to obtain an interphase signal between the two phase signals. Logic circuit 1212 is connected to comparison circuit 1211 and configured to receive the interphase signals output by comparison circuit 1211, determine the interphase voltages corresponding to the U-phase, V-phase, and W-phase signals based on the interphase signals, and determine the current variation region corresponding to each phase signal based on the interphase voltages.

[0099] The buffer circuit 123 receives the three-phase PWM signal transmitted from the external controller through the signal input terminal 110 , buffers the three-phase PWM signal, and then transmits the three-phase PWM signal to the first detection circuit 121 and the first switching circuit 122 respectively.

[0100] It should be noted that the transmission of the PWM signal can be controlled according to the corresponding clock. Furthermore, the multiple phase signals in the three-phase PWM signal are pulse signals, each having a high level and a low level. By applying the level of the pulse signal to the power switch 130, the power switch 130 can be turned on or off. Here, the high and low levels of the pulse signal are merely relative.

[0101] By obtaining the difference between any two phase signals in the three-phase PWM signal (for example, the duty cycle difference or the pulse width difference), multiple phase signals (the difference between the U-phase signal and the V-phase signal, the difference between the V-phase signal and the W-phase signal, and the difference between the W-phase signal and the U-phase signal) can be obtained.

[0102] FIG14 is a schematic diagram of obtaining the interphase voltage of multiple phase signals according to the interphase signal according to some embodiments. As shown in FIG14 , U N is the U-phase signal received by the low side, V N is the V phase signal received by the low side, W N It is the W phase signal received by the low side. N -V N is the interphase signal between the low-side U-phase signal and the V-phase signal, V N -W N It is the interphase signal between the low-side V-phase signal and the W-phase signal, W N -U N It is the interphase signal between the low-side W-phase signal and the U-phase signal. In addition, FIG14 shows the area where the U-phase signal is greater than the V-phase signal, the area where the V-phase signal is greater than the W-phase signal, and the area where the W-phase signal is greater than the U-phase signal. Gs_u is the interphase voltage of the U-phase signal, Gs_v is the interphase voltage of the V-phase signal, and Gs_w is the interphase voltage of the W-phase signal. The change area of ​​the phase-to-phase voltage corresponds to the current change area. The area corresponding to the arrow in FIG14 is the first current area, and vice versa, it is the second current area. In addition, the symbols "+" and "-" in FIG14 respectively represent the conduction of the high side and the low side. The above-mentioned high side refers to the power switching device 130 corresponding to the high-voltage integrated circuit, and the above-mentioned low side refers to the power switching device 130 corresponding to the low-voltage integrated circuit.

[0103] In other embodiments, when the interphase signal between the U-phase signal and the V-phase signal is a pulse width difference, the pulse width difference U can be directly converted to N -V NThe current variation region is determined to be a first current region, and an active signal is generated. This active signal is transmitted to the first switching circuit 122 as a first detection result, thereby controlling the gate resistor to switch to a high resistance mode to achieve noise reduction for the IPM 100 without significantly affecting power consumption. It should be noted that the preset value can be adaptively determined by those skilled in the art based on actual applications and relevant technologies.

[0104] In the IPM 100 provided in some embodiments of the present disclosure, the first detection circuit 121 uses a comparison circuit 1211 to compare the phase signals to obtain interphase signals, and uses a logic circuit 1212 to analyze the interphase voltages between the multiple phase signals. The current variation regions corresponding to the multiple phase signals are then determined based on the interphase voltages. This reduces interference between the multiple phase signals compared to conventional current detection circuits, improving the accuracy of the first detection result.

[0105] In some embodiments, the comparison circuit 1211 may include a first comparator, a second comparator, and a third comparator, and the logic circuit 1212 may include a first XNOR gate, a second XNOR gate, and a third XNOR gate.

[0106] The input terminals of the first comparator are connected to the U-phase signal input terminal and the V-phase signal input terminal, respectively. The output terminals of the first comparator are connected to the first XNOR gate and the second XNOR gate. The first comparator is configured to compare the U-phase signal inputted from the U-phase signal input terminal with the V-phase signal inputted from the V-phase signal input terminal to obtain a first interphase signal between the U-phase signal and the V-phase signal, and input the first interphase signal to the first XNOR gate and the second XNOR gate.

[0107] The second and third comparators have similar structures and functions to the first comparator. The input of the second comparator is connected to the U-phase signal input terminal and the W-phase signal input terminal, and the output of the second comparator is connected to the first and third XNOR gates to obtain a second interphase signal between the U-phase and W-phase signals, and input the second interphase signal to the first and third XNOR gates. The input of the third comparator is connected to the V-phase signal input terminal and the W-phase signal input terminal, and the output of the third comparator is connected to the second or third XNOR gates to obtain a third interphase signal between the V-phase and W-phase signals, and input the third interphase signal to the second and third XNOR gates.

[0108] The input terminals of the first XNOR gate are connected to the first comparator and the second comparator, respectively, and the output terminal of the first XNOR gate is connected to the first switching circuit 122. The first XNOR gate is configured to determine the interphase voltage of the U-phase signal based on the first interphase signal and the second interphase signal, and to determine the current variation region corresponding to the U-phase signal based on the interphase voltage of the U-phase signal, thereby outputting a first detection result to the first switching circuit 122.

[0109] The structure and function of the second and third XNOR gates are similar to those of the first XNOR gate. The inputs of the second XNOR gate are connected to the first and third comparators, and the output of the second XNOR gate is connected to the first switching circuit 122 to determine the interphase voltage of the V-phase signal and the current variation range corresponding to the V-phase signal based on the first and third interphase signals. The inputs of the third XNOR gate are connected to the second and third comparators, and the output of the third XNOR gate is connected to the first switching circuit 122 to determine the interphase voltage of the W-phase signal and the current variation range corresponding to the W-phase signal based on the second and third interphase signals.

[0110] It should be noted that the comparator is a circuit that compares an analog voltage signal (i.e., U, V, W phase signal) with a reference voltage (e.g., power supply voltage VDD). The two input signals of the comparator are analog signals, and the output signal is a binary digital signal 0 or 1. When the voltage difference of the input signal increases or decreases and the positive and negative signs remain unchanged, the output signal of the comparator remains constant. For example, FIG15 shows the structure of the first comparator 161. As shown in FIG15, the first comparator 161 includes two input terminals and an output terminal, and the two input terminals are respectively connected to the U phase signal input terminal (U N ) and V-phase signal input terminal (V N ), the output end of the first comparator 161 is used to output a first inter-phase signal after the U-phase signal and the V-phase signal are compared.

[0111] The XNOR gate, also known as the XNOR Gate or Equivalence Gate, is an XNOR gate formed by adding a NOT gate to the output of the XNOR gate. The XNOR gate is the basic unit of the digital logic circuit. The XNOR gate has two input terminals and one output terminal. When one and only one of the two input terminals is at a low level (i.e., logic 0), the output terminal is a low level; when the levels of the two input terminals are the same, the output terminal is a high level (i.e., logic 1). For example, Figure 16 shows the structure of the first XNOR gate 171. As shown in Figure 16, the first XNOR gate 171 includes two input terminals and one output terminal. The two input terminals are respectively connected to the output terminal of the first comparator 161 and the output terminal of the second comparator. The output terminal of the first XNOR gate 171 is used to output the phase-to-phase voltage of the U-phase signal to determine the current change range.

[0112] It can be understood that the structure and principle of the second comparator and the third comparator are similar to those of the first comparator 161, and the structure and principle of the second XNOR gate and the third XNOR gate are similar to those of the first XNOR gate 171, which will not be repeated here.

[0113] In some embodiments, for the first comparator, when the U-phase signal is greater than the V-phase signal (i.e., U>V), the first comparator outputs the first interphase signal to the first XNOR gate; when the U-phase signal is less than the V-phase signal (i.e., V>U), the first comparator outputs the first interphase signal to the second XNOR gate. For the second comparator, when the W-phase signal is greater than the U-phase signal (i.e., W>U), the second comparator outputs the second interphase signal to the first XNOR gate; when the W-phase signal is less than the U-phase signal (i.e., U>W), the second comparator outputs the second interphase signal to the third XNOR gate. For the third comparator, when the V-phase signal is greater than the W-phase signal (i.e., V>W), the third comparator outputs the third interphase signal to the second XNOR gate; when the V-phase signal is less than the W-phase signal (i.e., W>V), the third comparator outputs the third interphase signal to the third XNOR gate.

[0114] In some embodiments, the first XNOR gate is configured to determine whether the U-phase signal is greater than the V-phase signal, and the W-phase signal is greater than the U-phase signal. If the U-phase signal is greater than the V-phase signal, and the W-phase signal is greater than the U-phase signal, the first XNOR gate outputs the interphase voltage Gs_u of the U-phase signal, and the interphase voltage Gs_u is used to indicate that the corresponding gate resistor is switched to the first resistance mode. The second XNOR gate is configured to determine whether the V-phase signal is greater than the W-phase signal, and the U-phase signal is greater than the V-phase signal. If the V-phase signal is greater than the W-phase signal, and the U-phase signal is greater than the V-phase signal, the second XNOR gate outputs the interphase voltage Gs_v of the V-phase signal, and the interphase voltage Gs_v is used to indicate that the corresponding gate resistor is switched to the first resistance mode. The third XNOR gate is configured to determine whether the W-phase signal is greater than the U-phase signal, and the V-phase signal is greater than the W-phase signal. If the W phase signal is greater than the U phase signal and the V phase signal is greater than the W phase signal, the third XOR gate outputs the interphase voltage Gs_w of the W phase signal. The interphase voltage Gs_w is used to instruct the corresponding gate resistor to switch to the first resistance mode.

[0115] In the IPM 100 provided in some embodiments of the present disclosure, by using a comparator and a logic gate to detect the phase voltage, the accuracy of the first detection result can be improved.

[0116] In some embodiments, as shown in Figure 15, the comparison circuit 1211 also includes a diode 162 and a capacitor 163 corresponding to the first comparator 161, the second comparator, and the third comparator, respectively. The input end (e.g., anode) of the diode 162 is connected to the output end of the corresponding comparator, and the output end (i.e., cathode) of the diode 162 is connected to the corresponding XNOR gate. The input end of the capacitor 163 is connected to the wire between the corresponding diode 162 and the corresponding XNOR gate, and the output end of the capacitor 163 is grounded. In this way, by providing the diode 162 and the capacitor 163 in the comparison circuit 1211, current reverse and electromagnetic interference can be prevented, further improving the accuracy of the first detection result.

[0117] The specific structure of the first switching circuit 122 in some embodiments of the present disclosure is described in detail below.

[0118] 13, 17, and 18, the first switching circuit 122 includes a first sub-switching circuit 1221, a second sub-switching circuit 1222, and a third sub-switching circuit 1223. The second sub-switching circuit 1222 includes a first gate resistor RG1 and a second gate resistor RG2.

[0119] The input end of the first sub-switching circuit 1221 is connected to the buffer circuit 123, and the output end of the first sub-switching circuit 1221 is electrically connected to the second sub-switching circuit 1222. The first sub-switching circuit 1221 is configured to receive a PWM signal and switch its connection to the first gate resistor RG1 or the second gate resistor RG2 according to the PWM signal.

[0120] The first input terminal of the third sub-switching circuit 1223 is electrically connected to the conductive line between the first gate resistor RG1 and the second gate resistor RG2. The second input terminal of the third sub-switching circuit 1223 is electrically connected to the first detection circuit 121 to receive the first detection result of the first detection circuit 121. The output terminal of the third sub-switching circuit 1223 is connected to the power switching device 130. For example, the output terminal of the third sub-switching circuit 1223 is connected to the gate of the IGBT. The third sub-switching circuit 1223 includes a third gate resistor RG and a load switch 1224, which is connected in parallel with the third gate resistor RG. One end of the third gate resistor RG serves as the first input terminal, and the other end serves as the output terminal connected to the corresponding power switching device 130.

[0121] The third sub-switching circuit 1223 is configured to: receive the first detection result of the first detection circuit 121; when the first detection result is in the first current range, control the load switch 1224 to be off, so as to switch to the first resistance mode corresponding to the gate resistance value being the sum of the first gate resistor RG1 and the third gate resistor RG, or the first resistance mode corresponding to the gate resistance value being the sum of the second gate resistor RG2 and the third gate resistor RG; or, when the first detection result is in the second current range, control the load switch 1224 to be on, so as to switch to the second resistance mode having the gate resistance value being the first gate resistor RG1 or the gate resistance value being the second gate resistor RG2. In this way, switching of the gate resistance corresponding to the power switch device 130 can be achieved.

[0122] Because the region with low current output (i.e., the first current region) dominates the EMI noise level, if the gate resistors in the IPM 100 are divided into resistors corresponding to low current and resistors corresponding to high current, and the IPM 100 is configured to automatically switch to a high-resistance gate resistor (corresponding to the first resistance mode) when the current is low and automatically switch to a low-resistance gate resistor (corresponding to the second resistance mode) when the current is high, an IPM with suppressed EMI noise can be obtained.

[0123] As shown in Figure 17, the third gate resistor RG and load switch 1224 are provided on the output side of the gate drive circuit (i.e., the second sub-switching circuit 1222). When the current is high, the third gate resistor RG is short-circuited, and the resistance of the third gate resistor RG is zero. When the current is low, the load switch 1224 is disconnected to increase the resistance of the gate resistor. Because losses are proportional to current (or voltage), increasing the gate resistor value at low currents can suppress the impact of the current change rate on losses.

[0124] It should be noted that the front-end loop in FIG. 17 and FIG. 18 corresponds to the buffer circuit 123 and the first detection circuit 121 .

[0125] In the IPM 100 provided in some embodiments of the present disclosure, by changing the resistance value of the gate resistor, the resistance mode can be switched, thereby coordinating low noise and low loss of the IPM 100.

[0126] In some embodiments, taking the circuit of the IGBT corresponding to the U-phase signal as an example, as shown in Figures 17 and 18, the first sub-switching circuit 1221 includes an inverter 1225, a P-type metal oxide semiconductor (Positive Channel Metal Oxide Semiconductor, PMOS) and an N-type metal oxide semiconductor (Negative Channel Metal Oxide Semiconductor, NMOS).

[0127] The input end of the inverter 1225 is electrically connected to the buffer circuit 123, and the output end of the inverter 1225 is connected to the PMOS and NMOS, respectively. The inverter 1225 is configured to receive the PWM signal transmitted by the buffer circuit 123, invert the high-level signal or low-level signal corresponding to the PWM signal, and output it to the PMOS or NMOS, thereby turning on the PMOS and switching to the first gate resistor RG1, or turning on the NMOS and switching to the second gate resistor RG2.

[0128] The gate of the PMOS is electrically connected to the output of the inverter 1225 and the gate of the NMOS respectively. The source of the PMOS is electrically connected to the power supply VDD. The drain of the PMOS is electrically connected to the drain of the NMOS through the first gate resistor RG1 and the second gate resistor RG2 in sequence.

[0129] The gate of the NMOS is electrically connected to the output terminal of the inverter 1225 and the gate of the PMOS respectively. The source of the NMOS is grounded. The drain of the NMOS is connected to the drain of the PMOS via the second gate resistor RG2 and the first gate resistor RG1 in sequence.

[0130] By receiving the PWM signal output by the front-end loop to control the conduction or shutoff of the second sub-switching circuit 1222, and receiving the first detection result output by the front-end loop to control the conduction or shutoff of the load switch 1224, the switching between the first resistance mode and the second resistance mode can be realized. FIG17 shows the second resistance mode in which the load switch 1224 is turned on when the current change region is the second current region, and FIG18 shows the first resistance mode in which the load switch 1224 is turned off when the current change region is the first current region. In FIG17 and FIG18, the convex symbol at the input end of the inverter 1225 represents a low-level signal, and the concave symbol at the output end of the inverter 1225 represents a high-level signal, Q ON Indicates that the body diode is conducting, Q OFF Indicates that the body diode is turned off.

[0131] In some embodiments, the first sub-switching circuit 1221 may further include a current-limiting resistor connected to the output of the inverter 1225. For example, the output of the inverter 1225 may be connected in series with a PMOS and an NMOS transistor, respectively, via a current-limiting resistor. By adding a current-limiting resistor to the output of the inverter 1225, the flow of the output current can be limited, thereby controlling the current in the circuit, thereby protecting other components in the circuit and controlling the normal operation of the circuit.

[0132] In the IPM 100 provided in some embodiments of the present disclosure, the first sub-switching circuit 1221 uses an inverter 1225, a PMOS, and an NMOS to turn on or off the first gate resistor RG1 and the second gate resistor RG2 according to a PWM signal, thereby achieving noise reduction and low-loss processing during the turning on or off process of the power switching device 130.

[0133] The foregoing mainly describes how to coordinate the noise and loss of the IPM 100. Of course, in some embodiments, external access and control functions for the IPM 100 may also be added to meet the user's external access and control requirements for the IPM 100.

[0134] As shown in Figures 19 and 20, the intelligent power module 100 includes a signal input terminal 110 and a signal output terminal 140. The input end of the signal input terminal 110 is connected to the external controller, and the output end is electrically connected to the second switching circuit 126, and is configured to receive a PWM signal output by the external controller or transmit an I / F signal. The signal input terminal 110 can be the original signal input terminal of the IPM 100. For example, the signal input terminal 110 includes at least one of a U-phase signal input terminal, a V-phase signal input terminal, or a W-phase signal input terminal. The specific content of the signal input terminal 110 can be referred to the relevant content above and will not be repeated here.

[0135] The intelligent power module 100 includes a first integrated circuit 120 including a second detection circuit 129 . The second detection circuit 129 is electrically connected to the signal output terminal 140 and configured to detect a level signal of the signal output terminal 140 and transmit a second detection result to the second switching circuit 126 .

[0136] The first integrated circuit 120 further includes a second switching circuit 126. The second switching circuit 126 is electrically connected to the second detection circuit 129 and the signal input terminal 110, respectively. The second switching circuit 126 is configured to switch between the I / F control circuit 125 and the PWM signal input circuit 128 based on the second detection result; and to receive the I / F signal or PWM signal transmitted through the signal input terminal 110 and transmit the I / F signal to the I / F control circuit 125 or transmit the PWM signal to the PWM signal input circuit 128.

[0137] The first integrated circuit 120 further includes an interface (I / F) execution circuit 124 and an interface control circuit 125. The I / F control circuit 125 is electrically connected to the I / F execution circuit 124 and the second switching circuit 126, respectively, and is configured to control the I / F execution circuit 124 to perform corresponding processing based on the I / F signal when receiving the I / F signal.

[0138] The processing functions of the I / F execution circuit 124 include, but are not limited to, switching of gate resistors, temperature detection, and circuit protection. It should be noted that the above-mentioned interface may be a serial interface. Of course, the present disclosure is not limited thereto.

[0139] The first integrated circuit 120 also includes a PWM signal input circuit 128. The PWM signal input circuit 128 is electrically connected to the second switching circuit 126 and the power switch 130, respectively, and is configured to control the power switch 130 to turn on or off upon receiving a PWM signal. The intelligent power module 100 also includes the power switch 130. For details about the power switch 130, please refer to the previous section.

[0140] In some embodiments, the first integrated circuit 120 may be a LVIC. In practical applications, a protection circuit 127 is typically provided in the low voltage integrated circuit of the IPM 100 to output a corresponding fault signal, thereby realizing the function of the protection circuit.

[0141] For example, the first integrated circuit 120 also includes a protection circuit 127. The protection circuit 127 is electrically connected to the signal output terminal 140 and is configured to output a circuit protection signal (i.e., a fault signal) to the signal output terminal 140. The protection circuit 127 may include overcurrent (OC) protection and short circuit (SC) protection functions. For overcurrent protection, if the current flowing through the power switching device 130 is greater than or equal to a preset current threshold, and the time of exceeding is greater than or equal to 10ms, the gate current of the gate drive circuit is disconnected to block the gate drive circuit, and the protection circuit 127 outputs a fault signal. Since the protection circuit 127 performs protection by detecting the collector current of each IGBT, no matter which IGBT has an abnormality, the protection circuit 127 can perform timely protection.

[0142] The protection circuit 127 may also include an undervoltage (UV) protection function for the drive power supply. Each drive circuit may have a UV protection function. When the voltage of the drive power supply is less than a preset voltage threshold, the protection circuit 127 performs undervoltage protection. For example, if the IPM is powered by a +15V drive power supply, if the drive power supply voltage is less than 12.5V and exceeds the threshold for more than or equal to 10ms, the gate drive circuit is blocked and the protection circuit 127 outputs a fault signal.

[0143] The protection circuit 127 may also include an overheat (OH) protection function. The protection circuit 127 may use this function to prevent overheating of the IGBT and the fast recovery diode (FRD). For example, a temperature detection element (such as a temperature sensor) is provided on the insulating substrate inside the IPM 100 to detect the temperature of the insulating substrate. When the temperature of the insulating substrate exceeds a preset temperature threshold, the gate drive circuit is blocked, and the protection circuit 127 outputs a fault signal. Of course, a temperature detection element may also be provided in each IGBT to provide timely protection against abnormal heating of the chip.

[0144] In some embodiments, the protection circuit 127 includes a switching transistor, which is configured to be turned on when receiving a circuit protection signal and output the circuit protection signal to the signal output terminal 140, so that the signal output terminal 140 is in a low level state, and the external controller controls the IPM 100 according to the low level signal of the signal output terminal 140 to protect the circuit.

[0145] For example, the switching transistor is a metal-oxide-semiconductor field-effect-transistor (MOSFET or MOS). A MOS transistor is a device with an amplification function. The operating principle of a MOS transistor is as follows: when the MOS transistor is turned on, current flows into the input stage through a special resistor (i.e., a varistor). When the switching transistor is turned on after receiving a circuit protection signal, the voltage signal output from the signal output terminal 140 to the external controller is a low-level signal. For example, when the MOS transistor is turned on, the voltage level of the output terminal is pulled down to a low level, and the low-level signal is output to the signal output terminal 140.

[0146] It will be appreciated that signal output terminal 140 is equivalent to the drain of the MOS in protection circuit 127. Therefore, when the MOS is off, the voltage level of signal output terminal 140 is equal to the voltage level of pull-up resistor 20 (as shown in FIG. 22 ) external to IPM 100 (i.e., a high voltage level (e.g., 5V)). At this point, IPM 100 is not in a protection state, and an external controller can control the high-level signal of signal output terminal 140 to a low-level signal, thereby using signal output terminal 140 as an input or output terminal. When the MOS is on, it pulls the voltage level of signal output terminal 140 down to a low level, triggering the circuit protection function of IPM 100.

[0147] The signal output terminal 140 can be a fault output (FO) terminal of the IPM 100. For example, the input end of the signal output terminal 140 is connected to the output end of the protection circuit 127, and the output end of the signal output terminal 140 is connected to the input end of the external controller. The signal output terminal 140 is configured to output a corresponding level signal to the external controller when it does not receive the circuit protection signal output by the protection circuit 127, so that the external controller transmits the I / F signal to the I / F control circuit 125 through the signal input terminal 110. In addition, the signal output terminal 140 is further configured to output a fault signal (i.e., a circuit protection signal) to the external controller. In some examples, the fault signal can be output to the external controller in the form of a low-level signal so that the external controller can perform corresponding fault processing. For example, the external controller stops the continued input of the PWM signal.

[0148] In some embodiments of the present disclosure, by multiplexing the signal output terminal 140 and detecting the level signal of the signal output terminal 140 through the second detection circuit 129, the second switching circuit 126 can be switched to the corresponding circuit (i.e., the I / F control circuit 125 or the PWM signal input circuit 128) according to the second detection result, thereby realizing I / F signal transmission or PWM signal transmission.

[0149] The level signal of the signal output terminal 140 detected by the second detection circuit 129 may be a level signal corresponding to when no fault signal output is required, and the level signal may be a high level signal. Under the high level signal, the external controller may perform corresponding processing.

[0150] For example, the external controller can control the high-level signal to a low-level signal or to another level (e.g., to control the high-level signal within a preset range). In this case, the second switching circuit 126 switches from the PWM signal input circuit 128 to the I / F control circuit 125. Furthermore, the external controller can reuse the signal input terminal 110 to transmit the I / F signal, thereby controlling the processing function of the I / F execution circuit 124. If the high-level signal at the signal output terminal 140 is not processed accordingly or is restored after processing, the second switching circuit 126 switches to the PWM signal input circuit 128 to transmit the PWM signal, thereby controlling the power switching device 130.

[0151] In some embodiments, the high-level signal can be any value in the range of 3.5V to 5V. For example, the high-level signal can be any value in the range of 3.5V to 4V; or, the high-level signal can be any value in the range of 4V to 4.5V; or, the high-level signal can be any value in the range of 4.5V to 5V. The low-level signal can be any value in the range of 0V to 0.25V. For example, the low-level signal can be any value in the range of 0V to 0.1V; or, the low-level signal can be any value in the range of 0.1V to 0.2V; or, the low-level signal can be any value in the range of 0.2V to 0.25V.

[0152] The structure and function of the power switch device 130 can be found in the relevant content above and will not be described again here.

[0153] It should be noted that when the IPM 100 is operating normally, the second switching circuit 126 is disconnected from the I / F control circuit 125, and the second switching circuit 126 is connected to the PWM signal input circuit 128. In this case, the IPM 100 receives a PWM signal transmitted from an external controller through the signal input terminal 110 and drives the corresponding component (such as a motor or compressor) by controlling the power switch device 130.

[0154] Some embodiments of the present disclosure utilize serial switching between the PWM signal input circuit 128 and the I / F control circuit 125 to implement external interface functionality while avoiding impacting the transmission of the original PWM signal within the IPM 100. Furthermore, the IPM 100 provided in some embodiments of the present disclosure, while taking into account the number of terminals of the IPM 100, utilizes the IPM 100's own terminals to design a serial interface circuit. This allows the IPM 100 to have interface functionality without increasing the number of terminals, thereby satisfying the detailed control requirements of the IPM 100 by an external controller. Furthermore, by multiplexing the signal output terminals 140 and the signal input terminals 110, external control of the IPM 100 can be achieved without increasing the number of terminals on the IPM 100, thereby satisfying the miniaturization requirements of the IPM 100 and reducing the development costs of the IPM 100.

[0155] In some embodiments, the second detection circuit 129 is further electrically connected to the protection circuit 127 and is configured to transmit the second detection result to the second switching circuit 126 when the protection circuit 127 does not transmit the circuit protection signal. For example, as shown in FIG22 , the IPM 100 further includes a pull-up resistor 20 and a power supply 21. The output end of the signal output terminal 140 is further connected to one end of the pull-up resistor 20, and the other end of the pull-up resistor 20 is connected to the power supply 21. Thus, when the signal output terminal 140 does not receive the circuit protection signal output by the protection circuit 127, the signal output terminal 140 is in a high-level state corresponding to the pull-up resistor 20, allowing an external controller to control the high-level state of the signal output terminal 140 to a low-level state.

[0156] In this case, the second switching circuit 126 is configured to: when the protection circuit 127 does not output a circuit protection signal, when the second detection result is a low-level signal, switch to connect to the I / F control circuit 125; or, when the second detection result is a high-level signal, switch to connect to the PWM signal input circuit 128.

[0157] In some embodiments, the external controller can also control the high-level signal of the signal output terminal 140 to be within a preset range. The preset range is used to instruct the second switching circuit 126 to switch to the I / F control circuit 125. The present disclosure does not specifically limit the level of the signal used to switch the I / F control circuit 125 and the PWM signal input circuit 128.

[0158] Typically, when the IPM 100 issues a circuit protection signal, the signal output terminal 140 outputs a low-level signal to the external controller, causing the external controller to no longer input a PWM signal to the signal input terminal 110 of the IPM 100. Some embodiments of the present disclosure utilize this characteristic of the IPM 100. When an external controller needs to access and control the IPM 100, the IPM 100 is in its normal state (i.e., when no circuit protection signal is received) by controlling the high-level signal at the signal output terminal 140 to a low-level signal. This prevents the external controller from inputting a PWM signal to the signal input terminal 110. Furthermore, the signal input terminal 110, which is not receiving a PWM signal, is multiplexed to enable transmission of I / F signals between the external controller and the IPM 100. This process further optimizes I / F signal communication, ensuring that, in its normal state, the PWM signal and I / F signal of the IPM 100 are not interfered with.

[0159] FIG21 is a structural diagram of another intelligent power module according to some embodiments. As shown in FIG21 , the I / F execution circuit 124 includes at least one of a first sub-circuit 1241 , a second sub-circuit 1242 , or a third sub-circuit 1243 .

[0160] The first subcircuit 1241 is configured to switch the gate resistance according to the gate resistance switching signal (i.e., the I / F signal is the gate resistance switching signal). Once the model and drive voltage of the power switch device 130 are determined, the gate resistance becomes a key factor affecting the switching speed of the power switch device 130. When the gate resistance is small, the gate loop will oscillate; when the gate resistance is large, the loss of the power switch device 130 will increase. Some embodiments of the present disclosure can achieve switching of the gate resistance by transmitting an external I / F signal, and the processing results can be fed back to the external controller in the form of an I / F signal.

[0161] Second subcircuit 1242 is configured to set thresholds corresponding to protection functions of protection circuit 127 based on a circuit protection setting signal (i.e., the I / F signal is a circuit protection setting signal). The protection functions of protection circuit 127 may include at least one of overheat protection, overcurrent protection, or undervoltage protection. For example, second subcircuit 1242 sets the temperature threshold for overheat protection, the current threshold for overcurrent protection, and the voltage threshold for undervoltage protection. In other words, when the corresponding parameters are greater than or equal to the aforementioned thresholds, IPM 100 generates the corresponding circuit protection signal. Furthermore, second subcircuit 1242 may also provide feedback on the setting results to an external controller in the form of an I / F signal.

[0162] The third subcircuit 1243 is configured to detect the temperature information of the IPM 100 based on the temperature monitoring signal (i.e., the I / F signal is a temperature monitoring signal). Here, the temperature information can be understood as the temperature of the substrate in the IPM 100. Of course, the present disclosure is not limited to this. For example, the third subcircuit 1243 is a temperature sensor installed on the substrate of the IGBT. After receiving the temperature monitoring signal sent by the external controller, the temperature sensor detects the temperature of the IPM 100 and can feed back the temperature detection result to the external controller in the form of an I / F signal. In addition, the external controller can determine whether to send a corresponding signal based on the temperature detection result to activate the overheating protection scheme of the IPM 100.

[0163] It should be noted that the I / F execution circuit 124 is not limited to the above circuits. Those skilled in the art can adaptively set the I / F execution circuit 124 based on actual applications to flexibly utilize the I / F function to access and control the internal functional circuits of the IPM 100.

[0164] In some embodiments of the present disclosure, by fine-tuning the I / F execution circuit 124, multiple functions and operation modes can be implemented within a single IPM 100. This eliminates the need to create a corresponding product for each application, allowing a single IPM model to accommodate multiple products, simplifying product offerings. Furthermore, this reduces design and evaluation time, improving product quality while simplifying circuitry. Furthermore, the need to develop multiple IPM specifications is eliminated, reducing development costs.

[0165] In some embodiments, as shown in FIG22 , the PWM signal input circuit 128 includes an input signal circuit 1281 and a gate drive circuit (also referred to as a gate driver) 1282. The gate drive circuit 1282 can be a buffer circuit for amplifying low voltage or low current from an external controller, and can drive the power switch device 130, thereby driving the power switch device 130 on and off. It is understood that the gate resistor switched by the first sub-circuit 1241 is the gate resistor in the gate drive circuit 1282. In some examples, the structures of the first sub-circuit 1241 and the gate drive circuit 1282 can be similar to those of the first switching circuit 122 and are not further described here.

[0166] Since the 0V-5V PWM signal output by the external controller is not sufficient to fully turn on the power switch device 130, after the input signal circuit 1281 obtains the PWM signal output by the external controller, the gate drive circuit 1282 can be used to perform level conversion to achieve full conduction of the power switch device 130.

[0167] In some embodiments of the present disclosure, by providing a circuit including a circuit protection setting function, a gate resistance setting function, and a device temperature information setting function inside the IPM 100, it is possible to control the IPM 100 from the outside. Since the functions and operation modes can be finely configured in a single IPM, there is no need to set up corresponding products for each application. Multiple products can be applied to a single model of IPM, thereby simplifying the product variety. In addition, the design and evaluation time can be reduced, and costs can be reduced. In addition, the simplification of the circuit can also improve product quality, and there is no need to change the basic design of the IPM 100 for the I / F function, thereby improving the compatibility of the IPM 100.

[0168] The following describes in detail the transmission process of PWM signals and I / F signals between the external controller and the IPM 100 in some embodiments of the present disclosure.

[0169] In the case where the signal input terminal 110 includes U, V, and W phase signal input terminals, the three phase signal input terminals can be used as three pins of an external controller to implement input and output of I / F signals. For example, as shown in FIG22 , the signal input terminal 110 includes a U phase signal input terminal (i.e., U N Phase signal input terminal), V phase signal input terminal (ie, V N Phase signal input terminal) and W phase signal input terminal (ie, W N Phase signal input terminal). I / F signals include clock (CLK) signal, digital input (DI) signal and digital output (DO) signal.

[0170] The U-phase signal input terminal is configured to receive a U-phase signal or a CLK signal transmitted by an external controller. The W-phase signal input terminal is configured to receive a W-phase signal or a DI signal transmitted by an external controller. The V-phase signal input terminal is configured to receive a V-phase signal or transmit a DO signal to an external controller. Here, transmitting a DO signal to an external controller means that after the I / F execution circuit 124 completes the corresponding processing, it feeds back the processing result to the external controller in the form of an I / F signal. It should be noted that the U-phase, V-phase, and W-phase are three-phase lines (i.e., the three-phase AC power of the motor power supply), and the phase difference between the U-phase, V-phase, and W-phase is 120 degrees. In a three-phase inverter, the IPM has U, V, and W three-phase signal input terminals to realize the input of PWM signals.

[0171] In some embodiments of the present disclosure, by multiplexing the three-phase signal input terminals U, V, and W, the U, V, and W signal input terminals can be mapped to the CLK, DI, and DO pins of an external controller, respectively. This allows the external controller to input and output I / F signals when not inputting PWM signals, thereby enabling communication between the external controller and the IPM 100 and enabling external access and control of the IPM 100.

[0172] It should be noted that the aforementioned use of the U-phase signal input terminal to transmit the CLK signal, the V-phase signal input terminal to transmit the DO signal, and the W-phase signal input terminal to transmit the DI signal is a form of multiplexing of the signal input terminal 110 in some embodiments of the present disclosure. In other embodiments, the aforementioned three signal input terminals can serve as transmission terminals for any one of the CLK signal, the DI signal, and the DO signal. For example, the U-phase signal input terminal transmits the DI signal, the V-phase signal input terminal transmits one of the DO signal or the CLK signal, and the W-phase signal input terminal transmits the other of the DO signal or the CLK signal.

[0173] Figure 23 is a timing diagram of the external controller transmitting a PWM signal to the IPM. Figure 24 is a timing diagram of the external controller transmitting an I / F signal to the IPM. As shown in Figure 23, the external controller transmits a PWM signal to the IPM 100 in three stages.

[0174] In the first phase (1), when power supply VDD is activated or reset, if IPM 100 is operating normally (e.g., without receiving a circuit protection signal), signal output terminal 140 (i.e., FO in FIG. 23 ) is at the potential of pull-up resistor 20 external to IPM 100, which is in a high state. If IPM 100 experiences an abnormality (i.e., signal output terminal 140 is in a low state), the external controller protects IPM 100 and prevents it from entering the subsequent phases.

[0175] In the second phase (2), the external controller detects the potential of signal output terminal 140. When signal output terminal 140 is at a high level and external access and control of IPM 100 is required, the external controller can control or switch the potential of signal output terminal 140 to a low level. However, when the external controller is normally outputting a PWM signal, the external controller does not control the potential. With signal output terminal 140 at a high level, IPM 100 does not switch I / F control circuit 125, and IPM 100 can normally control power switch 130 according to the PWM signal. Therefore, the potential of signal output terminal 140 serves as a selection signal for whether IPM 100 switches to I / F control circuit 125.

[0176] In the third phase ③, the IPM 100 receives an externally transmitted PWM signal and drives the power switch device 130 according to the PWM signal.

[0177] As shown in FIG. 24 , the transmission of an I / F signal from the external controller to the IPM 100 is divided into nine stages.

[0178] In Phase I, when power supply VDD is activated or reset, if IPM 100 is operating normally, signal output terminal 140 (i.e., FO in FIG. 24 ) is at the potential of pull-up resistor 20 external to IPM 100, which is in a high state. If IPM 100 experiences an abnormality, the external controller protects IPM 100 and prevents it from entering the subsequent phases.

[0179] In the second phase II, the external controller detects the potential of the signal output terminal 140. When the signal output terminal 140 is in a high-level state and the IPM 100 needs to be accessed and controlled, the external controller can control the high-level potential of the signal output terminal 140 to a low-level potential, indicating that the external controller has switched to the serial I / F signal transmission state.

[0180] In the third phase III, the external controller inputs the U phase signal to the U phase signal input terminal (i.e., U in FIG. 24). N ) Input CLK signal (ie, CLK signal of serial I / F). Generally, data signal and CLK signal are transmitted synchronously. If the CLK signal is sent multiple times, the I / F signal transmission between the external controller and IPM 100 is not established.

[0181] In the fourth stage IV, the external controller continuously sends the CLK signal and the start command. It should be noted that this stage is optional and can be predetermined.

[0182] In the fifth phase (V), the CLK signal allows the IPM 100 to receive a start command from the external controller. Upon receiving this start command (i.e., the DI signal), the IPM 100 switches to the I / F control circuit and receives the I / F signal. At this point, the DI signal changes. The external controller continues to send the CLK signal and start command, achieving synchronous communication or data output.

[0183] In the sixth stage (VI), when the IPM 100 receives a command from the external controller, it sets the digital output signal (i.e., the DO signal in FIG. 24 ) to an active state, meaning the digital output signal's level changes to a low level. At this point, the IPM 100 outputs a return command. For example, after completing the corresponding processing, the I / F execution circuit 124 of the IPM 100 outputs a return command to the external controller. The IPM 100 can transmit any code (which can be a predetermined code) to the external controller by coordinating the external controller's CLK signal, thereby establishing communication between the IPM 100 and the external controller.

[0184] In the seventh stage (VII), after the serial interface is enabled for communication (i.e., I / F signal transmission is established), the external controller releases the signal output terminal 140, returning the signal output terminal 140 from a low level state to a high level state of the external pull-up resistor 20. At this point, the IPM 100 can set the potential to a low level state to indicate that the interface communication is continuing.

[0185] In Phase VIII, the external controller receives a return command from IPM 100, establishing a serial interface between the external controller and IPM 100. The return data from IPM 100 can be pre-determined for the CLK signal from Phase IV to determine whether synchronous communication is successful. If the return data matches the pre-determined data, synchronous communication is successful.

[0186] In the ninth stage IX, serial interface signal communication is performed between the external controller and the IPM 100 .

[0187] The above process includes signal input and signal output between the external controller and the IPM 100 .

[0188] When the CLK signal is input to U N Phase signal input terminal, signal input terminal 110 (such as U N 、V N and W N Signal input terminals 110 are connected to a circuit serving as a serial bus (i.e., I / F control circuit 125). Signal input terminals 110 enable the transmission of clock signals, digital input signals, and digital output signals between the external controller and IPM 100. It should be noted that in the timing diagram for transmitting PWM and I / F signals, the transmission process for these two signals changes starting in the second phase. Unlike the PWM signal transmission process, during I / F signal transmission, the potential control of the level enables stable I / F signal transmission.

[0189] Of course, in some embodiments, external access and control of the IPM 100 may also include obtaining product information and data such as manufacturing information of the IPM 100 .

[0190] FIG25 is a block diagram of another intelligent power module according to some embodiments. As shown in FIG25 , in addition to the second detection circuit 129, the second switching circuit 126, and the PWM signal input circuit 128, the first integrated circuit 120 also includes a storage circuit 131. The storage circuit 131 is electrically connected to the second switching circuit 126, thereby enabling the storage circuit 131 to be electrically connected to the signal input terminal 110 through the second switching circuit 126.

[0191] Storage circuit 131 is configured to store product information of IPM 100. This product information includes at least one of manufacturing information, circuit information, or test information of IPM 100. Upon receiving an I / F signal, storage circuit 131 is further configured to read the corresponding product information based on the I / F signal and transmit the product information in the form of an I / F signal to an external controller via signal input terminal 110. Here, the I / F signal sent by the external controller is configured to request the product information of IPM 100.

[0192] Manufacturing information can include information about the manufacturing process of the IPM 100. Circuit information can include wafer production lot numbers for circuit components such as the LVIC installed in the IPM 100. Test information can include data on the testing process and results of the IPM 100 on the production line. This allows the cause to be identified based on the IPM 100's product information when quality issues arise. For example, if the IPM 100 malfunctions, operates abnormally, or is damaged, the cause of the problem can be analyzed by referring to the IPM 100's manufacturing information, circuit information, and test information.

[0193] In some embodiments, the data writing range of the product information in the storage circuit 131 can be set according to the actual needs of the IPM 100. For example, the written data includes the power-on time, average current, error content, etc. since the product was powered on.

[0194] The second switching circuit 126 is configured to switch the connection to the storage circuit 131 or the PWM signal input circuit 128 according to the second detection result of the second detection circuit 129; and to receive the I / F signal or PWM signal transmitted by the external controller through the signal input terminal 110, and transmit the I / F signal to the storage circuit 131 or transmit the PWM signal to the PWM signal input circuit 128.

[0195] In some embodiments of the present disclosure, by providing a storage circuit 131 in the IPM 100, utilizing the storage circuit 131 to store product information during the manufacturing process of the IPM 100, and multiplexing the signal output terminal 140 and the signal input terminal 110 of the IPM 100, the transmission of interface signals can be realized, and external access and control of the IPM 100 can be realized without increasing the number of terminals of the IPM 100, thereby meeting the miniature requirements of the IPM 100 and reducing the development cost of the IPM 100.

[0196] Furthermore, the external controller can directly retrieve the product information corresponding to the IPM 100 from the storage circuit 131 without having to retrieve it from the manufacturer of the IPM 100. The manufacturer also does not need to remove the IPM 100 from the product in order to scan the corresponding product information through the barcode of the IPM 100, thereby reducing the time and labor costs for confirming, solving and analyzing problems with the IPM 100.

[0197] It should be noted that the above-mentioned product information (including but not limited to manufacturing information, test information, etc.) and data (including but not limited to data used for analysis, storage data, display data, etc.) are information and data authorized by users or manufacturers or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of the relevant regions, and corresponding operation entrances must be provided for users to choose to authorize or refuse.

[0198] It is understood that when the IPM 100 is operating normally (i.e., the signal output terminal 140 does not output the circuit protection signal), the storage circuit 131 does not operate, and the IPM 100 receives the PWM signal transmitted from the external controller through the signal input terminal 110 and controls the power switch device 130 to drive the corresponding component (such as a motor or compressor). By serially switching between the PWM signal input circuit 128 and the storage circuit 131, it is possible to achieve the external interface function while avoiding affecting the original PWM signal input of the IPM 100. In addition, it is also possible to provide a new terminal in the IPM 100 to communicate with the storage circuit 131 to achieve external access and control of the IPM 100. For example, as shown in Figure 26, the IPM 100 includes a preset terminal 190, which is connected to the storage circuit 131 for communication.

[0199] In some embodiments, the I / F signal input by the external controller to the IPM 100 may also include a data write request. This data write request carries the data to be written. For example, the data to be written may include current operating data or other data. In this case, upon receiving the corresponding I / F signal, the storage circuit 131 may write the corresponding data. This allows the storage circuit 131 to retrieve the corresponding data for analysis and processing if any issues arise during subsequent product operation, thereby improving the performance of the IPM 100.

[0200] Signal input terminals 110 may include a U-phase signal input terminal, a V-phase signal input terminal, and a W-phase signal input terminal. These three-phase signal input terminals can be used to transmit clock signals, digital input signals, and digital output signals. Here, the digital output signal can be understood as the IPM 100 transmitting product information to an external controller in the form of an I / F signal. The structure and function of signal input terminals 110 can be found in the relevant content above and will not be repeated here.

[0201] In this case, the storage circuit 131 can be a three-wire serial circuit to receive the clock signal and I / F signal (e.g., DI signal) transmitted from the corresponding signal input terminal, and output the I / F signal (e.g., DO signal) through the corresponding signal input terminal. In this case, the contents of the corresponding stages in Figures 23 and 24 remain substantially unchanged, with only the relevant contents changing from switching to the I / F control circuit 125 to switching to the storage circuit 131.

[0202] In some embodiments, as shown in FIG27 , the first integrated circuit 120 in FIG25 further includes a protection circuit 127. The protection circuit 127 is electrically connected to the signal output terminal 140 and the second detection circuit 129. The structure and function of the protection circuit 127 can be found in the relevant content above and will not be repeated here.

[0203] 28 , the storage circuit 131 may be a non-volatile memory (NVM) to allow an external controller to access product information stored in the IPM 100. A non-volatile memory is a memory that does not lose stored data after a power outage.

[0204] In some embodiments, the storage circuit 131 may be a non-volatile flash memory. Non-volatile flash memory is a type of non-volatile memory. In non-volatile memory, products can be divided into two major categories (i.e., read-only memory (ROM) and flash memory) based on whether the data in the memory can be rewritten at any time during use. Non-volatile flash memory is the flash memory in NVM. Here, flash memory is an electronically erasable programmable read-only memory that allows it to be erased or written multiple times during operation. Flash memory is a special electrically erasable programmable read-only memory (EEPROM) that is erased and written in macroblocks to facilitate data transmission between the external controller and the IPM 100.

[0205] It is understandable that the above-mentioned multiple embodiments of the IPM 100 can be combined or separated with each other, and will not be described in detail here.

[0206] In some embodiments, as shown in Figures 29A, 29B, and 29C, IPM 100 further includes a second integrated circuit 150. The first integrated circuit 120 and the second integrated circuit 150 are assembled using a lead frame. The power ground terminal VNC1 of the second integrated circuit 150 is connected to the power ground terminal VNC2 of the first integrated circuit 120. The first integrated circuit 120 may be a low-voltage integrated circuit, and the second integrated circuit 150 may be a high-voltage integrated circuit.

[0207] In some embodiments, the IPM 100 may further include multiple low-voltage integrated circuits and multiple high-voltage integrated circuits. That is, the IPM 100 may further include multiple first integrated circuits 120 and multiple second integrated circuits 150. Those skilled in the art may adaptably set the number of LVICs and HVICs based on actual applications.

[0208] Some embodiments of the present disclosure also provide an electronic device. As shown in Figures 30 and 31, the electronic device 300 includes an intelligent power module 100 and an external controller 200 electrically connected to the intelligent power module 100. The structure and function of the IPM 100 are similar to those of the IPM 100 described above and will not be further described here. The external controller 200 is configured to transmit an I / F signal or a PWM signal to the IPM 100.

[0209] For example, external controller 200 inputs a PWM signal to IPM 100. This PWM signal is used to turn the IGBTs on and off to drive the motor on and off. The PWM signal controls the on and off times of the IGBTs in IPM 100 by varying the duty cycle, thereby controlling the current flowing through the IGBTs. When the PWM signal's duty cycle is high, the IGBTs conduct a large amount of current. When the PWM signal's duty cycle is low, the IGBTs conduct a small amount of current.

[0210] In some embodiments, the external controller 200 is electrically connected to the signal output terminal 140 of the IPM 100 to transmit an I / F signal or a PWM signal to the IPM 100 according to a signal output from the signal output terminal 140 .

[0211] In some embodiments, the external controller 200 is also electrically connected to the signal input terminal 110 and is configured to control the high-level signal of the signal output terminal 140 to a low-level signal when there is an I / F transmission requirement and the signal output terminal 140 does not transmit a circuit protection signal, and transmit the I / F signal to the IPM 100 through the signal input terminal 110.

[0212] It should be noted that the structure and function of the external controller 200 can be found in the relevant content above and will not be described in detail here.

[0213] In household appliances such as air conditioners and washing machines, an external controller 200 can control the entire device. By multiplexing the existing signal input and output terminals of the IPM 100 and, when the signal output terminals output corresponding level signals, using the signal input terminals to transmit I / F signals to the IPM 100, the IPM 100 can have I / F functionality. Furthermore, while maintaining the specifications and circuit compatibility of the IPM 100, the external controller 200 can perform detailed control of the IPM 100. Some embodiments of the present disclosure also provide a control method for an intelligent power module. This method is applied to the aforementioned intelligent power module 100.

[0214] As shown in FIG32 , the method includes step 101 and step 102 .

[0215] In step 101, a first detection circuit receives a PWM signal transmitted from an external controller to the IPM 100 via a signal input terminal and detects a current variation region based on the PWM signal. The current variation region includes a first current region within a preset threshold range and a second current region outside the preset threshold range.

[0216] In step 102, the first switching circuit receives a first detection result from the first detection circuit and a PWM signal transmitted by an external controller to the IPM 100 via a signal input terminal. When the first detection result indicates a first current range, the first switching circuit switches the gate resistor to a first resistance mode, and controls the power switch device to be turned on or off according to the PWM signal in the first resistance mode. Alternatively, when the first detection result indicates a second current range, the first switching circuit switches the gate resistor to a second resistance mode, and controls the power switch device to be turned on or off according to the PWM signal in the second resistance mode. The resistance of the gate resistor in the first resistance mode is greater than the resistance of the gate resistor in the second resistance mode.

[0217] It should be noted that the principle and technical effect of this method are similar to those of the intelligent power module 100 described above, and will not be repeated here. In addition, the structure and function of the external controller can be found in the relevant content above, and will not be repeated here.

[0218] Some embodiments of the present disclosure further provide a method for controlling an intelligent power module. The method is applied to the external controller 200 described above. As shown in FIG33 , the method includes step 201.

[0219] In step 201, an I / F signal or a PWM signal is transmitted to a signal input terminal of an IPM. The I / F signal is configured to control the I / F execution circuit of the IPM to perform corresponding processing on the I / F signal. The PWM signal is configured to control the on or off of a power switching device.

[0220] When the protection circuit does not generate a circuit protection signal, the level signal output by the signal output terminal to the external controller 200 is a high-level signal. The external controller 200 can switch to the I / F function by controlling the high-level signal to a low-level signal. If the high-level signal is not controlled, the IPM performs normal PWM signal transmission. If the high-level signal is controlled to a low-level signal, the IPM switches the I / F function, and the external controller 200 transmits the I / F signal to the IPM. It should be noted that when the signal output terminal of the IPM receives the circuit protection signal output by the protection circuit, it outputs a low-level signal to the external controller 200. At this time, the external controller 200 performs corresponding circuit protection processing. For example, the external controller 200 stops the input of the PWM signal and does not transmit the I / F signal.

[0221] In some embodiments, as shown in FIG34 , step 201 includes step 2011 .

[0222] In step 2011 , before transmitting the I / F signal to the signal input terminal, when the signal output terminal of the IPM is in a high level state, the signal output terminal is controlled from a high level state to a low level state.

[0223] It should be noted that the principles and technical effects of this method are similar to those of the IPM 100 or electronic device described above. Furthermore, this method can implement the interaction process between all structures in the IPM 100 or electronic device described above, and can achieve the same technical effects. Furthermore, the IPM in the above method has similar structure and functions to the IPM 100 described above, and will not be further described here.

[0224] Some embodiments of the present disclosure further provide a method for controlling an intelligent power module. The method is applied to the external controller 200 described above. As shown in FIG35 , the method includes steps 301 and 302 .

[0225] In step 301, an I / F signal is transmitted to a signal input terminal of an IPM. The I / F signal is configured to request product information of the IPM, the product information including at least one of manufacturing information, circuit information, or test information of the IPM.

[0226] In step 302 , product information is read by the storage circuit according to the I / F signal and transmitted in the form of the I / F signal through the signal input terminal.

[0227] In some embodiments, as shown in FIG36 , step 301 also includes step 3011 .

[0228] In step 3011 , when the signal transmitted by the signal input terminal is an I / F signal and the signal output terminal of the IPM is in a high level state, the signal output terminal is controlled from the high level state to the low level state.

[0229] When controlling the signal output terminal from a high level state to a low level state, the external controller 200 transmits an I / F signal to the signal input terminal of the IPM.

[0230] In some embodiments, as shown in FIG37 , the method may further include step 303 .

[0231] In step 303, when the signal output terminal of the IPM is in a high level state, a PWM signal is transmitted to the signal input terminal of the IPM. The PWM signal is configured to control the on or off of the power switching device of the IPM.

[0232] It should be noted that the principles and technical effects of this method are similar to those of the IPM 100 or electronic device described above. Furthermore, this method can implement the interaction process between all structures in the IPM 100 or electronic device described above, and can achieve the same technical effects. Furthermore, the IPM in the above method has similar structure and functions to the IPM 100 described above, and will not be further described here.

[0233] The description of the steps in the figures of some embodiments of the present disclosure in a specific order does not require or imply that the steps must be performed in that specific order, or that all steps must be performed to achieve the desired result. Additional steps may be added to the steps in the figures, some steps may be omitted, multiple steps may be combined into one step, or one step may be broken down into multiple steps.

[0234] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0235] Those skilled in the art will understand that the scope of the present disclosure is not limited to the above specific embodiments, and that certain elements of the embodiments may be modified and replaced without departing from the spirit of the present disclosure. The scope of the present disclosure is limited by the appended claims.

Claims

1. An intelligent power module, comprising: A signal input terminal is configured to receive a pulse width modulation (PWM) signal input from an external controller; Power switching devices; as well as A first integrated circuit comprising: a first detection circuit, electrically connected to the signal input terminal and configured to receive a PWM signal transmitted by the signal input terminal and detect a current change region according to the PWM signal; wherein the current change region includes a first current region within a preset threshold range or a second current region outside the preset threshold range; and A first switching circuit is electrically connected to the signal input terminal, the first detection circuit and the power switch device respectively, and the first switching circuit is configured as follows: receiving a first detection result of the first detection circuit and the PWM signal transmitted by the signal input terminal; When the first detection result is the first current region, switching the gate resistance to a first resistance mode, and controlling the on or off of the power switch device according to the PWM signal in the first resistance mode; or When the first detection result is the second current region, switching the gate resistor to a second resistance mode, and controlling the on or off of the power switch device according to the PWM signal in the second resistance mode; Wherein, the resistance value of the gate resistor in the first resistance mode is greater than the resistance value of the gate resistor in the second resistance mode.

2. The intelligent power module according to claim 1, wherein: The first integrated circuit also includes a buffer circuit, an input end of the buffer circuit is electrically connected to the signal input terminal, and an output end of the buffer circuit is respectively connected to the first detection circuit and the first switching circuit, and the buffer circuit is configured to receive the PWM signal transmitted by the signal input terminal and cache the PWM signal to transmit the PWM signal to the first detection circuit and the first switching circuit respectively.

3. The intelligent power module according to claim 2, wherein: The first switching circuit comprises: a first sub-switching circuit, wherein an input end of the first sub-switching circuit is connected to the buffer circuit, an output end of the first sub-switching circuit is electrically connected to the second sub-switching circuit, and the first sub-switching circuit is configured to receive the PWM signal and switch to the first gate resistor or the second gate resistor according to the PWM signal; The second sub-switching circuit includes the first gate resistor and the second gate resistor; and A third sub-switching circuit, wherein a first input terminal of the third sub-switching circuit is electrically connected to a wire between the first gate resistor and the second gate resistor, a second input terminal of the third sub-switching circuit is electrically connected to the first detection circuit, and an output terminal of the third sub-switching circuit is connected to the power switch device; the third sub-switching circuit comprises a third gate resistor and a load switch, and the load switch is connected in parallel with the third gate resistor; the third sub-switching circuit is configured as follows: receiving a first detection result of the first detection circuit; When the first detection result is the first current region, controlling the load switch to be disconnected to switch to a first resistance mode in which the resistance value of the gate resistor is the sum of the first gate resistor and the third gate resistor, or a first resistance mode in which the resistance value of the gate resistor is the sum of the second gate resistor and the third gate resistor; or When the first detection result is the second current region, the load switch is controlled to be turned on to switch to a second resistance mode corresponding to a resistance value of the gate resistor being the first gate resistor or a resistance value of the gate resistor being the second gate resistor.

4. The intelligent power module according to claim 3, wherein: The first sub-switching circuit comprises: an inverter, wherein an input end of the inverter is electrically connected to the buffer circuit, and an output end of the inverter is respectively connected to a Positive Channel Metal Oxide Semiconductor (PMOS) and an N-type metal oxide semiconductor (NMOS), wherein the inverter is configured to receive a PWM signal transmitted by the buffer circuit, and invert a high level signal or a low level signal corresponding to the PWM signal and output it to the PMOS or the NMOS, so as to turn on the PMOS and switch to the first gate resistor, or turn on the NMOS and switch to the second gate resistor; The PMOS, the gate of the PMOS is electrically connected to the output end of the inverter and the gate of the NMOS respectively, the source of the PMOS is electrically connected to a power supply, and the drain of the PMOS is electrically connected to the drain of the NMOS via the first gate resistor and the second gate resistor in sequence; and The NMOS has a gate electrically connected to the inverter and a source connected to the ground.

5. The intelligent power module according to any one of claims 1 to 4, wherein: The signal input terminal includes a U-phase signal input terminal, a V-phase signal input terminal and a W-phase signal input terminal; the PWM signal includes a U-phase signal, a V-phase signal and a W-phase signal.

6. The intelligent power module according to claim 5, wherein: The first detection circuit comprises: a comparison circuit configured to compare any two phase signals among the U-phase signal, the V-phase signal and the W-phase signal to obtain an interphase signal between any two phase signals; and A logic circuit is connected to the comparison circuit and is configured to receive the interphase signal output by the comparison circuit, and determine the interphase voltages corresponding to the U-phase signal, the V-phase signal and the W-phase signal respectively according to the interphase signal, and determine the current change area corresponding to each phase signal according to the interphase voltage.

7. The intelligent power module according to claim 6, wherein: The comparison circuit comprises: a first comparator, wherein the input end of the first comparator is respectively connected to the U-phase signal input terminal and the V-phase signal input terminal, the output end of the first comparator is connected to a first XNOR gate and a second XNOR gate, the first comparator is configured to compare the U-phase signal inputted from the U-phase signal input terminal and the V-phase signal inputted from the V-phase signal input terminal to obtain a first interphase signal between the U-phase signal and the V-phase signal, and input the first interphase signal to the first XNOR gate and the second XNOR gate; a second comparator, wherein input terminals of the second comparator are respectively connected to the U-phase signal input terminal and the W-phase signal input terminal, output terminals of the second comparator are respectively connected to the first XNOR gate and the third XNOR gate, the second comparator is configured to compare the U-phase signal inputted from the U-phase signal input terminal and the W-phase signal inputted from the W-phase signal input terminal to obtain a second interphase signal between the U-phase signal and the W-phase signal, and input the second interphase signal to the first XNOR gate and the third XNOR gate; and a third comparator, wherein the input terminals of the third comparator are respectively connected to the V-phase signal input terminal and the W-phase signal input terminal, and the output terminals of the third comparator are respectively connected to the second XNOR gate and the third XNOR gate, and the third comparator is configured to compare the V-phase signal inputted from the V-phase signal input terminal and the W-phase signal inputted from the W-phase signal input terminal to obtain a third interphase signal between the V-phase signal and the W-phase signal, and input the third interphase signal to the second XNOR gate and the third XNOR gate; The logic circuit comprises: The first XNOR gate, the input end of the first XNOR gate is respectively connected to the first comparator and the second comparator, the output end of the first XNOR gate is connected to the first switching circuit, the first XNOR gate is configured to determine the phase-to-phase voltage of the U-phase signal according to the first phase-to-phase signal and the second phase-to-phase signal, and determine the current change region corresponding to the U-phase signal according to the phase-to-phase voltage of the U-phase signal, so as to output the first detection result to the first switching circuit; the second XNOR gate, the input terminals of the second XNOR gate are respectively connected to the first comparator and the third comparator, the output terminal of the second XNOR gate is connected to the first switching circuit, the second XNOR gate is configured to determine the phase-to-phase voltage of the V-phase signal according to the first phase-to-phase signal and the third phase-to-phase signal, and determine the current change region corresponding to the V-phase signal according to the phase-to-phase voltage of the V-phase signal, so as to output the first detection result to the first switching circuit; and The third XNOR gate, the input ends of the third XNOR gate are respectively connected to the second comparator and the third comparator, the output end of the third XNOR gate is connected to the first switching circuit, and the third XNOR gate is configured to determine the phase-to-phase voltage of the W-phase signal according to the second phase-to-phase signal and the third phase-to-phase signal, and determine the current change area corresponding to the W-phase signal according to the phase-to-phase voltage of the W-phase signal, so as to output the first detection result to the first switching circuit.

8. The intelligent power module according to claim 7, wherein: The comparison circuit further includes a diode and a capacitor corresponding to the first comparator, the second comparator and the third comparator respectively; The input end of the diode is connected to the output end of the corresponding comparator, and the output end of the diode is connected to the corresponding XOR gate; An input end of the capacitor is connected to a wire between a corresponding diode and a corresponding XOR gate, and an output end of the capacitor is grounded.

9. An electronic device, comprising: An intelligent power module, which is an intelligent power module as claimed in any one of claims 1 to 8; as well as The external controller is electrically connected to the intelligent power module and is configured to transmit a PWM signal or an I / F signal to the intelligent power module.

10. A control method for an intelligent power module, wherein: The intelligent power module comprises: A signal input terminal is configured to receive a PWM signal input from an external controller; Power switching devices; and A first integrated circuit comprising: A first detection circuit electrically connected to the signal input terminal; and A first switching circuit is electrically connected to the signal input terminal, the first detection circuit and the power switch device respectively; The method comprises: The first detection circuit receives a PWM signal transmitted by the external controller to the intelligent power module through the signal input terminal, and detects a current change region according to the PWM signal; the current change region includes a first current region within a preset threshold range and a second current region outside the preset threshold range; and The first switching circuit receives a first detection result of the first detection circuit and a PWM signal transmitted by the external controller to the intelligent power module through the signal input terminal; when the first detection result is the first current region, the gate resistance is switched to a first resistance mode, and the power switch device is controlled to be turned on or off according to the PWM signal in the first resistance mode; or, when the first detection result is the second current region, the gate resistance is switched to a second resistance mode, and the power switch device is controlled to be turned on or off according to the PWM signal in the second resistance mode; the resistance value of the gate resistance in the first resistance mode is greater than the resistance value of the gate resistance in the second resistance mode.

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