Array substrate and display panel

Abstract

An array substrate, comprising a base substrate and a driving circuit layer. The driving circuit layer comprises a plurality of column symmetric units arranged in a first direction and a plurality of first power lines extending in a second direction; each column symmetric unit comprises two columns of pixel circuits, and each column of pixel circuits comprises a plurality of pixel circuits arranged in the second direction; in the column symmetric unit, the two columns of pixel circuits are symmetrical about a first center line; the orthographic projection of each first power line on the base substrate is located within a first boundary extension line and a second boundary extension line of the orthographic projection of a column symmetric unit on the base substrate, and the first boundary extension line and the second boundary extension line are two boundary extension lines of the orthographic projection of the column symmetric unit on the base substrate that opposite in the first direction; at least some of the first power lines are connected, in the column symmetric units, to the two columns of pixel circuits in the column symmetric units.

Description

Array substrate and display panel

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 31, 2023, with application number 202310954273.9. The entire contents of the above application are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of display technology, for example, to an array substrate and a display panel. Background Art

[0003] With the development of display technology, high pixel density has become a development trend.

[0004] The display panel includes an array substrate, and the array substrate includes a pixel circuit. To ensure the display performance of the display panel, the pixel circuit included in the display panel includes more circuit devices.

[0005] There are many devices in the pixel circuit, which makes the topological area occupied by the pixel circuit larger, which is not conducive to the realization of high pixel density.

[0006] Summary of the Invention

[0007] The present application provides an array substrate to improve the compactness of pixel circuits and wiring in a display panel, thereby increasing pixel density, which is beneficial to improving the resolution of the display panel.

[0008] The present application provides an array substrate, comprising:

[0009] a substrate and a driving circuit layer on one side of the substrate;

[0010] The driving circuit layer includes a plurality of column symmetrical units arranged along a first direction and a plurality of first power lines extending along a second direction;

[0011] Each column-symmetrical unit includes two columns of pixel circuits, each column of pixel circuits includes a plurality of pixel circuits arranged along the second direction; the first direction and the second direction intersect; wherein, in the column-symmetrical unit, the two columns of pixel circuits are symmetrical about a first center line, and the first center line is a center line of the column-symmetrical unit extending along the second direction;

[0012] The orthographic projection of the first power line on the substrate is located within the first boundary extension line and the second boundary extension line of the orthographic projection of the column-symmetric unit on the substrate, and the first boundary extension line and the second boundary extension line are two boundary extension lines of the orthographic projection of the column-symmetric unit on the substrate that are opposite to each other in the first direction; wherein, at least part of the first power lines connects two columns of pixel circuits in the column-symmetric unit within the column-symmetric unit.

[0013] An embodiment of the present application further provides a display panel, comprising any array substrate as described above.

[0014] The array substrate and display panel of the embodiments of the present application are configured such that the driving circuit layer includes a plurality of column-symmetrical units, wherein the two columns of pixel circuits in the column-symmetrical units are symmetrical about a first center line. The symmetrical structure of the pixel circuits in the column-symmetrical units can make the arrangement of the pixel circuits in the array substrate more compact, and when the pixel circuits include the same number of circuit components, the pixel density of the display panel can be increased. The two columns of pixel circuits in the column-symmetrical units are symmetrically arranged, and a first power line connects the two symmetrical columns of pixel circuits in the column-symmetrical units. This can reduce the number of first power lines in the display panel, thereby saving wiring space and facilitating an increase in pixel density. Furthermore, the orthographic projection of the first power line on the substrate is located within the first and second extension lines of the orthographic projection of the corresponding column-symmetrical unit on the base, so that the additional planar area occupied by the first power line relative to the column-symmetrical unit is smaller, further improving the compactness of the pixel circuits and signal lines in the display panel and facilitating an increase in pixel density. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] FIG1 is a schematic structural diagram of a pixel circuit;

[0016] FIG2 is a top view of a display panel provided in an embodiment of the present application;

[0017] FIG3 is a cross-sectional view of a display panel provided in an embodiment of the present application;

[0018] FIG4 is a top view of an array substrate provided in an embodiment of the present application;

[0019] FIG5 is a top view of a partial film layer structure in the array substrate shown in FIG4 ;

[0020] FIG6 is a top view of another array substrate provided in an embodiment of the present application;

[0021] FIG7 is a top view of another partial film layer structure in the array substrate shown in FIG4 ;

[0022] FIG8 is a schematic structural diagram of a power line connection portion;

[0023] FIG9 is a schematic structural diagram of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The present application is described below in conjunction with the accompanying drawings and embodiments. The specific embodiments described herein are merely intended to explain the present application and are not intended to limit the present application. For ease of description, the accompanying drawings only show portions relevant to the present application, not all structures.

[0025] Figure 1 is a schematic diagram of the structure of a pixel circuit. Taking the pixel circuit shown in Figure 1 as an example, to ensure the display performance of the display panel, the pixel circuit typically includes a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first initialization transistor T4 configured to initialize the gate of the driving transistor T1, a second initialization transistor T5 configured to initialize the anode of the light-emitting device, a first light-emission control transistor T6, a second light-emission control transistor T7, and a storage capacitor Cst. As a result, the pixel circuit includes too many circuit components (including transistors and capacitors), and the circuit components are arranged loosely, making it difficult to achieve high pixel density.

[0026] An embodiment of the present application provides an array substrate, which can be used in a display panel. Figure 2 is a top view of a display panel provided by an embodiment of the present application, and Figure 3 is a cross-sectional view of a display panel provided by an embodiment of the present application, and Figure 3 can be obtained by cutting along the section line AA' corresponding to Figure 2. Referring to Figures 2 and 3, the array substrate includes: a substrate 100 and a driving circuit layer 200 on one side of the substrate 100; the driving circuit layer 200 includes column-symmetrical units 210 arranged along a first direction x, each column-symmetrical unit 210 includes two columns of pixel circuits 211, and each column of pixel circuits 211 includes a plurality of pixel circuits 211 arranged along a second direction y; the first direction x and the second direction y intersect; wherein, in the column-symmetrical unit 210, the two columns of pixel circuits 211 are symmetrical about the first center line L1, and the first center line L1 is the center line of the column-symmetrical unit 210 extending along the second direction y.

[0027] The driving circuit layer 200 further includes a plurality of first power lines 220 extending along the second direction y. The orthographic projections of the first power lines 220 on the substrate 100 are located within a first boundary extension line H1 and a second boundary extension line H2 of the orthographic projection of the column-symmetric unit 210 on the substrate 100. The first boundary extension line H1 and the second boundary extension line H2 are two opposite boundary extension lines of the orthographic projection of the column-symmetric unit 210 on the substrate 100 in the first direction x. At least some of the first power lines 220 connect two columns of pixel circuits 211 within the column-symmetric unit 210.

[0028] Substrate 100 can provide cushioning, protection, or support for the display device. Substrate 100 can be a flexible substrate made of materials such as polyimide (PI), polyethylene naphthalate diformic acid glycol ester (PEN), or polyethylene terephthalate (PET), or a mixture of these materials. Substrate 100 can also be a rigid substrate made of materials such as glass.

[0029] The driving circuit layer 200 may include an active layer located on one side of the substrate 100 and multiple metal layers stacked on the side of the active layer away from the substrate 100. The driving circuit layer 200 includes various driving circuits. Corresponding to the display area of ​​the display panel, the driving circuit layer 200 includes pixel circuits 211 arranged in an array. Corresponding to the non-display area of ​​the display panel, the driving circuit layer 200 includes a frame circuit, which may include a gate drive circuit, a multiplexing circuit, and the like. The array substrate also includes multiple scan lines and multiple data lines, where the scan lines and data lines extend in intersecting directions. Within the driving circuit layer 200, the pixel circuits 211 are arranged symmetrically. Exemplarily, the driving circuit layer 200 includes multiple column-symmetrical units 210, which are arranged along a first direction x, where the first direction x can be the direction in which the scan lines extend. The column-symmetrical units 210 include two columns of pixel circuits 211, which are symmetrical about the first centerline L1. The symmetrical structure of the pixel circuits 211 in the column symmetrical unit 210 can make the arrangement of the pixel circuits 211 in the array substrate more compact. When the pixel circuits 211 include the same number of circuit devices, the pixel density of the display panel can be higher.

[0030] The driving circuit layer 200 further includes a plurality of first power lines 220 extending along the second direction y. In some optional embodiments of the present application, the first power lines 220 correspond one-to-one to the column-symmetrical units 210. In this case, the number of first power lines 220 in the array substrate is equal to the number of column-symmetrical units 210. Exemplarily, each first power line 220 is connected to a power supply voltage. For the pixel circuit 211 shown in FIG1 , the first power lines 220 connected to the column-symmetrical units 210 are connected to the power supply voltage input terminals of the two columns of pixel circuits 211. The orthographic projection of the first power line 220 on the substrate 100 is located within the first boundary extension line H1 and the second boundary extension line H2 of the orthographic projection of the corresponding column symmetrical unit 210 on the substrate 100. The first boundary extension line H1 and the second boundary extension line H2 are two boundary extension lines of the orthographic projection of the column symmetrical unit 210 on the substrate 100 that are opposite in the first direction x. This arrangement can reduce the additional planar area occupied by the first power line 220 relative to the column symmetrical unit 210, further improving the compactness of the pixel circuit 211 and the signal line in the display panel. Referring to Figure 2, the first boundary extension line H1 can be the orthographic projection of the line parallel to the second direction y where the outermost point of the first side of the column symmetric unit 210 in the first direction x is located on the substrate 100, or the line parallel to the second direction y where the outermost point of the first side in the first direction x is located in the orthographic projection of the column symmetric unit 210 on the substrate 100; the second boundary extension line H2 can be the orthographic projection of the line parallel to the second direction y where the outermost point of the second side in the first direction x is located on the substrate 100, or the line parallel to the second direction y where the outermost point of the second side in the first direction x is located in the orthographic projection of the column symmetric unit 210 on the substrate 100.

[0031] At least a portion of the first power line 220 connects the two columns of pixel circuits 211 of the column-symmetrical unit 210 within the column-symmetrical unit 210, wherein the first power line 220 connects the two columns of pixel circuits 211 of the column-symmetrical unit 210 within the column-symmetrical unit 210. This can be understood as follows: the connection point between the first power line 220 and the two columns of pixel circuits 211 in the column-symmetrical unit 210 is located within the orthographic projection of the column-symmetrical unit 210 on the substrate 100. Alternatively, this can be understood as follows: the connection point between the first power line 220 and the two columns of pixel circuits 211 in the column-symmetrical unit 210 is surrounded by the outer contour of the orthographic projection of the column-symmetrical unit 210 on the substrate 100, wherein the outer contour of the orthographic projection of the column-symmetrical unit 210 on the substrate 100 is a figure enclosed by the first boundary, the second boundary in the first direction x, and the third boundary and the fourth boundary in the second direction y in the orthographic projection of the column-symmetrical unit 210 on the substrate 100 (specifically, it can be understood as a figure enclosed by the four boundaries of top, bottom, left, and right). Because the first power line 220 extends along the second direction y, and because the two columns of pixel circuits 211 in the column symmetrical unit 210 are symmetrically arranged, one first power line 220 connects the two symmetrical columns of pixel circuits 211 in the column symmetrical unit 210. For example, the connection points between the two pixel circuits 211 in the same row in the column symmetrical unit 210 and the first power line 220 can be set at the same position. For example, the connection points between the two pixel circuits 211 in the same row in the column symmetrical unit 210 and the first power line 220 are set on the first center line L1, so that the first power line 220 can be connected to the two pixel circuits 211 in the same row in the column symmetrical unit 210 at the same connection point; compared with a display panel in which one column of pixel circuits 211 is connected to one first power line 220, the number of first power lines 220 in the display panel can be reduced, thereby saving wiring space and being conducive to improving pixel density.

[0032] Optionally, the second center line L2 of the first power line 220 coincides with the first center line L1, the first power line 220 is symmetrical about the second center line L2, and the second center line L2 is the center line of the first power line 220 extending along the second direction y; such a setting can ensure that when the first power line 220 is connected to the two columns of pixel circuits 211 of the column symmetrical unit 210, the length of the connecting line between the first power line 220 and the two columns of pixel circuits 211 is relatively consistent, ensuring that the voltage drop when the first power line 220 transmits voltage to the two columns of pixel circuits 211 is relatively consistent, so that the display uniformity is better.

[0033] The array substrate of the embodiment of the present application comprises a plurality of column-symmetrical units by providing a driving circuit layer, wherein two columns of pixel circuits in the column-symmetrical units are symmetrical about a first center line. The design of the symmetrical structure of the pixel circuits in the column-symmetrical units can make the arrangement of the pixel circuits in the array substrate more compact. When the pixel circuits include the same number of circuit components, the pixel density of the display panel can be increased. The two columns of pixel circuits in the column-symmetrical units are symmetrically arranged, and a first power line connects the two symmetrical columns of pixel circuits in the column-symmetrical units. This can reduce the number of first power lines in the display panel, thereby saving wiring space and facilitating an increase in pixel density. Furthermore, the orthographic projection of the first power line on the substrate is within the first and second boundary extension lines of the orthographic projection of the corresponding column-symmetrical unit on the base, so that the additional planar area occupied by the first power line relative to the column-symmetrical unit is smaller, further improving the compactness of the pixel circuits and signal lines in the display panel, and facilitating an increase in pixel density.

[0034] It is understood that the first direction x and the second direction y in the present application can be arranged perpendicular to each other. Figure 4 is a top view of an array substrate provided in an embodiment of the present application, Figure 5 is a top view of a partial film layer structure in the array substrate shown in Figure 4, and Figure 6 is a top view of another array substrate provided in an embodiment of the present application. Referring to Figures 4-6, the driving circuit layer 200 optionally further includes a plurality of first initialization signal lines Vref1 extending along the first direction x, and each row of pixel circuits 211 arranged along the first direction x is connected to a corresponding first initialization signal line Vref1.

[0035] The pixel circuit shown in Figure 1 includes a driving transistor T1 and a light-emitting device, the first electrode of the light-emitting device is electrically connected to the driving transistor T1, and the second electrode of the light-emitting device is connected to a fixed voltage; the pixel circuit 211 also includes a first initialization transistor T4 and / or a second initialization transistor T5, the first initialization transistor T4 is electrically connected to the gate of the driving transistor T1, and is configured to initialize the gate of the driving transistor T1; the second initialization transistor T5 is electrically connected to the first electrode of the light-emitting device, and is configured to initialize the first electrode of the light-emitting device; the first initialization signal line Vref1 is electrically connected to the first initialization transistor T4 and / or the second initialization transistor T5.

[0036] In some optional embodiments of the present application, the pixel circuit 211 may also include only the first initialization transistor T4 but not the second initialization transistor T5; or may also include only the second initialization transistor T5 but not the first initialization transistor T4. In this embodiment, when the pixel circuit 211 includes the first initialization transistor T4, the first initialization signal line Vref1 is electrically connected to the first initialization transistor T4; when the pixel circuit 211 includes the second initialization transistor T5, the first initialization signal line Vref1 is electrically connected to the second initialization transistor T5; when the pixel circuit 211 includes the first initialization transistor T4 and the second initialization transistor T5, the first initialization signal line Vref1 is electrically connected to the first initialization transistors T4 in a row of pixel circuits 211 and to the second initialization transistors T5 in a row of pixel circuits 211, and the first initialization signal line Vref1 is configured to transmit an initialization voltage to the corresponding connected pixel circuits 211. Exemplarily, the first initialization signal line Vref1 can be connected to the initialization signal input terminal Vref in the pixel circuit 211.

[0037] 4 and 5 , optionally, the driving circuit layer 200 further includes a plurality of second initialization signal lines Vref2 extending along the second direction y, and the first initialization signal lines Vref1 and the second initialization signal lines Vref2 are interconnected in a mesh shape.

[0038] By setting the driving circuit layer 200 to also include multiple second initialization signal lines Vref2, the second initialization signal lines Vref2 and the first initialization signal lines Vref1 are interconnected to form a mesh, so that compared with only setting the first initialization signal line Vref1, the resistance of the second initialization signal lines Vref2 and the first initialization signal lines Vref1 connected to each other is smaller, so that the voltage drop during the transmission of the initialization signal is smaller, which is beneficial to improving the display effect.

[0039] Optionally, the orthographic projection of the second initialization signal line Vref2 on the substrate 100 is located within the first boundary extension line H1 and the second boundary extension line H2 of the orthographic projection of the column symmetric unit 210 on the substrate 100, so that the additional planar area occupied by the second initialization signal line Vref2 relative to the column symmetric unit 210 is smaller, further improving the compactness of the pixel circuits and signal lines in the display panel. For the display panel shown in Figure 4, the outermost device in the first direction x of the multiple column symmetric units 210 arranged along the first direction x is the data write transistor T2 in the outermost column of pixel circuits 211 in the outermost column symmetric unit 210. Accordingly, the outermost point of the column symmetric unit 210 in the first direction x is at least one of the active layer, gate, source lead structure, and drain lead structure of the data write transistor T2. Figure 4 schematically shows that the outermost point of the column symmetric unit 210 in the first direction x is the source lead structure of the data write transistor T2. The first boundary extension line H1 is an edge of the source lead-out structure of the data write transistor T2 extending along the second direction y (the edge is the outermost edge of the source lead-out structure along the first side in the first direction x) in one column of the pixel circuits 211 in the column symmetric unit 210, and the second boundary extension line H2 is an edge of the source lead-out structure of the data write transistor T2 extending along the second direction y (the edge is the outermost edge of the source lead-out structure along the second side in the first direction x) in the other column of the pixel circuits 211 in the column symmetric unit 210.

[0040] In some optional embodiments of the present application, a second initialization signal line Vref2 is provided for every at least one column symmetrical unit 210. In this way, on the one hand, the first initialization signal line Vref1 and the second initialization signal line Vref2 can be interconnected to form a mesh structure to reduce transmission resistance. On the other hand, the density of the second initialization signal line Vref2 can be reduced, reducing the total area occupied by the second initialization signal line Vref2, which is more conducive to improving pixel density. Figures 4 and 5 schematically illustrate the situation where a second initialization signal line Vref2 is provided for every other column symmetrical unit 210. For example, along the first direction x, the 2n-1th column symmetrical unit 210 is provided with a second initialization signal line Vref2, and the 2nth column symmetrical unit 210 is not provided with a second initialization signal line Vref2, where n is a positive integer greater than or equal to 1.

[0041] 4 and 5 , the first initialization signal line Vref1 and the second initialization signal line Vref2 are located in the same metal layer of the driving circuit layer 200 ; the second initialization signal line Vref2 and the first power line 220 are located in different metal layers of the driving circuit layer 200 .

[0042] The first initialization signal line Vref1 and the second initialization signal line Vref2 are located in the same metal layer. This connection can be achieved within the same layer, eliminating the need for vias, which simplifies the display panel manufacturing process. The second initialization signal line Vref2 and the first power line 220 are located in different metal layers, preventing short circuits between the first power line 220 and the second initialization signal line Vref2 or the first initialization signal line Vref1, which could adversely affect the display effect.

[0043] In some optional embodiments of the present application, the orthographic projection of the second initialization signal line Vref2 on the substrate 100 at least partially overlaps with the orthographic projection of the first power line 220 on the substrate 100, thereby making the projection areas of the second initialization signal line Vref2 and the first power line 220 on the substrate 100 smaller, making the signal line structure in the array substrate more compact, which is conducive to further improving the pixel density.

[0044] Continuing to refer to Figure 4, optionally, the multiple column symmetrical units 210 arranged along the first direction x include a first column symmetrical unit 2101 and a second column symmetrical unit 2102, and the orthographic projection of the second initialization signal line Vref2 on the substrate 100 is located within the first boundary extension line H1 and the second boundary extension line H2 of the orthographic projection of the first column symmetrical unit 2101 on the substrate 100, and is located outside the first boundary extension line H1 and the second boundary extension line H2 of the orthographic projection of the second column symmetrical unit 2102 on the substrate 100.

[0045] The first power line 220 corresponding to the second column of symmetrical units 2102 is connected to the two columns of pixel circuits 211 in the second column of symmetrical units 2102 within the second column of symmetrical units 2102; the first power line 220 corresponding to the first column of symmetrical units 2101 is not connected to the two columns of pixel circuits 211 in the first column of symmetrical units 2101; the orthographic projection of the first power line 220 on the substrate 100 at least partially overlaps with the orthographic projection of the gate of the driving transistor T1 on the substrate 100.

[0046] The orthographic projection of the first power line 220 on the substrate 100 overlaps with the orthographic projection of the gate of the driving transistor T1 on the substrate 100, thereby forming a capacitor between the first power line 220 and the gate of the driving transistor T1. The voltage on the first power line 220 is constant, so that the potential of the gate of the driving transistor T1 is not easily affected by potential jumps on other signal lines (such as the data line Data). Therefore, the first power line 220 can shield the coupling between the data line Data connected to the column symmetrical unit 210 and the gate of the driving transistor T1 in the pixel circuit 211.

[0047] Illustratively, each first-column symmetrical unit 2101 is provided with a corresponding second initialization signal line Vref2. In some embodiments of the present application, the second initialization signal line Vref2 is located on the first centerline L1 of the first-column symmetrical unit 2101. Optionally, the centerline of the second initialization signal line Vref2 extending along the second direction y coincides with the first centerline L1 of the corresponding column symmetrical unit 210. In this embodiment, the orthographic projection of the second initialization signal line Vref2 corresponding to the first-column symmetrical unit 2101 on the substrate 100 is located outside the first boundary extension line H1 and the second boundary extension line H2 of the projection of the second-column symmetrical unit 2102 on the substrate 100. The first power line 220 corresponding to the second-column symmetrical unit 2102 is connected within the second-column symmetrical unit 2102 to two columns of pixel circuits 211 in the second-column symmetrical unit 2102. This allows the first power line 220 to avoid the pixel circuits 211 connected to the second initialization signal line Vref2, thereby preventing a short circuit between the first power line 220 and the second initialization signal line Vref2, thereby ensuring normal display.

[0048] The orthographic projection of the first power line 220 corresponding to the first column of symmetrical units 2101 on the substrate 100 is located within the first boundary extension line H1 and the second boundary extension line H2 of the orthographic projection of the first column of symmetrical units 2101 on the substrate 100; the orthographic projection of the first power line 220 corresponding to the second column of symmetrical units 2102 on the substrate 100 is located within the first boundary extension line H1 and the second boundary extension line H2 of the orthographic projection of the second column of symmetrical units 2102 on the substrate 100.

[0049] The first power line 220 can be used to shield the coupling between the data line Data connected to the column symmetrical unit 210 and the gate of the driving transistor T1 in the pixel circuit 211. For example, each data line Data is connected to a column of pixel circuits 211, and the data voltage transmitted by the data line Data to different pixel circuits 211 may be different, so the voltage on the data line Data varies. However, the voltage signal connected to the first power line 220 is a fixed power supply voltage. In this embodiment, the first power line 220 can shield the coupling of the voltage variation on the data line Data to the gate potential of the driving transistor T1, ensuring that the gate potential of the driving transistor T1 is relatively stable. Because the driving current generated by the driving transistor T1 is directly related to the gate potential of the driving transistor T1, the stability of the gate potential of the driving transistor T1 can stabilize the driving current generated by the driving transistor T1, thereby ensuring a good display effect. Exemplarily, the orthographic projection of the first power line 220 on the substrate 100 can be arranged to overlap with the orthographic projection of the gate of the driving transistor T1 on the substrate 100, thereby forming a capacitor between the first power line 220 and the gate of the driving transistor T1 to achieve a shielding effect. Optionally, the metal layer where the first power line 220 is located can be located between the metal layer where the data line Data is located and the metal layer where the gate of the driving transistor T1 is located, thereby shielding the coupling of the data voltage change on the data line Data to the gate potential of the driving transistor T1.

[0050] Optionally, along the first direction x, the first column symmetrical units 2101 and the second column symmetrical units 2102 are alternately arranged in sequence; such an arrangement can make the second initialization signal line Vref2 evenly distributed in the first direction x, and the first power line 220 connected to the pixel circuit 211 in the column symmetrical unit 210 evenly distributed in the first direction x, so that within the same distance in the first direction x, the transmission voltage drop of the initialization signal is relatively consistent, and the transmission voltage drop of the power supply voltage is also relatively consistent, which is conducive to ensuring display uniformity.

[0051] Continuing to refer to Figures 4-6, optionally, the driving circuit layer 200 includes a first metal layer M1, a second metal layer M2 and a third metal layer M3 stacked in sequence on one side of the substrate 100; the third metal layer M3 is located on the side of the first metal layer M1 away from the substrate 100, and the second metal layer M2 is located between the first metal layer M1 and the third metal layer M3; the first power line 220 is located in the third metal layer M3, and the first initialization signal line Vref1 is located in the second metal layer M2.

[0052] The driving circuit layer 200 may further include an active layer and a fourth metal layer M4, wherein the active layer is located on one side of the substrate 100. The material of the active layer may be polysilicon or metal oxide. The fourth metal layer M4, the first metal layer M1, the second metal layer M2, and the third metal layer M3 are located on one side of the active layer and are stacked sequentially toward the side of the active layer away from the substrate 100. FIG5 is a schematic structural diagram of the active layer, the fourth metal layer M4, the first metal layer M1, and the second metal layer M2 in the array substrate. The driving circuit layer 200 also includes a plurality of scan lines and a plurality of light-emitting control signal lines EM. The scan lines include a first scan line Scan1, a second scan line Scan2, and a third scan line Scan3. Referring to FIG1, FIG4, and FIG5, the first scan line Scan1 is connected to the first scan signal input terminal S1, the second scan line Scan2 is connected to the second scan signal input terminal S2, and the third scan line Scan3 is connected to the third scan signal input terminal S3. The light-emitting control signal line EM is connected to the light-emitting control signal input terminal Emit. The scan lines and the light emitting control signal lines EM are both located in the fourth metal layer M4.

[0053] Optionally, the driving circuit layer 200 also includes a plurality of second power lines 2201 extending along the first direction x, and the plurality of second power lines 2201 and the plurality of first power lines 220 are interconnected to form a mesh; compared with only setting the first power lines 220, the scheme in which the second power lines 2201 and the first power lines 220 in the driving circuit layer 200 are interconnected to form a mesh can make the resistance of the meshed first power lines 220 and the second power lines 2201 smaller, which is beneficial to reducing the transmission voltage drop of the power supply voltage.

[0054] 4 , in some optional embodiments of the present application, the second power line 2201 is located in the first metal layer M1 , and the second power line 2201 and the first power line 220 may be connected through a via.

[0055] 6 , in another optional embodiment of the present application, the second power line 2201 is insulated from the first initialization signal line Vref1 in the same layer and is located on the second metal layer M2 and connected to the first power line 220 via a via.

[0056] Referring to Figure 6 , first power lines 220 are located on the third metal layer M3. The array substrate includes first initialization signal lines Vref1 located on the second metal layer M2, but does not include second initialization signal lines Vref2 extending along the second direction y. When second power lines 2201 are located on the second metal layer M2, each first power line 220 is connected to two columns of pixel circuits 211 in a column of symmetrical units 210.

[0057] When the second initialization signal line Vref2 extending along the second direction y is not provided in the array substrate, the connection between the first power line 220 and the pixel circuit 211 will not cause a short circuit with the second initialization signal Vref2. Therefore, each first power line 220 is provided to be connected to two columns of pixel circuits 211 of a column of symmetrical units 210, so that the total resistance of the first power line 220 and the second power line 2201 can be further reduced, thereby further reducing the signal transmission voltage drop of the power supply voltage.

[0058] 4 to 6 , among the signal lines connected to the same pixel circuit 211 , the first scan line Scan1 , the first initialization signal line Vref1 , the second scan line Scan2 , the light emitting control signal line EM and the third scan line Scan3 are sequentially arranged along the second direction y.

[0059] With reference to Figures 1, 4, and 6, a first initialization transistor T4 is formed where the first scan line Scan1 overlaps the active layer; a data write transistor T2 and a threshold compensation transistor T3 are formed where the second scan line Scan2 overlaps the active layer. Within the same column of symmetrical units 210, the threshold compensation transistor T3 in one column of pixel circuits 211 is closer to the other column of pixel circuits 211 than the data write transistor T2. A second initialization transistor T5 is formed where the third scan line Scan3 overlaps the active layer; and a first emission control transistor T6 and a second emission control transistor T7 are formed where the emission control signal line EM overlaps the active layer. Within the same column of symmetrical units 210, the second emission control transistor T7 in one column of pixel circuits 211 is closer to the other column of pixel circuits 211 than the first emission control transistor T6.

[0060] Continuing to refer to FIG. 4-FIG . 6 , optionally, the column symmetrical unit 210 includes a gate connection portion 230 located on the second metal layer M2 , and the orthographic projection of the gate connection portion 230 on the substrate 100 is located within the orthographic projection of the corresponding first power line 220 on the substrate 100 .

[0061] 1 and 4 to 6 , the pixel circuit 211 includes a first initialization transistor T4 and a threshold compensation transistor T3. Both the first initialization transistor T4 and the threshold compensation transistor T3 are connected to the gate of the driving transistor T1 via a gate connection portion 230. The gate connection portion 230 easily forms a coupling capacitor with other metal structures, causing the gate potential of the driving transistor T1 to be coupled and changed. In this embodiment, by setting the orthographic projection of the first power line 220 on the substrate 100 to cover the orthographic projection of the gate connection portion 230 on the substrate 100, the coupling of the potential of the gate connection portion 230 by other metal structures can be shielded, so that the gate potential of the driving transistor T1 is relatively stable, ensuring a good display effect.

[0062] Continuing to refer to Figures 4-6, the array substrate also includes a plurality of data lines Data extending along the second direction y. The data lines Data are located in the third metal layer M3. Each column of pixel circuits 211 is connected to a corresponding data line Data. Along the first direction x, the two data lines Data connected to the column symmetrical unit 210 are arranged on both sides of the first power line 220 corresponding to the column symmetrical unit 210.

[0063] Because the two columns of pixel circuits 211 in the column-symmetric unit 210 are connected to the same first power line 220, the first power line 220 is disposed in the middle of the column-symmetric unit 210 in the first direction x to facilitate the connection between the first power line 220 and the two columns of pixel circuits 211 in the column-symmetric unit 210. Accordingly, along the first direction x, the majority of the structures of the two columns of pixel circuits 211 in the column-symmetric unit 210 are arranged on either side of the first power line 220. Therefore, the two data lines Data connected to the column-symmetric unit 210 are arranged on either side of the corresponding first power line 220 in the column-symmetric unit 210 in the first direction x, thereby facilitating the connection between the data lines Data and the corresponding column of pixel circuits 211.

[0064] In some optional embodiments of the present application, the data line Data is located at two opposite edge positions of the column symmetrical unit 210 along the first direction x. As shown in Figures 4 to 6, in some optional embodiments of the present application, the data line Data and the first power line 220 are on the same layer (both located in the third metal layer M3). In this case, because the orthographic projection of the gate connection portion 230 located in the second metal layer M2 on the substrate 100 is covered by the orthographic projection of the first power line 220 on the substrate 100, and the signal transmitted on the first power line 220 remains unchanged, the first power line 220 can still shield the coupling between the data line Data connected to the column symmetrical unit 210 and the gate connection portion 230 in the pixel circuit 211, so that the potential of the gate connection portion 230 will not change due to the voltage jump on the data line Data, thereby ensuring the stability of the gate potential of the driving transistor T1.

[0065] In combination with Figures 1, 4 and 5, when the second power line 2201 is located in the first metal layer M1, the second initialization signal line Vref2 is located in the second metal layer M2; the pixel circuit 211 includes a storage capacitor Cst, and along the first direction x, the setting plates of the storage capacitor Cst in a row of pixel circuits 211 are interconnected as the second power line 2201.

[0066] Exemplarily, the storage capacitor Cst includes two plates, one of which is in the same layer as the gate of the driving transistor T1, for example, located in the fourth metal layer M4, and the other plate is located in the first metal layer M1. The plate located in the first metal layer M1 is the setting plate. The setting plates of the storage capacitors Cst of the pixel circuits 211 in the same row are connected to each other in the first direction x as the second power line 2201. Because the second initialization signal line Vref2 is in the second metal layer M2, the setting plates of the storage capacitors Cst in the pixel circuits 211 in a row along the first direction x are connected to each other as the second power line 2201 without forming a connection with the second initialization signal line Vref2, thereby ensuring normal operation of the display panel.

[0067] Figure 7 is a schematic diagram of another partial film layer structure of the array substrate shown in Figure 4 , wherein Figure 7 is a schematic diagram of the structure of the active layer, fourth metal layer M4, and first metal layer M1 in the array substrate. Continuing with reference to Figures 1 , 4 , 5 , and 7 , pixel circuit 211 further includes a driving transistor T1 and a threshold compensation transistor T3 . Threshold compensation transistor T3 is electrically connected to the gate of driving transistor T1 , and threshold compensation transistor T3 includes a first sub-transistor and a second sub-transistor connected in series.

[0068] The pixel circuit 211 further includes an active layer between the first metal layer M1 and the substrate 100 , and the active layer includes an active portion connecting the first sub-transistor and the second sub-transistor.

[0069] The column symmetric unit 210 further includes a metal portion 240 located in the first metal layer M1 . The orthographic projection of the metal portion 240 on the substrate overlaps with the orthographic projection of the active portion on the substrate. The metal portion 240 is electrically connected to the second power line 2201 or the first initialization signal line Vref1 .

[0070] Because the voltages on the second power line 2201 and the first initialization signal line Vref1 are fixed, and the first metal layer M1 is close to the active layer, by providing a metal portion 240 located in the first metal layer M1 and connecting the metal portion 240 to a fixed voltage (the voltage on the second power line 2201 and the first initialization signal line Vref1), it is possible to prevent other conductive structures with potential jumps from coupling the potential of the active portion, thereby ensuring the potential stability of the active portion. FIG4 schematically illustrates the connection between the metal portion 240 and the second power line 2201, wherein the metal portion 240 and the second power line 2201 are connected via a power line connection portion 250 located in the second metal layer M2, and the overlap position of the metal portion 240 and the power line connection portion 250 is the first position K1 in FIG4 .

[0071] 4 , 5 and 7 , along the second direction y, the orthographic projection of the metal portion 240 on the substrate 100 is located between the orthographic projections of the first scan line Scan1 and the second scan line Scan2 on the substrate 100 . Optionally, the metal portions 240 of multiple column symmetrical units 210 are connected to each other.

[0072] Referring to Figures 4 and 5, optionally, the array substrate also includes a plurality of power line connection portions 250 located in the second metal layer M2, and the orthographic projection of the power line connection portion 250 on the substrate 100 overlaps with the orthographic projection of the first power line 220 on the substrate 100. The second power line 2201 and the first power line 220 are overlapped through the power line connection portion 250, and the power line connection portion 250 is located between adjacent second initialization signal lines Vref2 and is insulated from the second initialization signal line Vref2.

[0073] When the first power line 220 is located in the third metal layer M3 and the second power line 2201 is located in the first metal layer M1, the first power line 220 and the second power line 2201 are connected through the power connection portion 250 located in the second metal layer M2. On the one hand, this allows the depth of the connection via to be made shallower during the preparation of the array substrate, which is easier to implement in terms of process. On the other hand, in order to reduce the voltage drop of the signal transmitted by the first power line 220 in the second direction y, the first power line 220 as a whole extends along the second direction y, and the shape of the power line connection portion 250 can be set to be more diverse. Therefore, the first power line 220 is connected to the second power line 2201 through the power overlap portion 250, so that the overlap position of the first power line 220 and the second power line 2201 can be more flexible. For example, for the array substrate shown in Figure 4, the overlapping position of the first power line 220 and the second power line 2201 is the second position K2 in Figure 4, and the first power line 220 in the third metal layer M3 is overlapped with the second power line 2201 in the first metal layer M1 through the power line connection part 250, and the power line connection part 250 is located in the second metal layer M2.

[0074] Figure 8 is a structural schematic diagram of the power line connection part. Continuing to refer to Figures 4, 5 and 8, optionally, the power line connection part 250 includes a first sub-connection part 251 and two second sub-connection parts 252. The second sub-connection part 252 is electrically connected to the first sub-connection part 251, and in the first direction x, the two second sub-connection parts 252 are located on both sides of the first sub-connection part 251; the first sub-connection part 251 extends along the second direction y, and the orthographic projection of the first sub-connection part 251 on the substrate 100 overlaps with the orthographic projection of the first power line 220 on the substrate 100, and the first power line 220 is overlapped with the first sub-connection part 251; each second sub-connection part 252 is respectively connected to the light-emitting control transistor (i.e., the first light-emitting control transistor M6 in Figure 1) connected to the driving transistor T1 in two pixel circuits 211 in the same row in the column symmetrical unit 210. By setting the shape of the power line connecting portion 250 as described above, the first power line 220 can be connected to the two columns of pixel circuits 211 of the column symmetrical unit 210, making the array substrate structure compact and facilitating improved pixel density.

[0075] When the power line connection portion 250 is in the shape shown in Figure 8, the first power line 220 is overlapped with the first sub-connection portion 251 at the second position K2, and then transmits the power voltage to the plate of the storage capacitor Cst connected to the second sub-connection portion 251 through the first sub-connection portion 251 and the second sub-connection portion 251, wherein the connection position between one pixel circuit 211 of the two pixel circuits 211 in the same row in the second column symmetrical unit 2102 and a second sub-connection portion 252 is the third position K3, and the connection position between the other pixel circuit 211 and the other second sub-connection portion 252 is the fourth position K4.

[0076] In other optional embodiments of the present application, the power line connection portion 250 may also be of other shapes. For example, when the second power line 2201 in Figure 4 is also overlapped with the power line connection portion 250 at the second position K2, then in the power line connection portion 250, the second sub-connection portion 252 may not need to overlap with the plate of the storage capacitor Cst. Accordingly, the orthographic projection of the second sub-connection portion 252 on the substrate 100 may not overlap with the orthographic projection of the storage capacitor Cst on the substrate 100.

[0077] The present application also provides a display panel. FIG9 is a schematic structural diagram of a display panel provided in an embodiment of the present application. The display panel 10 includes an array substrate according to any of the aforementioned embodiments of the present application. The display panel can be used in the mobile phone shown in FIG9 , as well as in computers, wearable products, or other devices with display functions.

Claims

1. An array substrate, comprising: A substrate and a driving circuit layer on one side of the substrate; The driving circuit layer includes a plurality of column symmetrical units arranged along a first direction and a plurality of first power lines extending along a second direction; Each of the column symmetric units includes two columns of pixel circuits, and each column of the pixel circuits includes a plurality of the pixel circuits arranged along a second direction; the first direction and the second direction intersect; wherein, in the column symmetric unit, the two columns of the pixel circuits are symmetrical about a first center line, and the first center line is a center line of the column symmetric unit extending along the second direction; The orthographic projection of the first power line on the substrate is located within the first boundary extension line and the second boundary extension line of the orthographic projection of the column symmetrical unit on the substrate, and the first boundary extension line and the second boundary extension line are two boundary extension lines opposite to each other in the first direction of the orthographic projection of the column symmetrical unit on the substrate; wherein, at least part of the first power line connects the two columns of pixel circuits in the column symmetrical unit within the column symmetrical unit.

2. The array substrate according to claim 1, wherein: The driving circuit layer further includes a plurality of first initialization signal lines extending along the first direction, and each row of the pixel circuits arranged along the first direction is correspondingly connected to one of the first initialization signal lines; The pixel circuit includes a driving transistor and a light emitting device, and at least one of a first initialization transistor and a second initialization transistor; The first electrode of the light emitting device is electrically connected to the driving transistor, and the second electrode of the light emitting device is connected to a fixed voltage; The first initialization transistor is electrically connected to the gate of the driving transistor and is configured to initialize the gate of the driving transistor; the second initialization transistor is electrically connected to the first electrode of the light emitting device and is configured to initialize the first electrode of the light emitting device; In the case where the pixel circuit includes the first initialization transistor, the first initialization signal line is electrically connected to the first initialization transistor; In the case where the pixel circuit includes the second initialization transistor, the first initialization signal line is electrically connected to the second initialization transistor; In a case where the pixel circuit includes the first initialization transistor and the second initialization transistor, the first initialization signal line is electrically connected to the first initialization transistor and the second initialization transistor.

3. The array substrate according to claim 2, wherein: The driving circuit layer further includes a plurality of second initialization signal lines extending along the second direction, wherein the first initialization signal lines and the second initialization signal lines are interconnected to form a mesh; The orthographic projection of the second initialization signal line on the substrate is located within the first boundary extension line and the second boundary extension line of the orthographic projection of the column symmetric unit on the substrate.

4. The array substrate according to claim 3, wherein: One second initialization signal line is correspondingly arranged for every at least one column of symmetrical units.

5. The array substrate according to claim 3, wherein: The driving circuit layer further comprises a plurality of metal layers, and the first initialization signal line and the second initialization signal line are located in the same metal layer of the driving circuit layer; The second initialization signal line and the first power line are located in different metal layers of the driving circuit layer; An orthographic projection of the second initialization signal line on the substrate at least partially overlaps with an orthographic projection of the first power line on the substrate.

6. The array substrate according to claim 3, wherein: The plurality of column symmetric units arranged along the first direction include a first column symmetric unit and a second column symmetric unit, the orthographic projection of the second initialization signal line on the substrate is located within a first boundary extension line and a second boundary extension line of the orthographic projection of the first column symmetric unit on the substrate, and is located outside the first boundary extension line and the second boundary extension line of the orthographic projection of the second column symmetric unit on the substrate; The first power line corresponding to the second column of symmetrical units is connected to two columns of pixel circuits in the second column of symmetrical units within the second column of symmetrical units; Along the first direction, the first column of symmetrical units and the second column of symmetrical units are alternately arranged in sequence.

7. The array substrate according to claim 2, wherein: An orthographic projection of the first power line on the substrate at least partially overlaps with an orthographic projection of the gate of the driving transistor on the substrate.

8. The array substrate according to any one of claims 2 to 6, wherein: The driving circuit layer further comprises a first metal layer, a second metal layer and a third metal layer which are sequentially stacked on one side of the substrate; the third metal layer is located on a side of the first metal layer away from the substrate; The first power line is located in the third metal layer, and the first initialization signal line is located in the second metal layer.

9. The array substrate according to claim 8, wherein: The driving circuit layer further includes a plurality of second power lines extending along the first direction, and the plurality of second power lines and the plurality of first power lines are interconnected to form a mesh; The second power line is located in the first metal layer or the second metal layer.

10. The array substrate according to claim 8, wherein: The column symmetric unit further includes a gate connection portion located on the second metal layer, and an orthographic projection of the gate connection portion on the substrate is located within an orthographic projection of the first power line on the substrate.

11. The array substrate according to claim 8 further includes a plurality of data lines extending along the second direction, each column of the pixel circuits is connected to a corresponding data line, the data line is located in the third metal layer, and along the first direction, the two data lines connected to the column symmetrical units are arranged on both sides of the first power line corresponding to the column symmetrical units.

12. The array substrate according to claim 9, wherein: The second power line is located in the first metal layer; the second initialization signal line is located in the second metal layer; the pixel circuit includes a storage capacitor, and along the first direction, the setting plates of the storage capacitors in a row of the pixel circuits are interconnected as the second power line.

13. The array substrate according to claim 9 further includes a plurality of power line connection parts located in the second metal layer, the orthographic projection of the power line connection part on the substrate overlaps with the orthographic projection of the first power line on the substrate, the second power line and the first power line are overlapped through the power line connection part, and the power line connection part is located between adjacent second initialization signal lines and is insulated from the second initialization signal line.

14. The array substrate according to claim 13, wherein: The power line connection portion includes a first sub-connection portion and two second sub-connection portions, the second sub-connection portions are electrically connected to the first sub-connection portion, and in the first direction, the two second sub-connection portions are located on both sides of the first sub-connection portion; the first sub-connection portion extends along the second direction, the orthographic projection of the first sub-connection portion on the substrate overlaps with the orthographic projection of the first power line on the substrate, and the first power line overlaps with the first sub-connection portion; each of the second sub-connection portions is respectively connected to the light-emitting control transistors connected to the driving transistor in the two pixel circuits in the same row in the column symmetrical unit.

15. The array substrate according to claim 9, wherein: The second power lines are located in the second metal layer, and each of the first power lines is correspondingly connected to two columns of pixel circuits in a column of symmetrical units.

16. The array substrate according to claim 8, wherein: The pixel circuit further includes a threshold compensation transistor and an active layer located between the first metal layer and the substrate; The threshold compensation transistor is electrically connected to the gate of the driving transistor in the pixel circuit, and the threshold compensation transistor includes a first sub-transistor and a second sub-transistor connected in series; The active layer includes an active portion connecting the first sub-transistor and the second sub-transistor.

17. The array substrate according to claim 16, wherein: The column symmetric unit further includes a metal portion located in the first metal layer, an orthographic projection of the metal portion on the substrate overlaps with an orthographic projection of the active portion on the substrate, and the metal portion is electrically connected to the second power line or the first initialization signal line.

18. The array substrate according to claim 1, wherein: The second center line of the first power line coincides with the first center line, the first power line is symmetrical about the second center line, and the second center line is the center line of the first power line extending along the second direction.

19. The array substrate according to claim 1, wherein: The first direction and the second direction are perpendicular to each other.

20. A display panel comprising the array substrate according to any one of claims 1 to 19.

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