Doherty amplifier

Abstract

The present invention comprises: a carrier amplifier and a peak amplifier each of which is a differential amplifier including a first phase amplifier and a second phase amplifier; and a balun which combines an output signal of the carrier amplifier and an output signal of the peak amplifier. The carrier amplifier and the peak amplifier are formed on a semiconductor device. The balun is formed on a printed wiring board on which the semiconductor device is mounted. One of a first wire, which electrically connects an output terminal of the first phase amplifier of the carrier amplifier to an output terminal of the first phase amplifier of the peak amplifier, and a second wire, which electrically connects an output terminal of the second phase amplifier of the carrier amplifier and an output terminal of the second phase amplifier of the peak amplifier, is formed on the printed wiring board, and the other is formed in the semiconductor device.

Description

Doherty Amplifier

[0001] The present disclosure relates to Doherty amplifiers.

[0002] Doherty amplifiers are known as highly efficient power amplifiers. A Doherty amplifier generally has a configuration in which a carrier amplifier, which operates regardless of the power level of the input signal, and a peaking amplifier, which is turned off when the power level of the input signal is low and turned on when the power level is high, are connected in parallel. In this configuration, when the power level of the high-frequency input signal is high, the carrier amplifier operates while maintaining saturation at the saturated output power level. This allows the Doherty amplifier to have improved efficiency compared to ordinary power amplifiers.

[0003] Patent Document 1 listed below (see FIG. 5 in particular) describes a differential current combining Doherty power amplifier that includes a carrier amplifier and a peak amplifier, each of which is a differential amplifier, a phase shifter provided between an output terminal of the carrier amplifier and an output terminal of the peak amplifier, and a transformer that combines an output signal of the carrier amplifier and an output signal of the peak amplifier and outputs the combined signal.

[0004] JP 2013-85179 A

[0005] Let us consider a case where the differential current combining Doherty amplifier described in Patent Document 1 is realized. For example, a carrier amplifier and a peak amplifier are formed on a semiconductor device (IC: Integrated Circuit). This semiconductor device is then mounted on a printed wiring board (PWB). This allows the differential current combining Doherty amplifier described in Patent Document 1 to be realized as a printed circuit board (PCB). However, in this case, output characteristics may be degraded depending on the wiring layout.

[0006] The present disclosure has been made in view of the above, and aims to suppress deterioration of the output characteristics of a Doherty amplifier.

[0007] A Doherty amplifier according to one aspect of the present disclosure includes a carrier amplifier and a peaking amplifier, each of which is a differential amplifier including a first-phase amplifier and a second-phase amplifier, and a balun that combines an output signal of the carrier amplifier and an output signal of the peaking amplifier. The carrier amplifier and the peaking amplifier are formed in a semiconductor device. The balun is formed on a printed wiring board on which the semiconductor device is mounted. One of a first wiring electrically connecting an output terminal of the first-phase amplifier of the carrier amplifier to an output terminal of the first-phase amplifier of the peaking amplifier and a second wiring electrically connecting an output terminal of the second-phase amplifier of the carrier amplifier to an output terminal of the second-phase amplifier of the peaking amplifier is formed on the printed wiring board, and the other is formed on the semiconductor device.

[0008] According to the present disclosure, it is possible to suppress deterioration of the output characteristics of a Doherty amplifier.

[0009] FIG. 1 is a diagram showing a circuit configuration common to the Doherty amplifiers of the first embodiment and comparative examples. FIG. 2 is a diagram showing the layout of the Doherty amplifier of the first comparative example. FIG. 3 is a diagram showing the layout of the Doherty amplifier of the second comparative example. FIG. 4 is a diagram showing the layout of the Doherty amplifier of the second comparative example. FIG. 5 is a diagram showing the layout of the Doherty amplifier of the first embodiment. FIG. 6 is a diagram showing the layout of the Doherty amplifier of the first embodiment. FIG. 7 is an equivalent circuit diagram focusing on the inductance of the Doherty amplifier of the first embodiment. FIG. 8 is a diagram showing the layout of the Doherty amplifier of the second embodiment. FIG. 9 is a diagram showing the layout of the Doherty amplifier of the second embodiment. FIG. 10 is an equivalent circuit diagram focusing on the inductance of the Doherty amplifier of the second embodiment.

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. However, the present invention is not limited to these embodiments. Each embodiment is an example, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. From the second embodiment onwards, a description of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, similar effects resulting from similar configurations will not be mentioned in each embodiment.

[0011] First Embodiment (Circuit Configuration Common to First Embodiment and Comparative Example) FIG. 1 is a diagram showing a circuit configuration common to the Doherty amplifiers of the first embodiment and the comparative example.

[0012] The Doherty amplifier 1 is a differential amplifier. A first-phase high-frequency signal RFin1-1 and a second-phase high-frequency signal RFin1-2, which are first differential signals, are input to the Doherty amplifier 1. In addition, a first-phase high-frequency signal RFin2-1 and a second-phase high-frequency signal RFin2-2, which are second differential signals, are input to the Doherty amplifier 1. The Doherty amplifier 1 amplifies the first-phase high-frequency signal RFin1-1 to the second-phase high-frequency signal RFin2-2, and outputs a first-phase high-frequency signal RFout1 and a second-phase high-frequency signal RFout2, which are differential signals.

[0013] The Doherty amplifier 1 includes a carrier amplifier 2 , a peak amplifier 3 , a phase shifter 4 , and a balun 5 .

[0014] Each of the carrier amplifier 2 and the peak amplifier 3 is a differential amplifier. The carrier amplifier 2 includes a first-phase amplifier 2-1 and a second-phase amplifier 2-2. The peak amplifier 3 includes a first-phase amplifier 3-1 and a second-phase amplifier 3-2.

[0015] In the embodiment, the first phase is a positive phase (positive polarity) and the second phase is a negative phase (negative polarity), but the present disclosure is not limited thereto. The first phase may be a negative phase and the second phase may be a positive phase.

[0016] The first-phase amplifier 2-1 of the carrier amplifier includes a transistor Q1. The emitter of the transistor Q1 is electrically connected to a reference potential. The reference potential is exemplified by the ground potential, but the present disclosure is not limited thereto. A first-phase high-frequency signal RFin1-1 and a base bias current (not shown) are input to the base of the transistor Q1. The collector of the transistor Q1 is electrically connected to a power supply potential via a choke coil. Note that the collector of the transistor Q1 can be supplied with power from a first winding 21 (described later) of the balun 5, so the choke coil is not essential. The transistor Q1 amplifies the first-phase high-frequency signal RFin1-1 input to the base and outputs the amplified first-phase high-frequency signal RF1-1 from the collector.

[0017] In this disclosure, each transistor is a bipolar transistor, but the present disclosure is not limited to this. An example of a bipolar transistor is a heterojunction bipolar transistor (HBT), but the present disclosure is not limited to this. The transistor may be, for example, a field effect transistor (FET). The transistor may be a multi-finger transistor in which multiple unit transistors are electrically connected in parallel. A unit transistor refers to the minimum configuration that constitutes a transistor.

[0018] When each transistor is a FET, the source corresponds to the emitter of the bipolar transistor, the gate corresponds to the base of the bipolar transistor, and the drain corresponds to the collector of the bipolar transistor.

[0019] The second-phase amplifier 2-2 of the carrier amplifier includes a transistor Q2. The emitter of the transistor Q2 is electrically connected to a reference potential. The second-phase high-frequency signal RFin1-2 and a base bias current (not shown) are input to the base of the transistor Q2. The collector of the transistor Q2 is electrically connected to a power supply potential via a choke coil. Note that the collector of the transistor Q2 can be supplied with power from a first winding 21 (described later) of the balun 5, so the choke coil is not essential. The transistor Q2 amplifies the second-phase high-frequency signal RFin1-2 input to the base and outputs the amplified second-phase high-frequency signal RF1-2 from the collector.

[0020] The first-phase amplifier 3-1 of the peak amplifier includes a transistor Q3. The emitter of the transistor Q3 is electrically connected to a reference potential. The first-phase high-frequency signal RFin2-1 and a base bias current (not shown) are input to the base of the transistor Q3. The collector of the transistor Q3 is electrically connected to a power supply potential via a choke coil. Note that the collector of the transistor Q3 can be supplied with power from a first winding 21 (described later) of the balun 5, so the choke coil is not essential. The transistor Q3 amplifies the first-phase high-frequency signal RFin2-1 input to the base and outputs the amplified first-phase high-frequency signal RF2-1 from the collector.

[0021] The second-phase amplifier 3-2 of the peak amplifier includes a transistor Q4. The emitter of the transistor Q4 is electrically connected to the reference potential. The second-phase high-frequency signal RFin2-2 and a base bias current (not shown) are input to the base of the transistor Q4. The collector of the transistor Q4 is electrically connected to the power supply potential via a choke coil. Note that the collector of the transistor Q4 can be supplied with power from a first winding 21 (described later) of the balun 5, so the choke coil is not essential. The transistor Q4 amplifies the second-phase high-frequency signal RFin2-2 input to the base and outputs the amplified second-phase high-frequency signal RF2-2 from the collector.

[0022] The phase shifter 4 includes an inductor 11 and an inductor 12. The inductor 11 and the inductor 12 can also be realized by a transmission line (for example, a wiring). The phase shifter 4 may further include a capacitor 13 and a capacitor 14.

[0023] When the phase shifter 4 includes the capacitor 13 and the capacitor 14, one end of the capacitor 13 is electrically connected to one end of the inductor 11, and the other end of the capacitor 13 is electrically connected to one end of the inductor 12. Furthermore, one end of the capacitor 14 is electrically connected to the other end of the inductor 11, and the other end of the capacitor 14 is electrically connected to the other end of the inductor 12.

[0024] When the phase shifter 4 includes the capacitors 13 and 14, the capacitors 13 and 14 may be formed on a semiconductor device 31 (described later) or on a printed wiring board 32 (described later).

[0025] One end of the inductor 11 is electrically connected to the collector of the transistor Q1. The other end of the inductor 11 is electrically connected to a node N1. The inductor 11 delays the phase of the first phase high frequency signal RF1-1 and outputs it to the node N1.

[0026] One end of the inductor 12 is electrically connected to the collector of the transistor Q2. The other end of the inductor 12 is electrically connected to a node N2. The inductor 12 delays the phase of the second phase high frequency signal RF1-2 and outputs it to the node N2.

[0027] The collector of the transistor Q3 is electrically connected to a node N1, where the first phase high frequency signal RF1-1 that has passed through the phase shifter 4 and the first phase high frequency signal RF2-1 are superimposed.

[0028] The collector of the transistor Q4 is electrically connected to a node N2, where the second-phase high-frequency signal RF1-2 and the second-phase high-frequency signal RF2-2 that have passed through the phase shifter 4 are superimposed on each other.

[0029] The balun 5 includes a first winding 21 and a second winding 22 .

[0030] One end of the first winding 21 is electrically connected to node N1. The other end of the first winding 21 is electrically connected to node N2. The midpoint of the first winding 21 is electrically connected to a power supply potential. The second winding 22 is magnetically coupled to the first winding 21. A first-phase high-frequency signal RFout1 is output from one end of the second winding 22. A second-phase high-frequency signal RFout2 is output from the other end of the second winding 22.

[0031] 2 is a diagram showing the layout of a Doherty amplifier of a first comparative example, and is a schematic plan view of a Doherty amplifier 200 of the first comparative example viewed in a direction perpendicular to its main surface.

[0032] The Doherty amplifier 200 is a printed circuit board in which a semiconductor device 31 is mounted on a printed wiring board 32. The main surface of the printed wiring board 32 is along the XY plane. A first side of the printed wiring board 32 and its opposite second side are along the X direction. A third side of the printed wiring board 32 and its opposite fourth side are along the Y direction.

[0033] The semiconductor device 31 is formed with a first phase amplifier 2-1, a second phase amplifier 2-2, a first phase amplifier 3-1, and a second phase amplifier 3-2.

[0034] The first-phase amplifier 2-1 and the second-phase amplifier 2-2 are arranged adjacent to each other, taking into consideration the symmetry of inductance. The fact that the first-phase amplifier 2-1 and the second-phase amplifier 2-2 are arranged adjacent to each other means that no other amplifiers are arranged between the first-phase amplifier 2-1 and the second-phase amplifier 2-2, and does not preclude the presence of elements other than amplifiers. Similarly, the first-phase amplifier 3-1 and the second-phase amplifier 3-2 are arranged adjacent to each other.

[0035] The first phase amplifier 2-1 to the second phase amplifier 3-2 are arranged on a straight line along the X direction. In other words, the second phase amplifier 2-2 and the first phase amplifier 3-1 are arranged next to each other.

[0036] 2, the amplifiers are arranged in the order of first-phase amplifier 2-1, second-phase amplifier 2-2, first-phase amplifier 3-1, and second-phase amplifier 3-2 along the X direction, but the present disclosure is not limited to this. For example, the amplifiers may be arranged in the order of second-phase amplifier 2-2, first-phase amplifier 2-1, second-phase amplifier 3-2, and first-phase amplifier 3-1. Alternatively, the amplifiers may be arranged in the order of first-phase amplifier 3-1, second-phase amplifier 3-2, first-phase amplifier 2-1, and second-phase amplifier 2-2. Alternatively, the amplifiers may be arranged in the order of second-phase amplifier 3-2, first-phase amplifier 3-1, second-phase amplifier 2-2, and first-phase amplifier 2-1.

[0037] That is, it is sufficient that the first phase amplifier 2-1 and the second phase amplifier 3-2 are formed adjacent to each other, or that the second phase amplifier 2-2 and the first phase amplifier 3-1 are formed adjacent to each other.

[0038] A metal portion 41 (metal electrode) is formed on the bottom surface (the surface on the far side of the paper) of the semiconductor device 31. The metal portion 41 is electrically connected to the output terminal (collector of transistor Q1 (see FIG. 1)) of the first phase amplifier 2-1. A bump 51 is formed below the metal portion 41 (on the far side of the paper).

[0039] A metal portion 42 is formed on the underside of the semiconductor device 31. The metal portion 42 is electrically connected to the output terminal (collector of transistor Q2 (see FIG. 1)) of the second-phase amplifier 2-2. A bump 52 is formed below the metal portion 42.

[0040] A metal portion 43 is formed on the underside of the semiconductor device 31. The metal portion 43 is electrically connected to the output terminal (collector of the transistor Q3 (see FIG. 1)) of the first phase amplifier 3-1. A bump 53 is formed below the metal portion 43.

[0041] A metal portion 44 is formed on the underside of the semiconductor device 31. The metal portion 44 is electrically connected to the output terminal (collector of transistor Q4 (see FIG. 1)) of the second-phase amplifier 3-2. A bump 54 is formed below the metal portion 44.

[0042] The metal portions 41 to 44 are arranged on a straight line along the X direction. The bumps 51 to 54 are arranged on a straight line along the X direction. The metal portions 41 to 44 are sometimes referred to as metal electrodes or under bump metals (UBM). The metal portions 41 to 44 are formed of a material containing at least one of Ti, Cr, Cu, Au, Ni, and Pd, for example. The bumps 51 to 54 are, for example, pillar bumps made of copper (Cu). The bumps 51 to 54 may be made of low-resistance metal materials such as aluminum (Al) and gold (Au) in addition to copper. The bumps 51 to 54 may also be, for example, solder bumps or stud bumps.

[0043] The semiconductor device 31 is electrically connected to the printed wiring board 32 via bumps 51 to 54 .

[0044] A first winding 61 (corresponding to first winding 21 (see FIG. 1 )) of the balun 5 is formed on the first metal layer (the metal layer closest to the paper surface) of the printed wiring board 32. One end of the first winding 61 is electrically connected to the bump 53. The other end of the first winding 61 is electrically connected to the bump 54. A second winding 64 of the balun 5 is formed on the layer below the first winding 61 (the second metal layer (the metal layer one layer further back than the first metal layer on the paper surface)).

[0045] A wiring 62 (corresponding to inductor 12 (see FIG. 1 )) is formed on a second metal layer (a metal layer one layer deeper on the paper than the first metal layer) of printed wiring board 32. One end of wiring 62 is electrically connected to bump 52. The other end of wiring 62 is electrically connected to bump 54.

[0046] A wiring 63 (corresponding to inductor 11 (see FIG. 1 )) is formed on the third metal layer (a metal layer one layer deeper on the paper than the second metal layer) of printed wiring board 32. One end of wiring 63 is electrically connected to bump 51. The other end of wiring 63 is electrically connected to bump 53.

[0047] 2 , when the wiring 62 and the wiring 63 are formed on the printed wiring board 32, at least one of the wiring 62 and the wiring 63 needs to bypass the bump. Therefore, it is difficult to shorten the wiring lengths of the wiring 62 and the wiring 63 in the Doherty amplifier 200. In other words, it is difficult to suppress the inductance values ​​of the wiring 62 and the wiring 63 in the Doherty amplifier 200.

[0048] As described above, it is difficult for the Doherty amplifier 200 to handle high-frequency signals because it is difficult to suppress the inductance values ​​of the wiring 62 and the wiring 63. Furthermore, it is difficult for the Doherty amplifier 200 to suppress the inductance values ​​of the wiring 62 and the wiring 63, which makes it difficult to suppress the characteristic impedance of the phase shifter 4, making it difficult to achieve high output.

[0049] In addition, when the frequency of the high-frequency signal increases or the characteristic impedance of the phase shifter 4 is reduced, the inductance values ​​of the wiring 62 and the wiring 63 of the Doherty amplifier 200 must be reduced (and at the same time, the capacitance values ​​of the capacitors 13 and 14 must be increased).

[0050] 3 and 4 are diagrams showing the layout of a Doherty amplifier of a second comparative example. FIG. 3 is a schematic plan view of a Doherty amplifier 210 of the second comparative example as viewed from a direction perpendicular to the main surface. FIG. 4 is a schematic side view of the Doherty amplifier 210 as viewed from a direction parallel to the main surface (the direction of arrow 300 in FIG. 3 ). In the schematic side view of FIG. 4 , the first winding 61 and the second winding 64 are omitted from illustration.

[0051] Referring to FIG. 3, in the Doherty amplifier 210 of the second comparative example, compared to the Doherty amplifier 200 of the first comparative example, the wiring 63 is formed in the shortest distance (in a straight line) from below the bump 51 (toward the back of the paper) to below the bump 53 (toward the back of the paper) in order to suppress the inductance value.

[0052] 4 , one end of the wiring 62 is electrically connected to the bump 52 through a via 71. One end of the wiring 62 is electrically connected to the bump 54 through a via 72. One end of the wiring 63 is electrically connected to the bump 51 through a via 73. The other end of the wiring 63 is electrically connected to the bump 53 through a via 74.

[0053] 3 and 4, the wiring 62 cannot be formed in a straight line because it must detour around the bump 53 and the via 74.

[0054] From the viewpoint of symmetry between the inductance value of the first phase and the inductance value of the second phase, it is desirable that the inductance value of the wiring 62 is the same as the inductance value of the wiring 63. In other words, it is desirable that the wiring length of the wiring 62 is the same as the wiring length of the wiring 63.

[0055] In the Doherty amplifier 210, even if the wiring 63 is formed linearly, symmetry cannot be ensured unless the wiring 62 is also formed linearly. In order to ensure symmetry in the Doherty amplifier 210, the wiring length of the wiring 63 must be increased (the wiring length must be the same as that of the wiring 62), and the wiring 63 cannot be made linear. In other words, it is difficult for the Doherty amplifier 210 to suppress the inductance values ​​of both the wiring 62 and the wiring 63.

[0056] 5 and 6 are diagrams showing the layout of the Doherty amplifier according to the first embodiment. Fig. 5 is a schematic plan view of the Doherty amplifier 1A according to the first embodiment as viewed from a direction perpendicular to the main surface.

[0057] Fig. 6 is a schematic side view of the Doherty amplifier 1A as viewed in a direction parallel to the main surface (the direction of arrow 310 in Fig. 5). In Fig. 6, the metal portions 41 to 44, the bumps 51, 53, and 54, and the wiring 82 are shown in cross section along line A-B in Fig. 5. Also, in Fig. 6, the wiring 81 and the first winding 61 are shown in cross section along line C-D in Fig. 5.

[0058] 5 , the Doherty amplifier 1A is different from the first and second comparative examples in that no bumps are formed on the metal portion 42 of the semiconductor device 31. The Doherty amplifier 1A has a wiring 81 formed on the underside (the surface on the far side of the page) of the semiconductor device 31. One end of the wiring 81 is electrically connected to the metal portion 42. The other end of the wiring 81 is electrically connected to the metal portion 44. The wiring 81 is made of, for example, copper (Cu). Alternatively to Cu, the wiring 81 may be made of a low-resistance metal material such as aluminum (Al) or gold (Au).

[0059] The wiring 81 corresponds to an example of the "second wiring" of the present disclosure.

[0060] Furthermore, in the Doherty amplifier 1A, a wiring 82 is formed in the second metal layer of the printed wiring board 32 from below the bump 51 to below the bump 53 in the shortest distance (in a straight line). The wiring 82 is made of, for example, copper (Cu). In addition to Cu, the wiring 82 may be made of a low-resistance metal material such as aluminum (Al) or gold (Au).

[0061] The wiring 82 corresponds to an example of the "first wiring" of the present disclosure.

[0062] 6 , the wiring 81 is formed on the lower surface of the semiconductor device 31. One end of the wiring 82 is electrically connected to the bump 51 through a via 91. One end of the wiring 82 is electrically connected to the bump 53 through a via 92.

[0063] In the embodiment, the wiring 82 is formed on the second metal layer of the printed wiring board 32, but the present disclosure is not limited to this. The wiring 82 may be formed on the first metal layer of the printed wiring board 32, for example. In that case, the vias 91 and 92 are not required. One end of the wiring 82 is electrically connected to the bump 51, and the other end of the wiring 82 is electrically connected to the bump 53.

[0064] Effect of the First Embodiment A bump has a certain degree of inductance. However, in the Doherty amplifier 1A, one end of the wiring 81 is connected directly to the metal portion 42 without going through a bump. The other end of the wiring 81 is connected directly to the metal portion 44 without going through the bump 54. Therefore, the Doherty amplifier 1A can reduce the inductance value of the path from the metal portion 42 to the wiring 81 to the metal portion 44 (hereinafter referred to as the first path) by the amount of two bumps.

[0065] Although the wiring 81 needs to detour around the bump 53, the detour distance can be made shorter than that of the wiring 62 (see FIGS. 2 and 3 ) of the first and second comparative examples. Therefore, the Doherty amplifier 1A can suppress the inductance value of the first path by the amount that the detour distance is shorter than that of the wiring 62.

[0066] The vias 91 and 92 can be made shorter than the vias 73 and 74 (see FIG. 4 ). Therefore, the Doherty amplifier 1A can suppress the inductance value of the path of the metal portion 41-bump 51-via 91-wiring 82-via 92-bump 53-metal portion 43 (hereinafter referred to as the second path) compared to the first and second comparative examples. Furthermore, if the wiring 82 is formed on the first metal layer of the printed wiring board 32, the Doherty amplifier 1A does not require the vias 91 and 92. Therefore, the Doherty amplifier 1A can further suppress the inductance value of the second path.

[0067] From the viewpoint of symmetry, it is desirable that the inductance value of the first path and the inductance value of the second path be the same. Therefore, in the Doherty amplifier 1A, the inductance value of the path with the smaller inductance value of the first path or the second path can be adjusted to match the inductance value of the path with the larger inductance value by, for example, increasing the wiring length or narrowing the wiring width.

[0068] As described above, the Doherty amplifier 1A can suppress the inductance values ​​of the first path and the second path compared to the first and second comparative examples, and therefore can handle high-frequency signals with high frequencies. Furthermore, the Doherty amplifier 1A can suppress the inductance values ​​of the first path and the second path, thereby lowering the characteristic impedance of the phase shifter 4 and enabling high output.

[0069] (Additional Note) In the Doherty amplifier 1A, the metal portion 42 and the metal portion 44 are electrically connected via the wiring 81 (second wiring) formed on the semiconductor device 31, and the metal portion 41 and the metal portion 43 are electrically connected via the wiring 82 (first wiring) formed on the printed wiring board 32. However, the present disclosure is not limited to this. The metal portion 41 and the metal portion 43 may be electrically connected via the first wiring formed on the semiconductor device 31, and the metal portion 42 and the metal portion 44 may be electrically connected via the second wiring formed on the printed wiring board 32. In other words, it is sufficient that one of the first wiring and the second wiring is formed on the semiconductor device 31, and the other is formed on the printed wiring board 32.

[0070] Second Embodiment The second embodiment takes into consideration the symmetry of the inductance. For comparison with the second embodiment, the inductance of the first embodiment will be described.

[0071] (Equivalent Circuit Diagram Focusing on Inductance of First Embodiment) FIG. 7 is an equivalent circuit diagram focusing on the inductance of the Doherty amplifier of the first embodiment.

[0072] The output terminal of the first phase amplifier 2-1 is electrically connected to a node N11 (a connection point between the via 92 and one end of the first winding 61) through a bump 51 and a wiring 82.

[0073] The output terminal of the first phase amplifier 3-1 is electrically connected to a node N11 via a bump 53.

[0074] The output terminal of the second phase amplifier 2-2 is electrically connected to a node N12 (metal portion 44) via a wiring 81.

[0075] The output terminal of the second phase amplifier 3-2 is electrically connected to a node N12.

[0076] One end of the first winding 61 is electrically connected to a node N11, and the other end of the first winding 61 is electrically connected to a node N12 via a bump 54.

[0077] 7, in the Doherty amplifier 1A of the first embodiment, a node N11 to which the other end of the wiring 82 is electrically connected is located between the bump 53 and one end of the first winding 61. Meanwhile, a node N12 to which the other end of the wiring 81 is electrically connected is located between the output terminal of the second-phase amplifier 3-2 and the bump 54. In other words, in the Doherty amplifier 1A, the way in which the first phase is connected and the way in which the second phase is connected are not symmetrical.

[0078] Therefore, in the Doherty amplifier 1A of the first embodiment, it is not easy to ensure symmetry between the inductance of the first phase and the inductance of the second phase.

[0079] 8 and 9 are diagrams showing the layout of a Doherty amplifier according to a second embodiment. Fig. 8 is a schematic plan view of a Doherty amplifier 1B according to the second embodiment as viewed in a direction perpendicular to a main surface thereof.

[0080] 9 is a schematic side view of the Doherty amplifier 1B as viewed in a direction parallel to the main surface (the direction of arrow 320 in FIG. 8 ). In FIG. 9 , the metal portions 41 to 44, the bumps 51, 55, 53, and 54, and the wiring 82 are shown in cross section along line E-F in FIG. 8 . In FIG. 9 , the wiring 81 is shown in cross section along line G-H in FIG. 8 . In FIG. 9 , the first winding 61 and the second winding 64 are shown in cross section along line I-J in FIG. One end of the second winding 64 is electrically connected to a via 93.

[0081] The Doherty amplifier 1B is a printed circuit board in which a semiconductor device 31B is mounted on a printed wiring board 32B.

[0082] 8 , compared to the Doherty amplifier 1A of the first embodiment, the Doherty amplifier 1B has a metal portion 43B of a semiconductor device 31B that is elongated in the X direction and has a wiring shape. Furthermore, in addition to the bump 53, a bump 55 is formed below the metal portion 43B (toward the back of the page). The other end of the wiring 82 is electrically connected to the bump 55.

[0083] The bump 54 corresponds to an example of a "first bump" in the present disclosure. The bump 51 corresponds to an example of a "second bump" in the present disclosure. The bump 55 corresponds to an example of a "third bump" in the present disclosure. The bump 53 corresponds to an example of a "fourth bump" in the present disclosure. The metal portion 43B corresponds to an example of a "third wiring" in the present disclosure.

[0084] 9, one end of the wiring 82 is electrically connected to the bump 51. The other end of the wiring 82 is electrically connected to the bump 55.

[0085] (Equivalent Circuit Diagram Focusing on Inductance of Second Embodiment) FIG. 10 is an equivalent circuit diagram focusing on the inductance of the Doherty amplifier of the second embodiment.

[0086] The output terminal of the first phase amplifier 2-1 is electrically connected to node N13 (metal portion 43B) via bump 51, wiring 82, and bump 55. The bump 51, wiring 82, and bump 55 can be regarded as one series circuit 100 (one inductance).

[0087] The output terminal of the first phase amplifier 3-1 is electrically connected to a node N13.

[0088] The output terminal of the second phase amplifier 2-2 is electrically connected to a node N12 (metal portion 44) via a wiring 81.

[0089] The output terminal of the second phase amplifier 3-2 is electrically connected to a node N12.

[0090] One end of the first winding 61 is electrically connected to a node N13 via a bump 53. The other end of the first winding 61 is electrically connected to a node N12 via a bump .

[0091] Effect of the Second Embodiment In the Doherty amplifier 1B, the first phase connection and the second phase connection are symmetrical if the inductance value of the series circuit 100 and the inductance value of the wiring 81 are made the same. It is easy to make the inductance value of the series circuit 100 and the inductance value of the wiring 81 the same.

[0092] This makes it easier for the Doherty amplifier 1B to suppress deterioration of the output characteristics.

[0093] <Configuration Example of the Present Disclosure> The present disclosure may also have the following configuration.

[0094] (1) A Doherty amplifier including: a carrier amplifier and a peak amplifier, each of which is a differential amplifier including a first-phase amplifier and a second-phase amplifier; and a balun that combines an output signal of the carrier amplifier and an output signal of the peak amplifier, wherein the carrier amplifier and the peak amplifier are formed in a semiconductor device, and the balun is formed on a printed wiring board on which the semiconductor device is mounted, and one of a first wiring that electrically connects an output terminal of the first-phase amplifier of the carrier amplifier to an output terminal of the first-phase amplifier of the peak amplifier and a second wiring that electrically connects an output terminal of the second-phase amplifier of the carrier amplifier to an output terminal of the second-phase amplifier of the peak amplifier is formed on the printed wiring board and the other is formed on the semiconductor device.

[0095] (2) The Doherty amplifier according to (1), wherein the semiconductor device is electrically connected to the printed wiring board by a plurality of bumps, and the plurality of bumps include: a first bump electrically connected to one of the first wiring and the second wiring formed on the semiconductor device; a second bump electrically connecting one end of the one of the first wiring and the second wiring formed on the printed wiring board to an output terminal of a first phase amplifier of the carrier amplifier; and a third bump electrically connecting the other end of the one of the first wiring and the second wiring formed on the printed wiring board to an output terminal of the first phase amplifier of the peak amplifier.

[0096] (3) The Doherty amplifier according to (2) above, wherein the third bump is electrically connected to a fourth bump that electrically connects an output terminal of a first phase amplifier of the peak amplifier and the balun via a third wiring formed on the semiconductor device.

[0097] (4) The Doherty amplifier according to any one of (1) to (3) above, wherein a first-phase amplifier and a second-phase amplifier of the carrier amplifier are formed adjacent to each other, a first-phase amplifier and a second-phase amplifier of the peak amplifier are formed adjacent to each other, and a first-phase amplifier of the carrier amplifier and a second-phase amplifier of the peak amplifier are formed adjacent to each other, or a second-phase amplifier of the carrier amplifier and a first-phase amplifier of the peak amplifier are formed adjacent to each other.

[0098] The above-described embodiment is intended to facilitate understanding of the present invention, and is not intended to limit the present invention. The present invention may be modified or improved without departing from the spirit and scope of the present invention, and equivalents thereof are also included in the present invention.

[0099] 1, 1A, 1B, 200, 210 Doherty amplifier 2 Carrier amplifier 2-1, 3-1 First phase amplifier 2-2, 3-2 Second phase amplifier 3 Peak amplifier 4 Phase shifter 5 Balun 11, 12 Inductor 13, 14 Capacitor 21, 61 First winding 22, 64 Second winding 31, 31B Semiconductor device 32, 32B Printed wiring board 41, 42, 43, 43B, 44 Metal part 51, 52, 53, 54, 55 Bump 62, 63, 81, 82 Wiring 71, 72, 73, 74, 91, 92, 93 Via

Claims

1. A Doherty amplifier comprising: a carrier amplifier and a peak amplifier, each of which is a differential amplifier including a first phase amplifier and a second phase amplifier; and a balun that combines an output signal of the carrier amplifier and an output signal of the peak amplifier, wherein the carrier amplifier and the peak amplifier are formed in a semiconductor device, and the balun is formed on a printed wiring board on which the semiconductor device is mounted, and one of a first wiring that electrically connects an output terminal of the first phase amplifier of the carrier amplifier and an output terminal of the first phase amplifier of the peak amplifier and a second wiring that electrically connects an output terminal of the second phase amplifier of the carrier amplifier and an output terminal of the second phase amplifier of the peak amplifier is formed on the printed wiring board and the other is formed in the semiconductor device.

2. A Doherty amplifier as claimed in claim 1, wherein the semiconductor device is electrically connected to the printed wiring board by a plurality of bumps, the plurality of bumps including: a first bump electrically connected to one of the first wiring and the second wiring formed on the semiconductor device; a second bump electrically connecting one end of the one of the first wiring and the second wiring formed on the printed wiring board and an output terminal of a first phase amplifier of the carrier amplifier; and a third bump electrically connecting the other end of the one of the first wiring and the second wiring formed on the printed wiring board and an output terminal of the first phase amplifier of the peak amplifier.

3. A Doherty amplifier as claimed in claim 2, wherein the third bump is electrically connected to a fourth bump that electrically connects between the output terminal of the first phase amplifier of the peak amplifier and the balun via a third wiring formed on the semiconductor device.

4. A Doherty amplifier according to any one of claims 1 to 3, wherein a first-phase amplifier and a second-phase amplifier of the carrier amplifier are formed adjacent to each other, a first-phase amplifier and a second-phase amplifier of the peak amplifier are formed adjacent to each other, a first-phase amplifier of the carrier amplifier and a second-phase amplifier of the peak amplifier are formed adjacent to each other, or a second-phase amplifier of the carrier amplifier and a first-phase amplifier of the peak amplifier are formed adjacent to each other.

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