Frequency division correction circuit and control method therefor, chip, and electronic device

Abstract

The present application relates to the technical field of circuits, and provides a frequency division correction circuit and a control method therefor, a chip, and an electronic device. According to the present application, a plurality of frequency division circuits and a plurality of correction circuits can share the same auxiliary correction circuit, and accurate error information can be obtained when frequency division is performed by a near integer. The frequency division correction circuit comprises a frequency division circuit, an auxiliary correction circuit, and a correction circuit; the frequency division circuit is configured to perform frequency division on a received input clock to obtain an output clock; the auxiliary correction circuit is configured to generate a correction clock, the clock frequency of the correction clock being a constant; and the correction circuit is configured to: perform phase discrimination on a received output clock and the correction clock to obtain a first phase discrimination result, perform phase discrimination on an ideal output clock and the correction clock to obtain a second phase discrimination result, and compare the first phase discrimination result with the second phase discrimination result to obtain error information of the output clock, so as to correct, on the basis of the error information, the clock frequency of the output clock outputted by the frequency division circuit.

Description

Frequency division correction circuit and control method thereof, chip, and electronic equipment Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to a frequency division correction circuit and a control method thereof, a chip, and an electronic device. Background Art

[0002] Multiple circuit modules in a chip may operate at different clock frequencies. Therefore, a frequency division circuit can be used to divide the high-frequency clock to generate different clock frequencies required by each circuit module for operation.

[0003] The frequency division circuit can include integer frequency division circuits and fractional frequency division circuits. The fractional frequency division circuit can include a digital-to-time converter (DTC). However, the DTC has gain error and integrated nonlinearity (INL) error, which leads to periodic deviation in the phase adjustment of the fractional frequency division, thus affecting the performance of the divided clock.

[0004] Summary of the Invention

[0005] The present application provides a frequency division correction circuit and its control method, chip, and electronic device, which can enable multiple frequency division circuits and multiple correction circuits to share the same auxiliary correction circuit on the basis of compensating gain error and nonlinear error, and can obtain accurate error information when frequency division is performed at a near-integer value.

[0006] In a first aspect, the present application provides a frequency division correction circuit, comprising a frequency division circuit, an auxiliary correction circuit, and a correction circuit. The frequency division circuit is configured to divide the frequency of a received input clock to obtain an output clock. The auxiliary correction circuit is configured to generate a correction clock having a constant clock frequency. The correction circuit is configured to perform phase detection between the received output clock and the correction clock to obtain a first phase detection result; perform phase detection between an ideal output clock and the correction clock to obtain a second phase detection result; and compare the first phase detection result with the second phase detection result to obtain error information of the output clock, thereby correcting the clock frequency of the output clock output by the frequency division circuit based on the error information.

[0007] In the present application, by obtaining the output clock and the correction clock, the output clock and the correction clock of a set of adjustment cycles are phase-detected to obtain a first phase-detection result, and the first phase-detection result and the second phase-detection result are compared to obtain error information, so that the frequency division circuit outputs the corrected output clock based on the error information until the frequency of the corrected output clock CLK OUT is the same as the ideal frequency (or the frequency of the corrected output clock CLK OUT approaches the ideal frequency), thereby solving the aforementioned gain error and nonlinear error problems.

[0008] Furthermore, because the auxiliary correction circuit is in operation, its output of the correction clock is independent of whether the output clock is received. Therefore, if there are multiple frequency divider circuits and correction circuits, the multiple frequency divider circuits and correction circuits can share the same auxiliary correction circuit. The multiple correction circuits can receive the correction clock output by the same auxiliary correction circuit and the output clock output by the corresponding frequency divider circuit, thereby correcting the frequency of the output clock output by the frequency divider circuit in the next set of adjustment cycles. This solves the problem in related art where each frequency divider circuit requires an auxiliary correction circuit for error compensation.

[0009] When using the frequency division correction circuit provided in the embodiments of the present application for frequency division, the clock frequency of the correction clock is constant and independent of the clock frequency of the output clock. Therefore, the clock frequency of the correction clock can be considered a DC signal. DC signals have no bandwidth and do not contain the aforementioned low-frequency gain errors and nonlinear errors. Therefore, using the frequency division correction circuit provided in the embodiments of the present application to achieve near-integer frequency division can solve the problem that related technologies cannot obtain accurate error information from the correction clock.

[0010] In some possible implementations, the frequency division circuit may include an integer frequency division circuit, a fractional frequency division circuit, a delta-sum modulator, and a fractional frequency division adjustment circuit to divide the input clock to obtain an output clock.

[0011] The incremental summation circuit is configured to input a value N to the integer frequency division circuit based on a first frequency ratio between the clock frequency of the input clock and the ideal frequency. N includes n and n+1, and the difference between the first frequency ratio and n, as well as the difference between n+1 and the first frequency ratio, is less than 1; n is a positive integer. The integer frequency division circuit is configured to receive the input clock and the value N, and perform integer frequency division on the input clock by interleaving the frequency division by n and n+1 to obtain a base clock, which is then sent to the fractional frequency division circuit. Optionally, the integer frequency division circuit may include a multi-modulus divider. The incremental summation circuit is further configured to input a base clock adjustment value to the fractional frequency division adjustment circuit based on the first frequency ratio. The base clock adjustment value is the decimal digit of the accumulated value of the first frequency ratio in each signal cycle. The fractional frequency division adjustment circuit is further configured to obtain a first adjustment code value based on the base clock adjustment value, and input the first adjustment code value to the fractional frequency division circuit. The fractional frequency division circuit is configured to adjust the base clock using the first adjustment code value to output the output clock.

[0012] For example, if the input clock frequency is 4.8 Hz and the ideal frequency is 2 Hz, the first frequency ratio is 4.8 Hz / 2 Hz = 2.4. The value n that satisfies the difference from 2.4 is less than 1 is 2, and n+1 is 3. If the integer frequency divider circuit divides 4.8 Hz by 2, the resulting basic clock frequency is 4.8 Hz / 2 = 2.4 Hz. If the integer frequency divider circuit 111 divides 4.8 Hz by 3, the resulting basic clock frequency is 4.8 Hz / 3 = 1.6 Hz.

[0013] Taking the frequency division of 4.8 Hz by 2 as an example, in the first signal cycle, the decimal place of the accumulated value of the first frequency ratio is 0.4; in the second signal cycle, the decimal place of the accumulated value of the first frequency ratio is 0.4+0.4=0.8; in the third signal cycle, the accumulated value of the first frequency ratio is 0.4+0.4+0.4=1.2, and the decimal place of the accumulated value of the first frequency ratio is 0.2 due to an integer carry; in the fourth signal cycle, the accumulated value of the first frequency ratio is 0.4+0.4+0.4+0.4=1.6, and the decimal place of the accumulated value of the first frequency ratio is 0.6; in the fifth signal cycle, the accumulated value of the first frequency ratio is 0.4+0.4+0.4+0.4+0.4=2, and the decimal place of the accumulated value of the first frequency ratio is 0 due to an integer carry.

[0014] In this way, the basic clock adjustment values ​​input by the incremental summation circuit 113 to the fractional frequency adjustment circuit 114 are 0.4, 0.8, 0.2, 0.6, 0, 0.4, 0.8, ..., and so on, with every 5 signal cycles forming a group.

[0015] Under ideal conditions with no gain error and nonlinear error, the clock frequency of the output clock CLK OUT output by the fractional frequency division circuit 112 is an ideal frequency, and the output clock is an ideal output clock. In this case, there is no need to use the solution of the present application to perform frequency compensation on the output clock.

[0016] For example, in the first signal cycle, the integer frequency divider circuit divides 4.8 Hz by 2, resulting in a base clock frequency of 2.4 Hz, a base clock period of (1 / 2.4 Hz) seconds, and a base clock adjustment value of 0.4. Adding the adjustment value of (0.4 / 4.8 Hz) seconds to the (1 / 2.4 Hz) second clock period results in an output clock period of (1 / 2.4 Hz) + (0.4 / 4.8 Hz) = 0.5 seconds, resulting in an ideal output clock frequency of 2 Hz.

[0017] In the second signal cycle, integer frequency division circuit 111 divides 4.8 Hz by an integer divider of 2, resulting in a base clock frequency of 2.4 Hz, a base clock period of (1 / 2.4 Hz) s, and a base clock adjustment value of 0.8. An adjustment value of [(0.8 - 0.4) / 4.8 Hz] s is added to the base clock period of (1 / 2.4 Hz) s, resulting in a base clock period of (1 / 2.4 Hz) + (0.4 / 4.8 Hz) = 0.5 s, and thus an ideal output clock frequency of 2 Hz. 0.8 - 0.4 represents the difference between the base clock adjustment value of the second signal cycle and the base clock adjustment value of the first signal cycle.

[0018] In the third signal cycle, the integer frequency divider circuit divides 4.8 Hz by 3, resulting in a base clock frequency of 1.6 Hz, a base clock period of (1 / 1.6 Hz) seconds, and a base clock adjustment value of 0.2. To the (1 / 1.6 Hz) seconds clock period, an adjustment value of [(0.2 - 0.8) / 4.8 Hz] seconds is added, resulting in an output clock period of (1 / 1.6 Hz) + [(0.2 - 0.8) / 4.8 Hz] = 0.5 seconds, and thus an ideal output clock frequency of 2 Hz. 0.2 - 0.8 represents the difference between the base clock adjustment value for the third signal cycle and the base clock adjustment value for the second signal cycle.

[0019] In the fourth signal cycle, the integer frequency divider circuit divides 4.8 Hz by 2, resulting in a base clock frequency of 2.4 Hz, a base clock period of (1 / 2.4 Hz) seconds, and a base clock adjustment value of 0.6. To the (1 / 2.4 Hz) seconds clock period, an adjustment value of [(0.6 - 0.2) / 4.8 Hz] seconds is added, resulting in an output clock period of (1 / 2.4 Hz) + [(0.6 - 0.2) / 4.8 Hz] = 0.5 seconds, and thus an ideal output clock frequency of 2 Hz. 0.6 - 0.2 represents the difference between the base clock adjustment value for the fourth signal cycle and the base clock adjustment value for the third signal cycle.

[0020] In the fifth signal cycle, the integer frequency divider divides 4.8 Hz by 3, resulting in a base clock frequency of 1.6 Hz, a base clock period of (1 / 1.6 Hz) seconds, and a base clock adjustment value of 0. Adding an adjustment value of [(0-0.6) / 4.8 Hz] seconds to the (1 / 1.6 Hz) second clock period results in an output clock period of (1 / 1.6 Hz) + [(0-0.6) / 4.8 Hz] = 0.5 seconds, yielding an ideal output clock frequency of 2 Hz. 0-0.6 represents the difference between the base clock adjustment value for the fifth signal cycle and the base clock adjustment value for the fourth signal cycle.

[0021] In some possible implementations, the auxiliary correction circuit may include a first clock generator, such as a voltage-controlled oscillator. However, the first clock generator may experience frequency drift due to factors such as time and temperature, resulting in the correction clock output by the auxiliary correction circuit being an unstable clock signal.

[0022] Based on this, the auxiliary correction circuit may also include, in addition to the first clock generator, a first phase detector and a first filter. The first phase detector is configured to receive the first reference clock and the correction clock fed back by the first clock generator, and perform phase detection on the first reference clock and the correction clock to obtain a third phase detection result. The first filter is configured to receive and filter the third phase detection result to ensure that the clock frequency of the correction clock output by the first clock generator is constant, thereby improving the quality and stability of the correction clock and saving time in calibrating the output clock.

[0023] In some possible implementations, the clock frequency of the corrected clock is fixed until the clock frequency of the corrected output clock equals the clock frequency of the ideal output clock. Of course, in some application scenarios, if a small error between the clock frequency of the corrected output clock and the clock frequency of the ideal output clock is allowed, the clock frequency of the corrected clock is fixed until the clock frequency of the corrected output clock approaches the clock frequency of the ideal output clock.

[0024] For example, the process of dividing 4.8 Hz using a frequency divider circuit to obtain an output clock and correcting the output clock frequency to 2 Hz (or close to 2 Hz) can be achieved over multiple signal cycles. Before the corrected output clock reaches the ideal output clock frequency of 2 Hz, the corrected clock frequency remains at a fixed frequency of 2.4 Hz for multiple signal cycles.

[0025] In some possible implementations, the correction circuit includes a second phase detector, an error comparison circuit, and a compensation circuit. The second phase detector is used to perform phase detection on the output clock of a group of signal cycles and the correction clock to obtain a first phase detection result; wherein, a group of signal cycles includes multiple signal cycles, and the first phase detection result is the cumulative value of the phase detection results of the output clock and the correction clock in multiple signal cycles. The second phase detector is also used to perform phase detection on the ideal output clock of a group of signal cycles and the correction clock to obtain a second phase detection result; wherein, the second phase detection result is the cumulative value of the phase detection results of the ideal output clock and the correction clock in multiple signal cycles. The error comparison circuit is also used to compare the first phase detection result and the second phase detection result of a group of signal cycles to obtain error information of the output signal. The compensation circuit is used to correct the clock frequency of the output clock of the next group of signal cycles according to the error information.

[0026] Specifically, the second phase detector is used to calculate a second frequency ratio between the clock frequency of the correction clock and the frequency of the output clock, or a third frequency ratio between the frequency of the output clock and the clock frequency of the correction clock, in each signal cycle; obtain a phase detection result between the output clock and the correction clock in each signal cycle based on the product of the second frequency ratio and the basic clock adjustment value, or based on the product of the third frequency ratio and the basic clock adjustment value; and accumulate the phase detection results between the output clock and the correction clock in a group of signal cycles to obtain a first phase detection result.

[0027] The second phase detector is further configured to calculate, in each signal cycle, a fourth frequency ratio between the clock frequency of the correction clock and the frequency of the ideal output clock, or a fifth frequency ratio between the frequency of the ideal output clock and the clock frequency of the correction clock; obtain, according to the product of the fourth frequency ratio and the basic clock adjustment value, a phase detection result between the ideal output clock and the correction clock in each signal cycle, or according to the product of the fifth frequency ratio and the basic clock adjustment value; and accumulate the phase detection results between the ideal output clock and the correction clock in a group of signal cycles to obtain a second phase detection result.

[0028] The error comparison circuit is configured to receive a first phase detection result and a second phase detection result, and to perform a subtraction between the first phase detection result and the second phase detection result to obtain error information; wherein, if the first phase detection result is calculated using the second frequency ratio and the basic clock adjustment value, the second phase detection result is calculated using the fourth frequency ratio and the basic clock adjustment value; and if the first phase detection result is calculated using the third frequency ratio and the basic clock adjustment value, the second phase detection result is calculated using the fifth frequency ratio and the basic clock adjustment value.

[0029] The compensation circuit is used to obtain a gain adjustment value and / or a nonlinear adjustment value according to the error information, and input the gain adjustment value and / or the nonlinear adjustment value to the frequency dividing circuit.

[0030] The frequency dividing circuit is further configured to output a corrected output clock in the next set of signal cycles according to the gain adjustment value and / or the nonlinear adjustment value.

[0031] For example, based on the error information from the first to fifth signal cycles in the first group of signal cycles, the total frequency adjustment value required to compensate for the first to fifth signal cycles is determined, and then the gain adjustment value and / or the nonlinear adjustment value is set to half the total frequency adjustment value required to compensate for the first to fifth signal cycles to adjust the clock frequency of the output clock of the next group of signal cycles. For details, see the example below for the first to fifteenth signal cycles, which will not be repeated here.

[0032] In other possible implementations, the correction circuit includes a second phase detector, an error comparison circuit, and a compensation circuit. The second phase detector is used to perform phase detection on the output clock received in the current signal period and the correction clock to obtain a first phase detection result. The second phase detector is also used to perform phase detection on the ideal output clock of the current signal period and the correction clock to obtain a second phase detection result. The error comparison circuit is used to compare the first phase detection result with the second phase detection result to obtain error information of the output clock. The compensation circuit is used to correct the clock frequency of the output clock output by the frequency divider circuit in the next signal period based on the error information.

[0033] Specifically, the second phase detector is used to calculate the second frequency ratio between the clock frequency of the correction clock and the frequency of the output clock, or the third frequency ratio between the frequency of the output clock and the clock frequency of the correction clock in the current signal cycle; according to the product of the second frequency ratio and the basic clock adjustment value, or according to the product of the third frequency ratio and the basic clock adjustment value, the first phase detection result of the output clock and the correction clock in the current signal cycle is obtained.

[0034] The second phase detector is also used to calculate a fourth frequency ratio between the clock frequency of the correction clock and the frequency of the ideal output clock, or a fifth frequency ratio between the frequency of the ideal output clock and the clock frequency of the correction clock in the current signal cycle; and obtain a second phase detection result between the ideal output clock and the correction clock in the current signal cycle according to the product of the fourth frequency ratio and the basic clock adjustment value, or according to the product of the fifth frequency ratio and the basic clock adjustment value.

[0035] The error comparison circuit is configured to receive a first phase detection result and a second phase detection result, and to perform a subtraction between the first phase detection result and the second phase detection result to obtain error information; wherein, if the first phase detection result is calculated using the second frequency ratio and the basic clock adjustment value, the second phase detection result is calculated using the fourth frequency ratio and the basic clock adjustment value; and if the first phase detection result is calculated using the third frequency ratio and the basic clock adjustment value, the second phase detection result is calculated using the fifth frequency ratio and the basic clock adjustment value.

[0036] The compensation circuit is used to obtain a gain adjustment value and / or a nonlinear adjustment value according to the error information, and input the gain adjustment value and / or the nonlinear adjustment value to the frequency dividing circuit.

[0037] The frequency dividing circuit is further configured to output a corrected output clock in the next signal cycle according to the gain adjustment value and / or the nonlinear adjustment value.

[0038] This implementation corrects the frequency of the output clock in the next signal cycle based on the error information from the current signal cycle. If a set of signal cycles also includes a single signal cycle, the calculation method for correcting the output clock frequency using the frequency division correction circuit is the same as that for the first through fifteenth signal cycles, and will not be further described here.

[0039] In some possible implementations, the clock frequency of the input clock changes, and / or the output frequency of the ideal output clock changes, and / or the clock frequency of the correction clock may remain unchanged after the frequency division correction circuit is powered on again, or the clock frequency of the correction clock may also change, depending on the comparison result of the fourth frequency ratio and the fifth frequency ratio with the preset accuracy.

[0040] Specifically, the correction circuit has a certain resolution in the process of phase detection and calculation of error information. When the decimal places of the fourth frequency ratio and the fifth frequency ratio are too small, due to the existence of the resolution, the correction circuit ignores the decimal places of the fourth frequency ratio and the fifth frequency ratio, thereby affecting the correction accuracy of the output clock.

[0041] Based on this, the present application can set a preset accuracy based on the resolution of the correction circuit. Further, based on the preset accuracy and the clock frequency of the ideal output clock, the clock frequency of the correction clock is set so that the decimal places of the fourth frequency ratio and the decimal places of the fifth frequency ratio are both greater than the preset accuracy, thereby improving the correction accuracy of the output clock.

[0042] In some possible implementations, the error information includes gain error information and / or nonlinear error information. The present application can correct periodic deviations caused by the gain error information and / or nonlinear error information.

[0043] In some possible implementations, the second phase detector includes a first calculation circuit, a second calculation circuit, and a first adder.

[0044] The first calculation circuit is configured to calculate the integer result of the first phase detection result. The second calculation circuit is configured to calculate the decimal result of the first phase detection result. The first adder is configured to receive the integer result and the decimal result and add the integer result and the decimal result to obtain the first phase detection result.

[0045] For example, if the second frequency ratio of the first signal cycle is 1.2 / 1.1, the first phase detection result is 0.4*1.2 / 1.1≈0.44, the first calculation circuit outputs the integer digit of 0.44 as 0, and the second calculation circuit outputs the decimal digit of 0.44 as 0.44. If the second frequency ratio of the second signal cycle is 1.2 / 1.1, the first phase detection result is 0.4*1.2 / 1.1+0.8*1.2 / 1.1≈1.31, the first calculation circuit outputs the integer digit of 1.31 as 1, and the second calculation circuit outputs the decimal digit of 1.31 as 0.31.

[0046] In some possible implementations, the clock frequency of the correction clock used to calculate the second phase-locked detection result and the ideal frequency of the ideal output frequency can be obtained in advance. In this case, the second phase-locked detection result can be calculated directly based on the known clock frequency of the correction clock and the ideal frequency.

[0047] In other possible implementation methods, it is considered that the first reference clock input to the auxiliary correction circuit may be affected by factors such as time and temperature, and may have low-frequency frequency drift, resulting in inaccurate clock frequency of the correction clock; or, the first reference clock cannot be predicted, that is, the clock frequency of the correction clock cannot be predicted, and thus the correct second phase-locked detection result cannot be calculated.

[0048] In this case, the present application can obtain the second phase detection result through the error comparison circuit and the first phase detection result input into the error comparison circuit, thereby obtaining the difference between the error information of the current cycle and the error information of the previous cycle based on the first phase detection result and the second phase detection result.

[0049] Specifically, the error comparison circuit includes a register, a second adder, a third adder, and a second filter. The register is used to input the phase detection result of the output clock and the correction clock in the previous signal cycle to the second adder, and receive and store the phase detection result of the output clock and the correction clock in the current signal cycle input by the second phase detector. The second adder is used to receive the phase detection result of the current signal cycle and the phase detection result of the previous signal cycle, and subtract the phase detection result of the current signal cycle from the phase detection result of the previous signal cycle to obtain the current phase detection result of the current signal cycle. The second filter is used to receive the current phase detection result and filter the current phase detection result to obtain the second phase detection result of the ideal output clock and the correction clock in the current signal cycle. The third adder is used to subtract the current phase detection result from the second phase detection result to obtain the difference between the error information of the current signal cycle and the error information of the previous signal cycle, and add the differences of the error information of a group of signal cycles to obtain the error information of a group of signal cycles.

[0050] For example, the first phase-locked loop result for the first signal cycle is 0.4*1.2 / 1.1, and the first phase-locked loop result for the second signal cycle is 0.4*1.2 / 1.1 + 0.8*1.2 / 1.1. The difference between the two yields the current phase-locked loop result FCW for the second signal cycle of 0.8*1.2 / 1.1. Filtering the current phase-locked loop result FCW of the second signal cycle of 0.8*1.2 / 1.1 yields the second phase-locked loop result of the current signal cycle of 0.8*2.4Hz / 2Hz = 0.8*1.2. The third adder 1323 is used to subtract the current first phase-detection result 0.8*1.2 / 1.1 (the first phase-detection result 0.8*1.2 / 1.1 of the second signal period) from the second phase-detection result 0.8*1.2 of the current signal period (the second phase-detection result 0.8*1.2 of the second signal period), and the difference in error information is approximately 0.09, that is, the error information of the second signal period minus the error information of the first signal period 1.2*1.2 / 1.1-1.44-(0.4*1.2 / 1.1-0.48)≈0.09.

[0051] In this way, when the clock frequency of the correction clock cannot be predicted or the accurate clock frequency of the correction clock cannot be obtained, the second phase detection result can be calculated, thereby obtaining the difference between the error information of the current cycle and the error information of the previous cycle based on the first phase detection result and the second phase detection result, and by accumulating the multiple calculated differences, the error information can be obtained.

[0052] In some possible implementations, the fractional frequency division adjustment circuit is further configured to obtain a second adjustment code value based on the gain adjustment value and / or the nonlinearity adjustment value. The fractional frequency division circuit is further configured to adjust at least one of the resistance, capacitance, voltage, and inductance values ​​of components included in the fractional frequency divider based on the second adjustment code value, thereby correcting the clock frequency of the output clock output in the next set of adjustment cycles to compensate for gain error and nonlinearity error.

[0053] In some possible implementations, the frequency division correction circuit further includes a clock generation circuit that can generate an input clock and input the input clock to the frequency division circuit.

[0054] Specifically, the clock generation circuit includes a third phase detector, a third filter, and a second clock generator. The second clock generator is configured to generate an input clock and input the input clock to the frequency divider circuit. The third phase detector is configured to receive a second reference clock and an output clock, perform phase detection on the second reference clock and the output clock, and obtain a fourth phase detection result. The third filter is configured to receive the fourth phase detection result and filter the fourth phase detection result to adjust the clock frequency of the input clock output by the second clock generator.

[0055] Continuing with the example of an ideal input clock frequency of 4.8Hz and an ideal output clock frequency of 2Hz, since 2Hz and 4.8Hz are not clock frequencies at the same rate, they cannot be phase-detected. Therefore, upon receiving the 4.8Hz input clock, the frequency divider circuit first divides the 4.8Hz input clock and inputs the divided output clock to the third phase detector. The third phase detector can perform phase detection on the output clock and the second reference clock to determine whether the input clock received by the frequency divider circuit is too fast or too slow. The third filter then filters the fourth phase detection result to adjust the frequency of the input clock output by the second clock generator.

[0056] However, in order to accurately correct the speed of the clock frequency of the input clock, it is hoped that the error of the output clock input by the frequency divider circuit to the third phase detector only comes from the input clock output by the clock generation circuit. However, as mentioned above, when the frequency divider circuit divides the input clock, there is also a gain error and / or nonlinear error. The output clock input to the third phase detector is mixed with the gain error and / or nonlinear error, which makes it unclear whether the frequency error source of the output clock is the input clock or the gain error and / or nonlinear error. Therefore, the auxiliary correction circuit and the correction circuit of the present application can be used to correct the frequency of the output clock CLK OUT of the output clock to compensate for the gain error and / or nonlinear error, so that the frequency error source of the output clock input by the frequency divider circuit to the second clock generator only comes from the input clock. In this way, it is only necessary to use the third filter to filter the fourth phase detection result to adjust the speed of the clock frequency of the input clock output by the second clock generator.

[0057] In a second aspect, the present application further provides a method for controlling a frequency division correction circuit, wherein the frequency division correction clock includes a frequency division circuit, an auxiliary correction circuit, and a correction circuit. The method for controlling the frequency division correction clock includes: dividing a received input clock by the frequency division circuit to obtain an output clock; generating a correction clock by the auxiliary correction circuit, wherein the clock frequency of the correction clock is constant; performing phase detection on the received output clock and the correction clock by the correction circuit to obtain a first phase detection result; performing phase detection on the ideal output clock and the correction clock to obtain a second phase detection result; and comparing the first phase detection result with the second phase detection result to obtain error information of the output clock, thereby correcting the clock frequency of the output clock output by the frequency division circuit based on the error information.

[0058] In some possible implementations, there are multiple frequency dividing circuits and correction circuits; multiple correction circuits share the correction clock output by the same auxiliary correction circuit; multiple frequency dividing circuits correspond one-to-one to multiple correction circuits, and any frequency dividing circuit inputs and outputs a clock to a corresponding correction circuit.

[0059] In some possible implementations, the auxiliary correction circuit includes a first phase detector, a first filter, and a first clock generator. Generating a correction clock using the auxiliary correction circuit includes: receiving a first reference clock and a correction clock fed back by the first clock generator via the first phase detector, performing phase detection on the first reference clock and the correction clock via the first phase detector to obtain a third phase detection result; receiving the third phase detection result via the first filter, and filtering the third phase detection result using the first filter to ensure that the clock frequency of the correction clock output by the first clock generator is constant.

[0060] In some possible implementations, a frequency division circuit includes an integer frequency division circuit, a fractional frequency division circuit, an incremental sum modulator, and a fractional frequency division adjustment circuit. The frequency division circuit divides a received input clock to generate an output clock, including: inputting a value N to the integer frequency division circuit based on a first frequency ratio between the clock frequency of the input clock and an ideal frequency via an incremental sum circuit; wherein N includes n and n+1, and the difference between the first frequency ratio and n, and the difference between n+1 and the first frequency ratio, are both less than 1; and n is a positive integer. The integer frequency division circuit receives the input clock and the value N, and performs integer division on the input clock by interleaving n-division and n+1-division to generate a base clock, which is then input to the fractional frequency division circuit. A base clock adjustment value is input to the fractional frequency division adjustment circuit via the incremental sum circuit; the base clock adjustment value is the decimal digit of the accumulated value of the first frequency ratio in each signal cycle. The fractional frequency division adjustment circuit generates a first adjustment code value based on the base clock adjustment value, which is then input to the fractional frequency division circuit. The fractional frequency division circuit adjusts the basic clock using the first adjustment code value to output an output clock.

[0061] In some possible implementations, the clock frequency of the corrected clock is fixed until the clock frequency of the corrected output clock equals the clock frequency of the ideal output clock. Of course, in some application scenarios, if a small error between the clock frequency of the corrected output clock and the clock frequency of the ideal output clock is allowed, the clock frequency of the corrected clock is fixed until the clock frequency of the corrected output clock approaches the clock frequency of the ideal output clock.

[0062] In some possible implementations, the correction circuit includes a second phase detector, an error comparison circuit, and a compensation circuit. The second phase detector performs phase detection on an output clock and a correction clock for a set of signal cycles to obtain a first phase detection result. The set of signal cycles includes multiple signal cycles, and the first phase detection result is the accumulated value of the phase detection results of the output clock and the correction clock for the multiple signal cycles.

[0063] Specifically, a second frequency ratio between the clock frequency of the correction clock and the frequency of the output clock, or a third frequency ratio between the frequency of the output clock and the clock frequency of the correction clock, is calculated in each signal cycle by the second phase detector; a phase detection result between the output clock and the correction clock in each signal cycle is obtained by the second phase detector based on the product of the second frequency ratio and the basic clock adjustment value, or based on the product of the third frequency ratio and the basic clock adjustment value; and a first phase detection result is obtained by accumulating the phase detection results between the output clock and the correction clock in a group of signal cycles by the second phase detector.

[0064] The second phase detector is used to perform phase detection on the ideal output clock and the correction clock of a group of signal cycles to obtain a second phase detection result; wherein the second phase detection result is the accumulated value of the phase detection results of the ideal output clock and the correction clock in multiple signal cycles.

[0065] Specifically, a fourth frequency ratio between the clock frequency of the correction clock and the frequency of the ideal output clock, or a fifth frequency ratio between the frequency of the ideal output clock and the clock frequency of the correction clock, is calculated by the second phase detector in each signal cycle; a phase detection result between the ideal output clock and the correction clock in each signal cycle is obtained by the second phase detector based on the product of the fourth frequency ratio and the basic clock adjustment value, or based on the product of the fifth frequency ratio and the basic clock adjustment value; and a second phase detection result is obtained by accumulating the phase detection results between the ideal output clock and the correction clock in a group of signal cycles by the second phase detector.

[0066] The error comparison circuit is used to compare the first phase detection result and the second phase detection result of a group of signal cycles to obtain error information of the output signal.

[0067] Specifically, an error comparison circuit is used to receive a first phase detection result and a second phase detection result, and a difference is taken between the first phase detection result and the second phase detection result through the error comparison circuit to obtain error information; wherein, if the first phase detection result is calculated by using the second frequency ratio and the basic clock adjustment value, then the second phase detection result is calculated by using the fourth frequency ratio and the basic clock adjustment value; if the first phase detection result is calculated by using the third frequency ratio and the basic clock adjustment value, then the second phase detection result is calculated by using the fifth frequency ratio and the basic clock adjustment value.

[0068] The method for correcting the frequency division circuit further includes correcting the clock frequency of the output clock of the next group of signal cycles according to the error information by the compensation circuit.

[0069] In some other possible implementations, the correction circuit includes a second phase detector, an error comparison circuit, and a compensation circuit.

[0070] The second phase detector is used to perform phase detection on the output clock received in the current signal period and the correction clock to obtain a first phase detection result.

[0071] Specifically, a second frequency ratio between the clock frequency of the correction clock and the frequency of the output clock, or a third frequency ratio between the frequency of the output clock and the clock frequency of the correction clock, in the current signal cycle is calculated by the second phase detector; and a first phase detection result between the output clock and the correction clock in the current signal cycle is obtained by the second phase detector based on the product of the second frequency ratio and the basic clock adjustment value, or based on the product of the third frequency ratio and the basic clock adjustment value.

[0072] The second phase detector is used to perform phase detection on the ideal output clock of the current signal period and the correction clock to obtain a second phase detection result.

[0073] Specifically, a fourth frequency ratio between the clock frequency of the correction clock and the frequency of the ideal output clock, or a fifth frequency ratio between the frequency of the ideal output clock and the clock frequency of the correction clock in the current signal cycle is calculated by the second phase detector; and a second phase detection result of the ideal output clock and the correction clock in the current signal cycle is obtained by multiplying the fourth frequency ratio and the basic clock adjustment value, or by multiplying the fifth frequency ratio and the basic clock adjustment value, using the second phase detector.

[0074] The error comparison circuit is used to compare the first phase detection result with the second phase detection result to obtain error information of the output clock.

[0075] Specifically, an error comparison circuit is used to receive a first phase detection result and a second phase detection result, and a difference is taken between the first phase detection result and the second phase detection result to obtain error information; wherein, if the first phase detection result is calculated by using the second frequency ratio and the basic clock adjustment value, then the second phase detection result is calculated by using the fourth frequency ratio and the basic clock adjustment value; if the first phase detection result is calculated by using the third frequency ratio and the basic clock adjustment value, then the second phase detection result is calculated by using the fifth frequency ratio and the basic clock adjustment value.

[0076] The compensation circuit corrects the clock frequency of the output clock output by the frequency dividing circuit in the next signal cycle according to the error information.

[0077] Specifically, the compensation circuit is used to obtain a gain adjustment value and / or a nonlinear adjustment value according to the error information, and the gain adjustment value and / or the nonlinear adjustment value are input to the frequency division circuit.

[0078] The method for correcting the frequency division circuit further includes: using the frequency division circuit to output a corrected output clock in a next signal cycle according to the gain adjustment value and / or the nonlinear adjustment value.

[0079] In some possible implementations, the decimal places of the fourth frequency ratio and the decimal places of the fifth frequency ratio are both greater than a preset accuracy.

[0080] In some possible implementations, the second phase detector includes a first calculation circuit, a second calculation circuit, and a first adder. The second phase detector calculates a second frequency ratio between the clock frequency of the correction clock and the frequency of the output clock, or a third frequency ratio between the frequency of the output clock and the clock frequency of the correction clock, in a current signal cycle. The second phase detector multiplies the second frequency ratio by a basic clock adjustment value, or multiplies the third frequency ratio by the basic clock adjustment value, to obtain a first phase detection result between the output clock and the correction clock in the current signal cycle, including:

[0081] A first calculation circuit is used to calculate a second frequency ratio between the clock frequency of the correction clock and the frequency of the output clock, or a third frequency ratio between the frequency of the output clock and the clock frequency of the correction clock, in the current signal cycle. The first calculation circuit multiplies the second frequency ratio by a basic clock adjustment value, or the third frequency ratio by the basic clock adjustment value, to obtain an integer bit result of a first phase detection result between the output clock and the correction clock in the current signal cycle. A second calculation circuit is used to calculate a second frequency ratio between the clock frequency of the correction clock and the frequency of the output clock, or a third frequency ratio between the frequency of the output clock and the clock frequency of the correction clock, in the current signal cycle. The first calculation circuit multiplies the second frequency ratio by a basic clock adjustment value, or the third frequency ratio by the basic clock adjustment value, to obtain an integer bit result of a first phase detection result between the output clock and the correction clock in the current signal cycle. A first adder is used to add the integer bit result and the decimal bit result to obtain a first phase detection result.

[0082] In some possible implementations, the error comparison circuit includes a register, a second adder, a third adder, and a second filter. The error comparison circuit receives the first phase detection result and the second phase detection result, and performs a subtraction between the first phase detection result and the second phase detection result to obtain error information, including:

[0083] The register is used to input the phase detection result of the output clock and the correction clock in the previous signal cycle to the second adder, and the register is used to receive and store the phase detection result of the output clock input by the second phase detector and the correction clock in the current signal cycle.

[0084] The second adder receives the phase detection result of the current signal cycle and the phase detection result of the previous signal cycle, and uses the second adder to subtract the phase detection result of the current signal cycle from the phase detection result of the previous signal cycle to obtain the current phase detection result of the current signal cycle.

[0085] The current phase detection result is received through the second filter and filtered to obtain a second phase detection result of the ideal output clock and the correction clock in the current signal period.

[0086] The third adder is used to subtract the current phase detection result from the second phase detection result to obtain the difference between the error information of the current signal cycle and the error information of the previous signal cycle. The difference in the error information of a group of signal cycles is added together to obtain the error information of a group of signal cycles.

[0087] In some possible implementations, using a frequency divider circuit to output a corrected output clock in a next set of signal cycles based on a gain adjustment value and / or a nonlinear adjustment value, or using a frequency divider circuit to output a corrected output clock in a next signal cycle based on a gain adjustment value and / or a nonlinear adjustment value, includes: obtaining a second adjustment code value using a fractional frequency divider adjustment circuit based on the gain adjustment value and / or the nonlinear adjustment value, and using the fractional frequency divider circuit to output the corrected output clock in a next set of signal cycles or a next signal based on the second adjustment code value.

[0088] In some possible implementations, a fractional frequency divider circuit is used to output a clock after correction in the next set of signal cycles or the next signal output according to a second adjustment code value, including: adjusting at least one of the resistance value, capacitance value, voltage value, and inductance value of the components included in the fractional frequency divider according to the second adjustment code value through the fractional frequency divider adjustment circuit, and outputting a clock after correction in the next set of signal cycles or the next signal output.

[0089] In some possible implementations, the clock correction circuit also includes a clock generation circuit; before dividing the received input clock by the frequency division circuit to obtain the output clock, the control method of the frequency division correction circuit also includes: using the clock generation circuit to generate the input clock, and inputting the input clock to the frequency division circuit.

[0090] In some possible implementations, the clock generation circuit includes a third phase detector, a third filter, and a second clock generator. Generating an input clock using the clock generation circuit includes: generating the input clock using the second clock generator and inputting the input clock into a frequency divider circuit. The third phase detector receives a second reference clock and an output clock, performs phase detection on the second reference clock and the output clock, and obtains a fourth phase detection result. The third filter receives the fourth phase detection result and filters the fourth phase detection result to adjust the clock frequency of the input clock output by the second clock generator.

[0091] The second aspect and any implementation of the second aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the second aspect and any implementation of the second aspect can be referred to the technical effects corresponding to the first aspect and any implementation of the first aspect, and will not be repeated here.

[0092] In a third aspect, the present application provides a chip comprising the frequency division correction circuit described in the first aspect.

[0093] The third aspect and any implementation of the third aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the third aspect and any implementation of the third aspect can be referred to the technical effects corresponding to the first aspect and any implementation of the first aspect, and will not be repeated here.

[0094] In a fourth aspect, the present application provides an electronic device, which includes a circuit board and the chip described in the third aspect, and the chip is arranged on the circuit board.

[0095] The fourth aspect and any implementation of the fourth aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the fourth aspect and any implementation of the fourth aspect can be referred to the technical effects corresponding to the first aspect and any implementation of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0096] FIG1 is a diagram showing the connection relationship between modules in a mobile phone provided in an embodiment of the present application;

[0097] FIG2 is a connection diagram of various modules in the frequency division correction circuit provided by the related art;

[0098] FIG3 is a connection diagram of various modules in a frequency division correction circuit provided by an embodiment of the present application;

[0099] FIG4 is a connection diagram of various modules in another frequency division correction circuit provided by an embodiment of the present application;

[0100] FIG5 is a connection diagram of various modules in another frequency division correction circuit provided by an embodiment of the present application;

[0101] FIG6 is a connection diagram of various modules in another frequency division correction circuit provided by an embodiment of the present application;

[0102] FIG7 is a diagram showing the connection relationship between modules in the auxiliary correction circuit provided in an embodiment of the present application;

[0103] FIG8 is a connection diagram of various modules in the second phase detection circuit provided in an embodiment of the present application;

[0104] FIG9 is a connection diagram of various modules in the error comparison circuit provided in an embodiment of the present application;

[0105] FIG10 is a connection diagram of various modules in another frequency division correction circuit provided in an embodiment of the present application;

[0106] FIG11 is a connection diagram of various modules in another frequency division correction circuit provided in an embodiment of the present application;

[0107] FIG12 is a control flow chart of the frequency division correction circuit provided in an embodiment of the present application.

[0108] Figure markings: 11-frequency division circuit; 111-integer frequency division circuit; 112-fractional frequency division circuit; 113-incremental sum modulator; 114-fractional frequency division adjustment circuit; 12-auxiliary correction circuit; 121-first phase detector; 122-first filter; 123-first clock generator; 13-correction circuit; 131-second phase detector; 1311-first calculation circuit; 1312-second calculation circuit; 1313-first adder; 132-error comparison circuit; 1321-register; 1322-second adder; 1323-third adder; 1324-second filter; 133-compensation circuit; 14-clock generation circuit; 141-third phase detector; 142-third filter; 143-second clock generator. DETAILED DESCRIPTION

[0109] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0110] The terms "first," "second," and so on in the specification, examples, claims, and drawings of this application are used solely for descriptive purposes and should not be construed as indicating or implying relative importance or order. "And / or" is used to describe an association between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist, where A and B can be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship. "Installed," "connected," and "connected" should be broadly construed, meaning, for example, fixed, removable, or integral; directly, indirectly through an intermediary, or internally connected between two components. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions, such as inclusion of a list of steps or elements. A method, system, product, or apparatus is not necessarily limited to the steps or elements explicitly listed and may include other steps or elements not explicitly listed or inherent to such process, method, product, or apparatus. "Up", "down", "left", "right", etc. are only used in relation to the orientation of the components in the drawings. These directional terms are relative concepts. They are used for relative description and clarification, and may change accordingly according to the change of the orientation of the components in the drawings.

[0111] An embodiment of the present application provides an electronic device, which may be a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, or other device containing a chip.

[0112] Consumer electronic products include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products include smart door locks, TVs, smart speakers, refrigerators, sweeping robots, etc. Car-mounted electronic products include car navigation systems and car displays, etc. Financial terminal products include automated teller machines (ATMs) and self-service terminals, etc. Communication electronic products include servers, storage devices, radars, base stations, and other communication equipment that contain chips.

[0113] For ease of explanation, the following uses a mobile phone as an example electronic device. As shown in Figure 1, a mobile phone may include a circuit board, a chip mounted on the circuit board, and various circuits mounted on the chip to form the components required by the mobile phone. For example, components such as a processor, internal memory, and charging circuits can be implemented using a variety of different circuit structures.

[0114] Taking internal memory as an example, it consists of multiple memory cells, word lines, and bit lines electrically connected to the memory cells. Operating voltages are input to the word lines and bit lines according to different timings to enable data to be read and written to the memory cells. During this process, the word lines and bit lines have different timings, and the clock frequencies required for them are also different.

[0115] In order to meet different clock frequency requirements, related technologies propose frequency dividing circuits, which use frequency dividing circuits to generate clocks with different clock frequencies to meet different requirements.

[0116] Frequency division circuits can include integer frequency division circuits and fractional frequency division circuits. The fractional frequency division circuit can be a direct current clock (DTC). However, DTCs have gain errors and nonlinear errors, which lead to periodic deviations in the phase adjustment of fractional frequency division, thus affecting the performance of the divided clock.

[0117] For example, to achieve digital-to-time phase shifting, a DTC includes multiple cascaded phase shifters. Suppose each phase shifter is required to produce a 2ps phase shift, but the actual phase shift produced is 3ps, with each phase shifter exhibiting a 1ps error. The errors in the outputs of these multiple phase shifters accumulate, resulting in gain error.

[0118] For another example, one phase shifter actually generates a phase shift of 3 ps, and another phase shifter actually generates a phase shift of 1.9 ps. Since the step sizes of the multiple phase shifters are different, nonlinear errors are caused.

[0119] As shown in FIG2 , related art typically uses a correction clock CLK ADPLL to correct the frequency of the output clock CLK OUT output by the frequency divider circuit 11. However, due to the circuit design, generating the correction clock CLK ADPLL requires certain triggering conditions. Specifically, the auxiliary correction circuit 12 generates a correction clock CLK ADPLL with the same frequency as the output clock CLK OUT only when triggered by each output clock CLK OUT. This results in each frequency divider circuit 11 requiring an auxiliary correction circuit 12 to compensate for various errors.

[0120] Furthermore, since the auxiliary correction circuit in related art is typically an all-digital phase-locked loop (ADPLL), which is a closed-loop structure with a limited loop bandwidth, when the frequency divider circuit implements near-integer frequency division, the gain error and nonlinearity error are within the loop bandwidth and are low-frequency signals. Therefore, the ADPLL cannot filter out the gain error and nonlinearity error. If the output clock CLK OUT input to the auxiliary correction circuit has nonlinearity and / or gain error, the correction clock CLK ADPLL output by the auxiliary correction circuit based on the output clock CLK OUT also has gain error and / or nonlinearity error. As a result, when the frequency divider circuit implements near-integer frequency division, accurate error information cannot be obtained by comparing the correction clock CLK ADPLL with the output clock CLK OUT.

[0121] Those skilled in the art will understand that when the frequency divider circuit 11 achieves near-integer frequency division, it means that the ratio of the ideal frequency of the ideal output clock output by the frequency divider circuit 11 to the clock frequency of the input clock CLK IN input to the frequency divider circuit 11 is close to an integer. For example, if the ideal frequency of the ideal output clock is 12.799 Hz and the clock frequency of the input clock CLK IN is 12 Hz, the ratio between the two is 12.799 / 12≈1, where 1 is an integer.

[0122] Based on this, an embodiment of the present application proposes a frequency division correction circuit. In addition to the frequency division circuit, the frequency division correction circuit also includes an auxiliary correction circuit and a correction circuit. The correction circuit is used to correct the clock generated by the frequency division circuit to solve the above problem.

[0123] As shown in Figure 3, frequency divider circuit 11 is used to divide the received input clock CLK IN to generate an output clock CLK OUT. The above example uses the DTC in frequency divider circuit 11 as an example to illustrate the periodic phase deviation of the output clock CLK OUT generated by frequency divider circuit 11. Of course, other circuits capable of clock division and exhibiting gain and nonlinear errors can also serve as frequency divider circuit 11 in the embodiments of the present application.

[0124] The auxiliary correction circuit 12 is used to generate a correction clock CLK ADPLL. The clock frequency of the correction clock CLK ADPLL is constant.

[0125] Correction circuit 13 is configured to perform phase detection between the received output clock CLK OUT and the correction clock CLK ADPLL to obtain a first phase detection result; perform phase detection between the ideal output clock and the correction clock CLK ADPLL to obtain a second phase detection result; and compare the first phase detection result with the second phase detection result to obtain error information of the output clock CLK OUT, so as to correct the clock frequency of the output clock CLK OUT output by the frequency divider circuit 11 based on the error information.

[0126] Correction circuit 13 performs phase detection on output clock CLK OUT and correction clock CLK ADPLL to obtain a first phase detection result, and compares the first phase detection result with the second phase detection result to obtain error information. Based on the error information, frequency divider circuit 11 outputs a corrected output clock CLK OUT until the frequency of the corrected output clock CLK OUT matches the ideal frequency (or the frequency of the corrected output clock CLK OUT approaches the ideal frequency), thereby resolving the aforementioned gain error and nonlinear error problems.

[0127] Furthermore, since the auxiliary correction circuit 12 is in operation, its generation of the correction clock CLK ADPLL does not depend on whether it receives the output clock CLK OUT. Therefore, as shown in FIG4 , when there are multiple frequency divider circuits 11 and correction circuits 13, the multiple frequency divider circuits 11 and correction circuits 13 share the same auxiliary correction circuit 12. The multiple correction circuits 13 can receive the correction clock CLK ADPLL output by the same auxiliary correction circuit 12 and the output clock CLK OUT output by the corresponding frequency divider circuit 11, thereby correcting the frequency of the output clock CLK OUT. This solves the problem in the related art where each frequency divider circuit 11 requires an auxiliary correction circuit 12 for error compensation.

[0128] When frequency division is performed using the frequency division correction circuit provided in the embodiments of the present application, the clock frequency of the correction clock CLK ADPLL is a constant (e.g., 2.4 Hz) and is independent of the clock frequency of the output clock CLK OUT. Therefore, the clock frequency of the correction clock CLK ADPLL can be considered a DC signal. DC signals have no bandwidth and do not contain the aforementioned low-frequency gain errors and nonlinear errors. Therefore, using the frequency division correction circuit provided in the embodiments of the present application to achieve near-integer frequency division can solve the problem of related technologies that cannot obtain accurate error information from the correction clock CLK ADPLL.

[0129] Phase detection is performed on the output clock CLK OUT and the correction clock CLK ADPLL. This means the phase of the output clock CLK OUT is differentiated from the phase of the correction clock CLK ADPLL. Since frequency can be obtained by differentiating the phase, the phase detection between the output clock CLK OUT and the correction clock CLK ADPLL can be obtained by calculating the frequency ratio between the two clock signals.

[0130] Optionally, the frequency ratio between the two clock signals may be the ratio between the clock frequency of the correction clock CLK ADPLL and the frequency of the output clock CLK OUT, which is referred to as the second frequency ratio. Alternatively, the frequency ratio between the two clock signals may be the ratio between the frequency of the output clock CLK OUT and the clock frequency of the correction clock CLK ADPLL, which is referred to as the third frequency ratio.

[0131] Correspondingly, if the output clock CLK OUT and the correction clock CLK ADPLL are phase-detected and calculated using the second frequency ratio, the phase-detection result between the ideal output clock and the correction clock CLK ADPLL is calculated using the ratio between the clock frequency of the correction clock of the correction clock CLK ADPLL and the ideal frequency of the ideal output clock. This ratio is named the fourth frequency ratio.

[0132] If phase detection is performed between the output clock CLK OUT and the correction clock CLK ADPLL, the phase detection result between the ideal output clock and the correction clock CLK ADPLL is calculated using the first frequency ratio. The ratio between the ideal frequency of the ideal output clock and the clock frequency of the correction clock CLK ADPLL is referred to as the fifth frequency ratio. Unless otherwise specified, the following description uses the second and fourth frequency ratios as examples.

[0133] The following describes the working principle of the frequency division circuit 11 for dividing the input clock CLK IN and the working principle of the correction circuit 13 for frequency compensation of the output clock CLK OUT with reference to the accompanying drawings.

[0134] As shown in FIG5 , the frequency division circuit 11 may include an integer frequency division circuit 111, a fractional frequency division circuit 112, a delta-sigma modulation (DSM) 113, and a fractional frequency division adjustment circuit 114 to divide the input clock CLK IN to obtain the output clock CLK OUT. The specific working principle is as follows:

[0135] Incremental summation circuit 113 is configured to input a value N to integer frequency divider circuit 111 based on a first frequency ratio between the clock frequency of input clock CLK IN and the ideal frequency. Wherein, N includes n and n+1, and the difference between the first frequency ratio and n, and the difference between n+1 and the first frequency ratio, are both less than 1; and n is a positive integer.

[0136] For example, the clock frequency of the input clock CLK IN is 4.8 Hz, the ideal frequency is 2 Hz, and the first frequency ratio is 4.8 Hz / 2 Hz = 2.4. The n whose difference from 2.4 is less than 1 is 2, and n+1 is 3.

[0137] Integer frequency division circuit 111 is configured to receive an input clock CLK IN and a value N, perform integer frequency division on the input clock by interleaving division by n and division by n+1, obtain a base clock CLK MMD, and send the base clock CLK MMD to fractional frequency division circuit 112. Optionally, integer frequency division circuit 111 may include a multi-modulus divider (MMD).

[0138] For example, if the input clock CLK IN has a clock frequency of 4.8 Hz and N is 2 or 3, then if the integer frequency divider circuit 111 integer divides 4.8 Hz by 2, the resulting clock frequency of the basic clock CLK MMD is 4.8 Hz / 2 = 2.4 Hz. If the integer frequency divider circuit 111 integer divides 4.8 Hz by 3, the resulting clock frequency of the basic clock CLK MMD is 4.8 Hz / 3 = 1.6 Hz.

[0139] Incremental summation circuit 113 is further configured to input a basic clock adjustment value to fractional frequency division adjustment circuit 114 based on the first frequency ratio. The basic clock adjustment value is the fractional digit of the accumulated value of the first frequency ratio in each signal cycle. The time period between the frequency division circuit 11 outputting one output clock CLK OUT and the next output clock CLK OUT is one signal cycle.

[0140] For example, taking the frequency division of 4.8 Hz by 2 as an example, in the first signal cycle, the decimal place of the accumulated value of the first frequency ratio is 0.4; in the second signal cycle, the decimal place of the accumulated value of the first frequency ratio is 0.4+0.4=0.8; in the third signal cycle, the accumulated value of the first frequency ratio is 0.4+0.4+0.4=1.2, and the decimal place of the accumulated value of the first frequency ratio is 0.2 due to an integer carry; in the fourth signal cycle, the accumulated value of the first frequency ratio is 0.4+0.4+0.4+0.4=1.6, and the decimal place of the accumulated value of the first frequency ratio is 0.6; in the fifth signal cycle, the accumulated value of the first frequency ratio is 0.4+0.4+0.4+0.4+0.4=2, and the decimal place of the accumulated value of the first frequency ratio is 0 due to an integer carry.

[0141] In this way, the basic clock adjustment values ​​input by the incremental summation circuit 113 to the fractional frequency adjustment circuit 114 are 0.4, 0.8, 0.2, 0.6, 0, 0.4, 0.8, ..., and so on, and every 5 signal cycles constitute a group of signal cycles.

[0142] The fractional frequency adjustment circuit 114 is further configured to obtain a first adjustment code value based on the basic clock adjustment value, and input the first adjustment code value to the fractional frequency adjustment circuit 112. Optionally, after receiving the basic clock adjustment value, the fractional frequency adjustment circuit 114 may obtain the first adjustment code value based on a preset formula or a lookup table.

[0143] The fractional frequency division circuit 112 is configured to adjust the basic clock CLK MMD using a first adjustment code value to output an output clock CLK OUT. Optionally, the fractional frequency division circuit 112 may include a DTC.

[0144] Under ideal conditions with no gain error and nonlinear error, the clock frequency of the output clock CLK OUT output by the fractional frequency division circuit 112 is an ideal frequency, and the output clock CLK OUT is an ideal output clock. In this case, there is no need to use the solution of the present application to perform frequency compensation on the output clock CLK OUT.

[0145] For example, in the first signal cycle, integer frequency divider circuit 111 integer divides 4.8 Hz by 2, resulting in a clock frequency of 2.4 Hz for the basic clock CLK MMD. The clock period of the basic clock CLK MMD is (1 / 2.4 Hz) s, and the basic clock adjustment value is 0.4. By adding the adjustment value (0.4 / 4.8 Hz) s to the clock period of (1 / 2.4 Hz) s, the resulting clock period of the output clock CLK OUT is (1 / 2.4 Hz) + (0.4 / 4.8 Hz) = 0.5 s, and thus the ideal frequency of the ideal output clock is 2 Hz.

[0146] During the second signal cycle, integer frequency division circuit 111 divides 4.8 Hz by an integer divider of 2, resulting in a clock frequency of 2.4 Hz for the basic clock CLK MMD. The clock period of the basic clock CLK MMD is (1 / 2.4 Hz) s, and the basic clock adjustment value is 0.8. To the clock period of (1 / 2.4 Hz) s, an adjustment value of [(0.8 - 0.4) / 4.8 Hz] s is added, resulting in a clock period of (1 / 2.4 Hz) + (0.4 / 4.8 Hz) = 0.5 s for the output clock CLK OUT, and thus an ideal frequency of 2 Hz for the ideal output clock. 0.8 - 0.4 represents the difference between the basic clock adjustment value for the second signal cycle and the basic clock adjustment value for the first signal cycle.

[0147] During the third signal cycle, integer frequency divider circuit 111 divides 4.8 Hz by 3, resulting in a clock frequency of 1.6 Hz for the basic clock CLK MMD. The clock period of the basic clock CLK MMD is (1 / 1.6 Hz) s, and the basic clock adjustment value is 0.2. To the clock period of (1 / 1.6 Hz) s, an adjustment value of [(0.2 - 0.8) / 4.8 Hz] s is added, resulting in a clock period of (1 / 1.6 Hz) + [(0.2 - 0.8) / 4.8 Hz] = 0.5 s for the output clock CLK OUT. This results in an ideal frequency of 2 Hz for the ideal output clock. 0.2 - 0.8 represents the difference between the basic clock adjustment value for the third signal cycle and the basic clock adjustment value for the second signal cycle.

[0148] In the fourth signal cycle, integer frequency divider circuit 111 integer divides 4.8 Hz by 2, resulting in a clock frequency of 2.4 Hz for the basic clock CLK MMD. The clock period of the basic clock CLK MMD is (1 / 2.4 Hz) s, and the basic clock adjustment value is 0.6. To the clock period of (1 / 2.4 Hz) s, an adjustment value of [(0.6 - 0.2) / 4.8 Hz] s is added, resulting in a clock period of (1 / 2.4 Hz) + [(0.6 - 0.2) / 4.8 Hz] = 0.5 s for the output clock CLK OUT, and thus an ideal frequency of 2 Hz for the ideal output clock. 0.6 - 0.2 represents the difference between the basic clock adjustment value for the fourth signal cycle and the basic clock adjustment value for the third signal cycle.

[0149] In the fifth signal cycle, integer frequency divider circuit 111 integer divides 4.8 Hz by 3, resulting in a clock frequency of 1.6 Hz for the basic clock CLK MMD. The clock period of the basic clock CLK MMD is (1 / 1.6 Hz) s, and the basic clock adjustment value is 0. To the clock period of (1 / 1.6 Hz) s, an adjustment value of [(0-0.6) / 4.8 Hz] s is added, resulting in a clock period of (1 / 1.6 Hz) + [(0-0.6) / 4.8 Hz] = 0.5 s for the output clock CLK OUT, and thus an ideal frequency of 2 Hz for the ideal output clock. 0-0.6 represents the difference between the basic clock adjustment value for the fifth signal cycle and the basic clock adjustment value for the fourth signal cycle.

[0150] The above describes the ideal case where the frequency divider circuit 11 has no gain error or nonlinearity error, and the clock frequency of the output clock CLK OUT (also known as the ideal clock frequency) calculated by the frequency divider circuit 11 is the ideal frequency. However, if the frequency divider circuit 11 has gain error and / or nonlinearity error, the error information output by the correction circuit 13 can be used to correct the clock frequency of the output clock CLK OUT. The operating process can be as follows:

[0151] For example, assuming that the input clock CLK IN received by the frequency divider circuit 11 has a clock frequency of 4.8 Hz and the ideal output clock frequency output by the frequency divider circuit 11 is 2 Hz, the process of using the frequency divider circuit 11 to divide the 4.8 Hz frequency to obtain the output clock CLK OUT and then correcting the clock frequency of the output clock CLK OUT to 2 Hz (or close to 2 Hz) can be achieved over multiple signal cycles. Before the corrected output clock CLK OUT reaches the ideal output clock frequency of 2 Hz, the clock frequency of the corrected clock remains fixed at 2.4 Hz for multiple signal cycles.

[0152] Due to gain error and / or nonlinear error in the frequency divider circuit 11, it is assumed that in the first group of signal cycles (the first to fifth signal cycles), the clock frequency of the output clock CLK OUT decreases by 0.2 Hz for every 0.4 decrease in the basic clock adjustment value, represented by dtc_step1, where dtc_step1 = 0.2 Hz / 0.4 = 0.5 Hz. Of course, depending on the actual design, the relationship between the decrease in the basic clock adjustment value and the decrease in the clock frequency of the output clock CLK OUT may also be different, and this embodiment of the present application is not limited thereto.

[0153] In the first signal cycle, integer divider circuit 111 integer divides 4.8 Hz by 2, with the basic clock adjustment value being 0.4. Due to gain error and / or nonlinearity in divider circuit 11, an error value of 0.4*dtc_step1 is added to the ideal clock frequency of 2 Hz, resulting in an output clock CLK OUT frequency of 2 Hz + 0.4*dtc_step1 = 2 Hz + 0.4*0.5 Hz = 2.2 Hz. The second frequency ratio is 2.4 Hz / 2.2 Hz = 1.2 / 1.1, and the first phase detection result is 0.4*1.2 / 1.1. The fourth frequency ratio is 2.4 Hz / 2 Hz = 1.2, and the second phase detection result is 1.2*0.4 = 0.48. The first phase detection result is calculated by multiplying the second frequency ratio by the basic clock adjustment value, and the second phase detection result is calculated by multiplying the fourth frequency ratio by the basic clock adjustment value. Therefore, 0.4*1.2 / 1.1 represents the first phase detection result of the first signal cycle, and 1.2*0.4 represents the second phase detection result of the first signal cycle.

[0154] Furthermore, by comparing the first phase detection result with the second phase detection result, error information is obtained. Optionally, by subtracting the first phase detection result from the second phase detection result, the error information obtained is 0.4*1.2 / 1.1-0.48, and the frequency adjustment value required to compensate for the first signal cycle is (2Hz-2.2Hz)*0.4=-0.08Hz.

[0155] In the second signal cycle, integer divider circuit 111 integer divides 4.8 Hz by 2, and the basic clock adjustment value is 0.8. Due to gain error and / or nonlinearity in divider circuit 11, the ideal clock frequency of 2 Hz is increased by an error value of (0.8-0.4)*dtc_step1, resulting in an output clock frequency of CLK OUT of 2 Hz + (0.8-0.4)*dtc_step1 = 2 Hz + 0.4*0.5 Hz = 2.2 Hz. The second frequency ratio is 2.4 Hz / 2.2 Hz = 1.2 / 1.1, and the first phase detection result is 0.4*1.2 / 1.1 + 0.8*1.2 / 1.1. The fourth frequency ratio is 2.4 Hz / 2 Hz = 1.2, and the second phase detection result is 1.2*0.4 + 1.2*0.8 = 1.44. The error information is 0.4*1.2 / 1.1+0.8*1.2 / 1.1-(1.2*0.4+1.2*0.8)=1.2*1.2 / 1.1-1.44. The frequency adjustment value required for compensation in the second signal cycle is (2 Hz-2.2 Hz)*0.8=-0.16 Hz.

[0156] In the third signal cycle, integer divider circuit 111 divides 4.8 Hz by 3, and the basic clock adjustment value is 0.2. Due to gain error and / or nonlinearity in divider circuit 11, the ideal clock frequency of 2 Hz is increased by an error value of (0.2-0.8)*dtc_step1, resulting in an output clock frequency of CLK OUT of 2 Hz + (0.2-0.8)*dtc_step1 = 2 Hz - 0.6*0.5 Hz = 1.7 Hz. The second frequency ratio is 2.4 Hz / 1.7 Hz, and the first phase detection result is 0.4*1.2 / 1.1 + 0.8*1.2 / 1.1 + 0.2*2.4 / 1.7. The fourth frequency ratio is 2.4 Hz / 2 Hz = 1.2, and the second phase detection result is 1.2*0.4 + 1.2*0.8 + 1.2*0.2 = 1.68. The error information is 0.4*1.2 / 1.1+0.8*1.2 / 1.1+0.2*2.4 / 1.7-1.68=1.2*1.2 / 1.1+0.48 / 1.7-1.68, and the frequency adjustment value required for compensation in the third signal cycle is (2 Hz-1.7 Hz)*0.2=0.06 Hz.

[0157] In the fourth signal cycle, the integer frequency division circuit 111 divides 4.8 Hz by an integer frequency of 2, and the basic clock adjustment value is 0.6. Because the frequency divider circuit 11 has a gain error and / or nonlinear error, the error value of (0.6-0.2)*dtc_step1 is added to the ideal clock frequency of 2 Hz, resulting in a frequency of the output clock CLK OUT of 2 Hz + (0.6-0.2)*dtc_step1 = 2 Hz + 0.4*0.5 Hz = 2.2 Hz. Therefore, the second frequency ratio is 2.4 Hz / 2.2 Hz = 1.2 / 1.1, and the first phase detection result is 0.4*1.2 / 1.1 + 0.8*1.2 / 1.1 + 0.2*2.4 / 1.7 + 0.6*1.2 / 1.1. The fourth frequency ratio is 2.4 Hz / 2 Hz = 1.2, and the second phase detection result is 1.2*0.4 + 1.2*0.8 + 1.2*0.2 + 1.2*0.6 = 2.4. The error information is 0.4*1.2 / 1.1+0.8*1.2 / 1.1+0.2*2.4 / 1.7+0.6*1.2 / 1.1-2.4=1.8*1.2 / 1.1+0.48 / 1.7-2.4. The frequency adjustment value required to compensate for the fourth signal cycle is (2 Hz-2.2 Hz)*0.6=-0.12 Hz.

[0158] In the fifth signal cycle, integer divider circuit 111 integer divides 4.8 Hz by 3, and the basic clock adjustment value is 0. Due to gain error and / or nonlinearity in divider circuit 11, the ideal clock frequency of 2 Hz is increased by (0-0.6)*dtc_step1, resulting in an output clock CLK OUT frequency of 2 Hz + (0-0.6)*dtc_step1 = 2 Hz - 0.6*0.5 Hz = 1.7 Hz. The second frequency ratio is 2.4 Hz / 1.7 Hz, and the first phase detection result is 0.4*1.2 / 1.1+0.8*1.2 / 1.1+0.2*2.4 / 1.7+0.6*1.2 / 1.1+0*2.4 / 1.7; the fourth frequency ratio is 2.4 Hz / 2 Hz=1.2, and the second phase detection result is 1.2*0.4+1.2*0.8+1.2*0.2+1.2*0.6+1.2*0=2.4. The error information is 0.4*1.2 / 1.1+0.8*1.2 / 1.1+0.2*2.4 / 1.7+0.6*1.2 / 1.1+0*2.4 / 1.7-2.4=1.8*1.2 / 1.1+0.48 / 1.7-2.4. The frequency adjustment value required to compensate for the fifth signal cycle is (2 Hz-1.7 Hz)*0=0 Hz.

[0159] In the first group of signal cycles (the first signal cycle to the fifth signal cycle), the first phase detection result is 1.8*1.2 / 1.1+0.48 / 1.7, the second phase detection result is 2.4, the error information is 1.8*1.2 / 1.1+0.48 / 1.7-2.4, and the total frequency adjustment value required to be compensated for the first group of signal cycles is -0.08-0.16+0.06-0.12+0=-0.3Hz.

[0160] During the second set of signal cycles (the sixth to tenth signal cycles), half of the total frequency adjustment value required for compensation can be corrected based on the error information from the first set of signal cycles, i.e., -0.3 Hz / 2 = -0.15 Hz. Thus, during the second set of signal cycles, for every 0.4 decrease in the difference in the basic clock adjustment value, the clock frequency of the output clock CLK OUT decreases by 0.2 Hz - 0.15 Hz = 0.05 Hz, represented by dtc_step2: dtc_step2 = 0.05 Hz / 0.4 = 0.125 Hz. The -0.15 Hz value can be used as the gain adjustment value Gain adj and / or the nonlinearity adjustment value INL adj described below.

[0161] Of course, in the second group of signal cycles, 1 / 3, 1 / 4, etc. of the total frequency adjustment value required for compensation may also be corrected, and this embodiment of the present application does not limit this.

[0162] The following describes the working process of the frequency division correction circuit in the second group of signal cycles:

[0163] In the sixth signal cycle, integer frequency divider circuit 111 integer divides 4.8 Hz by 2, and the basic clock adjustment value is 0.4. Due to gain error and / or nonlinearity in frequency divider circuit 11, an error value of 0.4*dtc_step2 is added to the ideal clock frequency of 2 Hz, resulting in an output clock CLK OUT frequency of 2 Hz + 0.4*dtc_step2 = 2 Hz + 0.4*0.125 Hz = 2.05 Hz. The second frequency ratio is 2.4 Hz / 2.05 Hz, and the first phase detection result is 0.4*2.4 / 2.05. The fourth frequency ratio is 2.4 Hz / 2 Hz = 1.2, and the second phase detection result is 1.2*0.4 = 0.48. The error information is 0.4*2.4 / 2.05-0.48, and the frequency adjustment value required for compensation in the sixth signal cycle is (2 Hz-2.05 Hz)*0.4 = -0.02 Hz.

[0164] In the seventh signal cycle, integer divider circuit 111 integer divides 4.8 Hz by 2, and the basic clock adjustment value is 0.4. Due to gain error and / or nonlinearity in divider circuit 11, the ideal clock frequency of 2 Hz is increased by an error value of (0.8-0.4)*dtc_step2, resulting in an output clock frequency of CLK OUT of 2 Hz + (0.8-0.4)*dtc_step2 = 2 Hz + 0.4*0.125 Hz = 2.05 Hz. The second frequency ratio is 2.4 Hz / 2.05 Hz, and the first phase detection result is 0.4*2.4 / 2.05 + 0.8*2.4 / 2.05. The fourth frequency ratio is 2.4 Hz / 2 Hz = 1.2, and the second phase detection result is 1.2*0.4 + 1.2*0.8 = 1.44. The error information is 0.4*2.4 / 2.05+0.8*2.4 / 2.05-1.44=1.2*2.4 / 2.05-1.44, and the frequency adjustment value required to compensate for the seventh signal cycle is (2 Hz-2.05 Hz)*0.8=-0.04 Hz.

[0165] In the eighth signal cycle, integer divider circuit 111 integer divides 4.8 Hz by 3, and the basic clock adjustment value is 0.2. Due to gain error and / or nonlinearity in divider circuit 11, the ideal clock frequency of 2 Hz is increased by an error value of (0.2-0.8)*dtc_step2, resulting in an output clock frequency of CLK OUT of 2 Hz + (0.2-0.8)*dtc_step2 = 2 Hz - 0.6*0.125 Hz = 1.925 Hz. The second frequency ratio is 2.4 Hz / 1.925 Hz, and the first phase detection result is 0.4*2.4 / 2.05 + 0.8*2.4 / 2.05 + 0.2*2.4 / 1.925. The fourth frequency ratio is 2.4 Hz / 2 Hz = 1.2, and the second phase detection result is 1.2*0.4 + 1.2*0.8 + 1.2*0.2 = 1.68. The error information is 0.4*2.4 / 2.05+0.8*2.4 / 2.05+0.2*2.4 / 1.925-1.68=1.2*2.4 / 2.05+0.48 / 1.925-1.68, and the frequency adjustment value required to compensate for the eighth signal cycle is (2 Hz-1.925 Hz)*0.2=0.015 Hz.

[0166] During the ninth signal cycle, integer divider circuit 111 divides the 4.8 Hz frequency by 2, resulting in a basic clock adjustment value of 0.6. Due to gain error and / or nonlinearity in divider circuit 111, an error value of (0.6-0.2)*dtc_step2 is added to the ideal clock frequency of 2 Hz, resulting in an output clock frequency of CLK OUT of 2 Hz + (0.6-0.2)*dtc_step2 = 2 Hz + 0.4*0.125 Hz = 2.05 Hz. The second frequency ratio is 2.4 Hz / 2.05 Hz, and the first phase detection result is 0.4*2.4 / 2.05+0.8*2.4 / 2.05+0.2*2.4 / 1.925+0.6*2.4 / 2.05; the fourth frequency ratio is 2.4 Hz / 2 Hz=1.2, and the second phase detection result is 1.2*0.4+1.2*0.8+1.2*0.2+1.2*0.6=2.4. The error information is 0.4*2.4 / 2.05+0.8*2.4 / 2.05+0.2*2.4 / 1.925+0.6*2.4 / 2.05-2.4=1.8*2.4 / 2.05+0.48 / 1.925-2.4. The frequency adjustment value required to compensate for the ninth signal cycle is (2 Hz-2.05 Hz)*0.6=-0.03 Hz.

[0167] In the tenth signal cycle, integer divider circuit 111 integer divides 4.8 Hz by 3, and the basic clock adjustment value is 0. Due to gain error and / or nonlinearity in divider circuit 111, the ideal clock frequency of 2 Hz is increased by (0-0.6)*dtc_step2, resulting in an output clock CLK OUT frequency of 2 Hz + (0-0.6)*dtc_step2 = 2 Hz - 0.6*0.125 Hz = 1.925 Hz. The second frequency ratio is 2.4 / 1.925, and the first phase detection result is 0.4*2.4 / 2.05+0.8*2.4 / 2.05+0.2*2.4 / 1.925+0.6*2.4 / 2.05+0; the fourth frequency ratio is 2.4 Hz / 2 Hz=1.2, and the second phase detection result is 1.2*0.4+1.2*0.8+1.2*0.2+1.2*0.6+1.2*0=2.4. The error information is 0.4*2.4 / 2.05+0.8*2.4 / 2.05+0.2*2.4 / 1.925+0.6*2.4 / 2.05+0*2.4 / 1.925-2.4=1.8*2.4 / 2.05+0.48 / 1.925-2.4. The frequency adjustment value required to compensate for the tenth signal cycle is (2 Hz-1.925 Hz)*0=0 Hz.

[0168] In the second group of signal cycles (the sixth signal cycle to the tenth signal cycle), the first phase detection result is 1.8*2.4 / 2.05+0.48 / 1.925, the second phase detection result is 2.4, the error information is 1.8*2.4 / 2.05+0.48 / 1.925-2.4, and the total frequency adjustment value required to be compensated for the second group of signal cycles is -0.02-0.04+0.015-0.03+0=-0.075Hz.

[0169] During the third set of signal cycles (the eleventh to fifteenth signal cycles), half of the total frequency adjustment value required for compensation can be corrected based on the error information from the second set of signal cycles, i.e., -0.075 Hz / 2 = -0.0375 Hz. Thus, during the third set of signal cycles, for every 0.4 decrease in the basic clock adjustment value, the clock frequency of the output clock CLK OUT decreases by 0.05-0.0375 Hz = 0.0125 Hz, represented by dtc_step3: dtc_step3 = 0.0125 Hz / 0.4 = 0.03125 Hz. The -0.0375 Hz value can be used as the gain adjustment value Gain adj and / or the nonlinear adjustment value INL adj described below.

[0170] The following describes the working process of the frequency division correction circuit in the third group of signal cycles:

[0171] In the eleventh signal cycle, integer divider circuit 111 integer divides 4.8 Hz by 2, and the basic clock adjustment value is 0.4. Due to gain error and / or nonlinearity in divider circuit 11, an error value of 0.4*dtc_step3 is added to the ideal clock frequency of 2 Hz, resulting in an output clock CLK OUT frequency of 2 Hz + 0.4*dtc_step2 = 2 Hz + 0.4*0.03125 Hz = 2.0125 Hz. The second frequency ratio is 2.4 Hz / 2.0125 Hz, and the first phase detection result is 0.4*2.4 / 2.0125. The fourth frequency ratio is 2.4 Hz / 2 Hz = 1.2, and the second phase detection result is 1.2*0.4 = 0.48. The error information is 0.4*2.4 / 2.0125-0.48, and the frequency adjustment value required for compensation in the eleventh signal cycle is (2 Hz-2.0125 Hz)*0.4=-0.005 Hz.

[0172] In the twelfth signal cycle, integer divider circuit 111 integer divides 4.8 Hz by 2, and the basic clock adjustment value is 0.4. Due to gain error and / or nonlinearity in divider circuit 11, the ideal clock frequency of 2 Hz is increased by an error value of (0.8-0.4)*dtc_step3, resulting in an output clock frequency of CLK OUT of 2 Hz + (0.8-0.4)*dtc_step3 = 2 Hz + 0.4*0.03125 Hz = 2.0125 Hz. The second frequency ratio is 2.4 Hz / 2.0125 Hz, and the first phase detection result is 0.4*2.4 / 2.0125 + 0.8*2.4 / 2.0125. The fourth frequency ratio is 2.4 Hz / 2 Hz = 1.2, and the second phase detection result is 1.2*0.4 + 1.2*0.8 = 1.44. The error information is 0.4*2.4 / 2.0125+0.8*2.4 / 2.0125-1.44=1.2*2.4 / 2.0125-1.44, and the frequency adjustment value required for compensation in the twelfth signal cycle is (2 Hz-2.0125 Hz)*0.8=-0.01 Hz.

[0173] In the thirteenth signal cycle, integer divider circuit 111 integer divides 4.8 Hz by 3, and the basic clock adjustment value is 0.2. Due to gain error and / or nonlinearity in divider circuit 111, the ideal clock frequency of 2 Hz is increased by (0.2 - 0.8) * dtc_step3, resulting in an output clock frequency of CLK OUT of 2 Hz + (0.2 - 0.8) * dtc_step3 = 2 Hz - 0.6 * 0.03125 Hz = 1.98125 Hz. The second frequency ratio is 2.4 Hz / 1.98125 Hz, and the first phase detection result is 0.4*2.4 / 2.05 + 0.8*2.4 / 2.05 + 0.2*2.4 / 1.98125 = 1.2*2.4 / 2.0125 + 0.2*2.4 / 1.98125. The fourth frequency ratio is 2.4 Hz / 2 Hz = 1.2, and the second phase detection result is 1.2 + 1.2*0.2 = 1.68. The error information is 1.2*2.4 / 2.0125 + 0.2*2.4 / 1.98125 - 1.68, and the frequency adjustment value required to compensate for the thirteenth signal cycle is (2 Hz - 1.98125 Hz) * 0.2 = 0.00375 Hz.

[0174] In the fourteenth signal cycle, integer divider circuit 111 integer divides 4.8 Hz by 2, resulting in a basic clock adjustment value of 0.6. Due to gain error and / or nonlinearity in divider circuit 111, the ideal clock frequency of 2 Hz is increased by (0.6 - 0.2) * dtc_step3, resulting in an output clock frequency of CLK OUT of 2 Hz + (0.6 - 0.2) * dtc_step3 = 2 Hz + 0.4 * 0.03125 Hz = 2.0125 Hz. The second frequency ratio is 2.4 Hz / 2.0125 Hz, and the first phase detection result is 0.4*2.4 / 2.0125 + 0.8*2.4 / 2.0125 + 0.2*2.4 / 1.98125 + 0.6*2.4 / 2.0125 = 1.8*2.4 / 2.0125 + 0.2*2.4 / 1.98125. The fourth frequency ratio is 2.4 Hz / 2 Hz = 1.2, and the second phase detection result is 1.68 + 1.2*0.6 = 2.4. The error information is 1.8*2.4 / 2.0125 + 0.2*2.4 / 1.98125 - 2.4. The frequency adjustment value required to compensate for the fourteenth signal cycle is (2 Hz - 2.0125 Hz) * 0.6 = -0.0075 Hz.

[0175] In the fifteenth signal cycle, integer divider circuit 111 integer divides 4.8 Hz by 3, and the basic clock adjustment value is 0. Due to gain error and / or nonlinearity in divider circuit 111, the ideal clock frequency of 2 Hz is increased by (0-0.6)*dtc_step3, resulting in an output clock CLK OUT frequency of 2 Hz + (0-0.6)*dtc_step3 = 2 Hz - 0.6*0.03125 Hz = 1.98125 Hz. The second frequency ratio is 2.4 / 1.98125, and the first phase detection result is 0.4*2.4 / 2.0125+0.8*2.4 / 2.0125+0.2*2.4 / 1.98125+0.6*2.4 / 2.0125+0=1.8*2.4 / 2.0125+0.2*2.4 / 1.98125. The fourth frequency ratio is 2.4Hz / 2Hz=1.2, and the second phase detection result is 2.4+1.2*0=2.4. The error information is 1.8*2.4 / 2.0125+0.2*2.4 / 1.98125-2.4, and the frequency adjustment value required to compensate for the fifteenth signal period is (2Hz-1.98125Hz)*0=0Hz.

[0176] In the third group of signal cycles (the eleventh signal cycle to the fifteenth signal cycle), the first phase detection result is 1.8*2.4 / 2.0125+0.2*2.4 / 1.98125, the second phase detection result is 2.4, the error information is 1.8*2.4 / 2.0125+0.2*2.4 / 1.98125-2.4, and the total frequency adjustment value required to be compensated for the third group of signal cycles is -0.005-0.01+0.00375-0.0075+0=-0.01875Hz.

[0177] It can be seen that from the first group of signal cycles to the third group of signal cycles, the frequency of the output clock CLK OUT gradually approaches 2 Hz, and the sum of the error information and the frequency adjustment value required for compensation also gradually approaches zero.

[0178] This process is repeated in this way until the frequency of the output clock CLK OUT is 2 Hz (or close to 2 Hz) in a group of signal cycles, and the sum of the error information and the required frequency adjustment value for compensation approaches 0. In this way, the frequency of the output clock CLK OUT in any signal cycle after this group of signal cycles is 2 Hz (or close to 2 Hz). This avoids the situation where, after the corrected frequency of the output clock CLK OUT is equal to the ideal frequency due to an excessively large sum of the error information and the required frequency adjustment value for compensation, the frequency of the output clock CLK OUT in subsequent groups of signal cycles is corrected using the sum of the error information and the required frequency adjustment value for compensation, resulting in a further significant difference between the frequency of the output clock CLK OUT and the ideal frequency.

[0179] The above describes the calibration process from the first to the fifteenth signal cycle, using the example of an input clock CLK IN with a clock frequency of 4.8 Hz and an ideal output clock frequency of 2 Hz. During this process, the calibration clock CLK ADPLL maintains a fixed clock frequency of 2.4 Hz.

[0180] In other possible implementations, the clock frequency of the input clock CLK IN changes, and / or the output frequency of the ideal output clock changes, and / or after the frequency division correction circuit is powered on again, the clock frequency of the correction clock CLK ADPLL may remain at 2.4 Hz, or the clock frequency of the correction clock CLK ADPLL may also change, depending on the comparison result of the fourth frequency ratio and the fifth frequency ratio with the preset accuracy.

[0181] Specifically, the correction circuit 13 has a certain resolution during the phase detection and error information calculation process. When the decimal places of the fourth frequency ratio and the fifth frequency ratio are too small, the correction circuit 13 ignores the decimal places of the fourth frequency ratio and the fifth frequency ratio due to the resolution, thereby affecting the correction accuracy of the output clock CLK OUT.

[0182] Based on this, the embodiment of the present application can set a preset accuracy based on the resolution of the correction circuit 13. Furthermore, based on the preset accuracy and the clock frequency of the ideal output clock, the clock frequency of the correction clock CLK ADPLL is set so that the decimal places of the fourth frequency ratio and the decimal places of the fifth frequency ratio are both greater than the preset accuracy, thereby improving the correction accuracy of the output clock.

[0183] For example, the preset accuracy is 0.01, the clock frequency of the ideal output clock is 2 Hz, the clock frequency of the correction clock CLK ADPLL is 2.01 Hz, and the fourth frequency ratio is 2.01 Hz / 2 Hz=1.005. The decimal place of 1.005 is smaller than the preset accuracy of 0.01 and is ignored by the correction circuit 13, thereby affecting the correction accuracy of the output clock CLK OUT.

[0184] For another example, the preset accuracy is 0.01, the clock frequency of the ideal output clock is 2 Hz, the clock frequency of the correction clock CLK ADPLL is 2.4 Hz, the fourth frequency ratio is 2.4 Hz / 2 Hz=1.2, and the fifth frequency ratio is 2 Hz / 2.4 Hz≈0.83. The decimal places of 1.2 and 0.83 are both greater than the preset accuracy of 0.01.

[0185] For another example, if the preset accuracy is 0.01, the ideal output clock frequency is 3 Hz, and the correction clock CLK ADPLL frequency remains at 2.4 Hz, the fourth frequency ratio is 2.4 Hz / 3 Hz = 0.8, and the fifth frequency ratio is 3 Hz / 2.4 Hz = 1.25. The decimal places of 0.8 and 1.25 are both greater than the preset accuracy of 0.01. Alternatively, if the correction clock CLK ADPLL frequency is changed to 3.5 Hz, the fourth frequency ratio is 3.5 Hz / 3 Hz ≈ 1.67, and the fifth frequency ratio is 3 Hz / 3.5 Hz ≈ 0.86. The decimal places of 1.67 and 0.86 are both greater than the preset accuracy of 0.01.

[0186] Of course, based on the resolution of the correction circuit 13 , the preset accuracy may also be set to other values, which is not limited in the embodiment of the present application.

[0187] In some embodiments, as shown in FIG6 , the correction circuit 13 includes a second phase detector 131 , an error comparison circuit 132 , and a compensation circuit 133 .

[0188] The process of calculating the first phase detection result and the second phase detection result is implemented by the second phase detector 131 , and the process of subtracting the first phase detection result from the second phase detection result is implemented by the error comparison circuit 132 .

[0189] On this basis, the compensation circuit 133 obtains a gain adjustment value Gain adj and / or a nonlinear adjustment value INL adj according to the received error information, and inputs the gain adjustment value Gainadj and / or the nonlinear adjustment value INL adj to the frequency divider circuit 11. The gain adjustment value Gainadj and / or the nonlinear adjustment value INL adj may be half of the sum of the frequency adjustment values ​​required for compensation (e.g., -1.5 Hz obtained based on the first set of signal cycles, -0.0375 Hz obtained based on the second set of signal cycles, etc.).

[0190] The frequency dividing circuit 11 adjusts the clock frequency of the output clock CLK OUT output in the next group of signal cycles according to the gain adjustment value Gain adj and / or the nonlinear adjustment value INL adj. The specific adjustment method can refer to the examples of the first to third groups of signal cycles mentioned above.

[0191] The first to third signal cycles described above represent the process of calibrating the frequency of the output clock CLK OUT. This process can occur during the adjustment phase, allowing the frequency divider circuit to provide an accurate output clock to other circuits during the subsequent operating phase. The adjustment phase refers to the period before the frequency divider circuit 11 provides the output clock to other circuits, enabling the other circuits to operate normally under the triggering of the output clock CLK OUT. The operating phase refers to the period after the output clock CLK OUT is accurately calibrated during the adjustment phase, when the frequency divider circuit 11 provides the output clock to other circuits, enabling the other circuits to operate normally under the triggering of the output clock CLK OUT.

[0192] Of course, the above process of correcting the clock frequency of the output clock CLK OUT can also occur during the working phase, and the output clock CLK OUT of the divided clock output can be corrected in real time to avoid affecting the operation of other circuits due to errors in the frequency of the output clock CLK OUT.

[0193] In the above, every five signal cycles are divided into a group of signal cycles based on the changing signal cycle of the basic clock adjustment value. The frequency of the output clock CLK OUT in the second group of signal cycles is corrected based on the error information of the first group of signal cycles. The frequency of the output clock CLK OUT in the third group of signal cycles is corrected based on the error information of the second group of signal cycles, and so on.

[0194] In other possible implementations, a group of signal cycles may further include one signal cycle, and the frequency of the output clock CLK OUT in the next signal cycle may be corrected based on the error information of the current signal cycle. When a group of signal cycles further includes one signal cycle, the frequency of the output clock CLK OUT is corrected using the frequency division correction circuit in the same manner as described above for the first through fifteenth signal cycles.

[0195] The second phase detector 131 is configured to calculate a second frequency ratio between the clock frequency of the correction clock and the frequency of the output clock CLK OUT, or a third frequency ratio between the frequency of the output clock CLK OUT and the clock frequency of the correction clock, in the current signal cycle; and obtain a first phase detection result between the output clock CLK OUT and the correction clock CLK ADPLL in the current signal cycle based on the product of the second frequency ratio and the basic clock adjustment value, or based on the product of the third frequency ratio and the basic clock adjustment value.

[0196] The second phase detector 131 is further configured to calculate a fourth frequency ratio between the clock frequency of the correction clock and the frequency of the ideal output clock CLK OUT, or a fifth frequency ratio between the frequency of the ideal output clock and the clock frequency of the correction clock, in the current signal cycle; and obtain a second phase detection result between the ideal output clock and the correction clock CLK ADPLL in the current signal cycle based on the product of the fourth frequency ratio and the basic clock adjustment value, or based on the product of the fifth frequency ratio and the basic clock adjustment value.

[0197] The error comparison circuit 132 is configured to receive the first phase detection result and the second phase detection result, and to perform a subtraction between the first phase detection result and the second phase detection result to obtain error information. If the first phase detection result is calculated using the second frequency ratio and the basic clock adjustment value, the second phase detection result is calculated using the fourth frequency ratio and the basic clock adjustment value. If the first phase detection result is calculated using the third frequency ratio and the basic clock adjustment value, the second phase detection result is calculated using the fifth frequency ratio and the basic clock adjustment value.

[0198] The compensation circuit 133 is configured to obtain a gain adjustment value and / or a nonlinear adjustment value according to the error information, and input the gain adjustment value and / or the nonlinear adjustment value to the frequency dividing circuit.

[0199] The frequency dividing circuit 11 is further configured to output a corrected output clock CLK OUT in the next signal cycle according to the gain adjustment value and / or the nonlinear adjustment value.

[0200] This calculation process is the same as the calculation process in the aforementioned example where a group of signal cycles includes 5 signal cycles, and will not be repeated here.

[0201] In some possible implementations, after receiving the error information, the compensation circuit 133 can obtain the gain adjustment value Gain adj and / or the nonlinear adjustment value INL adj according to a preset formula or lookup table, etc., which is not limited in the embodiments of the present application.

[0202] In some embodiments, the fractional frequency adjustment circuit 114 is further configured to obtain a second adjustment code value based on the gain adjustment value Gain adj and / or the nonlinear adjustment value INL adj, and to correct the clock frequency of the output clock CLK OUT output in the next signal cycle based on the second adjustment code value.

[0203] In some possible implementations, after the fractional frequency adjustment circuit 114 receives the gain adjustment value Gain adj and / or the nonlinear adjustment value INL adj, it can obtain a second adjustment code value according to a preset formula or lookup table, etc., which is not limited in the embodiments of the present application.

[0204] The above example describes how to use error information from the first signal cycle to the fifth signal cycle to obtain a gain adjustment value Gain adj and / or a nonlinear adjustment value INL adj, and use a second adjustment code value corresponding to the gain adjustment value Gain adj and / or the nonlinear adjustment value INL adj to correct the output clock of the next group of signal cycles.

[0205] In some other possible implementations, the error information may be used to obtain a second adjustment code value, and the second adjustment code value may be directly used to correct the output clock of the next group of signal cycles.

[0206] Whether the basic clock CLK MMD is adjusted according to the first adjustment code value by the fractional frequency division circuit 112, or the output clock CLK OUT is corrected according to the second adjustment code value by the fractional frequency division circuit 112, it can be achieved by adjusting at least one of the resistance value, capacitance value, voltage value, and inductance value of the components included in the fractional frequency division circuit 112.

[0207] Here, the embodiment of the present application does not limit the case where the frequency of the output clock CLK OUT is too large or too small, and at least one of the resistance value, capacitance value, voltage value, and inductance value of the components included in the fractional frequency division circuit 112 must be increased or decreased. The specific adjustment method is related to the components included in the fractional frequency division circuit 112 and their parameters, as well as the connection relationship between the components.

[0208] In some embodiments, as shown in FIG7 , the auxiliary calibration circuit 12 may include a first clock generator 123. For example, the first clock generator 123 may be a voltage-controlled oscillator (VCO). However, the first clock generator 123 may experience frequency drift due to factors such as time and temperature, resulting in the calibration clock output by the auxiliary calibration circuit 12 being an unstable clock signal.

[0209] Based on this, the auxiliary correction circuit 12 may further include, in addition to the first clock generator 123, a first phase detector 121 and a first filter 122. The first phase detector 121 is configured to receive the first reference clock CLK REF1 and the correction clock CLK ADPLL fed back by the first clock generator 123, and perform phase detection on the first reference clock CLK REF1 and the correction clock CLK ADPLL to obtain a third phase detection result. The first filter 122 is configured to receive the third phase detection result and filter the third phase detection result to ensure that the clock frequency of the correction clock CLK ADPLL output by the first clock generator 123 is a stable correction clock frequency, thereby improving the quality and stability of the correction clock CLK ADPLL and saving time in correcting the output clock CLK OUT. Optionally, the first filter 122 may be a low-pass filter (LPF).

[0210] Of course, the circuit structure of the auxiliary correction circuit 12 is only an example. Any technician familiar with this technical field who proposes a circuit structure of the auxiliary correction circuit 12 that can provide a stable correction clock CLK ADPLL within the technical scope disclosed in this application should be covered by the protection scope of this application.

[0211] In some possible implementations, the clock frequency of the first reference clock CLK REF1 may be a certain value. When the frequency drift problem is not considered, the auxiliary correction circuit 12 may send the first reference clock CLK REF1 as the correction clock CLK ADPLL to the correction circuit 13 .

[0212] In some possible implementations, as shown in FIG7 , a first phase detector 121 can be used to perform phase detection between the first reference clock CLK REF1 and the correction clock CLK ADPLL, thereby obtaining the correction clock CLK ADPLL from the first reference clock CLK REF1. Alternatively, a stable correction clock CLK ADPLL can be obtained from the first reference clock CLK REF1 using other methods. Alternatively, a stable correction clock CLK ADPLL can be obtained using other clocks, although this is not limited in this embodiment of the present application.

[0213] In some embodiments, as shown in FIG8 , the second phase detector 131 includes a first calculation circuit 1311 , a second calculation circuit 1312 , and a first adder 1313 .

[0214] The first calculation circuit 1311 receives the correction clock CLK ADPLL sent by the auxiliary correction circuit 12 and the output clock CLK OUT sent by the frequency division circuit 11, and calculates the second frequency ratio and the basic clock adjustment value, or the third frequency ratio and the basic clock adjustment value, in a group of signal cycles to obtain an integer bit result in the first phase detection result.

[0215] For example, the second frequency ratio of the first signal cycle is 1.2 / 1.1, the first phase detection result is 0.4*1.2 / 1.1≈0.44, and the first calculation circuit 1311 outputs the integer digit of 0.44 as 0. The second frequency ratio of the second signal cycle is 1.2 / 1.1, the first phase detection result is 0.4*1.2 / 1.1+0.8*1.2 / 1.1≈1.31, and the first calculation circuit 1311 outputs the integer digit of 1.31 as 1.

[0216] The second calculation circuit 1312 receives the correction clock CLK ADPLL sent by the auxiliary correction circuit 12 and the output clock CLK OUT sent by the frequency division circuit 11, and calculates the second frequency ratio and the basic clock adjustment value, or the third frequency ratio and the basic clock adjustment value, in a group of signal cycles to obtain the decimal point result in the first phase detection result.

[0217] For example, if the second frequency ratio of the first signal cycle is 1.2 / 1.1, the first phase detection result is 0.4*1.2 / 1.1≈0.44, and the second calculation circuit 1312 outputs the decimal point of 0.44 as 0.44. If the second frequency ratio of the second signal cycle is 1.2 / 1.1, the first phase detection result is 0.4*1.2 / 1.1+0.8*1.2 / 1.1≈1.31, and the second calculation circuit 1312 outputs the decimal point of 1.31 as 0.31.

[0218] The first adder 1313 receives the integer result and the decimal result, adds the integer result and the decimal result, and obtains a first phase detection result.

[0219] For example, in the first signal cycle, the first phase detection result calculated by the first adder 1313 is 0+0.44=0.44; in the second signal cycle, the first phase detection result calculated by the first adder 1313 is 1+0.31=1.31.

[0220] In some embodiments, the clock frequency of the correction clock CLK ADPLL and the ideal frequency of the ideal output frequency used to calculate the second phase detection result can be obtained in advance. In this case, the second phase detection result can be calculated directly based on the known clock frequency of the correction clock and the ideal frequency.

[0221] In other embodiments, the first reference clock CLK REF1 input to the auxiliary correction circuit 12 may have a low-frequency frequency drift due to factors such as time and temperature, resulting in an inaccurate clock frequency of the correction clock CLK ADPLL. Alternatively, the first reference clock CLK REF1 is unpredictable, that is, the clock frequency of the correction clock CLK ADPLL is unpredictable, and thus a correct second phase detection result cannot be calculated.

[0222] In this case, the embodiment of the present application can obtain the second phase-locked result through the error comparison circuit 132 and the first phase-locked result input to the error comparison circuit 132, thereby obtaining the difference between the error information of the current signal cycle and the error information of the previous signal cycle based on the first phase-locked result and the second phase-locked result.

[0223] Specifically, as shown in FIG9 , the error comparison circuit 132 includes a register 1321 , a second adder 1322 , a third adder 1323 , and a second filter 1324 .

[0224] The register 1321 inputs the phase detection result of the output clock CLK OUT and the correction clock CLK ADPLL in the previous signal cycle to the second adder 1322 through shifting, and then receives and stores the phase detection result of the input and output clock CLK OUT and the correction clock CLK ADPLL in the current signal cycle of the second phase detector 1321, so as to input the phase detection result of the current signal cycle to the second adder 1322 in the next signal cycle.

[0225] The second adder 1322 receives the phase detection result of the current signal cycle and the phase detection result of the previous signal cycle, and subtracts the phase detection result of the current signal cycle from the phase detection result of the previous signal cycle to obtain the current phase detection result of the current signal cycle.

[0226] For example, the first phase detection result of the first signal cycle is 0.4*1.2 / 1.1, and the first phase detection result of the second signal cycle is 0.4*1.2 / 1.1+0.8*1.2 / 1.1. The difference between the two is the current phase detection result FCW of the second signal cycle, which is 0.8*1.2 / 1.1.

[0227] The second filter 1324 receives the current phase detection result and filters the current phase detection result to obtain a second phase detection result of the ideal output clock and the correction clock in the current signal cycle. Optionally, the second filter 1324 can be an LPF.

[0228] For example, the current phase detection result FCW of the second signal cycle is 0.8*1.2 / 1.1, and filtering is performed to obtain the second phase detection result of the current signal cycle 0.8*2.4 Hz / 2 Hz=0.8*1.2.

[0229] The third adder 1323 performs a subtraction between the current phase detection result and the second phase detection result of the current signal cycle to obtain the difference between the error information of the current signal cycle and the error information of the previous signal cycle. The error information differences of a group of signal cycles are added together to obtain the error information of a group of signal cycles.

[0230] For example, the third adder 1323 is used to subtract the current first phase-detection result 0.8*1.2 / 1.1 (the first phase-detection result 0.8*1.2 / 1.1 of the second signal period) from the second phase-detection result 0.8*1.2 of the current signal period (the second phase-detection result 0.8*1.2 of the second signal period), and the difference in error information obtained is approximately 0.09, that is, the error information of the second signal period minus the error information of the first signal period 1.2*1.2 / 1.1-1.44-(0.4*1.2 / 1.1-0.48)≈0.09.

[0231] In this way, when the clock frequency of the correction clock cannot be predicted or the accurate clock frequency of the correction clock cannot be obtained, the second phase-locked detection result can be calculated, thereby obtaining the difference between the error information of the current signal period and the error information of the previous signal period based on the first phase-locked detection result and the second phase-locked detection result, and by accumulating the multiple calculated differences, the error information can be obtained.

[0232] On this basis, the second filter 1324 of the present application can be implemented by a digital circuit or an analog circuit, replacing the implementation method of the ADPLL, to avoid the situation where, when the frequency division circuit 11 implements near-integer frequency division, the second filter 1324 cannot be used to filter the current first phase-locked detection result to obtain an accurate correction clock CLK ADPLL, and thus accurate error information cannot be obtained.

[0233] The above description uses the example of a frequency division correction circuit including a frequency division circuit 11, an auxiliary correction circuit 12, and a correction circuit 13 to describe the modules and their operating principles within the frequency division circuit 11, the auxiliary correction circuit 12, and the correction circuit 13. As shown in FIG10 , the frequency division correction circuit may also include multiple frequency division circuits 11, an auxiliary correction circuit 12, and multiple correction circuits 13. The modules and their operating principles within the multiple frequency division circuits 11, the auxiliary correction circuit 12, and the correction circuit 13 are the same as those within the single frequency division circuit 11, the auxiliary correction circuit 12, and the correction circuit 13, but the signals transmitted by the two circuits may be the same or different.

[0234] For example, as shown in FIG. 10 , the frequency division correction circuit includes two frequency division circuits 11 , one auxiliary correction circuit 12 , and two correction circuits 13 .

[0235] In the first frequency divider circuit 11, the incremental summation circuit 113 receives the first frequency ratio 1, inputs the value N1 to the integer frequency divider circuit 111, and inputs the basic clock adjustment value 1 to the fractional frequency divider adjustment circuit 114; the integer frequency divider circuit 111 receives the input clock CLK IN1, and inputs the basic clock CLK MMD1 to the fractional frequency divider circuit 112; the fractional frequency divider adjustment circuit 114 receives the basic clock adjustment value 1, and inputs the first adjustment code value 1 to the fractional frequency divider circuit 112; the fractional frequency divider circuit 112 receives the first adjustment code value 1 and the basic clock CLK MMD1, and inputs the output clock CLK OUT1 to the second phase detector circuit 131.

[0236] In the second frequency divider circuit 12, the incremental summation circuit 113 receives the first frequency ratio 2, inputs the value N2 to the integer frequency divider circuit 111, and inputs the basic clock adjustment value 2 to the fractional frequency divider adjustment circuit 114; the integer frequency divider circuit 111 receives the input clock CLK IN2, and inputs the basic clock CLK MMD2 to the fractional frequency divider circuit 112; the fractional frequency divider adjustment circuit 114 receives the basic clock adjustment value 2, and inputs the first adjustment code value 2 to the fractional frequency divider circuit 112; the fractional frequency divider circuit 112 receives the first adjustment code value 2 and the basic clock CLK MMD2, and inputs the output clock CLK OUT2 to the second phase detector circuit 131.

[0237] The same auxiliary correction circuit 12 can input the same correction clock CLK ADPLL to the second phase detection circuit 131 of the first correction circuit 13 and the second phase detection circuit 131 of the second correction circuit 13 .

[0238] In the first correction circuit 13, the second phase detection circuit 131 receives the correction clock CLK ADPLL and the output clock CLK OUT1, and inputs a first phase detection result 1 to the error comparison circuit 132. The error comparison circuit 132 receives the first phase detection result 1 and inputs error information 1 to the compensation circuit 133. The compensation circuit 133 receives the error information 1 and inputs a gain adjustment value Gain adj1 and / or a nonlinear adjustment value INL adj1 to the fractional frequency adjustment circuit 114. In the first frequency division circuit 11, the fractional frequency adjustment circuit 114 receives the gain adjustment value Gain adj1 and / or the nonlinear adjustment value INL adj1 and inputs a second adjustment code value 1 to the fractional frequency division circuit 112.

[0239] In the second correction circuit 13, the second phase detection circuit 131 receives the correction clock CLK ADPLL and the output clock CLK OUT2, and inputs the first phase detection result 2 to the error comparison circuit 132. The error comparison circuit 132 receives the first phase detection result 2 and inputs the error information 2 to the compensation circuit 133. The compensation circuit 133 receives the error information 2 and inputs the gain adjustment value Gain adj2 and / or the nonlinear adjustment value INL adj2 to the fractional frequency adjustment circuit 114. In the second frequency division circuit 11, the fractional frequency adjustment circuit 114 receives the gain adjustment value Gain adj2 and / or the nonlinear adjustment value INL adj2 and inputs the second adjustment code value 2 to the fractional frequency division circuit 112.

[0240] In some embodiments, as shown in FIG11 , the frequency division correction circuit further includes a clock generation circuit 14 . The clock generation circuit 14 is configured to generate an input clock CLK IN and input the input clock CLK IN to the frequency division circuit 11 .

[0241] Specifically, as shown in FIG11 , the clock generating circuit 14 includes a third phase detector 141 , a third filter 142 , and a second clock generator 143 .

[0242] The second clock generator 143 generates an input clock CLK IN and inputs the input clock CLK IN to the frequency dividing circuit 11. Optionally, the second clock generator 143 may be a VCO.

[0243] The third phase detector 141 receives the second reference clock CLK REF2 and the output clock CLK OUT, performs phase detection on the second reference clock CLK REF2 and the output clock CLK OUT, and obtains a fourth phase detection result.

[0244] In some possible implementations, the third phase detector 141 is used to perform phase detection on the second reference clock CLK REF2 and the output clock CLK OUT. The calculation is not limited to calculating the ratio of the clock frequencies of the two. It only needs to correlate the second reference clock CLK REF2 and the output clock CLK OUT.

[0245] The third filter 142 receives the fourth phase detection result and filters the fourth phase detection result to adjust the clock frequency of the input clock CLK IN output by the second clock generator 143. Optionally, the third filter 142 may be an LPF.

[0246] Continuing with the example of an ideal input clock CLK IN with a clock frequency of 4.8 Hz and an ideal output clock with a frequency of 2 Hz, since 2 Hz and 4.8 Hz are not clock frequencies at the same rate, they cannot be phase-detected. Therefore, upon receiving the 4.8 Hz input clock CLK IN, the frequency divider circuit 11 first divides the 4.8 Hz input clock and then inputs the divided output clock CLK OUT to the third phase detector 141. The third phase detector 141 can perform phase detection on the output clock CLK OUT and the second reference clock CLK REF2 to determine whether the input clock CLK IN received by the frequency divider circuit 11 is too fast or too slow. The third filter 142 then filters the fourth phase detection result to adjust the clock frequency of the input clock CLK IN output by the second clock generator 143.

[0247] However, in order to accurately correct the clock frequency of the input clock CLK IN, it is desirable that the error in the output clock CLK OUT input by the frequency divider circuit 11 to the third phase detector 141 originates solely from the input clock CLK IN output by the clock generation circuit 14. However, as previously mentioned, when the frequency divider circuit 11 divides the input clock CLK IN, gain error and / or nonlinear error may also exist. The output clock CLK OUT input to the third phase detector 141 may be contaminated with the gain error and / or nonlinear error, making it unclear whether the frequency error in the output clock CLK OUT originates from the input clock CLK IN or the gain error and / or nonlinear error. Therefore, the auxiliary correction circuit 12 and correction circuit 13 of the present application can be used to correct the frequency of the output clock CLK OUT to compensate for the gain error and / or nonlinear error, thereby ensuring that the frequency error in the output clock CLK OUT input by the frequency divider circuit 11 to the second clock generator 143 originates solely from the input clock CLK IN. In this way, it is only necessary to filter the fourth phase detection result by the third filter 142 to adjust the clock frequency of the input clock CLK IN output by the second clock generator 143 .

[0248] Here, the specific process of using the auxiliary correction circuit 12 and the correction circuit 13 to correct the frequency of the output clock CLK OUT to compensate for the gain error and / or nonlinear error is described above and will not be repeated here.

[0249] In another embodiment, the present application also provides a control method for a clock correction circuit, wherein the clock correction circuit includes a frequency division circuit 11, an auxiliary correction circuit 12, and a correction circuit 13. As shown in FIG12 , the method can be implemented by the following steps:

[0250] S110 , the received input clock CLK IN is divided by the frequency dividing circuit 11 to obtain the output clock CLK OUT.

[0251] S120 , using the auxiliary correction circuit 12 to generate a correction clock CLK ADPLL, where the clock frequency of the correction clock CLK ADPLL is constant.

[0252] S130, using the correction circuit 13, performing phase detection on the received output clock CLK OUT and the correction clock CLK ADPLL to obtain a first phase detection result; using the correction circuit 13, performing phase detection on the ideal output clock and the correction clock CLK ADPLL to obtain a second phase detection result; and using the correction circuit 13, comparing the first phase detection result with the second phase detection result to obtain error information of the output clock CLK OUT, so as to correct the clock frequency of the output clock CLK OUT output by the frequency divider circuit 11 based on the error information.

[0253] Correction circuit 13 performs phase detection on output clock CLK OUT and correction clock CLK ADPLL to obtain a first phase detection result, and compares the first phase detection result with the second phase detection result to obtain error information. Based on the error information, frequency divider circuit 11 outputs a corrected output clock CLK OUT until the frequency of the corrected output clock CLK OUT matches the ideal frequency (or the frequency of the corrected output clock CLK OUT approaches the ideal frequency), thereby resolving the aforementioned gain error and nonlinear error problems.

[0254] Furthermore, since the auxiliary correction circuit 12 is in operation, its generation of the correction clock CLK ADPLL does not depend on whether it receives the output clock CLK OUT. Therefore, as shown in FIG4 , when there are multiple frequency divider circuits 11 and correction circuits 13, the multiple frequency divider circuits 11 and correction circuits 13 share the same auxiliary correction circuit 12. The multiple correction circuits 13 can receive the correction clock CLK ADPLL output by the same auxiliary correction circuit 12 and the output clock CLK OUT output by the corresponding frequency divider circuit 11, thereby correcting the frequency of the output clock CLK OUT. This solves the problem in the related art where each frequency divider circuit 11 requires an auxiliary correction circuit 12 for error compensation.

[0255] When frequency division is performed using the frequency division correction circuit provided in the embodiments of the present application, the clock frequency of the correction clock CLK ADPLL is a constant (e.g., 2.4 Hz) and is independent of the clock frequency of the output clock CLK OUT. Therefore, the clock frequency of the correction clock CLK ADPLL can be considered a DC signal. DC signals have no bandwidth and do not contain the aforementioned low-frequency gain errors and nonlinear errors. Therefore, using the frequency division correction circuit provided in the embodiments of the present application to achieve near-integer frequency division can solve the problem of related technologies that cannot obtain accurate error information from the correction clock CLK ADPLL.

[0256] Phase detection is performed on the output clock CLK OUT and the correction clock CLK ADPLL. This means the phase of the output clock CLK OUT is differentiated from the phase of the correction clock CLK ADPLL. Since frequency can be obtained by differentiating the phase, the phase detection between the output clock CLK OUT and the correction clock CLK ADPLL can be obtained by calculating the frequency ratio between the two clock signals.

[0257] Optionally, the frequency ratio between the two clock signals may be the ratio between the clock frequency of the correction clock CLK ADPLL and the frequency of the output clock CLK OUT, which is referred to as the second frequency ratio. Alternatively, the frequency ratio between the two clock signals may be the ratio between the frequency of the output clock CLK OUT and the clock frequency of the correction clock CLK ADPLL, which is referred to as the third frequency ratio.

[0258] Correspondingly, if the output clock CLK OUT and the correction clock CLK ADPLL are phase-detected and calculated using the second frequency ratio, the phase-detection result between the ideal output clock and the correction clock CLK ADPLL is calculated using the ratio between the clock frequency of the correction clock of the correction clock CLK ADPLL and the ideal frequency of the ideal output clock. This ratio is named the fourth frequency ratio.

[0259] If phase detection is performed between the output clock CLK OUT and the correction clock CLK ADPLL, the phase detection result between the ideal output clock and the correction clock CLK ADPLL is calculated using the first frequency ratio. The ratio between the ideal frequency of the ideal output clock and the clock frequency of the correction clock CLK ADPLL is referred to as the fifth frequency ratio. Unless otherwise specified, the following description uses the second and fourth frequency ratios as examples.

[0260] The following describes the working principle of the frequency division circuit 11 for dividing the input clock CLK IN and the working principle of the correction circuit 13 for frequency compensation of the output clock CLK OUT with reference to the accompanying drawings.

[0261] As shown in FIG5 , the frequency division circuit 11 may include an integer frequency division circuit 111, a fractional frequency division circuit 112, a delta-sum modulator 113, and a fractional frequency division adjustment circuit 114, to divide the input clock CLK IN to obtain the output clock CLK OUT. The specific working principle is as follows:

[0262] The incremental summation circuit 113 inputs a value N to the integer frequency divider circuit 111 based on a first frequency ratio between the clock frequency of the input clock CLK IN and the ideal frequency. N includes n and n+1, and the difference between the first frequency ratio and n, and the difference between n+1 and the first frequency ratio, are both less than 1. n is a positive integer.

[0263] For example, the clock frequency of the input clock CLK IN is 4.8 Hz, the ideal frequency is 2 Hz, and the first frequency ratio is 4.8 Hz / 2 Hz = 2.4. The n whose difference from 2.4 is less than 1 is 2, and n+1 is 3.

[0264] The integer frequency division circuit 111 receives the input clock CLK IN and the value N, and performs integer frequency division on the input clock by interleaving the frequency division by n and by n+1 to obtain the basic clock CLK MMD, and sends the basic clock CLK MMD to the fractional frequency division circuit 112. Optionally, the integer frequency division circuit 111 may include a multi-modulus divider.

[0265] For example, if the input clock CLK IN has a clock frequency of 4.8 Hz and N is 2 or 3, then if the integer frequency divider circuit 111 integer divides 4.8 Hz by 2, the resulting clock frequency of the basic clock CLK MMD is 4.8 Hz / 2 = 2.4 Hz. If the integer frequency divider circuit 111 integer divides 4.8 Hz by 3, the resulting clock frequency of the basic clock CLK MMD is 4.8 Hz / 3 = 1.6 Hz.

[0266] Based on the first frequency ratio, the basic clock adjustment value is input to the fractional frequency adjustment circuit 114 via the incremental summation circuit 113. The basic clock adjustment value is the fractional digit of the accumulated value of the first frequency ratio in each signal cycle. The time period between the frequency divider circuit 11 outputting one output clock CLK OUT and the next output clock CLK OUT is one signal cycle.

[0267] For example, the first frequency ratio is still 2.4, and in the first signal cycle, the decimal place of the accumulated value of the first frequency ratio is 0.4; in the second signal cycle, the decimal place of the accumulated value of the first frequency ratio is 0.4+0.4=0.8; in the third signal cycle, the accumulated value of the first frequency ratio is 0.4+0.4+0.4=1.2, and the decimal place of the accumulated value of the first frequency ratio is 0.2 due to integer carry; in the fourth signal cycle, the accumulated value of the first frequency ratio is 0.4+0.4+0.4+0.4=1.6, and the decimal place of the accumulated value of the first frequency ratio is 0.6; in the fifth signal cycle, the accumulated value of the first frequency ratio is 0.4+0.4+0.4+0.4+0.4=2, and the decimal place of the accumulated value of the first frequency ratio is 0 due to integer carry.

[0268] In this way, the basic clock adjustment values ​​input by the incremental summation circuit 113 to the fractional frequency adjustment circuit 114 are 0.4, 0.8, 0.2, 0.6, 0, 0.4, 0.8, ..., and so on, with every 5 signal cycles forming a group.

[0269] The fractional frequency adjustment circuit 114 obtains a first adjustment code value based on the basic clock adjustment value, and inputs the first adjustment code value into the fractional frequency adjustment circuit 112. Optionally, after receiving the basic clock adjustment value, the fractional frequency adjustment circuit 114 may obtain the first adjustment code value based on a preset formula or a lookup table.

[0270] The basic clock CLK MMD is adjusted by the first adjustment code value through the fractional frequency division circuit 112 to output the output clock CLK OUT. Optionally, the fractional frequency division circuit 112 may include a DTC.

[0271] Under ideal conditions with no gain error and nonlinear error, the clock frequency of the output clock CLK OUT output by the fractional frequency division circuit 112 is an ideal frequency, and the output clock CLK OUT is an ideal output clock.

[0272] For example, in the first signal cycle, integer frequency divider circuit 111 integer divides 4.8 Hz by 2, resulting in a clock frequency of 2.4 Hz for the basic clock CLK MMD. The clock period of the basic clock CLK MMD is (1 / 2.4 Hz) s, and the basic clock adjustment value is 0.4. By adding the adjustment value (0.4 / 4.8 Hz) s to the clock period of (1 / 2.4 Hz) s, the resulting clock period of the output clock CLK OUT is (1 / 2.4 Hz) + (0.4 / 4.8 Hz) = 0.5 s, and thus the ideal frequency of the output clock CLK OUT is 2 Hz.

[0273] During the second signal cycle, integer frequency divider circuit 111 integer divides 4.8 Hz by 2, resulting in a clock frequency of 2.4 Hz for the basic clock CLK MMD. The clock period of the basic clock CLK MMD is (1 / 2.4 Hz) s, and the basic clock adjustment value is 0.8. To the clock period of (1 / 2.4 Hz) s, an adjustment value of [(0.8 - 0.4) / 4.8 Hz] s is added, resulting in a clock period of (1 / 2.4 Hz) + (0.4 / 4.8 Hz) = 0.5 s for the output clock CLK OUT, and thus an ideal frequency of 2 Hz for the output clock CLK OUT. 0.8 - 0.4 represents the difference between the basic clock adjustment value for the second signal cycle and the basic clock adjustment value for the first signal cycle.

[0274] During the third signal cycle, integer frequency divider circuit 111 divides 4.8 Hz by 3, resulting in a clock frequency of 1.6 Hz for the basic clock CLK MMD. The clock period of the basic clock CLK MMD is (1 / 1.6 Hz) s, and the basic clock adjustment value is 0.2. To the clock period of (1 / 1.6 Hz) s, an adjustment value of [(0.2 - 0.8) / 4.8 Hz] s is added, resulting in a clock period of (1 / 1.6 Hz) + [(0.2 - 0.8) / 4.8 Hz] = 0.5 s for the output clock CLK OUT, and thus an ideal frequency of 2 Hz for the output clock CLK OUT. 0.2 - 0.8 represents the difference between the basic clock adjustment value for the third signal cycle and the basic clock adjustment value for the second signal cycle.

[0275] In the fourth signal cycle, integer frequency divider circuit 111 integer divides 4.8 Hz by 2, resulting in a clock frequency of 2.4 Hz for the basic clock CLK MMD. The clock period of the basic clock CLK MMD is (1 / 2.4 Hz) s, and the basic clock adjustment value is 0.6. To the clock period of (1 / 2.4 Hz) s, an adjustment value of [(0.6 - 0.2) / 4.8 Hz] s is added, resulting in a clock period of (1 / 2.4 Hz) + [(0.6 - 0.2) / 4.8 Hz] = 0.5 s for the output clock CLK OUT, and thus an ideal frequency of 2 Hz for the output clock CLK OUT. 0.6 - 0.2 represents the difference between the basic clock adjustment value for the fourth signal cycle and the basic clock adjustment value for the third signal cycle.

[0276] In the fifth signal cycle, integer frequency divider circuit 111 integer divides 4.8 Hz by 3, resulting in a clock frequency of 1.6 Hz for the basic clock CLK MMD. The clock period of the basic clock CLK MMD is (1 / 1.6 Hz) s, and the basic clock adjustment value is 0. To the clock period of (1 / 1.6 Hz) s, an adjustment value of [(0-0.6) / 4.8 Hz] s is added, resulting in a clock period of (1 / 1.6 Hz) + [(0-0.6) / 4.8 Hz] = 0.5 s for the output clock CLK OUT, and thus an ideal frequency of 2 Hz for the output clock CLK OUT. 0-0.6 represents the difference between the basic clock adjustment value for the fifth signal cycle and the basic clock adjustment value for the fourth signal cycle.

[0277] The above describes the ideal case where the frequency divider circuit 11 has no gain error or nonlinearity error, and the clock frequency of the output clock CLK OUT (also known as the ideal clock frequency) calculated by the frequency divider circuit 11 is the ideal frequency. However, if the frequency divider circuit 11 has gain error and / or nonlinearity error, the error information output by the correction circuit 13 can be used to correct the clock frequency of the output clock CLK OUT. The operating process can be as follows:

[0278] For example, assuming that the input clock CLK IN received by the frequency divider circuit 11 has a clock frequency of 4.8 Hz and the ideal output clock frequency output by the frequency divider circuit 11 is 2 Hz, the process of using the frequency divider circuit 11 to divide the 4.8 Hz frequency to obtain the output clock CLK OUT and then correcting the clock frequency of the output clock CLK OUT to 2 Hz (or close to 2 Hz) can be achieved over multiple signal cycles. Before the corrected output clock CLK OUT reaches the ideal output clock frequency of 2 Hz, the clock frequency of the corrected clock remains fixed at 2.4 Hz for multiple signal cycles.

[0279] Due to gain error and / or nonlinear error in the frequency divider circuit 11, during the first group of signal cycles (the first to fifth signal cycles), the clock frequency of the output clock CLKOUT decreases by 0.2 Hz for every 0.4 decrease in the basic clock adjustment value, represented by dtc_step1: dtc_step1 = 0.2 Hz / 0.4 = 0.5 Hz. Of course, depending on the actual design, the relationship between the decrease in the basic clock adjustment value and the decrease in the clock frequency of the output clock CLKOUT may also be other, and this embodiment of the present application is not limited thereto.

[0280] In the first signal cycle, integer divider circuit 111 integer divides 4.8 Hz by 2, with the basic clock adjustment value being 0.4. Due to gain error and / or nonlinearity in divider circuit 11, an error value of 0.4*dtc_step1 is added to the ideal clock frequency of 2 Hz, resulting in an output clock CLK OUT frequency of 2 Hz + 0.4*dtc_step1 = 2 Hz + 0.4*0.5 Hz = 2.2 Hz. The second frequency ratio is 2.4 Hz / 2.2 Hz = 1.2 / 1.1, and the first phase detection result is 0.4*1.2 / 1.1. The fourth frequency ratio is 2.4 Hz / 2 Hz = 1.2, and the second phase detection result is 1.2*0.4 = 0.48. The first phase detection result is calculated by multiplying the second frequency ratio by the basic clock adjustment value, and the second phase detection result is calculated by multiplying the fourth frequency ratio by the basic clock adjustment value. Therefore, 0.4*1.2 / 1.1 represents the first phase detection result of the first signal cycle, and 1.2*0.4 represents the second phase detection result of the first signal cycle.

[0281] Furthermore, by comparing the first phase detection result with the second phase detection result, error information is obtained. Optionally, by subtracting the first phase detection result from the second phase detection result, the error information obtained is 0.4*1.2 / 1.1-0.48, and the frequency adjustment value required to compensate for the first signal cycle is (2Hz-2.2Hz)*0.4=-0.08Hz.

[0282] In the second signal cycle, integer divider circuit 111 integer divides 4.8 Hz by 2, and the basic clock adjustment value is 0.8. Due to gain error and / or nonlinearity in divider circuit 11, the ideal clock frequency of 2 Hz is increased by an error value of (0.8-0.4)*dtc_step1, resulting in an output clock frequency of CLK OUT of 2 Hz + (0.8-0.4)*dtc_step1 = 2 Hz + 0.4*0.5 Hz = 2.2 Hz. The second frequency ratio is 2.4 Hz / 2.2 Hz = 1.2 / 1.1, and the first phase detection result is 0.4*1.2 / 1.1 + 0.8*1.2 / 1.1. The fourth frequency ratio is 2.4 Hz / 2 Hz = 1.2, and the second phase detection result is 1.2*0.4 + 1.2*0.8 = 1.44. The error information is 0.4*1.2 / 1.1+0.8*1.2 / 1.1-(1.2*0.4+1.2*0.8)=1.2*1.2 / 1.1-1.44. The frequency adjustment value required for compensation in the second signal cycle is (2 Hz-2.2 Hz)*0.8=-0.16 Hz.

[0283] In the third signal cycle, integer divider circuit 111 divides 4.8 Hz by 3, and the basic clock adjustment value is 0.2. Due to gain error and / or nonlinearity in divider circuit 11, the ideal clock frequency of 2 Hz is increased by an error value of (0.2-0.8)*dtc_step1, resulting in an output clock frequency of CLK OUT of 2 Hz + (0.2-0.8)*dtc_step1 = 2 Hz - 0.6*0.5 Hz = 1.7 Hz. The second frequency ratio is 2.4 Hz / 1.7 Hz, and the first phase detection result is 0.4*1.2 / 1.1 + 0.8*1.2 / 1.1 + 0.2*2.4 / 1.7. The fourth frequency ratio is 2.4 Hz / 2 Hz = 1.2, and the second phase detection result is 1.2*0.4 + 1.2*0.8 + 1.2*0.2 = 1.68. The error information is 0.4*1.2 / 1.1+0.8*1.2 / 1.1+0.2*2.4 / 1.7-1.68=1.2*1.2 / 1.1+0.48 / 1.7-1.68, and the frequency adjustment value required for compensation in the third signal cycle is (2 Hz-1.7 Hz)*0.2=0.06 Hz.

[0284] In the fourth signal cycle, the integer frequency division circuit 111 divides 4.8 Hz by an integer frequency of 2, and the basic clock adjustment value is 0.6. Because the frequency divider circuit 11 has a gain error and / or nonlinear error, the error value of (0.6-0.2)*dtc_step1 is added to the ideal clock frequency of 2 Hz, resulting in a frequency of the output clock CLK OUT of 2 Hz + (0.6-0.2)*dtc_step1 = 2 Hz + 0.4*0.5 Hz = 2.2 Hz. Therefore, the second frequency ratio is 2.4 Hz / 2.2 Hz = 1.2 / 1.1, and the first phase detection result is 0.4*1.2 / 1.1 + 0.8*1.2 / 1.1 + 0.2*2.4 / 1.7 + 0.6*1.2 / 1.1. The fourth frequency ratio is 2.4 Hz / 2 Hz = 1.2, and the second phase detection result is 1.2*0.4 + 1.2*0.8 + 1.2*0.2 + 1.2*0.6 = 2.4. The error information is 0.4*1.2 / 1.1+0.8*1.2 / 1.1+0.2*2.4 / 1.7+0.6*1.2 / 1.1-2.4=1.8*1.2 / 1.1+0.48 / 1.7-2.4. The frequency adjustment value required to compensate for the fourth signal cycle is (2 Hz-2.2 Hz)*0.6=-0.12 Hz.

[0285] In the fifth signal cycle, integer divider circuit 111 integer divides 4.8 Hz by 3, and the basic clock adjustment value is 0. Due to gain error and / or nonlinearity in divider circuit 11, the ideal clock frequency of 2 Hz is increased by (0-0.6)*dtc_step1, resulting in an output clock CLK OUT frequency of 2 Hz + (0-0.6)*dtc_step1 = 2 Hz - 0.6*0.5 Hz = 1.7 Hz. The second frequency ratio is 2.4 Hz / 1.7 Hz, and the first phase detection result is 0.4*1.2 / 1.1+0.8*1.2 / 1.1+0.2*2.4 / 1.7+0.6*1.2 / 1.1+0*2.4 / 1.7; the fourth frequency ratio is 2.4 Hz / 2 Hz=1.2, and the second phase detection result is 1.2*0.4+1.2*0.8+1.2*0.2+1.2*0.6+1.2*0=2.4. The error information is 0.4*1.2 / 1.1+0.8*1.2 / 1.1+0.2*2.4 / 1.7+0.6*1.2 / 1.1+0*2.4 / 1.7-2.4=1.8*1.2 / 1.1+0.48 / 1.7-2.4. The frequency adjustment value required to compensate for the fifth signal cycle is (2 Hz-1.7 Hz)*0=0 Hz.

[0286] In the first group of signal cycles (the first signal cycle to the fifth signal cycle), the first phase detection result is 1.8*1.2 / 1.1+0.48 / 1.7, the second phase detection result is 2.4, the error information is 1.8*1.2 / 1.1+0.48 / 1.7-2.4, and the total frequency adjustment value required to be compensated for the first group of signal cycles is -0.08-0.16+0.06-0.12+0=-0.3Hz.

[0287] During the second set of signal cycles (the sixth to tenth signal cycles), half of the total frequency adjustment value required for compensation can be corrected based on the error information from the first set of signal cycles, i.e., -0.3 Hz / 2 = -0.15 Hz. Thus, during the second set of signal cycles, for every 0.4 decrease in the difference in the basic clock adjustment value, the clock frequency of the output clock CLKOUT decreases by 0.2 Hz - 0.15 Hz = 0.05 Hz, represented by dtc_step2: dtc_step2 = 0.05 Hz / 0.4 = 0.125 Hz.

[0288] Of course, in the second group of signal cycles, 1 / 3, 1 / 4, etc. of the total frequency adjustment value required for compensation may also be corrected, and this embodiment of the present application does not limit this.

[0289] The following describes the working process of the frequency division correction circuit in the second group of signal cycles:

[0290] In the sixth signal cycle, integer frequency divider circuit 111 integer divides 4.8 Hz by 2, and the basic clock adjustment value is 0.4. Due to gain error and / or nonlinearity in frequency divider circuit 11, an error value of 0.4*dtc_step2 is added to the ideal clock frequency of 2 Hz, resulting in an output clock CLK OUT frequency of 2 Hz + 0.4*dtc_step2 = 2 Hz + 0.4*0.125 Hz = 2.05 Hz. The second frequency ratio is 2.4 Hz / 2.05 Hz, and the first phase detection result is 0.4*2.4 / 2.05. The fourth frequency ratio is 2.4 Hz / 2 Hz = 1.2, and the second phase detection result is 1.2*0.4 = 0.48. The error information is 0.4*2.4 / 2.05-0.48, and the frequency adjustment value required for compensation in the sixth signal cycle is (2 Hz-2.05 Hz)*0.4 = -0.02 Hz.

[0291] In the seventh signal cycle, integer divider circuit 111 integer divides 4.8 Hz by 2, and the basic clock adjustment value is 0.4. Due to gain error and / or nonlinearity in divider circuit 11, the ideal clock frequency of 2 Hz is increased by an error value of (0.8-0.4)*dtc_step2, resulting in an output clock frequency of CLK OUT of 2 Hz + (0.8-0.4)*dtc_step2 = 2 Hz + 0.4*0.125 Hz = 2.05 Hz. The second frequency ratio is 2.4 Hz / 2.05 Hz, and the first phase detection result is 0.4*2.4 / 2.05 + 0.8*2.4 / 2.05. The fourth frequency ratio is 2.4 Hz / 2 Hz = 1.2, and the second phase detection result is 1.2*0.4 + 1.2*0.8 = 1.44. The error information is 0.4*2.4 / 2.05+0.8*2.4 / 2.05-1.44=1.2*2.4 / 2.05-1.44, and the frequency adjustment value required to compensate for the seventh signal cycle is (2 Hz-2.05 Hz)*0.8=-0.04 Hz.

[0292] In the eighth signal cycle, integer divider circuit 111 integer divides 4.8 Hz by 3, and the basic clock adjustment value is 0.2. Due to gain error and / or nonlinearity in divider circuit 11, the ideal clock frequency of 2 Hz is increased by an error value of (0.2-0.8)*dtc_step2, resulting in an output clock frequency of CLK OUT of 2 Hz + (0.2-0.8)*dtc_step2 = 2 Hz - 0.6*0.125 Hz = 1.925 Hz. The second frequency ratio is 2.4 Hz / 1.925 Hz, and the first phase detection result is 0.4*2.4 / 2.05 + 0.8*2.4 / 2.05 + 0.2*2.4 / 1.925. The fourth frequency ratio is 2.4 Hz / 2 Hz = 1.2, and the second phase detection result is 1.2*0.4 + 1.2*0.8 + 1.2*0.2 = 1.68. The error information is 0.4*2.4 / 2.05+0.8*2.4 / 2.05+0.2*2.4 / 1.925-1.68=1.2*2.4 / 2.05+0.48 / 1.925-1.68, and the frequency adjustment value required to compensate for the eighth signal cycle is (2 Hz-1.925 Hz)*0.2=0.015 Hz.

[0293] During the ninth signal cycle, integer divider circuit 111 divides the 4.8 Hz frequency by 2, resulting in a basic clock adjustment value of 0.6. Due to gain error and / or nonlinearity in divider circuit 111, an error value of (0.6-0.2)*dtc_step2 is added to the ideal clock frequency of 2 Hz, resulting in an output clock frequency of CLK OUT of 2 Hz + (0.6-0.2)*dtc_step2 = 2 Hz + 0.4*0.125 Hz = 2.05 Hz. The second frequency ratio is 2.4 Hz / 2.05 Hz, and the first phase detection result is 0.4*2.4 / 2.05+0.8*2.4 / 2.05+0.2*2.4 / 1.925+0.6*2.4 / 2.05; the fourth frequency ratio is 2.4 Hz / 2 Hz=1.2, and the second phase detection result is 1.2*0.4+1.2*0.8+1.2*0.2+1.2*0.6=2.4. The error information is 0.4*2.4 / 2.05+0.8*2.4 / 2.05+0.2*2.4 / 1.925+0.6*2.4 / 2.05-2.4=1.8*2.4 / 2.05+0.48 / 1.925-2.4. The frequency adjustment value required to compensate for the ninth signal cycle is (2 Hz-2.05 Hz)*0.6=-0.03 Hz.

[0294] In the tenth signal cycle, integer divider circuit 111 integer divides 4.8 Hz by 3, and the basic clock adjustment value is 0. Due to gain error and / or nonlinearity in divider circuit 111, the ideal clock frequency of 2 Hz is increased by (0-0.6)*dtc_step2, resulting in an output clock CLK OUT frequency of 2 Hz + (0-0.6)*dtc_step2 = 2 Hz - 0.6*0.125 Hz = 1.925 Hz. The second frequency ratio is 2.4 / 1.925, and the first phase detection result is 0.4*2.4 / 2.05+0.8*2.4 / 2.05+0.2*2.4 / 1.925+0.6*2.4 / 2.05+0; the fourth frequency ratio is 2.4 Hz / 2 Hz=1.2, and the second phase detection result is 1.2*0.4+1.2*0.8+1.2*0.2+1.2*0.6+1.2*0=2.4. The error information is 0.4*2.4 / 2.05+0.8*2.4 / 2.05+0.2*2.4 / 1.925+0.6*2.4 / 2.05+0*2.4 / 1.925-2.4=1.8*2.4 / 2.05+0.48 / 1.925-2.4. The frequency adjustment value required to compensate for the tenth signal cycle is (2 Hz-1.925 Hz)*0=0 Hz.

[0295] In the second group of signal cycles (the sixth signal cycle to the tenth signal cycle), the first phase detection result is 1.8*2.4 / 2.05+0.48 / 1.925, the second phase detection result is 2.4, the error information is 1.8*2.4 / 2.05+0.48 / 1.925-2.4, and the total frequency adjustment value required to be compensated for the second group of signal cycles is -0.02-0.04+0.015-0.03+0=-0.075Hz.

[0296] During the third set of signal cycles (the eleventh to fifteenth signal cycles), half of the total frequency adjustment value required for compensation can be corrected based on the error information from the second set of signal cycles, i.e., -0.075 Hz / 2 = -0.0375 Hz. Thus, during the third set of signal cycles, for every 0.4 decrease in the basic clock adjustment value, the clock frequency of the output clock CLKOUT decreases by 0.05-0.0375 Hz = 0.0125 Hz, represented by dtc_step3: dtc_step3 = 0.0125 Hz / 0.4 = 0.03125 Hz.

[0297] The following describes the working process of the frequency division correction circuit in the third group of signal cycles:

[0298] In the eleventh signal cycle, integer divider circuit 111 integer divides 4.8 Hz by 2, and the basic clock adjustment value is 0.4. Due to gain error and / or nonlinearity in divider circuit 11, an error value of 0.4*dtc_step3 is added to the ideal clock frequency of 2 Hz, resulting in an output clock CLK OUT frequency of 2 Hz + 0.4*dtc_step2 = 2 Hz + 0.4*0.03125 Hz = 2.0125 Hz. The second frequency ratio is 2.4 Hz / 2.0125 Hz, and the first phase detection result is 0.4*2.4 / 2.0125. The fourth frequency ratio is 2.4 Hz / 2 Hz = 1.2, and the second phase detection result is 1.2*0.4 = 0.48. The error information is 0.4*2.4 / 2.0125-0.48, and the frequency adjustment value required for compensation in the eleventh signal cycle is (2 Hz-2.0125 Hz)*0.4=-0.005 Hz.

[0299] In the twelfth signal cycle, integer divider circuit 111 integer divides 4.8 Hz by 2, and the basic clock adjustment value is 0.4. Due to gain error and / or nonlinearity in divider circuit 11, the ideal clock frequency of 2 Hz is increased by an error value of (0.8-0.4)*dtc_step3, resulting in an output clock frequency of CLK OUT of 2 Hz + (0.8-0.4)*dtc_step3 = 2 Hz + 0.4*0.03125 Hz = 2.0125 Hz. The second frequency ratio is 2.4 Hz / 2.0125 Hz, and the first phase detection result is 0.4*2.4 / 2.0125 + 0.8*2.4 / 2.0125. The fourth frequency ratio is 2.4 Hz / 2 Hz = 1.2, and the second phase detection result is 1.2*0.4 + 1.2*0.8 = 1.44. The error information is 0.4*2.4 / 2.0125+0.8*2.4 / 2.0125-1.44=1.2*2.4 / 2.0125-1.44, and the frequency adjustment value required for compensation in the twelfth signal cycle is (2 Hz-2.0125 Hz)*0.8=-0.01 Hz.

[0300] In the thirteenth signal cycle, integer divider circuit 111 integer divides 4.8 Hz by 3, and the basic clock adjustment value is 0.2. Due to gain error and / or nonlinearity in divider circuit 111, the ideal clock frequency of 2 Hz is increased by (0.2 - 0.8) * dtc_step3, resulting in an output clock frequency of CLK OUT of 2 Hz + (0.2 - 0.8) * dtc_step3 = 2 Hz - 0.6 * 0.03125 Hz = 1.98125 Hz. The second frequency ratio is 2.4 Hz / 1.98125 Hz, and the first phase detection result is 0.4*2.4 / 2.05 + 0.8*2.4 / 2.05 + 0.2*2.4 / 1.98125 = 1.2*2.4 / 2.0125 + 0.2*2.4 / 1.98125. The fourth frequency ratio is 2.4 Hz / 2 Hz = 1.2, and the second phase detection result is 1.2 + 1.2*0.2 = 1.68. The error information is 1.2*2.4 / 2.0125 + 0.2*2.4 / 1.98125 - 1.68, and the frequency adjustment value required to compensate for the thirteenth signal cycle is (2 Hz - 1.98125 Hz) * 0.2 = 0.00375 Hz.

[0301] In the fourteenth signal cycle, integer divider circuit 111 integer divides 4.8 Hz by 2, resulting in a basic clock adjustment value of 0.6. Due to gain error and / or nonlinearity in divider circuit 111, the ideal clock frequency of 2 Hz is increased by (0.6 - 0.2) * dtc_step3, resulting in an output clock frequency of CLK OUT of 2 Hz + (0.6 - 0.2) * dtc_step3 = 2 Hz + 0.4 * 0.03125 Hz = 2.0125 Hz. The second frequency ratio is 2.4 Hz / 2.0125 Hz, and the first phase detection result is 0.4*2.4 / 2.0125 + 0.8*2.4 / 2.0125 + 0.2*2.4 / 1.98125 + 0.6*2.4 / 2.0125 = 1.8*2.4 / 2.0125 + 0.2*2.4 / 1.98125. The fourth frequency ratio is 2.4 Hz / 2 Hz = 1.2, and the second phase detection result is 1.68 + 1.2*0.6 = 2.4. The error information is 1.8*2.4 / 2.0125 + 0.2*2.4 / 1.98125 - 2.4. The frequency adjustment value required to compensate for the fourteenth signal cycle is (2 Hz - 2.0125 Hz) * 0.6 = -0.0075 Hz.

[0302] In the fifteenth signal cycle, integer divider circuit 111 integer divides 4.8 Hz by 3, and the basic clock adjustment value is 0. Due to gain error and / or nonlinearity in divider circuit 111, the ideal clock frequency of 2 Hz is increased by (0-0.6)*dtc_step3, resulting in an output clock CLK OUT frequency of 2 Hz + (0-0.6)*dtc_step3 = 2 Hz - 0.6*0.03125 Hz = 1.98125 Hz. The second frequency ratio is 2.4 / 1.98125, and the first phase detection result is 0.4*2.4 / 2.0125+0.8*2.4 / 2.0125+0.2*2.4 / 1.98125+0.6*2.4 / 2.0125+0=1.8*2.4 / 2.0125+0.2*2.4 / 1.98125. The fourth frequency ratio is 2.4Hz / 2Hz=1.2, and the second phase detection result is 2.4+1.2*0=2.4. The error information is 1.8*2.4 / 2.0125+0.2*2.4 / 1.98125-2.4, and the frequency adjustment value required to compensate for the fifteenth signal period is (2Hz-1.98125Hz)*0=0Hz.

[0303] In the third group of signal cycles (the eleventh signal cycle to the fifteenth signal cycle), the first phase detection result is 1.8*2.4 / 2.0125+0.2*2.4 / 1.98125, the second phase detection result is 2.4, the error information is 1.8*2.4 / 2.0125+0.2*2.4 / 1.98125-2.4, and the total frequency adjustment value required to be compensated for the third group of signal cycles is -0.005-0.01+0.00375-0.0075+0=-0.01875Hz.

[0304] It can be seen that from the first group of signal cycles to the third group of signal cycles, the frequency of the output clock CLK OUT gradually approaches 22 Hz, and the sum of the error information and the frequency adjustment value required for compensation gradually approaches zero.

[0305] This process is repeated in this way until the frequency of the output clock CLK OUT is 2 Hz (or close to 2 Hz) in a group of signal cycles, and the sum of the error information and the required frequency adjustment value for compensation approaches 0. In this way, the frequency of the output clock CLK OUT in any signal cycle after this group of signal cycles is 2 Hz (or close to 2 Hz). This avoids the situation where, after the corrected frequency of the output clock CLK OUT is equal to the ideal frequency due to an excessively large sum of the error information and the required frequency adjustment value for compensation, the frequency of the output clock CLK OUT in subsequent groups of signal cycles is corrected using the sum of the error information and the required frequency adjustment value for compensation, resulting in a further significant difference between the frequency of the output clock CLK OUT and the ideal frequency.

[0306] The above describes the calibration process from the first to the fifteenth signal cycle, using the example of an input clock CLK IN with a clock frequency of 4.8 Hz and an ideal output clock frequency of 2 Hz. During this process, the calibration clock CLK ADPLL maintains a fixed clock frequency of 2.4 Hz.

[0307] In other possible implementations, the clock frequency of the input clock CLK IN changes, and / or the output frequency of the ideal output clock changes, and / or after the frequency division correction circuit is powered on again, the clock frequency of the correction clock CLK ADPLL may remain at 2.4 Hz, or the clock frequency of the correction clock CLK ADPLL may also change, depending on the comparison result of the fourth frequency ratio and the fifth frequency ratio with the preset accuracy.

[0308] Specifically, the correction circuit 13 has a certain resolution during the phase detection and error information calculation process. When the decimal places of the fourth frequency ratio and the fifth frequency ratio are too small, the correction circuit 13 ignores the decimal places of the fourth frequency ratio and the fifth frequency ratio due to the resolution, thereby affecting the correction accuracy of the output clock CLK OUT.

[0309] Based on this, the embodiment of the present application can set a preset accuracy based on the resolution of the correction circuit 13. Furthermore, based on the preset accuracy and the clock frequency of the ideal output clock, the clock frequency of the correction clock CLK ADPLL is set so that the decimal places of the fourth frequency ratio and the decimal places of the fifth frequency ratio are both greater than the preset accuracy, thereby improving the correction accuracy of the output clock.

[0310] For example, the preset accuracy is 0.01, the clock frequency of the ideal output clock is 2 Hz, the clock frequency of the correction clock CLK ADPLL is 2.01 Hz, and the fourth frequency ratio is 2.01 Hz / 2 Hz=1.005. The decimal place of 1.005 is smaller than the preset accuracy of 0.01 and is ignored by the correction circuit 13, thereby affecting the correction accuracy of the output clock CLK OUT.

[0311] For another example, the preset accuracy is 0.01, the clock frequency of the ideal output clock is 2 Hz, the clock frequency of the correction clock CLK ADPLL is 2.4 Hz, the fourth frequency ratio is 2.4 Hz / 2 Hz=1.2, and the fifth frequency ratio is 2 Hz / 2.4 Hz≈0.83. The decimal places of 1.2 and 0.83 are both greater than the preset accuracy of 0.01.

[0312] For another example, if the preset accuracy is 0.01, the ideal output clock frequency is 3 Hz, and the correction clock CLK ADPLL frequency remains at 2.4 Hz, the fourth frequency ratio is 2.4 Hz / 3 Hz = 0.8, and the fifth frequency ratio is 3 Hz / 2.4 Hz = 1.25. The decimal places of 0.8 and 1.25 are both greater than the preset accuracy of 0.01. Alternatively, if the correction clock CLK ADPLL frequency is changed to 3.5 Hz, the fourth frequency ratio is 3.5 Hz / 3 Hz ≈ 1.67, and the fifth frequency ratio is 3 Hz / 3.5 Hz ≈ 0.86. The decimal places of 1.67 and 0.86 are both greater than the preset accuracy of 0.01.

[0313] Of course, based on the resolution of the correction circuit 13 , the preset accuracy may also be set to other values, which is not limited in the embodiment of the present application.

[0314] In some embodiments, as shown in FIG6 , the correction circuit 13 includes a second phase detector 131 , an error comparison circuit 132 , and a compensation circuit 133 .

[0315] The process of calculating the first phase detection result and the second phase detection result is implemented by the second phase detector 131 , and the process of subtracting the first phase detection result from the second phase detection result is implemented by the error comparison circuit 132 .

[0316] On this basis, the compensation circuit 133 obtains a gain adjustment value Gain adj and / or a nonlinear adjustment value INL adj according to the received error information, and inputs the gain adjustment value Gainadj and / or the nonlinear adjustment value INL adj to the frequency divider circuit 11. The gain adjustment value Gainadj and / or the nonlinear adjustment value INL adj may be half of the sum of the frequency adjustment values ​​required for compensation (e.g., -1.5 Hz obtained based on the first set of signal cycles, -0.0375 Hz obtained based on the second set of signal cycles, etc.).

[0317] The frequency dividing circuit 11 adjusts the clock frequency of the output clock CLK OUT output in the next group of signal cycles according to the gain adjustment value Gain adj and / or the nonlinear adjustment value INL adj. The specific adjustment method can refer to the examples of the first to third groups of signal cycles mentioned above.

[0318] The first to third signal cycles described above represent the process of calibrating the frequency of the output clock CLK OUT. This process can occur during the adjustment phase, allowing the frequency divider circuit to provide an accurate output clock to other circuits during the subsequent operating phase. The adjustment phase refers to the period before the frequency divider circuit 11 provides the output clock to other circuits, enabling the other circuits to operate normally under the triggering of the output clock CLK OUT. The operating phase refers to the period after the output clock CLK OUT is accurately calibrated during the adjustment phase, when the frequency divider circuit 11 provides the output clock to other circuits, enabling the other circuits to operate normally under the triggering of the output clock CLK OUT.

[0319] Of course, the above process of correcting the clock frequency of the output clock CLK OUT can also occur during the working phase, and the output clock CLK OUT of the divided clock output can be corrected in real time to avoid affecting the operation of other circuits due to errors in the frequency of the output clock CLK OUT.

[0320] In the above, every five signal cycles are divided into a group of signal cycles based on the changing signal cycle of the basic clock adjustment value. The frequency of the output clock CLK OUT in the second group of signal cycles is corrected based on the error information of the first group of signal cycles. The frequency of the output clock CLK OUT in the third group of signal cycles is corrected based on the error information of the second group of signal cycles, and so on.

[0321] In other possible implementations, a group of signal cycles may further include one signal cycle, and the frequency of the output clock CLK OUT in the next signal cycle may be corrected based on the error information of the current signal cycle. When a group of signal cycles further includes one signal cycle, the frequency of the output clock CLK OUT is corrected using the frequency division correction circuit in the same manner as described above for the first through fifteenth signal cycles.

[0322] The second phase detector 131 is configured to calculate a second frequency ratio between the clock frequency of the correction clock and the frequency of the output clock CLK OUT, or a third frequency ratio between the frequency of the output clock CLK OUT and the clock frequency of the correction clock, in the current signal cycle; and obtain a first phase detection result between the output clock CLK OUT and the correction clock CLK ADPLL in the current signal cycle based on the product of the second frequency ratio and the basic clock adjustment value, or based on the product of the third frequency ratio and the basic clock adjustment value.

[0323] The second phase detector 131 is further configured to calculate a fourth frequency ratio between the clock frequency of the correction clock and the frequency of the ideal output clock CLK OUT, or a fifth frequency ratio between the frequency of the ideal output clock and the clock frequency of the correction clock, in the current signal cycle; and obtain a second phase detection result between the ideal output clock and the correction clock CLK ADPLL in the current signal cycle based on the product of the fourth frequency ratio and the basic clock adjustment value, or based on the product of the fifth frequency ratio and the basic clock adjustment value.

[0324] The error comparison circuit 132 is configured to receive the first phase detection result and the second phase detection result, and to perform a subtraction between the first phase detection result and the second phase detection result to obtain error information. If the first phase detection result is calculated using the second frequency ratio and the basic clock adjustment value, the second phase detection result is calculated using the fourth frequency ratio and the basic clock adjustment value. If the first phase detection result is calculated using the third frequency ratio and the basic clock adjustment value, the second phase detection result is calculated using the fifth frequency ratio and the basic clock adjustment value.

[0325] The compensation circuit 133 is configured to obtain a gain adjustment value and / or a nonlinear adjustment value according to the error information, and input the gain adjustment value and / or the nonlinear adjustment value to the frequency dividing circuit.

[0326] The frequency dividing circuit 11 is further configured to output a corrected output clock CLK OUT in the next signal cycle according to the gain adjustment value and / or the nonlinear adjustment value.

[0327] This calculation process is the same as the calculation process in the aforementioned example where a group of signal cycles includes 5 signal cycles, and will not be repeated here.

[0328] In some possible implementations, after receiving the error information, the compensation circuit 133 can obtain the gain adjustment value Gain adj and / or the nonlinear adjustment value INL adj according to a preset formula or lookup table, etc., which is not limited in the embodiments of the present application.

[0329] In some embodiments, the fractional frequency adjustment circuit 114 is further configured to obtain a second adjustment code value based on the gain adjustment value Gain adj and / or the nonlinear adjustment value INL adj, and to correct the clock frequency of the output clock CLK OUT output in the next signal cycle based on the second adjustment code value.

[0330] In some possible implementations, after the fractional frequency adjustment circuit 114 receives the gain adjustment value Gain adj and / or the nonlinear adjustment value INL adj, it can obtain a second adjustment code value according to a preset formula or lookup table, etc., which is not limited in the embodiments of the present application.

[0331] The above example describes how to use error information from the first signal cycle to the fifth signal cycle to obtain a gain adjustment value Gain adj and / or a nonlinear adjustment value INL adj, and use a second adjustment code value corresponding to the gain adjustment value Gain adj and / or the nonlinear adjustment value INL adj to correct the output clock of the next group of signal cycles.

[0332] In some other possible implementations, the error information may be used to obtain a second adjustment code value, and the second adjustment code value may be directly used to correct the output clock of the next group of signal cycles.

[0333] Whether the basic clock CLK MMD is adjusted according to the first adjustment code value by the fractional frequency division circuit 112, or the output clock CLK OUT is corrected according to the second adjustment code value by the fractional frequency division circuit 112, it can be achieved by adjusting at least one of the resistance value, capacitance value, voltage value, and inductance value of the components included in the fractional frequency division circuit 112.

[0334] Here, the embodiment of the present application does not limit the case where the frequency of the output clock CLK OUT is too large or too small, and at least one of the resistance value, capacitance value, voltage value, and inductance value of the components included in the fractional frequency division circuit 112 must be increased or decreased. The specific adjustment method is related to the components included in the fractional frequency division circuit 112 and their parameters, as well as the connection relationship between the components.

[0335] In some embodiments, as shown in FIG7 , the auxiliary calibration circuit 12 may include a first clock generator 123 , for example, a VCO. However, the first clock generator 123 may experience frequency drift due to factors such as time and temperature, resulting in the calibration clock output by the auxiliary calibration circuit 12 being an unstable clock signal.

[0336] Based on this, the auxiliary correction circuit 12 may also include, in addition to the first clock generator 123, a first phase detector 121 and a first filter 122. Generating the correction clock using the auxiliary correction circuit includes: receiving, via the first phase detector 121, the first reference clock CLK REF1 and the correction clock CLK ADPLL fed back by the first clock generator 123, and performing phase detection on the first reference clock CLK REF1 and the correction clock CLK ADPLL to obtain a third phase detection result. The first filter 122 receives the third phase detection result and filters it to ensure that the clock frequency of the correction clock CLK ADPLL output by the first clock generator 123 is stable, thereby improving the quality and stability of the correction clock CLK ADPLL and saving time in correcting the output clock CLK OUT. Optionally, the first filter 122 may be an LPF.

[0337] Of course, the circuit structure of the auxiliary correction circuit 12 is only an example. Any technician familiar with this technical field who proposes a circuit structure of the auxiliary correction circuit 12 that can provide a stable correction clock CLK ADPLL within the technical scope disclosed in this application should be covered by the protection scope of this application.

[0338] In some possible implementations, the clock frequency of the first reference clock CLK REF1 may be a certain value. When the frequency drift problem is not considered, the auxiliary correction circuit 12 may send the first reference clock CLK REF1 as the correction clock CLK ADPLL to the correction circuit 13 .

[0339] In some possible implementations, as shown in FIG7 , a first phase detector 121 can be used to perform phase detection between the first reference clock CLK REF1 and the correction clock CLK ADPLL, thereby obtaining the correction clock CLK ADPLL from the first reference clock CLK REF1. Alternatively, a stable correction clock CLK ADPLL can be obtained from the first reference clock CLK REF1 using other methods. Alternatively, a stable correction clock CLK ADPLL can be obtained using other clocks, although this is not limited in this embodiment of the present application.

[0340] In some embodiments, as shown in FIG8 , the second phase detector 131 includes a first calculation circuit 1311 , a second calculation circuit 1312 , and a first adder 1313 .

[0341] The first calculation circuit 1311 receives the correction clock CLK ADPLL sent by the auxiliary correction circuit 12 and the output clock CLK OUT sent by the frequency division circuit 11, and calculates the second frequency ratio and the basic clock adjustment value, or the third frequency ratio and the basic clock adjustment value, in a group of signal cycles to obtain the integer bit result in the first phase detection result.

[0342] For example, the second frequency ratio of the first signal cycle is 1.2 / 1.1, the first phase detection result is 0.4*1.2 / 1.1≈0.44, and the first calculation circuit 1311 outputs the integer digit of 0.44 as 0. The second frequency ratio of the second signal cycle is 1.2 / 1.1, the first phase detection result is 0.4*1.2 / 1.1+0.8*1.2 / 1.1≈1.31, and the first calculation circuit 1311 outputs the integer digit of 1.31 as 1.

[0343] The second calculation circuit 1312 receives the correction clock CLK ADPLL sent by the auxiliary correction circuit 12 and the output clock CLK OUT sent by the frequency division circuit 11, and calculates the second frequency ratio and the basic clock adjustment value, or the third frequency ratio and the basic clock adjustment value in a group of signal cycles to obtain the decimal point result in the first phase detection result.

[0344] For example, if the second frequency ratio of the first signal cycle is 1.2 / 1.1, the first phase detection result is 0.4*1.2 / 1.1≈0.44, and the first calculation circuit 1311 outputs the decimal point of 0.44 as 0.44. If the second frequency ratio of the second signal cycle is 1.2 / 1.1, the first phase detection result is 0.4*1.2 / 1.1+0.8*1.2 / 1.1≈1.31, and the first calculation circuit 1311 outputs the decimal point of 1.31 as 0.31.

[0345] The first adder 1313 is used to receive the integer result and the decimal result 0, and the integer result and the decimal result are added to obtain a first phase detection result.

[0346] For example, in the first signal cycle, the first phase detection result calculated by the first adder 1313 is 0+0.44=0.44; in the second signal cycle, the first phase detection result calculated by the first adder 1313 is 1+0.31=1.31.

[0347] In some embodiments, the clock frequency of the correction clock CLK ADPLL and the ideal frequency of the ideal output frequency used to calculate the second phase detection result can be obtained in advance. In this case, the second phase detection result can be calculated directly based on the known clock frequency of the correction clock and the ideal frequency.

[0348] In other embodiments, the first reference clock CLK REF1 input to the auxiliary correction circuit 12 may have a low-frequency frequency drift due to factors such as time and temperature, resulting in an inaccurate clock frequency of the correction clock CLK ADPLL. Alternatively, the first reference clock CLK REF1 is unpredictable, that is, the clock frequency of the correction clock CLK ADPLL is unpredictable, and thus a correct second phase detection result cannot be calculated.

[0349] In this case, the embodiment of the present application can obtain the second phase-locked result through the error comparison circuit 132 and the first phase-locked result input to the error comparison circuit 132, thereby obtaining the difference between the error information of the current signal cycle and the error information of the previous signal cycle based on the first phase-locked result and the second phase-locked result.

[0350] Specifically, as shown in FIG9 , after the phase detection result of the output clock CLK OUT and the correction clock CLK ADPLL in the previous signal cycle is input to the second adder 1322 by shifting using the register 1321, the phase detection result of the input and output clock CLK OUT and the correction clock CLK ADPLL in the current signal cycle of the second phase detector 1321 is received and stored, so that the phase detection result of the current signal cycle can be input to the second adder 1322 in the next signal cycle.

[0351] The second adder 1322 receives the phase detection result of the current signal cycle and the phase detection result of the previous signal cycle, and subtracts the phase detection result of the current signal cycle from the phase detection result of the previous signal cycle to obtain the current phase detection result of the current signal cycle.

[0352] For example, the first phase detection result of the first signal cycle is 0.4*1.2 / 1.1, and the first phase detection result of the second signal cycle is 0.4*1.2 / 1.1+0.8*1.2 / 1.1. The difference between the two is the current phase detection result FCW of the second signal cycle, which is 0.8*1.2 / 1.1.

[0353] The second filter 1324 receives the current phase detection result and filters the current phase detection result to obtain a second phase detection result of the ideal output clock and the correction clock in the current signal cycle. Optionally, the second filter 1324 can be an LPF.

[0354] For example, the current first phase detection result FCW of the second signal cycle is 0.8*1.2 / 1.1, and filtering is performed to obtain the second phase detection result of the current signal cycle as 0.8*2.4 Hz / 2 Hz=0.8*1.2.

[0355] The third adder 1323 performs a subtraction between the current phase detection result and the second phase detection result of the current signal cycle to obtain the difference between the error information of the current signal cycle and the error information of the previous signal cycle. The error information differences of a group of signal cycles are added together to obtain the error information of a group of signal cycles.

[0356] For example, the third adder 1323 is used to subtract the current first phase-detection result 0.8*1.2 / 1.1 (the first phase-detection result 0.8*1.2 / 1.1 of the second signal period) from the second phase-detection result 0.8*1.2 of the current signal period (the second phase-detection result 0.8*1.2 of the second signal period), and the difference in error information obtained is approximately 0.09, that is, the error information of the second signal period minus the error information of the first signal period 1.2*1.2 / 1.1-1.44-(0.4*1.2 / 1.1-0.48)≈0.09.

[0357] In this way, when the clock frequency of the correction clock cannot be predicted or the accurate clock frequency of the correction clock cannot be obtained, the second phase-locked detection result can be calculated, thereby obtaining the difference between the error information of the current signal period and the error information of the previous signal period based on the first phase-locked detection result and the second phase-locked detection result, and by accumulating the multiple calculated differences, the error information can be obtained.

[0358] On this basis, the second filter 1324 of the present application can be implemented by a digital circuit or an analog circuit, replacing the implementation method of the ADPLL, to avoid the situation where, when the frequency division circuit 11 implements near-integer frequency division, the second filter 1324 cannot be used to filter the current first phase-locked detection result to obtain an accurate correction clock CLK ADPLL, and thus accurate error information cannot be obtained.

[0359] In some embodiments, as shown in FIG11 , the frequency division correction circuit further includes a clock generation circuit 14 . The clock generation circuit 14 is configured to generate an input clock CLK IN and input the input clock CLK IN to the frequency division circuit 11 .

[0360] Specifically, as shown in FIG11 , the clock generating circuit 14 includes a third phase detector 141 , a third filter 142 , and a second clock generator 143 .

[0361] The second clock generator 143 is used to generate the input clock CLK IN, and the input clock CLK IN is input to the frequency dividing circuit 11. Optionally, the second clock generator 143 may be a VCO.

[0362] The third phase detector 141 receives the second reference clock CLK REF2 and the output clock CLK OUT, performs phase detection on the second reference clock CLK REF2 and the output clock CLK OUT, and obtains a fourth phase detection result.

[0363] In some possible implementations, the third phase detector 141 is used to perform phase detection on the second reference clock CLK REF2 and the output clock CLK OUT. The calculation is not limited to calculating the ratio of the clock frequencies of the two. It only needs to correlate the second reference clock CLK REF2 and the output clock CLK OUT.

[0364] The fourth phase detection result is received by the third filter 142 and filtered to adjust the clock frequency of the input clock CLK IN output by the second clock generator 143. Optionally, the third filter 142 may be an LPF.

[0365] Continuing with the example of an ideal input clock CLK IN with a clock frequency of 4.8 Hz and an ideal output clock with a frequency of 2 Hz, since 2 Hz and 4.8 Hz are not clock frequencies at the same rate, they cannot be phase-detected. Therefore, upon receiving the 4.8 Hz input clock CLK IN, the frequency divider circuit 11 first divides the 4.8 Hz input clock and then inputs the divided output clock CLK OUT to the third phase detector 141. The third phase detector 141 can perform phase detection on the output clock CLK OUT and the second reference clock CLK REF2 to determine whether the input clock CLK IN received by the frequency divider circuit 11 is too fast or too slow. The third filter 142 then filters the fourth phase detection result to adjust the clock frequency of the input clock CLK IN output by the second clock generator 143.

[0366] However, in order to accurately correct the clock frequency of the input clock CLK IN, it is desirable that the error in the output clock CLK OUT input by the frequency divider circuit 11 to the third phase detector 141 originates solely from the input clock CLK IN output by the clock generation circuit 14. However, as previously mentioned, when the frequency divider circuit 11 divides the input clock CLK IN, gain error and / or nonlinear error may also exist. The output clock CLK OUT input to the third phase detector 141 may be contaminated with the gain error and / or nonlinear error, making it unclear whether the frequency error in the output clock CLK OUT originates from the input clock CLK IN or the gain error and / or nonlinear error. Therefore, the auxiliary correction circuit 12 and correction circuit 13 of the present application can be used to correct the frequency of the output clock CLK OUT to compensate for the gain error and / or nonlinear error, thereby ensuring that the frequency error in the output clock CLK OUT input by the frequency divider circuit 11 to the second clock generator 143 originates solely from the input clock CLK IN. In this way, it is only necessary to filter the fourth phase detection result by the third filter 142 to adjust the clock frequency of the input clock CLK IN output by the second clock generator 143 .

[0367] Here, the specific process of using the auxiliary correction circuit 12 and the correction circuit 13 to correct the frequency of the output clock CLK OUT to compensate for the gain error and / or nonlinear error is described above and will not be repeated here.

[0368] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A frequency division correction circuit, characterized in that: include: Frequency division circuit: used to divide the received input clock to obtain the output clock; Auxiliary correction circuit: used for generating a correction clock, the clock frequency of the correction clock is a constant; Correction circuit: used for performing phase detection on the received output clock and the correction clock to obtain a first phase detection result; performing phase detection on the ideal output clock and the correction clock to obtain a second phase detection result; and comparing the first phase detection result with the second phase detection result to obtain error information of the output clock, so as to correct the clock frequency of the output clock output by the frequency division circuit according to the error information.

2. The frequency division correction circuit according to claim 1, characterized in that: The number of the frequency division circuit and the number of the correction circuit are both multiple; The plurality of correction circuits share the correction clock output by the same auxiliary correction circuit; the plurality of frequency division circuits correspond one-to-one to the plurality of correction circuits, and any of the frequency division circuits inputs the output clock to a correction circuit corresponding thereto.

3. The frequency division correction circuit according to claim 1 or 2, characterized in that: The auxiliary correction circuit includes a first phase detector, a first filter, and a first clock generator; The first phase detector is used to receive the first reference clock and the correction clock fed back by the first clock generator, and perform phase detection on the first reference clock and the correction clock to obtain a third phase detection result; The first filter is used to receive the third phase detection result and filter the third phase detection result so that the clock frequency of the correction clock output by the first clock generator is constant.

4. The frequency division correction circuit according to claim 3, characterized in that: Before the clock frequency of the corrected output clock is equal to the clock frequency of the ideal output clock, the clock frequency of the corrected clock is a fixed frequency.

5. The frequency division correction circuit according to any one of claims 1 to 4, characterized in that: The frequency division circuit includes the integer frequency division circuit, the fractional frequency division circuit, the incremental sum modulator, and the fractional frequency division adjustment circuit; The incremental summation circuit is used to input a value N to the integer frequency division circuit according to a first frequency ratio between the clock frequency of the input clock and the ideal frequency; wherein N includes n and n+1, and the difference between the first frequency ratio and n, and the difference between n+1 and the first frequency ratio are both less than 1; and n is a positive integer; The integer frequency division circuit is used to receive the input clock and the value N, and perform integer frequency division on the input clock in a manner of interleaving n-division and n+1-division to obtain a basic clock, and input the basic clock to the fractional frequency division circuit; The incremental summing circuit is also used to input a basic clock adjustment value to the fractional frequency division adjustment circuit; the basic clock adjustment value is the decimal place of the accumulated value of the first frequency ratio in each signal cycle; The fractional frequency division adjustment circuit is used to obtain a first adjustment code value according to the basic clock adjustment value, and input the first adjustment code value into the fractional frequency division circuit; The fractional frequency division circuit is used to adjust the basic clock using the first adjustment code value to output the output clock.

6. The frequency division correction circuit according to claim 5, characterized in that: The correction circuit includes a second phase detector, an error comparison circuit, and a compensation circuit; The second phase detector is used to perform phase detection on the output clock and the correction clock of a group of signal cycles to obtain the first phase detection result; wherein the group of signal cycles includes multiple signal cycles, and the first phase detection result is the accumulated value of the phase detection results of the output clock and the correction clock in the multiple signal cycles; The second phase detector is further used to perform phase detection on the ideal output clock and the correction clock of the group of signal cycles to obtain the second phase detection result; wherein the second phase detection result is the accumulated value of the phase detection results of the ideal output clock and the correction clock in multiple signal cycles; The error comparison circuit is further used to compare the first phase detection result and the second phase detection result of the group of signal cycles to obtain error information of the output signal; The compensation circuit is used to correct the clock frequency of the output clock of the next group of signal cycles according to the error information.

7. The frequency division correction circuit according to claim 6, characterized in that: The second phase detector is used to calculate a second frequency ratio between the clock frequency of the correction clock and the frequency of the output clock, or a third frequency ratio between the frequency of the output clock and the clock frequency of the correction clock in each signal cycle; Obtaining a phase detection result between the output clock and the correction clock in each of the signal cycles according to the product of the second frequency ratio and the basic clock adjustment value, or according to the product of the third frequency ratio and the basic clock adjustment value; and accumulating the phase detection results between the output clock and the correction clock in the group of signal cycles to obtain the first phase detection result; The second phase detector is further configured to calculate, in each of the signal cycles, a fourth frequency ratio between the clock frequency of the correction clock and the frequency of the ideal output clock, or a fifth frequency ratio between the frequency of the ideal output clock and the clock frequency of the correction clock; Obtaining a phase detection result between the ideal output clock and the correction clock in each of the signal cycles according to the product of the fourth frequency ratio and the basic clock adjustment value, or according to the product of the fifth frequency ratio and the basic clock adjustment value; and accumulating the phase detection results between the ideal output clock and the correction clock in the group of signal cycles to obtain the second phase detection result; The error comparison circuit is used to receive the first phase detection result and the second phase detection result, and to perform a difference between the first phase detection result and the second phase detection result to obtain the error information; wherein, if the first phase detection result is calculated by the second frequency ratio and the basic clock adjustment value, the second phase detection result is calculated by the fourth frequency ratio and the basic clock adjustment value; if the first phase detection result is calculated by the third frequency ratio and the basic clock adjustment value, the second phase detection result is calculated by the fifth frequency ratio and the basic clock adjustment value; The compensation circuit is used to obtain a gain adjustment value and / or a nonlinear adjustment value according to the error information, and input the gain adjustment value and / or the nonlinear adjustment value into the frequency division circuit; The frequency division circuit is also used to output the corrected output clock in the next group of signal cycles according to the gain adjustment value and / or the nonlinear adjustment value.

8. The frequency division correction circuit according to claim 5, characterized in that: The correction circuit includes a second phase detector, an error comparison circuit, and a compensation circuit; The second phase detector is used to perform phase detection on the output clock received in the current signal period and the correction clock to obtain the first phase detection result; The second phase detector is further used to perform phase detection on the ideal output clock of the current signal period and the correction clock to obtain the second phase detection result; The error comparison circuit is used to compare the first phase detection result with the second phase detection result to obtain error information of the output clock; The compensation circuit is used to correct the clock frequency of the output clock output by the frequency division circuit in the next signal cycle according to the error information.

9. The frequency division correction circuit according to claim 8, characterized in that: The second phase detector is used to calculate a second frequency ratio between the clock frequency of the correction clock and the frequency of the output clock, or a third frequency ratio between the frequency of the output clock and the clock frequency of the correction clock in the current signal cycle; Obtaining the first phase detection result between the output clock and the correction clock in the current signal cycle according to the product of the second frequency ratio and the basic clock adjustment value, or according to the product of the third frequency ratio and the basic clock adjustment value; The second phase detector is further configured to calculate a fourth frequency ratio between the clock frequency of the correction clock and the frequency of the ideal output clock, or a fifth frequency ratio between the frequency of the ideal output clock and the clock frequency of the correction clock in the current signal cycle; Obtaining a second phase detection result between the ideal output clock and the correction clock in the current signal cycle according to the product of the fourth frequency ratio and the basic clock adjustment value, or according to the product of the fifth frequency ratio and the basic clock adjustment value; The error comparison circuit is used to receive the first phase detection result and the second phase detection result, and to perform a difference between the first phase detection result and the second phase detection result to obtain the error information; wherein, if the first phase detection result is calculated by the second frequency ratio and the basic clock adjustment value, the second phase detection result is calculated by the fourth frequency ratio and the basic clock adjustment value; if the first phase detection result is calculated by the third frequency ratio and the basic clock adjustment value, the second phase detection result is calculated by the fifth frequency ratio and the basic clock adjustment value; The compensation circuit is used to obtain a gain adjustment value and / or a nonlinear adjustment value according to the error information, and input the gain adjustment value and / or the nonlinear adjustment value into the frequency division circuit; The frequency division circuit is further configured to output the corrected output clock in the next signal cycle according to the gain adjustment value and / or the nonlinear adjustment value.

10. The frequency division correction circuit according to claim 7 or 9, characterized in that: The decimal places of the fourth frequency ratio and the decimal places of the fifth frequency ratio are both greater than a preset accuracy.

11. The frequency division correction circuit according to claim 7 or 9, characterized in that: The error information includes gain error information and / or nonlinear error information.

12. The frequency division correction circuit according to claim 7 or 9, characterized in that: The second phase detector includes a first calculation circuit, a second calculation circuit, and a first adder; The first calculation circuit is used to calculate the integer result of the first phase detection result; The second calculation circuit is used to calculate the decimal place result of the first phase discrimination result; The first adder is used to receive the integer result and the decimal result, and add the integer result and the decimal result to obtain the first phase detection result.

13. The frequency division correction circuit according to any one of claims 8 to 12, characterized in that: The error comparison circuit includes a register, a second adder, a third adder, and a second filter; The register is used to input the phase detection result of the output clock and the correction clock in the previous signal cycle to the second adder, receive and store the phase detection result of the output clock and the correction clock input by the second phase detector in the current signal cycle; The second adder is used to receive the phase-lock result of the current signal cycle and the phase-lock result of the previous signal cycle, and to make a difference between the phase-lock result of the current signal cycle and the phase-lock result of the previous signal cycle to obtain a current phase-lock result of the current signal cycle; The second filter is used to receive the current phase detection result and filter the current phase detection result to obtain a second phase detection result of the ideal output clock and the correction clock in the current signal period; The third adder is used to subtract the current phase-locked detection result from the second phase-locked detection result to obtain the difference between the error information of the current signal period and the error information of the previous signal period, and to add the difference between the error information of the group of signal periods to obtain the error information of the group of signal periods.

14. The frequency division correction circuit according to any one of claims 5 to 13, characterized in that: The fractional frequency division adjustment circuit is further configured to obtain a second adjustment code value according to the gain adjustment value and / or the nonlinear adjustment value; The fractional frequency division circuit is also used to output the clock after correction in the next group of signal cycles or the next signal output according to the second adjustment code value.

15. The frequency division correction circuit according to claim 14, characterized in that: The fractional frequency division adjustment circuit is also used to adjust at least one of the resistance value, capacitance value, voltage value, and inductance value of the components included in the fractional frequency divider according to the second adjustment code value, so as to output the corrected output clock in the next group of signal cycles or the next signal cycle.

16. The frequency division correction circuit according to any one of claims 1 to 11, characterized in that: Also included is a clock generating circuit; The clock generating circuit is used to generate the input clock and input the input clock to the frequency dividing circuit.

17. The frequency division correction circuit according to claim 16, characterized in that: The clock generating circuit includes a third phase detector, a third filter, and a second clock generator; The second clock generator is used to generate the input clock and input the input clock to the frequency division circuit; The third phase detector is used to receive the second reference clock and the output clock, perform phase detection on the second reference clock and the output clock, and obtain a fourth phase detection result; The third filter is used to receive the fourth phase-detection result and filter the fourth phase-detection result to adjust the clock frequency of the input clock output by the second clock generator.

18. A control method for a frequency division correction circuit, characterized in that: The frequency division correction clock includes a frequency division circuit, an auxiliary correction circuit, and a correction circuit; the control method of the frequency division correction clock includes: The received input clock is divided by the frequency dividing circuit to obtain an output clock; generating a correction clock using the auxiliary correction circuit, wherein the clock frequency of the correction clock is a constant; The correction circuit is used to perform phase detection on the received output clock and the correction clock to obtain a first phase detection result; the ideal output clock and the correction clock are phase detected to obtain a second phase detection result; and the first phase detection result is compared with the second phase detection result to obtain error information of the output clock, so as to correct the clock frequency of the output clock output by the frequency division circuit according to the error information.

19. The control method of the frequency division correction circuit according to claim 18, characterized in that: The number of the frequency division circuit and the number of the correction circuit are both multiple; The plurality of correction circuits share the correction clock output by the same auxiliary correction circuit; the plurality of frequency division circuits correspond one-to-one to the plurality of correction circuits, and any of the frequency division circuits inputs the output clock to a correction circuit corresponding thereto.

20. The control method of the frequency division correction circuit according to claim 18 or 19, characterized in that: The auxiliary correction circuit includes a first phase detector, a first filter, and a first clock generator; The method of generating a correction clock by using the auxiliary correction circuit comprises: receiving, by the first phase detector, a first reference clock and the correction clock fed back by the first clock generator, and performing phase detection on the first reference clock and the correction clock by the first phase detector to obtain a third phase detection result; The third phase detection result is received through the first filter, and the third phase detection result is filtered by the first filter, so that the clock frequency of the correction clock output by the first clock generator is a clock frequency constant of the correction clock.

21. The control method of the frequency division correction circuit according to claim 20, characterized in that: Before the clock frequency of the corrected output clock is equal to the clock frequency of the ideal output clock, the clock frequency of the corrected clock is a fixed frequency.

22. The control method of the frequency division correction circuit according to any one of claims 18 to 21, characterized in that: The frequency division circuit includes the integer frequency division circuit, the fractional frequency division circuit, the incremental sum modulator, and the fractional frequency division adjustment circuit; The step of dividing the received input clock by the frequency dividing circuit to obtain the output clock comprises: Inputting a value N into the integer frequency division circuit through the incremental summation circuit according to a first frequency ratio between the clock frequency of the input clock and the ideal frequency; wherein N includes n and n+1, and the difference between the first frequency ratio and n, and the difference between n+1 and the first frequency ratio are both less than 1; and n is a positive integer; Utilize the integer frequency division circuit to receive the input clock and the value N, and perform integer frequency division on the input clock in a manner of interleaving n-division and n+1-division to obtain a basic clock, and input the basic clock to the fractional frequency division circuit; Inputting a basic clock adjustment value into the fractional frequency division adjustment circuit through the incremental summing circuit; the basic clock adjustment value is the decimal place of the accumulated value of the first frequency ratio in each signal cycle; Obtaining a first adjustment code value according to the basic clock adjustment value through the fractional frequency division adjustment circuit, and inputting the first adjustment code value into the fractional frequency division circuit; The fractional frequency division circuit adjusts the basic clock using the first adjustment code value to output the output clock.

23. The control method of the frequency division correction circuit according to claim 22, characterized in that: The correction circuit includes a second phase detector, an error comparison circuit, and a compensation circuit; Using the second phase detector to perform phase detection on the output clock and the correction clock of a group of signal cycles to obtain the first phase detection result; wherein the group of signal cycles includes multiple signal cycles, and the first phase detection result is the accumulated value of the phase detection results of the output clock and the correction clock in the multiple signal cycles; Using the second phase detector to perform phase detection on the ideal output clock and the correction clock of the group of signal cycles to obtain the second phase detection result; wherein the second phase detection result is the accumulated value of the phase detection results of the ideal output clock and the correction clock in multiple signal cycles; Using the error comparison circuit to compare the first phase discrimination result and the second phase discrimination result of the group of signal cycles to obtain error information of the output signal; The clock frequency of the output clock of the next group of signal cycles is corrected according to the error information by the compensation circuit.

24. The control method of the frequency division correction circuit according to claim 23, characterized in that: The using the second phase detector to perform phase detection on the output clock and the correction clock of a group of signal cycles to obtain the first phase detection result includes: calculating, by the second phase detector, a second frequency ratio between the clock frequency of the correction clock and the frequency of the output clock, or a third frequency ratio between the frequency of the output clock and the clock frequency of the correction clock in each of the signal cycles; using the second phase detector to obtain a phase detection result between the output clock and the correction clock in each of the signal cycles according to the product of the second frequency ratio and the basic clock adjustment value, or according to the product of the third frequency ratio and the basic clock adjustment value; and accumulating, by the second phase detector, the phase detection results between the output clock and the correction clock in the group of signal cycles to obtain the first phase detection result; The using the second phase detector to perform phase detection on the ideal output clock and the correction clock of the group of signal cycles to obtain the second phase detection result includes: calculating, by the second phase detector, a fourth frequency ratio between the clock frequency of the correction clock and the frequency of the ideal output clock, or a fifth frequency ratio between the frequency of the ideal output clock and the clock frequency of the correction clock in each of the signal cycles; using the second phase detector to obtain a phase detection result between the ideal output clock and the correction clock in each of the signal cycles according to the product of the fourth frequency ratio and the basic clock adjustment value, or according to the product of the fifth frequency ratio and the basic clock adjustment value; and accumulating the phase detection results between the ideal output clock and the correction clock in the group of signal cycles by the second phase detector to obtain the second phase detection result; The using the error comparison circuit to compare the first phase detection result and the second phase detection result of the group of signal cycles to obtain the error information of the output signal includes: using the error comparison circuit to receive the first phase detection result and the second phase detection result, and performing a difference between the first phase detection result and the second phase detection result through the error comparison circuit to obtain the error information; wherein, if the first phase detection result is calculated by the second frequency ratio and the basic clock adjustment value, the second phase detection result is calculated by the fourth frequency ratio and the basic clock adjustment value; if the first phase detection result is calculated by the third frequency ratio and the basic clock adjustment value, the second phase detection result is calculated by the fifth frequency ratio and the basic clock adjustment value; The step of correcting the clock frequency of the output clock of the next group of signal cycles according to the error information by the compensation circuit comprises: obtaining a gain adjustment value and / or a nonlinear adjustment value according to the error information by the compensation circuit, and inputting the gain adjustment value and / or the nonlinear adjustment value into the frequency division circuit by the compensation circuit; The method of the frequency division correction circuit further includes: using the frequency division circuit to output the corrected output clock in the next group of signal cycles according to the gain adjustment value and / or the nonlinear adjustment value.

25. The control method of the frequency division correction circuit according to claim 22, characterized in that: The correction circuit includes a second phase detector, an error comparison circuit, and a compensation circuit; Using the second phase detector to perform phase detection on the output clock received in the current signal period and the correction clock to obtain the first phase detection result; Using the second phase detector to perform phase detection on the ideal output clock of the current signal period and the correction clock to obtain the second phase detection result; Using the error comparison circuit to compare the first phase detection result with the second phase detection result to obtain error information of the output clock; The compensation circuit corrects the clock frequency of the output clock output by the frequency division circuit in the next signal cycle according to the error information.

26. The control method of the frequency division correction circuit according to claim 25, characterized in that: The using the second phase detector to perform phase detection on the output clock received in the current signal period and the correction clock to obtain the first phase detection result includes: calculating, by the second phase detector, a second frequency ratio between the clock frequency of the correction clock and the frequency of the output clock, or a third frequency ratio between the frequency of the output clock and the clock frequency of the correction clock in the current signal period; using the second phase detector to obtain the first phase detection result between the output clock and the correction clock in the current signal period according to the product of the second frequency ratio and the basic clock adjustment value, or according to the product of the third frequency ratio and the basic clock adjustment value; The using the second phase detector to perform phase detection on the ideal output clock of the current signal cycle and the correction clock to obtain the second phase detection result includes: calculating, by the second phase detector, a fourth frequency ratio between the clock frequency of the correction clock and the frequency of the ideal output clock, or a fifth frequency ratio between the frequency of the ideal output clock and the clock frequency of the correction clock in the current signal cycle; using the second phase detector to obtain the second phase detection result between the ideal output clock and the correction clock in the current signal cycle according to the product of the fourth frequency ratio and the basic clock adjustment value, or according to the product of the fifth frequency ratio and the basic clock adjustment value; The using the error comparison circuit to compare the first phase detection result with the second phase detection result to obtain the error information of the output clock includes: using the error comparison circuit to receive the first phase detection result and the second phase detection result, and performing a difference between the first phase detection result and the second phase detection result to obtain the error information; wherein, if the first phase detection result is calculated by the second frequency ratio and the basic clock adjustment value, the second phase detection result is calculated by the fourth frequency ratio and the basic clock adjustment value; if the first phase detection result is calculated by the third frequency ratio and the basic clock adjustment value, the second phase detection result is calculated by the fifth frequency ratio and the basic clock adjustment value; The step of correcting the clock frequency of the output clock output by the frequency dividing circuit in the next signal cycle according to the error information by the compensation circuit comprises: obtaining a gain adjustment value and / or a nonlinear adjustment value according to the error information by using the compensation circuit, and inputting the gain adjustment value and / or the nonlinear adjustment value into the frequency dividing circuit; The control method of the frequency division correction circuit further includes: using the frequency division circuit to output the corrected output clock in the next signal cycle according to the gain adjustment value and / or the nonlinear adjustment value.

27. The control method of the frequency division correction circuit according to claim 24 or 26, characterized in that: The decimal places of the fourth frequency ratio and the decimal places of the fifth frequency ratio are both greater than a preset accuracy.

28. The control method of the frequency division correction circuit according to claim 24 or 26, characterized in that: The second phase detector comprises a first calculation circuit, a second calculation circuit, and a first adder; the second phase detector is used to calculate a second frequency ratio between the clock frequency of the correction clock and the frequency of the output clock, or a third frequency ratio between the frequency of the output clock and the clock frequency of the correction clock in the current signal cycle; Obtaining, by the second phase detector, the first phase detection result between the output clock and the correction clock in the current signal cycle according to the product of the second frequency ratio and the basic clock adjustment value, or according to the product of the third frequency ratio and the basic clock adjustment value, comprising: Calculating, by using the first calculation circuit, a second frequency ratio between the clock frequency of the correction clock and the frequency of the output clock, or a third frequency ratio between the frequency of the output clock and the clock frequency of the correction clock in the current signal cycle; and obtaining, by using the first calculation circuit, an integer bit result of the first phase detection result of the output clock and the correction clock in the current signal cycle according to the product of the second frequency ratio and the basic clock adjustment value, or according to the product of the third frequency ratio and the basic clock adjustment value; Calculating, by using the second calculation circuit, a second frequency ratio between the clock frequency of the correction clock and the frequency of the output clock, or a third frequency ratio between the frequency of the output clock and the clock frequency of the correction clock in the current signal cycle; and obtaining, by using the first calculation circuit, an integer bit result of the first phase detection result of the output clock and the correction clock in the current signal cycle according to the product of the second frequency ratio and the basic clock adjustment value, or according to the product of the third frequency ratio and the basic clock adjustment value; The first adder is used to add the integer result and the decimal result to obtain the first phase detection result.

29. The control method of the frequency division correction circuit according to claim 24, characterized in that: The error comparison circuit includes a register, a second adder, a third adder, and a second filter; The step of receiving the first phase detection result and the second phase detection result by the error comparison circuit, and performing a subtraction between the first phase detection result and the second phase detection result by the error comparison circuit to obtain the error information includes: Using the register to input the phase detection result of the output clock and the correction clock in the previous signal cycle to the second adder, and using the register to receive and store the phase detection result of the output clock and the correction clock input by the second phase detector in the current signal cycle; Receiving the phase discrimination result of the current signal cycle and the phase discrimination result of the previous signal cycle through the second adder, and using the second adder to subtract the phase discrimination result of the current signal cycle from the phase discrimination result of the previous signal cycle to obtain a current phase discrimination result of the current signal cycle; The current phase discrimination result is received by the second filter, and the current phase discrimination result is filtered to obtain a second phase discrimination result between the ideal output clock and the correction clock in the current signal period; The third adder is used to subtract the current phase-locked detection result from the second phase-locked detection result to obtain the difference between the error information of the current signal period and the error information of the previous signal period, and the difference between the error information of the group of signal periods is added to obtain the error information of the group of signal periods.

30. The control method of the frequency division correction circuit according to any one of claims 22 to 29, characterized in that: The method of using the frequency division circuit to output the corrected output clock in the next group of signal cycles according to the gain adjustment value and / or the nonlinear adjustment value, or using the frequency division circuit to output the corrected output clock in the next signal cycle according to the gain adjustment value and / or the nonlinear adjustment value, comprises: Obtaining a second adjustment code value according to the gain adjustment value and / or the nonlinear adjustment value by the fractional frequency division adjustment circuit; The fractional frequency division circuit is used to correct the output clock in the next group of signal cycles or the next signal output according to the second adjustment code value.

31. The control method of the frequency division correction circuit according to claim 30, characterized in that: The output clock after correction in the next group of signal cycles or the next signal output by the fractional frequency division circuit according to the second adjustment code value comprises: The fractional frequency divider adjustment circuit adjusts at least one of the resistance value, capacitance value, voltage value, and inductance value of the components included in the fractional frequency divider according to the second adjustment code value, so as to output the corrected output clock in the next group of signal cycles or the next signal cycle.

32. The control method of the frequency division correction circuit according to any one of claims 18 to 31, characterized in that: The clock correction circuit also includes a clock generating circuit; before dividing the received input clock by the frequency dividing circuit to obtain the output clock, the control method of the frequency division correction circuit also includes: The input clock is generated by the clock generation circuit, and the input clock is input to the frequency division circuit.

33. The control method of the frequency division correction circuit according to claim 32, characterized in that: The clock generating circuit includes a third phase detector, a third filter, and a second clock generator; and using the clock generating circuit to generate the input clock includes: generating the input clock by using the second clock generator, and inputting the input clock to the frequency dividing circuit; Receiving the second reference clock and the output clock through the third phase detector, performing phase detection on the second reference clock and the output clock, and obtaining a fourth phase detection result; The fourth phase detection result is received through the third filter and filtered to adjust the clock frequency of the input clock output by the second clock generator.

34. A chip, characterized in that: It comprises the frequency division correction circuit as described in any one of claims 1-17.

35. An electronic device, characterized in that: It comprises a circuit board and the chip as claimed in claim 34, wherein the chip is arranged on the circuit board.

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