Epitaxial silicon wafer and method for manufacturing same

Abstract

Provided is an epitaxial silicon wafer (100) having a silicon epitaxial layer (2) on a main surface of a silicon wafer (1) having a chamfered part (13) in order to suppress peeling of an annular protrusion formed by epitaxial processing. The silicon wafer (1) contains boron and has a resistivity of 5 to 30 mΩcm, the resistivity of the silicon epitaxial layer (2) is higher than the resistivity of the silicon wafer 1, and the thickness of the silicon epitaxial layer 2 is 0.5 to 15 μm. The surface of a chamfered part (131) on the main surface side of the silicon wafer (1) and the surface of an end surface (133) of the chamfered part are covered with the silicon epitaxial layer (2), and a chamfered part (132) on the back surface side has an annular protruding part (4) formed at a boundary (14) between a region (R1) that is covered by the silicon epitaxial layer (2) and a region (R2) that is not covered with the silicon epitaxial layer (2).

Description

Epitaxial silicon wafer and method for manufacturing the same

[0001] The present invention relates to an epitaxial silicon wafer and a method for manufacturing the same.

[0002] Epitaxial silicon wafers are wafers in which an epitaxial silicon film is formed on the main surface of a bulk silicon substrate, and they have high crystalline perfection. Therefore, they are widely used as substrate materials for high-quality, highly reliable semiconductor devices. For example, BSPDN (Backside Power Distribution Network) applications in cutting-edge, highly integrated logic devices that process massive amounts of data at high speeds require large-diameter epitaxial silicon wafers in which a high-resistivity epitaxial film with a low dopant concentration is grown on a low-resistivity bulk silicon substrate with a high dopant concentration.

[0003] When manufacturing such epitaxial silicon wafers, there is a problem of so-called autodoping, in which dopants contained in the bulk silicon substrate volatilize and are incorporated into the epitaxial film during the epitaxial growth process, resulting in a locally high dopant concentration in the epitaxial film. As a method for preventing autodoping, a method is known in which an oxide film (SiOx) is formed on the back surface of the bulk silicon substrate to prevent dopant volatilization (see Patent Document 1).

[0004] JP 2013-182910 A

[0005] However, during epitaxial growth, the source gas for the epitaxial process flows around to the region on the back surface edge of the wafer where no oxide film is formed, so that epitaxial growth occurs in this region (a phenomenon known as backside deposition), while epitaxial growth does not occur in the region on the back surface of the wafer where an oxide film is formed. As a result, an annular protrusion (a portion where a step caused by the epitaxial film is formed in a circular shape along the circumferential direction) is formed by the epitaxial film at the boundary between the region on the back surface of the wafer where an oxide film is formed and the region on the back surface where no oxide film is formed.

[0006] In the manufacturing process of semiconductor devices, when an epitaxial silicon wafer on which this annular protrusion is formed is loaded onto a boat or the like, the annular protrusion may come into contact with the boat or a handling jig, causing it to peel off and adhere to other wafers, resulting in a problem of light point defects (LPDs).

[0007] The problem to be solved by the present invention is to provide an epitaxial silicon wafer and a manufacturing method thereof that suppresses peeling of an annular protrusion formed by epitaxial processing.

[0008] The present invention provides an epitaxial silicon wafer having a silicon epitaxial layer on a main surface of a silicon wafer having a chamfered portion, wherein the silicon wafer contains boron and has a resistivity of 5 to 30 mΩ cm, the resistivity of the silicon epitaxial layer is higher than the resistivity of the silicon wafer, the silicon epitaxial layer has a thickness of 0.5 to 15 μm, the chamfered portion on the main surface side of the silicon wafer and the surfaces of the end faces of the chamfered portion are covered with the silicon epitaxial layer, and the chamfered portion on the back surface side has an annular protrusion formed by the boundary between the region covered with the silicon epitaxial layer and the region not covered with the silicon epitaxial layer. This solves the above-mentioned problem.

[0009] In the above invention, it is preferable that the in-plane variation in resistivity of the silicon epitaxial layer is 3.5% or less.

[0010] In the above invention, it is preferable that the maximum value of ESFQR is 30 nm or less and the average value is 20 nm or less when the edge exclusion region is 1 mm, and therefore the chamfer width of the chamfered portion on the main surface side is 200 to 300 μm. It is preferable.

[0011] In the above invention, it is preferable that the height of the annular protrusion from the surface of the silicon wafer is 4 μm or less.

[0012] In the above invention, it is preferable that no nodules are present in the chamfered portion, the root mean square roughness Rq of the back surface of the silicon wafer is preferably 0.1 to 0.3 nm, the angle formed between the back surface of the silicon wafer and the chamfered portion on the back surface side is preferably 30 to 40°, and the resistivity of the silicon epitaxial layer is preferably 0.1 to 1000 Ω cm, more preferably 8 to 12 Ω cm. Note that Rq here refers to the root mean square roughness calculated from an image measured with an AFM (Atomic Force Microscope), and is a value calculated from an image obtained by flattening an image having a measurement field of view of 1 × 1 μm and a measurement pixel size of 512 pixels in the X direction and 256 pixels in the Y direction and then low-pass filtering the image.

[0013] The present invention also provides a method for manufacturing an epitaxial silicon wafer, comprising: a wafer preparation step of preparing a boron-doped silicon wafer having a resistivity of 5 to 30 mΩ cm, preferably 5 to 10 mΩ cm; an oxide film formation step of forming an oxide film on the back surface of the silicon wafer, the chamfered portion on the front surface, the end faces of the chamfered portion, and the entire chamfered portion on the back surface; a first oxide film removal step of removing the oxide film so that the oxide film on the back surface of the silicon wafer and a portion of the oxide film on the chamfered portion on the back surface remain; an epitaxial growth step of forming a silicon epitaxial layer having a resistivity higher than that of the silicon wafer on the main surface of the silicon wafer after the first oxide film removal step; and a second oxide film removal step of removing the oxide film present on the silicon wafer after the epitaxial step.

[0014] In the above invention, it is preferable that the silicon epitaxial layer formed on the main surface of the silicon wafer in the epitaxial growth step has a thickness of 0.5 to 10 μm.

[0015] In the above invention, the thickness of the oxide film formed on the back surface of the silicon wafer in the oxide film formation step is preferably 500 to 5000 angstroms, and more preferably 500 to 1500 angstroms from the viewpoint of productivity of the oxide film formation process and the oxide film removal process.

[0016] In the above invention, it is preferable that in the first oxide film removal step, the oxide film on the chamfered portion is removed by rotating the silicon wafer and polishing the chamfered portion with a polishing pad in contact with the chamfered portion.

[0017] In the above invention, it is preferable to control the width of the oxide film removed from the chamfered portion on the rear surface by controlling the pressing force of the polishing pad that is brought into contact with the end face of the chamfered portion.

[0018] In the above invention, it is preferable that the second oxide film removing step involves etching the oxide film using a molten solution containing hydrofluoric acid.

[0019] In the above invention, the etching process is preferably carried out using a single-wafer spin cleaner.

[0020] In the above invention, the resistivity of the silicon epitaxial layer is preferably 0.1 to 1000 Ω·cm, and more preferably 8 to 12 Ω·cm.

[0021] According to the present invention, peeling of the annular protrusion formed by the epitaxial process can be suppressed. By providing this type of wafer, the occurrence of defects in the semiconductor device manufacturing process is suppressed, and efforts such as reducing defective products, reusing, and recycling can be promoted by improving the yield of the semiconductor manufacturing process. It is expected that this will also reduce waste from the semiconductor manufacturing process.

[0022] 1 is a cross-sectional view showing an embodiment of an epitaxial silicon wafer according to the present invention. FIG. 2 is an enlarged cross-sectional view of part II in FIG. 1. FIG. 3 is a cross-sectional view showing an edge of the silicon wafer of FIG. 1. FIG. 4 is a cross-sectional view showing an edge of a silicon wafer after an oxide film formation process according to an embodiment of the present invention. FIG. 5 is a cross-sectional view showing an edge of a silicon wafer in a first oxide film removal process according to an embodiment of the present invention. FIG. 6 is a cross-sectional view showing an edge of a silicon wafer after a first oxide film removal process according to an embodiment of the present invention. FIG. 7 is a cross-sectional view showing an edge of a silicon wafer after an epitaxial growth process according to an embodiment of the present invention. FIG. 8 is a plan view showing measurement points for resistivity variations in an epitaxial silicon wafer according to an embodiment of the present invention. FIG. 9 is a cross-sectional view of a wafer edge showing a contact point with a handling jig or the like in a device manufacturing process of an epitaxial silicon wafer according to an embodiment of the present invention. FIG. 10 is a cross-sectional view of a wafer edge showing the position of an annular protrusion in an example and a comparative example of the present invention. FIG. 11 is an SEM photograph showing the edge of a wafer according to Examples 1 and 2 of the present invention. FIG. 12 is an SEM photograph showing the edge of a wafer according to Comparative Examples 1 and 2 of the present invention. FIG. 13 is an SEM photograph showing the edge of a wafer according to Comparative Examples 3 and 4 of the present invention. 1 is a graph showing the measurement results of the height of the annular protrusion relative to the film thickness of the silicon epitaxial layer in Examples 1 and 2 of the present invention. 2 is a graph obtained by extrapolating the measurement results of the height of the annular protrusion relative to the film thickness of the silicon epitaxial layer in Examples 1 and 2 of the present invention.

[0023] <Epitaxial Silicon Wafer 100> Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the specification, claims, and drawings of the present invention, numerical ranges indicated by the symbol "to" include both ends of the range. Fig. 1 is a cross-sectional view showing one embodiment of an epitaxial silicon wafer according to the present invention, Fig. 2 is an enlarged cross-sectional view of part II in Fig. 1, and Fig. 3 is a cross-sectional view showing the edge of the silicon wafer before a silicon epitaxial layer is formed.

[0024] The epitaxial silicon wafer 100 of this embodiment includes a silicon wafer 1 having a chamfered portion 13 and a silicon epitaxial layer 2 formed on a main surface 11 of the silicon wafer 1. The diameter and thickness of the epitaxial silicon wafer 100 of this embodiment are not particularly limited, and may be, for example, 300 mm in diameter and 761 to 795 μm in thickness.

[0025] The silicon wafer 1 of this embodiment is a bulk silicon substrate cut from a silicon single crystal by the Czochralski method, and has a main surface 11, a back surface 12, and a chamfered portion 13. The silicon wafer 1 of this embodiment is doped with boron and has a resistivity of 5 to 30 mΩ·cm, more preferably 5 to 10 mΩ·cm, which is set low relative to the resistivity of the silicon epitaxial layer 2. The concentration of boron contained in the silicon wafer 1 can be measured by secondary ion mass spectrometry (SIMS), and the resistivity of the silicon wafer 1 is a value obtained by measuring the resistivity of the back surface of the epitaxial silicon wafer 100 by a four-probe method.

[0026] The silicon wafer 1 of this embodiment has a chamfered portion 13 on its outer periphery. The outer periphery of the silicon wafer 1 of this embodiment is chamfered in a chamfering process between the lapping (rough polishing) process and the oxide film formation process described below. As shown in FIG. 3 , the chamfered portion 13 of the silicon wafer 1 of this embodiment includes a chamfered portion 131 on the main surface side, a chamfered portion 132 on the back surface side, and an end face 133 of the chamfered portion. Here, the boundary line between the main surface 11 of the silicon wafer 1 and the chamfered portion 131 on the main surface side is a circle connecting the rounded ends of the chamfered portion 131 on the main surface side. Similarly, the boundary line between the back surface 12 of the silicon wafer 1 and the chamfered portion 132 on the back surface side is a circle connecting the rounded ends of the chamfered portion 132 on the back surface side. Furthermore, the boundary line between the end face 133 of the chamfered portion and the chamfered portion 131 on the main surface side is a circle connecting the end of the R of the chamfered portion 131 on the main surface side, and similarly, the boundary line between the end face 133 of the chamfered portion and the chamfered portion 132 on the back surface side is a circle connecting the end of the R of the chamfered portion 132 on the back surface side.

[0027] 3, the width A1 of the chamfered portion 131 on the main surface side in a side view of the wafer is referred to as the chamfer width of the chamfered portion 131 on the main surface side, and similarly, the width A2 of the chamfered portion 132 on the back surface side is referred to as the chamfer width of the chamfered portion 132 on the back surface side. Also, as shown in FIG. 3, the angle formed between the main surface 11 of the silicon wafer 1 and the chamfered portion 131 on the main surface side is referred to as θ1, and the angle formed between the back surface 12 of the silicon wafer 1 and the chamfered portion 132 on the back surface side is referred to as θ2. The chamfer widths A1 and A2 and the angles θ1 and θ2 can be measured using an edge profiler.

[0028] In the chamfered portion 13 defined as above, which includes the chamfered portion 131 on the main surface side, the chamfered portion 132 on the back surface side, and the end face 133 of the chamfered portion, the silicon wafer 1 of this embodiment has a chamfer width A1 of 200 to 300 μm for the chamfered portion 131 on the main surface side. By setting the chamfer width A1 of 200 to 300 μm for the chamfered portion 131 on the main surface side, the flatness quality of the outer peripheral portion, such as ESFQR (Edge Site Front surface referenced least squares / Range), can be improved. As a result, for example, when the edge exclusion region is set to 1 mm, the maximum value of ESFQR can be 30 nm or less, and the average value can be 20 nm or less.

[0029] Here, ESFQR (Edge Flatness Metric, Sector Based, Front Surface Referenced, Site Front Least Squares Range) is an index indicating the flatness measured by SFQR within a sector-shaped area formed on the periphery of the wafer, and the smaller the value, the higher the flatness. In this specification, ESFQR is a value measured within a sector in which the measurement exclusion area (edge ​​exclusion area) is 1 mm, the entire circumference of the wafer is divided into 72 at 5 degree intervals, and the sector length D is 15 mm, using a flatness measuring device (KLA-Tencor: Wafer Sight 2). SFQR (Site Front Least Squares Range) is an index that indicates the flatness within a given site according to the SEMI standard. This SFQR is a value evaluated for each site, expressed as the sum of the absolute values ​​of the maximum displacements on the positive and negative sides from a reference plane calculated by the least squares method within the set site.

[0030] Furthermore, in the silicon wafer 1 of this embodiment, the angle θ2 formed between the back surface 12 of the silicon wafer 1 and the chamfered portion 132 on the back surface side is 30 to 40°. If the angle θ2 formed between the back surface 12 of the silicon wafer 1 and the chamfered portion 132 on the back surface side is smaller than 30°, there is a risk of particles being generated, whereas if this angle θ2 is larger than 40°, there is a risk of a large amount of source gas getting around to the back surface 12 side of the silicon wafer 1 during epitaxial growth, resulting in an increased amount of deposition on the back surface 12.

[0031] The silicon epitaxial layer 2 of this embodiment is formed at least on the main surface 11 of the silicon wafer 1. The resistivity of the silicon epitaxial layer 2 of this embodiment is at least higher than the resistivity of the silicon wafer 1, and is preferably 0.1 to 1000 Ω·cm, and more preferably 8 to 12 Ω·cm. Although not particularly limited, it is more preferable that the in-plane variation in resistivity of the silicon epitaxial layer 2 is 3.5% or less. If the in-plane variation in resistivity of the silicon epitaxial layer 2 exceeds 3.5%, this is undesirable because it leads to product variation in the device process and a decrease in manufacturing yield, such as increased variation in threshold voltage during semiconductor device formation. The variation in resistivity of the silicon epitaxial layer 2 is measured using the Hg-CV method, which is a type of capacitance-voltage method, at a total of nine locations: one location at the center P0 of the epitaxial silicon wafer 100 shown in FIG. 8, four locations at a portion P1 that is half the radius, and four locations at a portion P2 that is 5 mm from the edge, and the variation in resistivity of the silicon epitaxial layer 2 refers to the variation in the measured values ​​at these nine locations.

[0032] In this embodiment, the thickness t of the silicon epitaxial layer 2 is 0.5 to 15 μm. If the thickness t of the silicon epitaxial layer 2 is less than 0.5 μm, there is a high risk of defects due to COPs (crystal-originating particles) and PIDs (process-induced defects) present on the silicon substrate surface. On the other hand, if the thickness t exceeds 15 μm, the productivity of the epitaxial growth process deteriorates, which is undesirable. Furthermore, since the height of the annular protrusion increases as the thickness of the epitaxial layer increases, it is desirable for the thickness t of the silicon epitaxial layer 2 to be 10 μm or less. In the case of a 300 mm wafer, the thickness t of the silicon epitaxial layer 2 is measured at 31 locations at 10 mm intervals on the diameter line of the epitaxial silicon wafer 100, starting from a point 3 mm from the outer periphery, using a film thickness measuring device that uses Fourier transform-infrared spectroscopy (FT-IR).

[0033] The silicon epitaxial layer 2 of this embodiment is formed not only on the main surface 11 of the silicon wafer 1 but also on a chamfered portion 131 and an end face 133 of the chamfered portion on the main surface side of the silicon wafer 1. The silicon epitaxial layer 2 extends to a part of the chamfered portion 132 on the back surface side, and the chamfered portion 132 on the back surface side has an annular protrusion 4. As shown in the enlarged cross-sectional view of FIG. 2 , the annular protrusion 4 of this embodiment is a raised portion of the silicon epitaxial layer 2 formed at a boundary 14 between a region R1 covered with the silicon epitaxial layer 2 and a region R2 not covered with the silicon epitaxial layer 2, and this protrusion extends annularly around the entire circumference of the wafer.

[0034] 9 is a cross-sectional view showing an example of contact points between various devices used in a semiconductor device manufacturing process and an epitaxial silicon wafer 100. T1 indicates a contact point with a wafer support boat or a wafer transfer device that supports the backside edge of the wafer, T2 indicates a contact point with a wafer cassette (FOUP or FOSB), and T3 indicates a contact point with a handling ring jig of a wafer inspection device that grips the wafer edge. The annular protrusion 4 of this embodiment is located within the chamfered portion 132 on the backside and is not present on the backside of the wafer. This reliably avoids contact at contact point T1 with the inspection device stage or wafer transfer device, thereby preventing peeling of the annular protrusion 4. Furthermore, by forming the annular protrusion 4 of this embodiment at a position that avoids contact points T2 and T3, peeling due to contact with the wafer cassette or handling jig can also be suppressed.

[0035] Although not particularly limited, it is more preferable that the height of the annular protrusion 4 from the surface of the silicon wafer 1 be 4 μm or less. The basis for this value will be explained in the examples described later.

[0036] Before epitaxial processing, the epitaxial silicon wafer 100 of this embodiment is fabricated by forming an oxide film having a thickness of 500 angstroms or more on the back surface 12 of the silicon wafer 1, the chamfered portion 131 on the main surface side, the end face 133 of the chamfered portion, and the chamfered portion 132 on the back surface side, and then removing the oxide film 3 so that the oxide film 3 on the back surface 12 of the silicon wafer 1 and a portion of the oxide film 3 on the chamfered portion 132 on the back surface side remain. Then, in this state, the silicon epitaxial layer 2 is formed on the main surface 11 of the silicon wafer 1, and the silicon epitaxial layer 2 extends not only to the main surface 11 of the silicon wafer 1 but also to the chamfered portion 131 on the main surface side of the silicon wafer 1, the end face 133 of the chamfered portion, and a portion of the chamfered portion 132 on the back surface side. Therefore, the epitaxial layer 2 is formed without the oxide film 3 on the end face 133 of the chamfered portion, and therefore nodules formed by abnormal growth of polysilicon are generated on the end face 133 of the chamfered portion, and an epitaxial silicon wafer 100 without nodules is obtained in the chamfered portion 13. This will be explained in the examples below. The thickness of the oxide film 3 can be measured using an ellipsometer for both an oxide film formed by atmospheric pressure CVD and a native oxide film.

[0037] In the epitaxial silicon wafer 100 of this embodiment, the oxide film 3 formed on the back surface 12 of the silicon wafer 1 is removed by etching, so that the back surface 12 of the silicon wafer 1 maintains the surface texture after the double-side polishing process, and the root-mean-square roughness Rq of the back surface 12 of the silicon wafer 1 is 0.1 to 0.3 nm.

[0038] <<Method for Manufacturing Epitaxial Silicon Wafer 100>> Next, an example of a method for manufacturing the epitaxial silicon wafer 100 of this embodiment will be described. First, a silicon wafer doped with boron and having a resistivity of 5 to 30 mΩ cm is prepared (wafer preparation step). A bulk silicon substrate having a resistivity of 5 to 30 mΩ cm is cut from a silicon single crystal grown by the Czochralski method, and the silicon wafer 1 is prepared by performing lapping, chamfering, grinding, double-side polishing, and chamfered portion polishing. It is more preferable that the resistivity of the silicon wafer is 5 to 10 mΩ cm.

[0039] An oxide film 3 for preventing autodoping is formed on this silicon wafer 1 (oxide film formation step). In the oxide film formation step, for example, a single-sheet atmospheric pressure CVD apparatus is used, and the silicon wafer 1 is placed on a susceptor of the atmospheric pressure CVD apparatus with the main surface 11 facing downward. The silicon wafer 1 is then heated to form an oxide film 3 having a thickness of 500 to 1500 angstroms (0.05 to 0.15 μm) on the back surface 12 facing upward and on the chamfered portion 13 (the chamfered portion 131 on the main surface side, the end face 133 of the chamfer, and the chamfered portion 132 on the back surface side). If the thickness of the oxide film 3 is less than 500 angstroms, a sufficient autodoping suppression effect cannot be obtained. On the other hand, if the thickness of the oxide film 3 exceeds 1500 angstroms, the silicon wafer 1 may be warped and the cost of removing the oxide film 3 increases, which is undesirable. FIG. 4 is a cross-sectional view showing an edge portion of the silicon wafer 1 after the oxide film formation step according to an embodiment of the present invention has been completed. FIG. 4 shows the silicon wafer 1 on which the oxide film 3 has been formed on the back surface 12 and the chamfered portion 13 (the chamfered portion 131 on the main surface side, the end face 133 of the chamfered portion, and all of the chamfered portion 132 on the back surface side) by this oxide film formation step.

[0040] Next, the oxide film 3 is removed so that the oxide film 3 on the back surface 12 of the silicon wafer 1 and a portion of the oxide film 3 in the chamfered portion 132 on the back surface side remain (first oxide film removal step). Fig. 5 is a cross-sectional view showing the edge of the silicon wafer 1 in the first oxide film removal step according to an embodiment of the present invention. In this first oxide film removal step, for example, a polishing device used in the polishing process of the chamfered portion 13 is used, and as shown in Fig. 5, the silicon wafer 1 is rotated and polished by bringing polishing pads 15 and 16 into contact with the chamfered portion 13, thereby removing the oxide film in the chamfered portion 13.

[0041] That is, in the first oxide film removal step of this embodiment, the oxide film 3 on the back surface 12 of the silicon wafer 1 and a part of the oxide film 3 on the chamfered portion 132 on the back surface side are left, so as shown in FIG. 5 , the polishing pad 15 corresponding to the chamfered portion 131 on the main surface side and the polishing pad 16 corresponding to the end face 133 of the chamfered portion are operated to remove the oxide film 3 formed on the chamfered portion 131 on the main surface side and the oxide film 3 formed on the end face 133 of the chamfered portion.

[0042] The width of the oxide film 3 removed from the backside chamfer 132 is controlled by controlling the pressing force of the polishing pad 16 that contacts the end face 133 of the chamfer. That is, by utilizing the sinking of the polishing pad 16, the pressing force of the polishing pad 16 is controlled to be large when it is desired to increase the width of the oxide film 3 removed from the backside chamfer 132, and the pressing force of the polishing pad 16 is controlled to be small when it is desired to decrease the width of the oxide film 3 removed. Figure 6 is a cross-sectional view showing the edge of a silicon wafer after the first oxide film removal step according to an embodiment of the present invention. In the second oxide film removal step of this embodiment, the oxide film 3 is removed by polishing using the polishing pads 15 and 16, which allows for more accurate control of the removal width than etching the oxide film 3 using a hydrofluoric acid-containing molten solution.

[0043] 6, with the oxide film 3 on the back surface 12 of the silicon wafer 1 and a portion of the oxide film 3 in the chamfered portion 132 on the back surface remaining, a silicon epitaxial layer 2 having a resistivity higher than that of the silicon wafer 1 (for example, a resistivity of 0.1 to 1000 Ω·cm, preferably 8 to 12 Ω·cm) and a thickness t of 0.5 to 10 μm is formed on the main surface 11 of the silicon wafer 1 (epitaxial growth step). In this epitaxial growth step, for example, a single-sheet atmospheric pressure CVD apparatus is used, and the silicon wafer 1 is placed on a susceptor of the atmospheric pressure CVD apparatus with the main surface 11 facing up, and trisilane Si ３ H ８ , dichlorosilane SiH ２ Cl ２ , trichlorosilane SiHCl ３ , tetrachlorosilane SiCl ４While supplying source gases such as these, silicon is vapor-phase grown at a temperature in the range of 900 to 1200° C. Fig. 7 is a cross-sectional view showing an edge of the silicon wafer 1 after the epitaxial growth step according to an embodiment of the present invention.

[0044] Finally, the oxide film 3 present on the silicon wafer 1 after the epitaxial process is removed (second oxide film removal process). While this oxide film 3 does not necessarily need to be removed, it may be etched using a hydrofluoric acid-containing melt in this second oxide film removal process. Etching the oxide film 3 using a hydrofluoric acid-containing melt restores the surface texture of the backside 12 before the oxide film 3 was formed, i.e., the quality of the polished surface obtained by the double-side polishing process. The etching process using a hydrofluoric acid-containing melt can be performed using a single-wafer spin cleaner. This type of spin cleaning method can prevent particles from adhering to the surface of the silicon epitaxial layer 2 and contaminating the silicon epitaxial layer 2. Figure 2 is a cross-sectional view showing the edge of the epitaxial silicon wafer 100 obtained after the second oxide film removal process, and is an enlarged cross-sectional view of part II in Figure 1.

[0045] As described above, the epitaxial silicon wafer 100 of this embodiment is an epitaxial silicon wafer 100 having a silicon epitaxial layer 2 on the main surface 11 of a silicon wafer 1 having a chamfered portion 13, wherein the silicon wafer 1 contains boron and has a resistivity of 5 to 30 mΩ cm, more preferably 5 to 10 mΩ cm, the resistivity of the silicon epitaxial layer 2 being higher than the resistivity of the silicon wafer 1, the thickness of the silicon epitaxial layer 2 being 0.5 to 15 μm, the surfaces of the chamfered portion 131 and the chamfered portion end face 133 on the main surface side of the silicon wafer 1 are covered with the silicon epitaxial layer 2, and the chamfered portion 132 on the back surface side has an annular protrusion 4 constituted by a boundary 14 between a region R1 covered with the silicon epitaxial layer 2 and a region R2 not covered with the silicon epitaxial layer 2. Therefore, since the annular protrusion 4 is formed on the chamfered portion 132 on the back surface side, when the epitaxial silicon wafer 100 is handled in various steps in the manufacturing process of a semiconductor device, the annular protrusion 4 is prevented from coming into contact with a boat, a handling jig, etc. As a result, it is possible to prevent the annular protrusion 4 from peeling off and adhering to other wafers to become bright point defects (LPDs).

[0046] Furthermore, the epitaxial silicon wafer 100 of this embodiment is epitaxially grown in a state in which the oxide film 3, which causes the formation of the annular protrusion 4, is formed on the back surface 12 of the silicon wafer 1 and part of the chamfered portion 13. This prevents autodoping from the silicon wafer 1 to the silicon epitaxial layer 2, and as a result, the in-plane variation in resistivity of the silicon epitaxial layer 2 can be maintained at 3.5% or less.

[0047] Furthermore, in the epitaxial silicon wafer 100 of the present embodiment, the chamfer width A1 of the chamfered portion 131 on the main surface side is 200 to 300 μm. Therefore, when the edge exclusion region is 1 mm, the maximum value of ESFQR can be set to 30 nm or less, and the average value can be set to 20 nm or less.

[0048] The method for producing an epitaxial silicon wafer according to this embodiment includes a wafer preparation step of preparing a silicon wafer 1 doped with boron and having a resistivity of 5 to 30 mΩ cm, more preferably 5 to 10 mΩ cm; an oxide film formation step of forming an oxide film 3 on the back surface 12 of the silicon wafer 1, the chamfered portion 131 on the main surface side, the end face 133 of the chamfered portion, and all of the chamfered portion 132 on the back surface side; and a first oxidation step of removing the oxide film 3 so that the oxide film 3 on the back surface 12 of the silicon wafer 1 and a part of the oxide film 3 on the chamfered portion 132 on the back surface side remain. The method includes a film removal step, an epitaxial growth step of forming a silicon epitaxial layer 2 having a resistivity higher than that of the silicon wafer 1 on the main surface 11 of the silicon wafer 1 after the first oxide film removal step, and a second oxide film removal step of removing the oxide film 3 present on the silicon wafer 1 after the epitaxial step. This makes it possible to accurately form the annular protrusion 4 at the boundary 14 of the chamfered portion 132 on the back surface side between the region R1 covered with the silicon epitaxial layer 2 and the region R2 not covered with the silicon epitaxial layer 2.

[0049] In the method for producing an epitaxial silicon wafer according to this embodiment, in the first oxide film removal step, the silicon wafer 1 is rotated and polishing pads 15, 16 are brought into contact with the chamfered portion 13 to polish it, thereby removing the oxide film 3 from the chamfered portion 13. In particular, the removal width of the oxide film 3 from the chamfered portion 132 on the back surface side is controlled by controlling the pressing force of the polishing pad 16 brought into contact with the end face 133 of the chamfered portion, which enables more accurate control of the removal width than in an etching process of the oxide film 3 using a molten solution containing hydrofluoric acid.

[0050] A number of boron-doped silicon wafers with a resistivity of 10 mΩ cm were prepared. A 750 Å thick oxide film was formed on the back surface and chamfer of each silicon wafer by CVD. The oxide film formed on the chamfer was then polished to produce six levels of silicon wafers with different remaining positions of the oxide film, as described below (see "Position of Formation of Annular Protrusion 4" for details).

[0051] A boron-doped silicon epitaxial layer with a resistivity of 10 Ω-cm was formed on the surface of each of the six silicon wafers to produce epitaxial silicon wafers. The thickness of the silicon epitaxial layer was set to one of four levels described below (see "Height h of annular protrusion 4" for details). Finally, the oxide film remaining on the back surface and the chamfered portion on the back surface of each epitaxial silicon wafer was removed by etching using a hydrofluoric acid solution in a spin cleaner.

[0052] <<Formation Position of Annular Protrusion 4>> As described above, in order to set an appropriate formation position of the annular protrusion 4 according to the present invention, six levels of epitaxial silicon wafers 100 were fabricated in which the position of the boundary 14 between the region R1 covered with the silicon epitaxial layer 2 and the region R2 not covered with the silicon epitaxial layer 2 was changed in the oxide film formation step. The positions of the boundary 14 in each of Examples 1 and 2 and Comparative Examples 1 to 4 are shown in FIG. 10 . Note that the first oxide film removal step was not performed in Comparative Example 4. The epitaxial silicon wafers 100 in Examples 1 and 2 and Comparative Examples 1 to 4 were fabricated under the same conditions except for changing the position of the boundary 14.

[0053] The epitaxial silicon wafers 100 produced at each of the six levels were cleaved, and the cross sections were observed with an optical microscope to identify the positions of the boundaries 14 (steps) where the oxide films 3 had been formed. The cross sections were then observed with an SEM (Scanning Electron Microscope) to measure the height h (step) of the annular protrusions 4 at the boundaries 14. The measurement results of the height h of the annular protrusions 4 are shown in Table 1.

[0054]

[0055] The height h of the annular protrusion 4 in Comparative Examples 2 to 4, in which the boundary 14 between the region R1 covered with the silicon epitaxial layer 2 and the region R2 not covered with the silicon epitaxial layer 2 is located in the chamfered portion 131 on the main surface side, tends to be higher than the height h of the annular protrusion 4 in Examples 1 and 2, in which the boundary 14 is located in the chamfered portion 132 on the back surface side. This is because the amount of source gas that flows around during epitaxial growth is greater in the chamfered portion 131 on the main surface side. As a result, it was confirmed that it is preferable to form the boundary 14 between the region R1 covered with the silicon epitaxial layer 2 and the region R2 not covered with the silicon epitaxial layer 2 at the chamfered portion 132 on the back surface side rather than the chamfered portion 131 on the main surface side.

[0056] <<Nodule Generation>> The boundary 14 of the epitaxial silicon wafers 100 of Examples 1 and 2 and Comparative Examples 1 to 4 was observed by SEM from the chamfered end face 133 side to confirm the presence or absence of abnormal protruding growth of polysilicon, known as nodules. The results are shown in FIGS. 11 to 13. The nodules are indicated by arrows in the SEM photographs of Comparative Examples 2 to 4 in FIGS. 12 and 13. In the epitaxial silicon wafers 100 of Comparative Examples 2 to 4, the oxide film 3 was formed up to the chamfered end face 133. It is presumed that this oxide film 3 was locally ruptured by contact with a handling jig during wafer transport prior to the epitaxial growth step, or that silicon was locally exposed by etching in the cleaning step after the oxide film 3 was formed, resulting in abnormal growth of polysilicon at the locally exposed silicon locations during epitaxial growth. From this perspective, it is preferable that the annular protrusion 4 be located in the chamfered portion 132 on the back surface side, as in Examples 1 and 2, in order to suppress nodule generation.

[0057] <Height h of Annular Protrusion 4> Next, a preferred height h of the annular protrusion 4 was confirmed. For the epitaxial silicon wafers 100 of Examples 1 and 2 described above, in which the annular protrusion 4 was formed in the chamfered portion 132 on the back surface side as shown in FIG. 10 , wafers were produced in which the film thickness of the silicon epitaxial layer 2 was changed to 1.0 μm, 2.0 μm, 4.0 μm, or 6.0 μm. These epitaxial silicon wafers 100 were then cleaved, and the cross sections were observed with an optical microscope to identify the position of the boundary 14 (step) where the oxide film 3 had been formed. The height h (step) of the annular protrusion 4 at the boundary 14 was measured by observation with an SEM. The measurement results of the height h of the annular protrusion 4 are shown in Table 2.

[0058]

[0059] As shown in the results in Table 2, increasing the film thickness of the silicon epitaxial layer 2 tended to increase the height h of the annular protrusion 4 in both Examples 1 and 2. It was also confirmed that the height h of the annular protrusion 4 in Example 1 was lower than that in Example 2. This is presumably because the amount of source gas that reached the end face during epitaxial growth was smaller in Example 1 than in Example 2.

[0060] FIG. 14 is a graph of the measurement results in Table 2. It was confirmed that the height h of the annular protrusion 4 increases linearly as the thickness of the silicon epitaxial layer 2 increases. FIG. 15 is a graph extrapolating the height h of the annular protrusion 4 when the thickness of the silicon epitaxial layer 2, which is the horizontal axis of FIG. 14, increases. As shown in the figure, even when the thickness of the silicon epitaxial layer 2 is set to 15 μm, the height h of the annular protrusion 4 is estimated to be 4 μm or less. Therefore, even when a film formation process such as a nitride film is performed on the annular protrusion 4 during the semiconductor device manufacturing process, the annular protrusion 4 of this embodiment has a low height h, which prevents film peeling defects.

[0061] According to the present invention, it is possible to provide an epitaxial silicon wafer in which the occurrence of film peeling defects is suppressed, and also to provide an epitaxial silicon wafer in which the in-plane resistivity distribution of the silicon epitaxial layer is excellent and the outer circumferential flatness is excellent.

[0062] Epitaxial wafers are essential materials for semiconductor devices, supporting our daily lives. Logic semiconductors in particular have excellent energy-saving properties and can contribute to making products lighter and more compact.

[0063] By producing high-quality epitaxial wafers according to the present invention, energy savings in electronic devices and CO ２ This will lead to a reduction in emissions and contribute to efforts to combat climate change. Systems such as self-driving cars and smart grids controlled by logic semiconductors are also important technologies for promoting efficient energy use, and will contribute to sustainable activities such as achieving Goal 13 of the Sustainable Development Goals (SDGs): "Improve education, awareness, and human capacity and institutions for climate change mitigation, adaptation, impact reduction and early warning."

[0064] REFERENCE SIGNS LIST 100... epitaxial silicon wafer 1... silicon wafer 11... main surface 12... back surface 13... chamfered portion 131... chamfered portion on main surface side 132... chamfered portion on back surface side 133... end face of chamfered portion R1... region covered with silicon epitaxial layer R2... region not covered with silicon epitaxial layer 14... boundary between R1 and R2 A1... chamfer width of chamfered portion on main surface side A2... chamfer width of chamfered portion on back surface side 15, 16... polishing pad 2... silicon epitaxial layer 3... oxide film 4... annular protrusion t... thickness of silicon epitaxial layer h... height of annular protrusion

Claims

1. An epitaxial silicon wafer having a silicon epitaxial layer on a main surface of a silicon wafer having a chamfered portion, wherein the silicon wafer contains boron and has a resistivity of 5 to 30 mΩ·cm, the resistivity of the silicon epitaxial layer is higher than the resistivity of the silicon wafer, the silicon epitaxial layer has a thickness of 0.5 to 15 μm, the chamfered portion on the main surface side of the silicon wafer and the surfaces of the end faces of the chamfered portion are covered with the silicon epitaxial layer, and the chamfered portion on the back surface side has an annular protrusion formed by the boundary between an area covered with the silicon epitaxial layer and an area not covered with the silicon epitaxial layer.

2. The epitaxial silicon wafer according to claim 1, wherein the in-plane variation in resistivity of the silicon epitaxial layer is 3.5% or less.

3. The epitaxial silicon wafer according to claim 1, wherein the maximum value of ESFQR is 30 nm or less and the average value is 20 nm or less when the edge exclusion region is 1 mm.

4. The epitaxial silicon wafer according to claim 3, wherein the chamfer width of the chamfered portion on the main surface side is 200 to 300 μm.

5. The epitaxial silicon wafer according to claim 1, wherein the height of said annular protrusion from the surface of said silicon wafer is 4 μm or less.

6. The epitaxial silicon wafer according to claim 1, wherein said chamfered portion is free of nodules.

7. The epitaxial silicon wafer according to claim 1, wherein the root mean square roughness Rq of the back surface of the silicon wafer is 0.1 to 0.3 nm.

8. The epitaxial silicon wafer according to claim 1, wherein the angle between the back surface of the silicon wafer and the chamfer on the back surface side is 30 to 40 degrees.

9. The epitaxial silicon wafer according to claim 1, wherein the resistivity of the silicon epitaxial layer is 0.1 to 1000 Ω·cm.

10. A method for manufacturing an epitaxial silicon wafer, comprising: a wafer preparation step of preparing a boron-doped silicon wafer having a resistivity of 5 to 30 mΩ cm; an oxide film formation step of forming an oxide film on the back surface of the silicon wafer, on the chamfered portion on the front surface side, the end faces of the chamfered portion, and on the chamfered portion on the back surface side; a first oxide film removal step of removing the oxide film so that the oxide film on the back surface of the silicon wafer and a part of the oxide film on the chamfered portion on the back surface side remain; an epitaxial growth step of forming a silicon epitaxial layer having a resistivity higher than that of the silicon wafer on the main surface of the silicon wafer after the first oxide film removal step; and a second oxide film removal step of removing the oxide film present on the silicon wafer after the epitaxial growth step.

11. The method for producing an epitaxial silicon wafer according to claim 10, wherein the silicon epitaxial layer formed on the main surface of the silicon wafer in the epitaxial growth step has a thickness of 0.5 to 10 μm.

12. The method for producing an epitaxial silicon wafer according to claim 10, wherein the oxide film formed on the back surface of the silicon wafer in the oxide film forming step has a thickness of 500 to 5,000 angstroms.

13. A method for producing an epitaxial silicon wafer as set forth in claim 10, wherein in the first oxide film removal step, the oxide film on the chamfered portion of the silicon wafer is removed by rotating the silicon wafer and polishing the chamfered portion by contacting a polishing pad with the chamfered portion of the silicon wafer.

14. A method for producing an epitaxial silicon wafer according to claim 13, wherein the pressing force of the polishing pad brought into contact with the end face of the chamfered portion is controlled to control the removal width of the oxide film from the chamfered portion on the back surface side.

15. The method for producing an epitaxial silicon wafer according to claim 10, wherein in the second oxide film removal step, the oxide film is etched using a molten liquid containing hydrofluoric acid.

16. The method for producing an epitaxial silicon wafer according to claim 15, wherein the etching process is carried out using a single-wafer spin cleaner.

17. The method for producing an epitaxial silicon wafer according to claim 10, wherein the resistivity of the silicon epitaxial layer is 0.1 to 1000 Ω·cm.

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