Semiconductor mask to define quantum well intermixing region of LED

Abstract

The invention concerns an optoelectronic device comprising a semiconductor layer stack of at least a first layer of a first conductivity type, a second layer of a second conductivity type as well as an active region arranged between the first and the second layer. The active region comprises a quantum well structure, and the semiconductor layer stack comprises a central region and an edge region laterally surrounding the central region. The optoelectronic device further comprises a first semiconductor contact layer arranged on the first layer, wherein the first semiconductor contact layer comprises a different material as the first layer. The first contact layer covers the central region but exposes the edge region. In addition, the active region in the edge region and / or the active region in an edge portion of the central region adjacent to the edge region comprises a quantum well intermixing while the active region in at least a central portion of the central region comprises substantially no quantum well intermixing.

Description

[0001] SEMICONDUCTOR MASK TO DEFINE QUANTUM WELL INTERMIXING REGION OF LED

[0002] The present invention concerns an optoelectronic device comprising a quantum well intermixing at the sidewalls of the LED, wherein a semiconductor mask is used for the quantum well intermixing which remains in the final optoelectronic device . The present invention concerns a method for manufacturing such an optoelectronic device .

[0003] BACKGROUND

[0004] InGaAlP optoelectronic devices , for example light emitting devices (LEDs ) suffer from nonradiative losses at the LED sidewall (NRR) . The smaller the LED, the more these losses become dominant . For very small LED ( e . g . 10 pm) such as pLEDs , significant light output is only possible , if NRR can be reduced .

[0005] NRR can be reduced by doing quantum well intermixing ( QWI ) at the LED sidewalls . This can be done using for example Zn-Diffusion / defect driven QWI . To define regions of QWI and no QWI usually a hard mas k is used, e . g . Si02 , SiON, SiN, which is arranged on the semiconductor material of the later LED . These types of hard masks effectively block material from entering the semiconductor surface thereby preventing a QWI of the underlying structure . The material of such a dielectric hard mas k can however apply strain to the semiconductor material of the LED, therefore introducing defects , e . g . Ga-vacancies . In addition, a deposition of a dielectric hard mask and a subsequent removal can lead to additional defects .

[0006] In general , attempts are being made to provide improved doping processes .

[0007] The present invention is based on the obj ect of providing an improved method for producing an optoelectronic device and an improved optoelectronic device .

[0008] SUMMARY OF THE INVENTION This and other obj ects are addressed by the subj ect matter of the independent claims . Features and further aspects of the proposed principles are outlined in the dependent claims .

[0009] The idea of the inventors is to locally apply an on wafer level grown semiconductor strain free layer , such as for example a GaAs top layer, on a semiconductor layer stack which is used as a mas k for quantum well intermixing ( QWI ) the sidewalls of the semiconductor layer stack . The material of the semiconductor strain free layer is for example chosen such that its lattice constant is by a maximum of 10% different to the lattice constant of the adj acent layer of the semiconductor layer stack to provide a certain level of strain freeness . In addition, the material of the semiconductor strain free layer is chosen such that during the QWI process , the semiconductor structure below the semiconductor strain free layer experiences substantially no quantum well intermixing . The mas ked area will thus show substantially no QWI , whereas the exposed area is showing QWI , resulting in NRR reduction and therefore higher efficient LEDs / pLEDs . The use of the semiconductor strain free layer thereby is beneficial in comparison to e . g . a SiO2 hard mas k, as the degradation behaviour of the semiconductor strain free layer is significantly improved compared to a SiO2 hard mask . In addition, by means of using the semiconductor strain free layer less wafer processes for providing a mas k for QWI are necessary .

[0010] According to one aspect , an optoelectronic device is provided . The optoelectronic device comprises a semiconductor layer stack of at least a first layer of a first conductivity type , a second layer of a second conductivity type as well as an active region arranged between the first and the second layer .

[0011] The active region of the semiconductor layer stack comprises a quantum well structure , and in particular at least one quantum well arranged between a first and a second barrier layer . The active region can however also comprise a multi quantum well structure comprising several quantum wells as well as several barrier layers , wherein each a quantum well is arranged between the two barrier layers . In addition, the semiconductor layer stack comprises a central region and an edge region laterally surrounding the central region, wherein each the central region and the edge region comprises respective portions of the first and second layer as well as the active region . In other words , the semiconductor layer stack can be separated into a central region and an edge region laterally surrounding the central region, with the active region being separated in a respective way . The separation into regions may however not necessarily be understood as a geometrical separation in terms of separate components or geometrical differences but may for example be understood as regions of one and the same body . In some embodiments these regions can for example comprise different properties but may also be more or less similar to each other in terms of properties .

[0012] The optoelectronic device further comprises a first semiconductor contact layer arranged on the first layer , the first semiconductor contact layer covering the central region of the semiconductor layer stack but exposing the edge region . This is in particular to be understood that a top surface of the semiconductor layer stack can be separated into the edge region and the central region in a respective way, and that the first semiconductor contact layer covers the central region of the top surface but exposes the edge region of the top surface . Further, the first semiconductor contact layer comprises a different material as the first layer .

[0013] Further , the active region in the edge region and / or the active region in an edge portion of the central region adj acent to the edge region comprises a quantum well intermixing . This can mean that due to diffusion of a certain promoter into the vicinity of the active region in the edge region and / or the active region in an edge portion of the central region a quantum well intermixing can have taken place thereby increasing the bandgap of the active region in the edge region and / or the active region in an edge portion of the central region . At the same time , the active region in at least a central portion of the central region comprises substantially no quantum well intermixing . The first semiconductor contact layer can thereby have been acted as a mask preventing a quantum well intermixing in at least a central portion of the central region . Due to quantum well mixing, the band gap of the active region in the edge region and / or the active region in an edge portion of the central region may therefore be increased compared to at least the central portion of the central region, thus reducing NRR along the side surfaces of the LED .

[0014] The first semiconductor contact layer can thereby in particular have been acted as a mask layer masking the central region during / f or a quantum well intermixing process , which however compared to classical hard mas ks used for QWI remains in the final optoelectronic device . Compared to classical hard masks used for QWI , such as hard masks made of Si02 , the material of the semiconductor contact layer can be chosen to have an improved aging behaviour during lifetime of the optoelectronic device and to avoid introducing dislocations into the semiconductor material of the optoelectronic device due to high strains and / or migration of e . g . Ga and / or passivation / depassivation of dangling bonds between the hard mas k and the semiconductor layer stack e . g . due to a high difference in lattice constants .

[0015] The separation of the central region into an edge portion and a central portion can in particular be understood as a virtual separation, wherein the separation lie can be defined by a grade of quantum well intermixing of the active region of the edge portion and the central portion . For example , the central region may relate to the region of the semiconductor layer stack in which the active region comprises no or substantially no QWI , whereas the edge region may relate to the region of the semiconductor layer stack in which the active region comprises a QWI . In case of the whole central region comprises no or substantially no QWI , a separation into edge portion and central portion may be dispensed with .

[0016] According to some aspects , the first semiconductor contact layer comprises a lattice constant that is at most 10 % different from the lattice constant of the first layer . The first semiconductor contact layer can for example be substantially strain free with regard to the first layer of the semiconductor layer stack or comprise an at least sufficiently reduced strain compared to the first layer of the semiconductor layer stack .

[0017] According to some aspects , the edge region and in particular the portion of the active region of the edge region comprises a higher concentration of a promoter promoting a quantum well intermixing than the central region . However , this is not to be understood as meaning that the central region necessarily also comprises a QWI , but it cannot be completely ruled out that the central region may also comprise a minimum concentration of the promoter promoting a quantum well intermixing . In particular also an edge portion of the central region can comprise a concentration of the promoter promoting a quantum well intermixing, in particular a higher concentration than the central portion of the central region . It can however also be that due to the active region in the edge region has been removed when patterning the semiconductor layer stack, only the edge portion of the central region can comprise a concentration of the promoter promoting a quantum well intermixing, in particular a higher concentration than the central portion of the central region .

[0018] According to some aspects , the promoter promoting a quantum well intermixing contains zinc . For example , the promoter promoting a quantum well intermixing may be produced by degrading or decomposing an organometallic precursor, for example , diethylzinc or dimethylzinc before diffusing it into the edge region and / or an edge portion of the central region of the semiconductor layer stack .

[0019] According to some aspects , the first semiconductor contact layer comprises at least one layer of AlxGa (i-X) As , with 0 0 , 95 . In particular the first semiconductor contact layer can comprise at least one layer of GaAs or a layer of AlGaAs . However , the first semiconductor contact layer can also comprise a combination of GaAs and / or AlGaAs layers .

[0020] According to some aspects , the first semiconductor contact layer comprises an Al content of up to 50% . For example , the total content of Al of the first semiconductor contact layer can be greater than 0% , greater than 20% , or greater than 30% up to a maximum value of 50% .

[0021] According to some aspects , the first semiconductor contact layer can be of the first conductivity type acting as a current spreading or current confinement layer on the semiconductor layer stack . For example , the first semiconductor contact layer can act as a contact layer for applying a first potential to the light emitting diode .

[0022] According to some aspects , the first semiconductor contact layer comprises a thickness between 3 nm and 30 nm, in particular the first semiconductor contact layer can comprise a thickness between 6 nm and 8 nm . In particular the first semiconductor contact layer can be chosen to have an comparable thin thickness , as depending on the material chosen for the first semiconductor contact layer the light absorption of the material can be comparably high . By choosing the first semiconductor contact layer having a thin thickness , a shading of the top surface of the optoelectronic device can be prevented .

[0023] According to some aspects , the layers of the semiconductor layer stack comprise InxGayAl u-x-y) P , with O ^ x ^ l , O ^ y ^ l and x + 1 , or AlxGai-xAs with 0 1 . In particular , the layers of the semiconductor layer stack may, for example , comprise a II I-V compound semiconductor material . The semiconductor layer stack may, for example , contain a phosphide semiconductor material . For example , the semiconductor layer stack may comprise a material of the composition InxGayAl u-x-y) P, where x and y may each assume values between 0 and 1 . According to further embodiments , the I II-V compound material may also be an arsenide compound semiconductor material . For example , the semiconductor layer stack may comprise a material of the composition AlxGai-xAs , where x may assume values between 0 and 1 .

[0024] According to some aspects , the optoelectronic device is configured to emit light having a wavelength that is in the range between 560 nm and 670 nm . According to some aspects , the optoelectronic device is configured to emit light having a wavelength that is in a range up to 1050 nm and thus light in the infrared range . This is in particular to understood in such that the optoelectronic device is configured to emit light with a wavelength subrange that lies within the range between 560 nm and 670 nm or up to 1050 nm. For example , the optoelectronic device can be configured to emit light with green, yellow, orange , red or infrared light .

[0025] Prior to the QWI process the exposed surface of the edge region may be surface treated by means of a plasma treatment with halogens . As a result of the plasma treatment with halogens , a subsequent diffusion process for introducing the promoter may be greatly accelerated . Furthermore , undesirable surface effects may be suppressed . This improves the homogeneity of the promoter in the structure .

[0026] According to some aspects , an exposed surface of the edge region adj acent to the first semiconductor contact layer, in particular the edge portion of the top surface of the semiconductor layer stack, is conditioned using halogenides . This conditioning can in particular result from a prior plasma treatment with halogens . In addition or as an alternative , an exposed side surface of the central region adj acent to the first semiconductor contact layer is conditioned using halogenides . This conditioning can in particular result from a prior plasma treatment with halogens .

[0027] According to some aspects , the exposed surface of the edge region adj acent to the first semiconductor contact layer, in particular the edge portion of the top surface of the semiconductor layer stack, comprises a nano-structuring . In addition or as an alternative , an exposed side surface of the central region adj acent to the first semiconductor contact layer comprises a nano-structuring . The nanostructuring can in particular result from a prior plasma treatment with halogens , which may in particular not substantially etch the exposed surface but may result in a nano-structuring of the exposed surface .

[0028] According to some aspects , the exposed surface of the edge region adj acent to the first semiconductor contact layer, in particular the edge portion of the top surface of the semiconductor layer stack, comprises a non-volatile compound . In addition or as an alternative , an exposed side surface of the central region adj acent to the first semiconductor contact layer comprises a non-volatile compound . The nonvolatile compound can in particular result from a prior plasma treatment with halogens and can lower the activation energy for a subsequent diffusion process , in which the atoms to be diffused are first degraded and subsequently penetrate the crystal lattice . The nonvolatile compound may be retained on the exposed surface ( s ) over a longer period of time . For example , the non-volatile compound may be retained for several months , for example , half a year . The non-volatile compound may also survive cleaning in an oxygen plasma , for example , cleaning in an oxygen plasma to remove a photoresist layer used for a patterning . Furthermore , the non-volatile compound has sufficient stability at elevated temperatures , for example , temperatures greater than 500 ° C . or 520 ° C . , which may occur during a diffusion process .

[0029] According to some aspects , the central region extends over at least 50 % , in particular at least 75 % or at least 90 % , or at least 95 % of the lateral extension of the semiconductor layer stack . This can in particular be understood as the ratio between the lateral extension of the central region versus the lateral extension of the whole semiconductor layer stack at at least one or any cross sectional plane through the semiconductor layer stack in a plane parallel to the top surface of the semiconductor layer stack .

[0030] According to some aspects , the central portion of the central region extends over at least 75 % or at least 90 % , or at least 95 % , or at least 99 % of the lateral extension of the central region . This can in particular be understood as the ratio between the lateral extension of the central portion of the central region versus the lateral extension of the whole central region at at least one or any cross sectional plane through the semiconductor layer stack in a plane parallel to the top surface of the semiconductor layer stack .

[0031] According to some aspects , the first conductivity type is an n-type and the second conductivity type is a p-type . The first layer can thus be an n-type semiconductor layer and the second layer can be a p-type semiconductor layer . The optoelectronic device can in particular be a small light emitting or light detecting component / element such as a small LED or pLED or a small photodetector . A pLED can in particular be a very small LED with edge lengths down to 40 pm, down to 10 pm, down to 5 pm or even less . Such small components can be free of a growth substrate and require a special handling and processing to improve their IQE and light out- / incoupling efficiency .

[0032] According to a further aspect , a method for manufacturing a optoelectronic device is provided . The method can in particular be a method for manufacturing an optoelectronic device according to at least some of aforementioned aspects . Hence all aspects already described for the optoelectronic device can in the same way be applied to the method for manufacturing the same .

[0033] The method for manufacturing an optoelectronic device comprises the steps :

[0034] Providing a semiconductor layer stack of at least a first layer of a first conductivity type , a second layer of a second conductivity type as well as an active region arranged between the first and the second layer , wherein the active region comprises a quantum well structure ;

[0035] Providing a first semiconductor contact layer on the first layer , wherein the first semiconductor contact layer comprises a different material as the first layer, and wherein the first contact layer covers a central region of the semiconductor layer stack but exposes an edge region of the semiconductor layer stack laterally surrounding the central region; and

[0036] Quantum well intermixing the active region in the edge region and / or the active region in an edge portion of the central region adj acent to the edge region such that the active region in the edge region and / or the active region in an edge portion comprises a quantum well intermixing but the active region in at least a central portion of the central region comprises substantially no quantum well intermixing .

[0037] According to some aspects , the method further comprises a step of patterning the semiconductor layer stack thereby removing a portion of the edge region adj acent to the first semiconductor contact layer resulting in an exposed side surface of the central region adj acent to the first semiconductor contact layer . The step of patterning can thereby be an etching step , in particular mesa etching step . The exposed side surfaces can in particular extend from the top surface of the semiconductor layer stack into the direction of the bottom surface of the semiconductor layer stack . The side surfaces can thereby be directly adj acent to the first semiconductor contact layer or distant from the first semiconductor contact layer . By means of the patterning for example a whole upper portion of the edge region can be removed or a portion distant from the central region .

[0038] According to some aspects , the step of patterning the semiconductor layer stack comprises a removal of a portion of the edge region comprising the first layer and / or the active region and / or the second layer .

[0039] According to some aspects , the step of quantum well intermixing comprises a step of diffusing a promoter promoting the quantum well intermixing , in particular zinc ( Zn ) and / or magnesium (Mg ) , into the exposed edge region and / or into an exposed side surface of the central region adj acent to the exposed edge region .

[0040] According to some aspects , the step of providing the first semiconductor contact layer comprises a structuring of a continuous layer using lithography process ( es ) and etching process ( es ) such as for example wet chemical etching or plasma etching . By means of this it can be provided that the first contact layer is locally arranged and covers the central region of the semiconductor layer stack but exposes the edge region of the semiconductor layer stack . It can however also be conceivable to locally grow the first semiconductor contact layer .

[0041] According to some aspects , a step of structuring a continuous layer to provide the first semiconductor contact layer can comprise a structuring of the first layer of the semiconductor layer stack and optionally also at least partially of the active region . In particular in case of a structuring using a plasma etching to structure the continuous layer resulting in the first semiconductor contact layer , a typically etch depth can be 150 nm which can exceed the thickness of the first semiconductor contact layer . Hence the edge region of the semiconductor layer stack can at the same time be partially removed while the central region is present entirely under the first semiconductor contact layer .

[0042] According to some aspects , and in particular in case of the semiconductor layer stack comprising a layer containing As , it can be desired to structure all As containing layers of the semiconductor layer stack in the same way as the first semiconductor contact layer . Hence in some aspects all As containing layers can be limited to the central region . This is as particularly As contained in the layer can prevent a f ast / ef f icient diffusion of the promoter into the underlying layer ( s ) .

[0043] According to some aspects , the step of diffusing the promoter into the exposed edge region and / or the n exposed side surface of the central region is conducted with temperatures in the range of 460 ° C to 650 ° C, for example 520 ° C . By means of such a temperature , it can be prevented or at least slowed that the promoter penetrates the first semiconductor contact layer or introduces crystal defects .

[0044] According to some aspects , the promoter or foreign atoms may be diffused from the gas phase or from a solid . The promoter may for example contain zinc .

[0045] According to some aspects , the promoter may be produced by degrading or decomposing an organometallic precursor, for example , diethylzinc or dimethylzinc . The plasma treatment may be performed with fluorine or chlorine or bromine .

[0046] According to some aspects , the step of diffusing the promoter into the exposed edge region is conducted in a PH3 , a AsHs or a group V element atmosphere . Using PH3 atmosphere during QWI process can for example supress a nodule growth on the surface of the first semiconductor contact layer .

[0047] According to some aspects , the method further comprises a step of performing a plasma treatment of the exposed edge region of the semiconductor layer stack and in particular edge region of the top surface of the semiconductor layer stack with halogens . In addition or as an alternative , the method further comprises a step of performing a plasma treatment of the exposed side surface of the central region adj acent to the exposed edge region . This step ( s ) are conducted prior to the step of diffusing the promoter into the exposed edge region and / or the exposed side surface . The step may thereby be performed in an area-selective manner by forming a respective mas k on the semiconductor layer stack prior to the plasma treatment . However, the first semiconductor contact layer also acting as diffusion mas k may be used for the plasma treatment as well .

[0048] According to some aspects , the plasma treatment may be performed in such a manner that the exposed surface and / or the exposed side surface is substantially not etched . However, due to the plasma treatment , the exposed edge region and / or the exposed side surface of the semiconductor layer stack may comprise a nano-structuring and / or a nonvolatile compound .

[0049] According to some aspects , the plasma treatment is performed with a halogenide like fluorine , chlorine or bromine .

[0050] According to some aspects , the method further comprises a step of performing an oxygen plasma treatment of the exposed edge region and / or the exposed side surface after performing the plasma treatment with halogens and before performing the diffusion process .

[0051] According to some aspects , the first semiconductor contact layer compared to common hard mas ks remains on the first layer in the final optoelectronic device .

[0052] SHORT DESCRIPTION OF THE DRAWINGS Further aspects and embodiments in accordance with the proposed principle will become apparent in relation to the various embodiments and examples described in detail in connection with the accompanying drawings in which

[0053] Fig . 1 shows a cross section of an optoelectronic device in accordance with some aspects of the proposed principle ;

[0054] Fig . 2 shows a step of a method for manufacturing an optoelectronic device in accordance with some aspects of the proposed principle ;

[0055] Fig . 3 shows a step of a method for manufacturing a further embodiment a optoelectronic device in accordance with some aspects of the proposed principle ;

[0056] Fig . 4 shows a cross section of another embodiment of an optoelectronic device in accordance with some aspects of the proposed principle ; and

[0057] Fig . 5 shows a cross section of yet another embodiment of an optoelectronic device in accordance with some aspects of the proposed principle .

[0058] DETAILED DESCRIPTION

[0059] The following embodiments and examples disclose various aspects and their combinations according to the proposed principle . The embodiments and examples are not always to scale . Likewise , different elements can be displayed enlarged or reduced in size to emphasize individual aspects . It goes without saying that the individual aspects of the embodiments and examples shown in the figures can be combined with each other without further ado , without this contradicting the principle according to the invention . Some aspects show a regular structure or form. It should be noted that in practice slight differences and deviations from the ideal form may occur without , however, contradicting the inventive idea . In addition, the individual figures and aspects are not necessarily shown in the correct size , nor do the proportions between individual elements have to be essentially correct . Some aspects are highlighted by showing them enlarged . However , terms such as "above" , "over" , "below" , "under" "larger" , "smaller" and the like are correctly represented with regard to the elements in the figures . So it is possible to deduce such relations between the elements based on the figures .

[0060] The term "semiconductor layer stack" used in the following description may include any semiconductor-based structure that has a semiconductor surface . The layer stack is to be understood to include doped and undoped semiconductors , epitaxial semiconductor layers , possibly supported by a base , and further semiconductor structures . For example , several layers made of a semiconductor material may be grown on a growth substrate made of another semiconductor material or of an insulating material , for example , on a sapphire substrate . Depending on the intended use , the semiconductor may be based on a direct or an indirect semiconductor material . Examples of semiconductor materials particularly suited for generating electromagnetic radiation include , in particular , nitride semiconductor compounds through which, for example , ultraviolet , blue or longer-wave light may be generated, such as GaN, InGaN, AIN, AlGaN, AlGainN, lGainBN, phosphide semiconductor compounds , through which, for example , green or longer-wave light may be generated, such as GaAsP, AlGainP , GaP, AlGaP, as well as other semiconductor materials such as AlGaAs , SiC, ZnSe , GaAs , ZnO , Ga2O3 , diamond, hexagonal BN, and combinations of the materials mentioned . The stoichiometric ratio of the compound semiconductor materials may vary . Further examples of semiconductor materials may include silicon, silicon germanium and germanium. In the context of the present description, the term "semiconductor" also includes organic semiconductor materials .

[0061] The terms "lateral" and "horizontal" , as used in this description, are intended to describe an orientation or alignment which runs essentially parallel to a top surface of the semiconductor layer stack . The horizontal direction may, for example , lie in a plane perpendicular to a direction of growth when layers are grown on .

[0062] The term "vertical" , as used in this description, is intended to describe an orientation which is essentially perpendicular to the top surface of the semiconductor layer stack . The vertical direction may, for example , correspond to a direction of growth when layers are grown on .

[0063] To the extent that the terms "have" , "contain" , "comprise" , "include" and the like are used herein, they are open-ended terms that indicate the presence of said elements or features , but do not rule out the presence of other elements or features . The indefinite articles and the definite articles include both the plural and the singular , unless the context clearly indicates otherwise .

[0064] FIG . 1 shows a cross-sectional view of an optoelectronic device 1 as a result of performing a method in accordance with some aspects of the proposed principle . The optoelectronic device 1 is thereby only shown in part , and the structure can be continued in a respective way on the right side of the figure , as indicated by the dotted vertical line . The optoelectronic device 1 comprises a semiconductor layer stack 2 . The semiconductor layer stack may, for example , be of a I II-V compound semiconductor material . The semiconductor material may, for example , contain a phosphide semiconductor material . For example , the semiconductor layer stack 2 may comprise a material of the composition InxGayAli-x-yP, where x and y may each assume values between 0 and 1 . According to further embodiments , the I II-V compound material may also be an arsenide compound semiconductor material . For example , the semiconductor layer stack may comprise a material of the composition AlxGai-xAs , where x may assume values between 0 and 1 .

[0065] The semiconductor layer stack includes different layers or areas made of different materials .

[0066] As shown in Figure 1 , the semiconductor layer stack 2 comprises a first layer 3 of a first conductivity type , a second layer 4 of a second conductivity type as well as an active region 5 arranged between the first and the second layer 3 , 4 . The active region 5 comprises a quantum well structure 6 . The quantum well structure may be formed by arranging layers of a suitable band gap and layer thickness within the active region 5 . The quantum well structure may, for example , have a single quantum well structure ( SQW, single quantum well ) or a multiple quantum well structure (MQW, multiple quantum well ) for generating radiation, for example . In this process , the term "quantum well structure" has no meaning with regard to the dimensionality of the quantization . Thus , it includes , among other things , quantum wells , quantum wires and quantum dots , as well as any combination of these layers .

[0067] The semiconductor layer stack 2 can be separated into a central region 5a and an edge region 5b laterally surrounding the central region 5a . Each of the central region 5a and the edge region 5b comprises a respective portion of the first and second layer 3 , 4 as well as of the active region 5 .

[0068] On top of the central region 5a, in particular on a central region of a top surface 8 of the semiconductor layer stack 2 , a first semiconductor contact layer 7 is arranged . The first semiconductor contact layer 7 is arranged on the semiconductor layer stack 2 covering the central region 5a of the semiconductor layer stack but exposing the edge region 5b . This is in particular to be understood that a top surface 8 of the semiconductor layer stack 2 can be separated into the edge region and the central region in a respective way, and that the first semiconductor contact layer 7 covers the central region of the top surface but exposes the edge region of the top surface . Further, the first semiconductor contact layer 7 comprises a different material as the first layer 3 with the lattice constant of the first semiconductor contact layer 7 being maximum 10 % different from the lattice constant of the first layer 3 . The first semiconductor contact layer 7 is therefore in particular substantially strain free with regard to the first layer 3 of the semiconductor layer stack 2 . For example the first semiconductor contact layer 7 can be of GaAs and / or AlGaAs . The edge region 5b and in particular the portion of the active region 5 of the edge region 5b comprises a quantum well intermixing ( indicated by the dotted lines ) . In particular the edge region 5b comprises a higher quantum well intermixing than the central region 5a . However , this is not to be understood as meaning that the central region 5a necessarily also comprises a QWI , but it cannot be completely ruled out that the central region may also comprise a little bit of quantum well intermixing in an edge portion 9b of the central region 5a . This is indicated in figure 1 by means of the partially dotted lines of the active region 5 in the edge portion . Hence also an area even in the central region 5a below the first semiconductor contact layer 7 can comprise a little bit of quantum well intermixing . The diffusion profile 11 of the promoter promoting a quantum well intermixing indicates that the edge region 5b as well as the edge portion 9b comprises a higher concentration of a promoter promoting a quantum well intermixing than the central portion 9a resulting in the band gap of the active region 5 is increased in the edge region 5b and the edge portion 9b compared to the central portion 9a , thus reducing NRR along the side surfaces of the LED . The depth of the diffusion profile 11 as well as the lateral extension below the semiconductor contact layer 7 and thus the lateral extension of the edge portion 9b is thereby a result of the time of how long the diffusion is conducted . It can thereby in particular be desired that the diffusion profile 11 stops well before a bottom surface opposite the top surface 8 of the semiconductor layer stack 2 to prevent a short within the optoelectronic device through the edge region 5b and / or the edge portion 9b .

[0069] The first semiconductor contact layer 7 can thereby in particular have been acted as a mas k layer mas king the central region 5a during / for a quantum well intermixing process , which however compared to classical hard masks used for QWI remains in the final optoelectronic device 1 . Compared to classical hard masks used for QWI , such as hard masks made of SiO2, the material of the first semiconductor contact layer 7 can be chosen to have an improved aging behaviour during QWI and to reduce diffusion of the promoter at locations with high strain between the hard mas k and the semiconductor layer stack due to a high difference in lattice constants .

[0070] Figures 2 and 3 each show a diffusion step of a method for manufacturing an optoelectronic device in accordance with some aspects of the proposed principle . Besides providing a respective semiconductor layer stack 2 , as well as a structured first semiconductor contact layer 7 , the method comprises performing a diffusion process with a promoter promoting a quantum well intermixing on the exposed top surface 8 ( indicated by means of the arrows ) . The structured first semiconductor contact layer 7 thereby serves as a mas k, preventing or at least reducing the speed of the promoter to diffuse into the semiconductor layer stack 2 below the structured first semiconductor contact layer 7 .

[0071] According to embodiments , the diffusion process , as shown in Figure 2 and 3 , may be performed from the gas phase . For example , a diffusion of zinc atoms as a promoter may be performed . An organometallic precursor material may be used in this process . For example , diethylzinc or dimethylzinc may be provided as a gaseous precursor material . According to further embodiments , the diffusion process may be performed from the solid phase . For example , a suitable material such as a zinc compound may be vapor deposited on the exposed top surface 8 . The promoter is diffused into the material of the semiconductor layer stack 2 by a subsequent temperature treatment step .

[0072] For example , a so-called intermixing of quantum wells may be brought about by diffusion of zinc atoms . In this process , the energy levels of the quantum wells of the quantum well structure 6 each shift in the edge region 5b , as a result of which a lateral leakage of charge carriers at the mesa edge is prevented . As a result , a non-radiative surface recombination on the side flanks of the mesa may be prevented . Diffusion does not or substantially not take place in the central region 5a , however the edge portion 9b may comprise some quantum well intermixing . To receive the structure of Figure 3 , in addition to aforementioned steps , the method comprises a step of performing a plasma treatment of the exposed top surface 8 of the semiconductor layer stack 2 with halogens prior to the diffusion step . The exposed top surface portion is thereby substantially not etched by the plasma treatment , but prepared in such a way that the subsequent diffusion step can be accelerated ( indicated by the serrated line ) .

[0073] The plasma treatment can for example be conducted using a plasma reactor . This plasma treatment modifies the exposed top surface 8 of the semiconductor layer stack 2 , so that a modified surface results . For example , this modification or conditioning produces a non-volatile compound on the exposed top surface 8 , which has a catalytic effect on the subsequent diffusion process for introducing atoms from the gas phase or from the solid phase . For example , a surface coverage with the process gas may form in the area of the modified surface , by which the subsequent process is catalyzed .

[0074] The process parameters for the plasma treatment are selected such that a lowest possible removal rate of the material of the semiconductor layer stack 2 is achieved for the adequate formation of the surface modification described . The removal rate is at least a factor of 10 , for example , at least a factor of 100 , lower than for conventional plasma etching processes with etching gases such as BCI3 , CI2 , or SiC14 . For example , the removal rate or etching rate may be less than 1 nm / sec . The term "substantially not etched" means that the removal rate of the semiconductor material is at least a factor of 10 lower than for these conventional plasma etching processes .

[0075] As a result of the plasma treatment with halogens , a subsequent diffusion process , as shown in Figures 2 and 3 , for introducing the promoter may be greatly accelerated . Furthermore , undesirable surface effects may be suppressed . This improves the homogeneity of the promoter in the structure .

[0076] In particular , the formation of a non-volatile compound can lower the activation energy for the diffusion process , in which the atoms to be diffused are first degraded and subsequently penetrate the crystal lattice .

[0077] It has been found experimentally that , due to the plasma treatment being performed with halogens , a wavelength shift in the electromagnetic radiation may be achieved after a shorter diffusion time . The wavelength shift is achieved by the so-called intermixing of the quantum wells , i . e . the shift of the energy levels within the quantum wells as a result of diffusion of zinc atoms . In this process , the diffusion time may, for example , be reduced to less than 1 / 10 of the original value .

[0078] The diffusion profile 11 of the promoter promoting a quantum well intermixing indicates that the edge region 5b as well as the edge portion 9b comprises a higher concentration of a promoter promoting a quantum well intermixing than the central portion 9a . The depth of the diffusion profile 11 as well as the lateral extension below the semiconductor contact layer 7 and thus the lateral extension of the edge portion 9b is thereby a result of the time of how long the diffusion is conducted and whether a plasma treatment of the exposed top surface 8 of the semiconductor layer stack 2 has been performed .

[0079] Figures 4 and 5 each show a cross section of a further embodiment of an optoelectronic device 1 in accordance with some aspects of the proposed principle . In contrast to aforementioned embodiments the semiconductor layer stack 2 has been patterned and portions of the edge region 5b have been removed exposing side surfaces 10 of the semiconductor layer stack 2 .

[0080] In case of figure 4 , an edge portion of only the first layer 3 has been removed, whereas in case of figure 5 an edge portion of the first layer 3 , the active region 5 and the second layer 4 has been removed . In particular in case of figure 5 the whole edge region of the first layer 3 and the active region 5 and an edge portion of the second layer 4 has been removed . The patterning has thereby been conducted before the step of quantum well intermixing . Thus a diffusion of the promoter into the semiconductor layer stack 2 not only happens with an increased speed into the exposed top surface of the edge region 5b but also into the exposed side surfaces 10 not being covered by the first semiconductor contact layer 7 . A proportion of quantum well intermixing of the central region 5a is therefore increased compared to the embodiments shown in figures 1 to 3 and the edge portion 9a can therefore be larger for the embodiments shown in figures 4 and 5 compared to the embodiments shown in figures 1 to 3 .

[0081] In case of the embodiment shown in figure 5 , a quantum well intermixing is limited to the edge portion 9b of the central region 5a , as the active region 5 of the edge region 5b has been removed . In both cases the first semiconductor contact layer 7 thereby prevents that a quantum well intermixing, when diffusing the promoter on the whole structure , also takes place in the central portion 9a .

[0082] The patterning is thereby to be understood exemplary and a patterning does not have to be conducted directly along the separation of central region 5a and edge region 5b but can also be conducted spaced from the interface between central region 5a and edge region 5b . In addition, the patterning does not have to be conducted to result in vertical side surfaces 10 as shown in the figures but can also result in for example inclined side surfaces 10 , due to for example a mesa etching .

[0083] The diffusion profile 11 of the promoter promoting a quantum well intermixing shown in Figures 4 and 5 indicates that an at least partially conducted diffusion of the promoter trough the side surface 10 results in a steeper diffusion profile within the edge portion 9b . The depth of the diffusion profile 11 as well as the lateral extension below the semiconductor contact layer 7 and thus the lateral extension of the edge portion 9b is not only a result of the time of how long the diffusion is conducted and whether a plasma treatment of the exposed top surface 8 of the semiconductor layer stack 2 has been performed but also if a diffusion of the promoter is conducted from an exposed side surface 10 of the semiconductor layer stack 2 . Although specific embodiments have been illustrated and described herein, persons s killed in the art will recognize that the specific embodiments shown and described may be replaced by a multitude of alternative and / or equivalent embodiments without departing from the scope of the invention . The application is intended to cover any adaptations or variations of the specific embodiments discussed herein . Therefore , the invention is to be limited only by the claims and their equivalents .

[0084] LIST OF REFERENCES

[0085] 1 optoelectronic device

[0086] 2 semiconductor layer stack

[0087] 3 first layer

[0088] 4 second layer

[0089] 5 active region

[0090] 5a central region

[0091] 5b edge region

[0092] 6 quantum well

[0093] 7 first semiconductor contact layer

[0094] 8 top surface

[0095] 9a central portion

[0096] 9b edge portion

[0097] 10 side surface

[0098] 11 diffusion profile

Claims

CLAIMS1. Optoelectronic device comprising: a semiconductor layer stack (2) of at least a first layer (3) of a first conductivity type, a second layer (4) of a second conductivity type as well as an active region (5) arranged between the first and the second layer (3, 4) , wherein the active region (5) comprises a quantum well structure (6) , and wherein the semiconductor layer stack (2) comprises a central region (5a) and an edge region (5b) laterally surrounding the central region (5a) ; and a first semiconductor contact layer (7) arranged on the first layer (3) , wherein the first semiconductor contact layer (7) comprises a different material than the first layer (3) , and wherein the first semiconductor contact layer (7) covers the central region (5a) but exposes the edge region (5b) ; wherein the active region (5) in the edge region (5b) and / or the active region (5) in an edge portion (5b) of the central region (5a) adjacent to the edge region (5) comprises a quantum well intermixing; and wherein the active region (5) in at least a central portion (9a) of the central region (5a) comprises substantially no quantum well intermixing .

2. Optoelectronic device according to claim 1, wherein the lattice constant of the first semiconductor contact layer (7) is at most 10% different from the lattice constant of the first layer (3) .

3. Optoelectronic device according to claim 1 or 2 , wherein the edge region (5b) comprises a higher concentration of a promoter promoting a quantum well intermixing than the central region (5a) ; and / or wherein the edge portion (9b) of the central region (5a) comprises a higher concentration of the promoter promoting a quantum well intermixing than the central portion (9a) of the central region (5a) ;wherein in particular the promoter promoting a quantum well intermixing contains zinc and / or magnesium.

4. Optoelectronic device according to any one of the preceding claims, wherein the first semiconductor contact layer (7) comprises at least one layer of AlxGa (i-X) s ,0, 95.

5. Optoelectronic device according to any one of the preceding claims, wherein the first semiconductor contact layer (7) is of the first conductivity type and in particular comprises an Al content of up to 50%.

6. Optoelectronic device according to any one of the preceding claims, wherein the layers of the semiconductor layer stack (2) comprise7. Optoelectronic device according to any one of the preceding claims, wherein an exposed surface of the edge region (5b) adjacent to the first semiconductor contact layer (7) comprises a nanostructuring; and / or wherein an exposed side surface (10) of the central region (5a) adjacent to the first semiconductor contact layer (7) comprises a nano-structuring .

8. Optoelectronic device according to any one of the preceding claims, wherein an exposed surface of the edge region (5b) adjacent to the first semiconductor contact layer (7) comprises a non-volatile compound; and / or wherein an exposed side surface (10) of the central region (5a) adjacent to the first semiconductor contact layer (7) comprises a non-volatile compound.

9. Optoelectronic device according to any one of the preceding claims, wherein the central region (5a) extends over at least 50%, in particular at least 75% or at least 90%, or at least 95%, of the lateral extension of the semiconductor layer stack (2) ; and / orwherein the central portion (9a) of the central region (5a) extends over at least 75% or at least 90%, or at least 95%, of the lateral extension of the central region (5a) .

10. Optoelectronic device according to any one of the preceding claims, wherein the optoelectronic device (1) is configured to emit light having a wavelength that is in the range between 560 nm and 670 nm.

11. Method for manufacturing an optoelectronic device (1) comprising the steps :Providing a semiconductor layer stack (2) of at least a first layer (3) of a first conductivity type, a second layer (4) of a second conductivity type as well as an active region (5) arranged between the first and the second layer (3, 4) , wherein the active region (5) comprises a quantum well structure (6) ;Providing a first semiconductor contact layer (7) on the first layer (3) , wherein the first semiconductor contact layer (7) comprises a different material as the first layer (3) , and wherein the first contact layer (7) covers a central region (5a) of the semiconductor layer stack (2) but exposes an edge region (5b) of the semiconductor layer stack (2) laterally surrounding the central region (5a) ; andQuantum well intermixing the active region (5) in the edge region (5b) and / or the active region (5) in an edge portion (9b) of the central region (5a) adjacent to the edge region (5b) such that the active region (5) in at least a central portion (9a) of the central region (5a) comprises substantially no quantum well intermixing .

12. Method according to claim 11, further comprising a step of patterning the semiconductor layer stack thereby removing a portion of the edge region (5b) adjacent to the first semiconductor contact layer (7) resulting in an exposed side surface (10) of the central region (5a) adjacent to the first semiconductor contact layer (7) .

13. Method according to claim 11 or 12, wherein the step of quantum well intermixing comprises a step of diffusing a promoter promoting the quantum well intermixing, in particular zinc and / or magnesium, into the exposed edge region (5b) and / or into an exposed side surface (10) of the central region (5a) adjacent to the exposed edge region (5b) .

14. Method according to claim 13, wherein the promoter is diffused from the gas phase; and / or wherein the promoter is produced by degrading an organometallic precursor .

15. Method according to claim 13 or 14,Further comprising a step of plasma treating the exposed edge region (5b) and / or the exposed side surface (10) of the central region (5a) adjacent to the exposed edge region (5b) prior to the step of diffusing the promoter into the exposed edge region (5b) and / or into an exposed side surface (10) of the central region (5a) adjacent to the exposed edge region (5b) with halogens, with the exposed edge region (5b) and / or the exposed side surface (10) of the central region (5a) adjacent to the exposed edge region (5b) being substantially not etched by the plasma treatment.

16. Method according to claim 15, further comprising a step of performing an oxygen plasma treatment after performing the plasma treatment with halogens and before performing the step of diffusing the promoter into the exposed edge region (5b) and / or the exposed side surface (10) of the central region (5a) adjacent to the exposed edge region (5b) .

17. Method according to any one of claims 11 to 16, wherein the step of quantum well intermixing is conducted at least partially in a PH3, a AsH3, or a group V element atmosphere.

18. Method according to any one of claims 11 to 17, wherein the first semiconductor contact layer (7) remains on the first layer ( 3 ) .

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