Display panel and display apparatus

Abstract

A display panel and a display apparatus. The display panel comprises: a base substrate, pixel driving circuit row groups (CP) and light-emitting units (OLED), wherein the pixel driving circuit row groups (CP) each comprise two adjacent pixel driving circuit rows (PH) in a column direction (Y), and each pixel driving circuit row (PH) comprises a plurality of pixel driving circuits (Pix) distributed in a row direction (X); the pixel driving circuits (Pix) are used for driving the light-emitting units (OLED), each pixel driving circuit (Pix) comprises a seventh transistor (T7), a first electrode of the seventh transistor (T7) is connected to a second initial signal line (Vinit2), a second electrode of the seventh transistor (T7) is connected to a first electrode of the corresponding light-emitting unit (OLED), a gate of the seventh transistor (T7) is formed by part of the structure of a second reset signal line (RE2), and an orthographic projection of the second reset signal line (Re2) on the base substrate extends in the row direction (X); and the orthographic projections of two adjacent pixel driving circuit rows (PH) in the same pixel driving circuit row group (CP) on the base substrate are at least partially mirror-symmetric with respect to a first symmetry axis, the first symmetry axis extends in the row direction (X), and two adjacent pixel driving circuit rows (PH) in the same pixel driving circuit row group (CP) share the same second initial signal line (Vinit2).The display panel has high integration and preparation yield.

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In high-pixel-density display panels, a large number of pixel driving circuits need to be integrated within a limited space. Consequently, the display panel has a high wiring density and many vias. This arrangement leads to problems such as high manufacturing difficulty and low production yield.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Summary of the Invention

[0005] According to one aspect of the present disclosure, there is provided a display panel, comprising:

[0006] substrate;

[0007] a pixel driving circuit row group, the pixel driving circuit row group including two adjacent pixel driving circuit rows in the column direction, the pixel driving circuit rows including a plurality of pixel driving circuits distributed in the row direction;

[0008] a light-emitting unit, the pixel driving circuit being used to drive the light-emitting unit, the pixel driving circuit comprising a seventh transistor, a first electrode of the seventh transistor being connected to a second initial signal line, a second electrode of the seventh transistor being connected to a first electrode of the light-emitting unit, a gate of the seventh transistor being formed by a portion of a second reset signal line, an orthographic projection of the second reset signal line on the substrate extending along a row direction;

[0009] In which, the orthographic projections of two adjacent rows of pixel driving circuit rows in the same pixel driving circuit row group on the substrate are at least partially mirror-symmetrically arranged about a first symmetry axis, the first symmetry axis extends along the row direction, and the two adjacent rows of pixel driving circuit rows in the same pixel driving circuit row group share the same second initial signal line.

[0010] In an exemplary embodiment of the present disclosure, the second initial signal line forms the first symmetry axis, and the orthographic projections of two adjacent rows of pixel driving circuits in the same pixel driving circuit row group on the substrate are at least partially mirror-symmetrically arranged about the second initial signal line.

[0011] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a driving transistor and a fifth transistor, wherein a first electrode of the fifth transistor is connected to the first power line, and a second electrode of the fifth transistor is connected to the first electrode of the driving transistor;

[0012] The display panel further includes:

[0013] a first conductive portion, wherein the first conductive portion is used to form a gate of the driving transistor;

[0014] an enable signal line, an orthographic projection of the enable signal line on the substrate extending along a row direction, and a partial structure of the enable signal line being used to form a gate of the fifth transistor;

[0015] In the same pixel driving circuit, an orthographic projection of the second reset signal line on the base substrate is located on a side of the orthographic projection of the enable signal line on the base substrate away from an orthographic projection of the first conductive portion on the base substrate;

[0016] An orthographic projection of the second initial signal line on the base substrate is at least partially located between two adjacent second reset signal lines in the same pixel driving circuit row group.

[0017] In an exemplary embodiment of the present disclosure, the second initial signal line includes:

[0018] a first main body portion, wherein an orthographic projection of the first main body portion on the base substrate extends along a row direction;

[0019] a first raised portion;

[0020] a second protrusion, wherein the first protrusion and the second protrusion are respectively connected to two sides of the first main body in a column direction;

[0021] In the two rows of pixel driving circuits that share the same second initial signal line, the first main body connects the two rows of pixel driving circuits via the first protrusion and the second protrusion.

[0022] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a driving transistor and a second transistor, wherein a first electrode of the second transistor is connected to a gate electrode of the driving transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor;

[0023] The display panel further includes:

[0024] a first active layer located on one side of the base substrate, the first active layer comprising a third active portion, the third active portion being used to form a channel region of the driving transistor;

[0025] a first conductive layer, located on a side of the first active layer facing away from the base substrate, the first conductive layer comprising a first conductive portion, an orthographic projection of the first conductive portion on the base substrate covering an orthographic projection of the third active portion on the base substrate, and the first conductive portion being used to form a gate of the driving transistor;

[0026] a second active layer, located on a side of the first conductive layer facing away from the substrate, the second active layer comprising a second active portion, the second active portion being used to form a channel region of the second transistor;

[0027] a third conductive layer, located on a side of the second active layer facing away from the base substrate, the third conductive layer comprising a first gate line, an orthographic projection of the first gate line on the base substrate extending along a row direction and covering an orthographic projection of the second active portion on the base substrate, and a portion of the first gate line forming a top gate of the second transistor;

[0028] Wherein, the third conductive layer further includes the second initial signal line.

[0029] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a driving transistor and a first transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to a second electrode of the driving transistor;

[0030] The display panel includes a plurality of pixel driving circuit row groups, the plurality of pixel driving circuit row groups are distributed in a column direction, and two adjacent pixel driving circuit rows in different pixel driving circuit row groups share the same first initial signal line.

[0031] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0032] a first conductive portion, wherein the first conductive portion is used to form a gate of the driving transistor;

[0033] a first reset signal line, wherein an orthographic projection of the first reset signal line on the substrate extends along a row direction, and a portion of the first reset signal line is used to form a gate of the first transistor;

[0034] The orthographic projection of the first reset signal line on the base substrate is located on a side where the orthographic projection of the first conductive portion on the base substrate is away from the orthographic projection of the second reset signal line on the base substrate;

[0035] In two adjacent pixel driving circuit rows sharing the same first initial signal line, the orthographic projection of the first initial signal line on the substrate is at least partially located between the orthographic projections of the first reset signal lines in the two adjacent pixel driving circuit rows on the substrate.

[0036] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0037] a first active layer located on one side of the base substrate, the first active layer comprising a first active portion and a ninth active portion, the first active portion being used to form a channel region of the first transistor, and in two adjacent pixel driving circuit rows sharing the same first initial signal line, the ninth active portion being connected between two first active portions in the two adjacent pixel driving circuit rows;

[0038] The first initial signal line is connected to the ninth active portion through a via hole.

[0039] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a second transistor, a first electrode of the second transistor being connected to the gate electrode of the driving transistor, and a second electrode of the second transistor being connected to the second electrode of the driving transistor;

[0040] The display panel further includes:

[0041] a first active layer, located on one side of the base substrate, wherein at least a portion of the first active layer is used to form a channel region of the driving transistor;

[0042] a first conductive layer, located on a side of the first active layer facing away from the base substrate, wherein at least a portion of the first conductive layer is used to form a gate of the driving transistor;

[0043] a second active layer, located on a side of the first conductive layer facing away from the substrate, wherein at least a portion of the second active layer is used to form a channel region of the second transistor;

[0044] a third conductive layer, located on a side of the second active layer facing away from the substrate, wherein at least a portion of the third conductive layer is used to form a top gate of the second transistor;

[0045] The fourth conductive layer is located on a side of the third conductive layer away from the base substrate, and the fourth conductive layer includes the first initial signal line.

[0046] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a driving transistor and an eighth transistor, wherein a first electrode of the eighth transistor is connected to a third initial signal line, and a second electrode of the eighth transistor is connected to the first electrode of the driving transistor;

[0047] Two adjacent rows of pixel driving circuits in the same pixel driving circuit row group share the same third initial signal line.

[0048] In an exemplary embodiment of the present disclosure, the third initial signal line includes:

[0049] a second main body portion, wherein an orthographic projection of the second main body portion on the base substrate extends along a row direction;

[0050] a third raised portion;

[0051] a fourth protrusion, wherein the third protrusion and the fourth protrusion are respectively connected to two sides of the second main body in the column direction;

[0052] In the two pixel driving circuit rows that share the same third initial signal line, the second main body portion connects the two pixel driving circuit rows via the third protrusion and the fourth protrusion.

[0053] In an exemplary embodiment of the present disclosure, an orthographic projection of the third initial signal line on the substrate and an orthographic projection of the second initial signal line on the substrate at least partially overlap.

[0054] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a second transistor, a first electrode of the second transistor being connected to the gate electrode of the driving transistor, and a second electrode of the second transistor being connected to the second electrode of the driving transistor;

[0055] The display panel further includes:

[0056] a first active layer, located on one side of the base substrate, wherein at least a portion of the first active layer is used to form a channel region of the driving transistor;

[0057] a first conductive layer, located on a side of the first active layer facing away from the base substrate, wherein at least a portion of the first conductive layer is used to form a gate of the driving transistor;

[0058] a second active layer, located on a side of the first conductive layer facing away from the substrate, wherein at least a portion of the second active layer is used to form a channel region of the second transistor;

[0059] a third conductive layer, located on a side of the second active layer facing away from the substrate, wherein at least a portion of the third conductive layer is used to form a top gate of the second transistor;

[0060] Wherein, the third conductive layer includes the third initial signal line.

[0061] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a driving transistor and a second transistor, wherein a first electrode of the second transistor is connected to a gate electrode of the driving transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor;

[0062] The display panel further includes:

[0063] a first active layer, located on one side of the base substrate, wherein at least a portion of the first active layer is used to form a channel region of the driving transistor;

[0064] a first conductive layer, located on a side of the first active layer facing away from the base substrate, wherein at least a portion of the first conductive layer is used to form a gate of the driving transistor;

[0065] a second active layer, located on a side of the first conductive layer facing away from the substrate, wherein at least a portion of the second active layer is used to form a channel region of the second transistor;

[0066] a third conductive layer, located on a side of the second active layer facing away from the substrate, wherein at least a portion of the third conductive layer is used to form a top gate of the second transistor;

[0067] The third conductive layer further includes a first bridge portion, and the first bridge portion is connected to the gate of the driving transistor and the first electrode of the second transistor through via holes.

[0068] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a capacitor, a first electrode of the capacitor is connected to the gate of the driving transistor, and a second electrode of the capacitor is connected to the first power line;

[0069] The first conductive layer includes a first conductive portion, the first conductive portion is used to form a gate of the driving transistor, and the first conductive portion is multiplexed as a first electrode of the capacitor;

[0070] The display panel further includes:

[0071] a second conductive layer located between the third conductive layer and the first conductive layer, the second conductive layer comprising a second conductive portion, an orthographic projection of the second conductive portion on the base substrate at least partially overlapping with an orthographic projection of the first conductive portion on the base substrate, the second conductive portion being used to form a second electrode of the capacitor;

[0072] The first bridge portion includes a main portion and an extension portion, the main portion is connected to the gate of the driving transistor and the first electrode of the second transistor through a via, and the orthographic projection of the extension portion on the base substrate and the orthographic projection of the second conductive portion on the base substrate at least partially overlap;

[0073] The main body includes a first side, the extension includes a second side, the first side is connected to the second side, and an angle between an orthographic projection of the first side on the base substrate and an orthographic projection of the second side on the base substrate is less than 180°.

[0074] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a driving transistor and a second transistor, wherein a first electrode of the second transistor is connected to a gate electrode of the driving transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor;

[0075] The display panel further includes:

[0076] a first active layer, located on one side of the base substrate, wherein at least a portion of the first active layer is used to form a channel region of the driving transistor;

[0077] a first conductive layer, located on a side of the first active layer facing away from the base substrate, wherein at least a portion of the first conductive layer is used to form a gate of the driving transistor;

[0078] a second active layer, located on a side of the first conductive layer facing away from the substrate, wherein at least a portion of the second active layer is used to form a channel region of the second transistor;

[0079] a third conductive layer, located on a side of the second active layer facing away from the substrate, wherein at least a portion of the third conductive layer is used to form a top gate of the second transistor;

[0080] The third conductive layer further includes a second bridge portion, and the second bridge portion is connected to the second electrode of the second transistor and the second electrode of the driving transistor through via holes.

[0081] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a driving transistor, a second transistor, a fifth transistor, and an eighth transistor, wherein a first electrode of the second transistor is connected to a gate of the driving transistor, a second electrode of the second transistor is connected to a second electrode of the driving transistor, a first electrode of the fifth transistor is connected to a first power line, a second electrode of the fifth transistor is connected to the first electrode of the driving transistor, a first electrode of the eighth transistor is connected to a third initial signal line, and a second electrode of the eighth transistor is connected to the first electrode of the driving transistor;

[0082] The display panel further includes:

[0083] a first active layer, located on one side of the base substrate, wherein at least a portion of the first active layer is used to form a channel region of the driving transistor;

[0084] a first conductive layer, located on a side of the first active layer facing away from the base substrate, wherein at least a portion of the first conductive layer is used to form a gate of the driving transistor;

[0085] a second active layer, located on a side of the first conductive layer facing away from the substrate, wherein at least a portion of the second active layer is used to form a channel region of the second transistor;

[0086] a third conductive layer, located on a side of the second active layer facing away from the substrate, wherein at least a portion of the third conductive layer is used to form a top gate of the second transistor;

[0087] a third conductive layer, located on one side of the substrate, the third conductive layer comprising a first gate line, a portion of the first gate line being used to form a top gate of the second transistor;

[0088] The third conductive layer further includes a third bridge portion, and the third bridge portion is connected to the first electrode of the driving transistor, the second electrode of the fifth transistor, and the second electrode of the eighth transistor through via holes.

[0089] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a driving transistor and a second transistor, wherein a first electrode of the second transistor is connected to a gate electrode of the driving transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor;

[0090] The display panel further includes:

[0091] a third conductive layer, located on one side of the substrate, the third conductive layer comprising a first gate line, a portion of the first gate line being used to form a top gate of the second transistor;

[0092] A fourth conductive layer is located on a side of the third conductive layer away from the base substrate, the fourth conductive layer includes a first gate connection line, the orthographic projection of the first gate connection line on the base substrate extends along the row direction, and the first gate connection line is connected to the first gate line through one or more vias.

[0093] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a driving transistor, a second transistor, and a fourth transistor, wherein a first electrode of the second transistor is connected to a gate of the driving transistor, a second electrode of the second transistor is connected to a second electrode of the driving transistor, a first electrode of the fourth transistor is connected to a data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor;

[0094] The display panel further includes:

[0095] a first active layer located on one side of the base substrate, the first active layer comprising a fourth active portion, the fourth active portion being used to form a channel region of the fourth transistor;

[0096] a first conductive layer located on a side of the first conductive layer facing away from the base substrate, the first conductive layer comprising a second gate line, an orthographic projection of the second gate line on the base substrate covering an orthographic projection of the fourth active portion on the base substrate, and a portion of the second gate line forming a gate of the fourth transistor;

[0097] a second active layer, located on a side of the first conductive layer away from the substrate, wherein a portion of the second active layer is used to form a channel region of the second transistor;

[0098] a third conductive layer, located on a side of the second active layer facing away from the substrate, wherein a portion of the third conductive layer is used to form a top gate of the second transistor;

[0099] A fourth conductive layer is located on a side of the third conductive layer away from the base substrate, the fourth conductive layer includes a second gate connection line, the orthographic projection of the second gate connection line on the base substrate extends along the row direction, and the second gate connection line is connected to the second gate line through one or more vias.

[0100] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a driving transistor and a second transistor, wherein a first electrode of the second transistor is connected to a gate electrode of the driving transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor;

[0101] The display panel further includes:

[0102] a first active layer, located on one side of the base substrate, wherein at least a portion of the first active layer is used to form a channel region of the driving transistor;

[0103] a first conductive layer, located on a side of the first active layer facing away from the base substrate, wherein at least a portion of the first conductive layer is used to form a gate of the driving transistor;

[0104] a second active layer located on a side of the first conductive layer facing away from the base substrate, the second active layer comprising a second active portion, and a twentieth active portion and a twenty-first active portion connected to both ends of the second active portion in a row direction, the second active portion being used to form a channel region of the second transistor, the twentieth active portion being used to form a first electrode of the second transistor, and the twenty-first active portion being used to form a second electrode of the second transistor;

[0105] A third conductive layer is located on a side of the second active layer facing away from the base substrate, the third conductive layer includes a first gate line, the first gate line includes a third main body portion and a fifth protrusion portion connected to one side of the third main body portion in the column direction, the orthographic projection of the third main body portion on the base substrate extends along the row direction, and the orthographic projection of the fifth protrusion portion on the base substrate covers the orthographic projection of the second active portion on the base substrate.

[0106] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a driving transistor, a fourth transistor, and a fifth transistor, wherein a first electrode of the fifth transistor is connected to a first power line, a second electrode of the fifth transistor is connected to the first electrode of the driving transistor, a first electrode of the fourth transistor is connected to a data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor;

[0107] The display panel further includes:

[0108] a first active layer, the first active layer including a third active portion, a fourth active portion, and a fifth active portion, the third active portion being used to form a channel region of the driving transistor, the fourth active portion being used to form a channel region of the fourth transistor, and the fifth active portion being used to form a channel region of the fifth transistor;

[0109] a first conductive layer, located on a side of the first active layer facing away from the base substrate, the first conductive layer comprising a first conductive portion, a second gate line, and an enable signal line, an orthographic projection of the second gate line on the base substrate extending in a row direction and covering an orthographic projection of the fourth active portion on the base substrate, a portion of the second gate line being used to form a gate of the fourth transistor, an orthographic projection of the enable signal line on the base substrate extending in a row direction and covering an orthographic projection of the fifth active portion on the base substrate, and a portion of the enable signal line being used to form a gate of the fifth transistor;

[0110] Wherein, in the same pixel driving circuit, the orthographic projection of the second gate line on the base substrate is located between the orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the enable signal line on the base substrate.

[0111] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a driving transistor and a first transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to a second electrode of the driving transistor;

[0112] The display panel further includes:

[0113] a first active layer located on one side of the base substrate, the first active layer comprising a third active portion and a first active portion, the third active portion being used to form a channel region of the driving transistor, and the first active portion being used to form a channel region of the first transistor;

[0114] In the same pixel driving circuit, the first active portion and the third active portion are connected in the same layer.

[0115] In an exemplary embodiment of the present disclosure, orthographic projections of two adjacent pixel driving circuits in the same pixel driving circuit row on the substrate are at least partially mirror-symmetrically arranged about a second symmetry axis, and the second symmetry axis extends along a column direction.

[0116] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes:

[0117] driver transistors;

[0118] a first transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to a second electrode of the driving transistor;

[0119] a second transistor, wherein a first electrode of the second transistor is connected to the gate electrode of the driving transistor, and a second electrode of the second transistor is connected to the second electrode of the driving transistor;

[0120] a fourth transistor, wherein a first electrode of the fourth transistor is connected to the data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor;

[0121] a fifth transistor, wherein a first electrode of the fifth transistor is connected to the first power line, and a second electrode of the fifth transistor is connected to the first electrode of the driving transistor;

[0122] a sixth transistor, wherein a first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and a second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit;

[0123] an eighth transistor, wherein a first electrode of the eighth transistor is connected to the third initial signal line, and a second electrode of the eighth transistor is connected to the first electrode of the driving transistor;

[0124] a capacitor, wherein a first electrode of the capacitor is connected to the gate of the driving transistor, and a second electrode of the capacitor is connected to the first power line;

[0125] The first transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are P-type transistors, and the second transistor is an N-type transistor.

[0126] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0127] a first active layer located on one side of the base substrate, wherein at least a portion of the first active layer is used to form channel regions of the first transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor;

[0128] a first conductive layer, located on a side of the first active layer facing away from the base substrate, wherein at least a portion of the first conductive layer is used to form gates of the first transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor;

[0129] a second active layer, located on a side of the first conductive layer facing away from the substrate, wherein at least a portion of the second active layer is used to form a channel region of the second transistor;

[0130] The third conductive layer is located on a side of the second active layer away from the substrate. At least a portion of the structure of the third conductive layer is used to form a top gate of the second transistor.

[0131] According to one aspect of the present disclosure, a display device is provided, comprising the above-mentioned display panel.

[0132] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0133] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0134] FIG1 is a schematic structural diagram of an exemplary embodiment of a pixel driving circuit disclosed herein;

[0135] FIG2 is a timing diagram of some nodes in an exemplary embodiment of the pixel driving circuit shown in FIG1 ;

[0136] FIG3 is a schematic structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0137] FIG4 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0138] FIG5 is a structural diagram of the shielding layer in FIG4 ;

[0139] FIG6 is a structural diagram of the first active layer in FIG4 ;

[0140] FIG7 is a structural diagram of the first conductive layer in FIG4 ;

[0141] FIG8 is a structural diagram of the second conductive layer in FIG4 ;

[0142] FIG9 is a structural diagram of the second active layer in FIG4 ;

[0143] FIG10 is a structural diagram of the third conductive layer in FIG4 ;

[0144] FIG11 is a structural diagram of the fourth conductive layer in FIG4 ;

[0145] FIG12 is a structural diagram of the fifth conductive layer in FIG4;

[0146] FIG13 is a structural diagram of the shielding layer and the first active layer in FIG4 ;

[0147] FIG14 is a structural layout diagram of the shielding layer, the first active layer, and the first conductive layer in FIG4 ;

[0148] FIG15 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, and the second conductive layer in FIG4 ;

[0149] FIG16 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG4 ;

[0150] FIG17 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG4 ;

[0151] FIG18 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG4 ;

[0152] FIG19 is a partial cross-sectional view of the display panel shown in FIG4 taken along the dotted line CC;

[0153] FIG20 is an equivalent circuit diagram of another exemplary embodiment of a display panel according to the present disclosure;

[0154] FIG21 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0155] FIG22 is a structural diagram of the shielding layer in FIG21;

[0156] FIG23 is a structural layout diagram of the first active layer in FIG21;

[0157] FIG24 is a structural diagram of the first conductive layer in FIG21;

[0158] FIG25 is a structural diagram of the second conductive layer in FIG21;

[0159] FIG26 is a structural diagram of the second active layer in FIG21;

[0160] FIG27 is a structural diagram of the third conductive layer in FIG21;

[0161] FIG28 is a structural layout diagram of the fourth conductive layer in FIG21;

[0162] FIG29 is a structural layout diagram of the fifth conductive layer in FIG21;

[0163] FIG30 is a structural layout diagram of the shielding layer and the first active layer in FIG21;

[0164] FIG31 is a structural layout diagram of the shielding layer, the first active layer, and the first conductive layer in FIG21;

[0165] FIG32 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, and the second conductive layer in FIG21;

[0166] FIG33 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG21 ;

[0167] FIG34 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG21 ;

[0168] FIG35 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG21 ;

[0169] FIG36 is a partial cross-sectional view of the display panel shown in FIG21 taken along the dotted line CC;

[0170] FIG37 is a structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0171] FIG38 is a structural diagram of the shielding layer in FIG37 ;

[0172] FIG39 is a structural layout diagram of the first active layer in FIG37;

[0173] FIG40 is a structural layout diagram of the first conductive layer in FIG37;

[0174] FIG41 is a structural layout diagram of the second conductive layer in FIG37;

[0175] FIG42 is a structural layout diagram of the second active layer in FIG37;

[0176] FIG43 is a structural layout diagram of the third conductive layer in FIG37;

[0177] FIG44 is a structural layout diagram of the fourth conductive layer in FIG37;

[0178] FIG45 is a structural layout diagram of the fifth conductive layer in FIG37;

[0179] FIG46 is a structural layout diagram of the shielding layer and the first active layer in FIG37;

[0180] FIG47 is a structural layout diagram of the shielding layer, the first active layer, and the first conductive layer in FIG37;

[0181] FIG48 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, and the second conductive layer in FIG37 ;

[0182] FIG49 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG37 ;

[0183] FIG50 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG37 ;

[0184] FIG51 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG37 ;

[0185] FIG52 is a partial cross-sectional view of the display panel shown in FIG37 taken along the dotted line CC. DETAILED DESCRIPTION

[0186] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent like or similar structures, and thus their detailed description will be omitted.

[0187] The terms "a", "an", and "said" are used to indicate that there are one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0188] This exemplary embodiment first provides a pixel driving circuit, as shown in Figures 1 and 2. Figure 1 is a structural diagram of an exemplary embodiment of the pixel driving circuit disclosed in the present invention, and Figure 2 is a timing diagram of some nodes in an exemplary embodiment of the pixel driving circuit shown in Figure 1.

[0189] The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor C. A first electrode of the fourth transistor T4 is connected to the data signal terminal Da, a second electrode of the fourth transistor T4 is connected to the first electrode of the driving transistor T3, and a gate of the fourth transistor T4 is connected to the second gate driving signal terminal G2; a first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, a second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T3, and a gate of the fifth transistor T5 is connected to the enable signal terminal EM; a gate of the driving transistor T3 is connected to a node N; a first electrode of the second transistor T2 is connected to the node N, a second electrode of the second transistor T2 is connected to the second electrode of the driving transistor T3, and a gate of the second transistor T2 is connected to the first gate driving signal terminal G1; a first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, and a second electrode of the sixth transistor T6 is connected to the seventh transistor T8. The second electrode of transistor T7 and the gate of the sixth transistor T6 are connected to the enable signal terminal EM, the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate of the seventh transistor T7 is connected to the second reset signal terminal Re2; the first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1, the second electrode of the first transistor T1 is connected to the second electrode of the driving transistor T3, and the gate of the first transistor T1 is connected to the first reset signal terminal Re1; the first electrode of the eighth transistor T8 is connected to the third initial signal terminal Vinit3, the second electrode of the eighth transistor T8 is connected to the first electrode of the driving transistor T3, and the gate of the eighth transistor T8 is connected to the second reset signal terminal Re2; the first electrode of the capacitor C is connected to the node N, and the second electrode of the capacitor C is connected to the first power supply terminal VDD. This pixel driving circuit can be used to drive a light-emitting unit OLED. The first electrode of the light-emitting unit OLED can be connected to the second electrode of the sixth transistor T6, and the second electrode of the light-emitting unit can be connected to the second power supply terminal VSS. The first electrode of the light-emitting unit can be the anode of the light-emitting unit, and the second electrode of the light-emitting unit can be the cathode of the light-emitting unit. The second transistor T2 may be an N-type transistor, for example, an N-type metal oxide transistor. N-type transistors have a relatively low leakage current, thereby preventing leakage of power from the node N through the second transistor T2 during the light-emitting phase. Meanwhile, the first transistor T1, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be P-type transistors, for example, P-type low-temperature polysilicon transistors. P-type transistors have a relatively high carrier mobility, thereby facilitating the realization of display panels with high resolution, high response speed, high pixel density, and high aperture ratio.The first initial signal terminal, the second initial signal terminal, and the third initial signal terminal can output the same or different voltage signals according to actual conditions.

[0190] As shown in Figure 2, where G1 represents the timing of the first gate drive signal terminal G1, G2 represents the timing of the second gate drive signal terminal G2, Re2 represents the timing of the second reset signal terminal Re2, Re1 represents the timing of the first reset signal terminal Re1, and EM represents the timing of the enable signal terminal EM, a driving cycle of the pixel driving circuit may include a first reset phase t1, a second reset phase t2, a data writing phase t3, a third reset phase t5, and a light-emitting phase t6.

[0191] During the first reset phase t1, the second reset signal terminal Re2 outputs a low-level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal terminal Vinit2 inputs a second initial signal to the first electrode of the light-emitting unit OLED, and the third initial signal terminal Vinit3 inputs a third initial signal to the first electrode of the driving transistor T3 to improve the hysteresis problem of the driving transistor T3. During the second reset phase t2, the first gate drive signal terminal G1 outputs a high-level signal, the first reset signal terminal Re1 outputs a low-level signal, the first transistor T1 and the second transistor T2 are turned on, and the first initial signal terminal Vinit1 inputs the first initial signal to the node N through the first transistor T1 and the second transistor T2. During the data writing phase t3, the second gate drive signal terminal G2 outputs a low-level signal, the first gate drive signal terminal G1 outputs a high-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal terminal Da writes the compensation voltage Vdata+Vth to the node N through the fourth transistor T4 and the second transistor T2, where Vdata is the voltage of the data signal on the data signal terminal and Vth is the threshold voltage of the driving transistor T3. In the third reset phase t5: the second reset signal terminal RE2 outputs a low-level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal terminal Vinit2 inputs the second initial signal to the first electrode of the light-emitting unit OLED, and the third initial signal terminal Vinit3 inputs the third initial signal to the first electrode of the driving transistor T3. In the light-emitting phase t6: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the compensation voltage Vdata + Vth stored in the capacitor C. The output current formula of the driving transistor is as follows: I = (μWCox / 2L)(Vgs-Vth) 2

[0192] Where I is the output current of the driver transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driver transistor channel, L is the length of the driver transistor channel, Vgs is the gate-source voltage difference of the driver transistor, and Vth is the threshold voltage of the driver transistor. The output current of the driver transistor in the above pixel driving circuit is I = (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0193] It should be understood that in other exemplary embodiments, the pixel driving circuit may also have other driving methods. For example, in the third reset stage t5, the second reset signal terminal Re2 may not output a low-level pulse signal. For another example, in the light-emitting stage t6, the enable signal terminal EM may also output multiple low-level pulse signals.

[0194] FIG3 is a schematic structural diagram of an exemplary embodiment of a display panel according to the present disclosure. The display panel includes: a substrate, a pixel driving circuit row group CP, and a light-emitting unit OLED. The pixel driving circuit row group CP includes two adjacent pixel driving circuit rows PH in the column direction. The pixel driving circuit row PH includes a plurality of pixel driving circuits Pix distributed in the row direction X. The pixel driving circuit Pix is ​​used to drive the light-emitting unit OLED. The pixel driving circuit Pix includes a seventh transistor T7. A first electrode of the seventh transistor T7 is connected to a second initial signal line Vinit2. A second electrode of the seventh transistor T7 is connected to a first electrode of the light-emitting unit OLED. A gate of the seventh transistor T7 is formed by a portion of a second reset signal line. The orthographic projection of the second reset signal line on the substrate extends along the row direction X. The orthographic projections of two adjacent pixel driving circuit rows PH in the same pixel driving circuit row group CP on the substrate are mirror-symmetrically arranged about a first symmetry axis, which extends along the row direction X. The two adjacent pixel driving circuit rows in the same pixel driving circuit row group CP share the same second initial signal line Vinit2.

[0195] The display panel provided by this exemplary embodiment utilizes mirror-symmetric arrangement of two adjacent pixel driver circuit rows within the same pixel driver circuit row group CP, thereby improving the display panel's integration. Furthermore, in this exemplary embodiment, two adjacent pixel driver circuit rows PH within the same pixel driver circuit row group CP can share the same second initial signal line Vinit2. This arrangement can reduce the number of traces and vias in the display panel, thereby improving the display panel's manufacturing yield.

[0196] In this exemplary embodiment, the second initial signal line Vinit2 may form a first symmetry axis, that is, the orthographic projections of two adjacent pixel driving circuit rows PH in the same pixel driving circuit row group CP on the substrate are mirror-symmetrically arranged about the second initial signal line Vinit2.

[0197] As shown in Figure 3, the pixel driving circuit also includes a driving transistor T3 and a first transistor T1. The first electrode of the first transistor T1 is connected to the first initial signal line Vinit1, and the second electrode of the first transistor T1 is connected to the second electrode of the driving transistor T3. The display panel includes multiple rows of pixel driving circuit row groups CP. The multiple rows of pixel driving circuit row groups CP are distributed in the column direction Y. Two adjacent pixel driving circuit rows PH located in different pixel driving circuit row groups CP share the same first initial signal line Vinit1.

[0198] In this exemplary embodiment, two adjacent pixel driving circuit rows PH located in different pixel driving circuit row groups CP share the same first initial signal line Vinit1. This setting can also reduce the number of wirings and vias in the display panel, thereby improving the manufacturing yield of the display panel.

[0199] As shown in FIG3 , the structure of the pixel driving circuit Pix may be as shown in FIG1 . Accordingly, the second initial signal line Vinit2 may be used to provide the second initial signal terminal in FIG1 , and the first initial signal line Vinit1 may be used to provide the first initial signal terminal in FIG1 .

[0200] 3 , the orthographic projections of two adjacent pixel driving circuits Pix in the same pixel driving circuit row PH on the substrate may be mirror-symmetric about a second symmetry axis extending along the column direction Y. This arrangement can also improve the integration of the display panel.

[0201] Furthermore, in other exemplary embodiments, the orthographic projections of two adjacent pixel driving circuit rows PH in the same pixel driving circuit row group CP on the substrate may also be partially mirror-symmetrically arranged about the first symmetry axis. Similarly, the orthographic projections of two adjacent pixel driving circuits Pix in the same pixel driving circuit row PH on the substrate may also be at least partially mirror-symmetrically arranged about the second symmetry axis.

[0202] In this exemplary embodiment, the display panel shown in FIG3 may include a base substrate, a blocking layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer stacked in sequence. Among them, an insulating layer may be provided between the above-mentioned adjacent layers. As shown in FIG4-18, FIG4 is a structural layout diagram of an exemplary embodiment of the display panel disclosed in the present invention, FIG5 is a structural layout diagram of the blocking layer in FIG4, FIG6 is a structural layout diagram of the first active layer in FIG4, FIG7 is a structural layout diagram of the first conductive layer in FIG4, FIG8 is a structural layout diagram of the second conductive layer in FIG4, FIG9 is a structural layout diagram of the second active layer in FIG4, FIG10 is a structural layout diagram of the third conductive layer in FIG4, FIG11 is a structural layout diagram of the fourth conductive layer in FIG4, FIG12 is a structural layout diagram of the fifth conductive layer in FIG4, FIG13 is a structural layout diagram of the blocking layer and the first active layer in FIG4, and FIG14 is Figure 4 is the structural layout of the blocking layer, the first active layer, and the first conductive layer. Figure 15 is the structural layout of the blocking layer, the first active layer, the first conductive layer, and the second conductive layer in Figure 4. Figure 16 is the structural layout of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in Figure 4. Figure 17 is the structural layout of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in Figure 4. Figure 18 is the structural layout of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in Figure 4.

[0203] As shown in Figure 4-18, the orthographic projections of two adjacent rows of pixel driving circuits PH in the same pixel driving circuit row group CP on the substrate are at least partially mirror-symmetrically arranged about the first symmetry axis AA; the orthographic projections of two adjacent rows of pixel driving circuits in the same pixel driving circuit row PH on the substrate are at least partially mirror-symmetrically arranged about the second symmetry axis BB.

[0204] 4 , 5 , and 13 , the shielding layer may include a plurality of shielding portions 81 , which are distributed in an array in the row direction X and the column direction Y. It should be understood that in other exemplary embodiments, the display panel may not include a shielding layer.

[0205] As shown in Figures 4, 6, 13 and 14, the first active layer may include: a first active portion 71, a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, a seventh active portion 77, an eighth active portion 78, a ninth active portion 79, a tenth active portion 710, an eleventh active portion 711, a twelfth active portion 712, a thirteenth active portion 713, a fourteenth active portion 714, a fifteenth active portion 715, a sixteenth active portion 716, a seventeenth active portion 717, an eighteenth active portion 718 and a nineteenth active portion 719. The first active portion 71 is used to form the channel region of the first transistor T1; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 can be used to form the channel region of the eighth transistor T8; the ninth active portion 79 is connected to the end of the first active portion 71 away from the third active portion 73, and in two adjacent pixel driving circuit rows sharing the same first initial signal line Vinit1, the ninth active portion 79 is connected to the two adjacent pixel driving circuit rows. The first active portion 71 is connected to the first active portion 71; the tenth active portion 710 is connected between the first active portion 71 and the third active portion 73; the eleventh active portion 711 is connected between the third active portion 73 and the fourth active portion 74; the twelfth active portion 712 is connected to the end of the fourth active portion 74 away from the third active portion 73; the thirteenth active portion 713 is connected to the end of the sixth active portion away from the seventh active portion 77; the fourteenth active portion 714 is connected between the sixth active portion 76 and the seventh active portion 77; the fifteenth active portion 715 is connected to the end of the seventh active portion 77 away from the sixth active portion 76; the sixteenth active portion 716 and the seventeenth active portion 717 are connected to both ends of the fifth active portion 75; the eighteenth active portion 718 and the nineteenth active portion 719 are connected to both ends of the eighth active portion 78. In this exemplary embodiment, the first active layer can be formed of polysilicon material, and accordingly, the first transistor T1, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type low-temperature polysilicon thin film transistors.

[0206] In this exemplary embodiment, as shown in Figures 4, 6, 13, and 14, the third active portion 73 is "L"-shaped. It should be understood that in other exemplary embodiments, the third active portion 73 can also be other shapes. For example, the third active portion 73 can also be "J"-shaped, "I"-shaped, etc.

[0207] It should be noted that in other exemplary embodiments, adjacent shielding portions 81 in the row direction X can be connected by connecting portions located in the shielding layer, and adjacent shielding portions 81 in the column direction Y can be connected by connecting portions located in the shielding layer. This arrangement can form a grid structure of the shielding layer. The shielding layer can also be connected to a stable power supply terminal. For example, the shielding layer can be connected to stable voltage terminals such as the first power supply terminal VDD, the first initial signal terminal Vinit1, the second initial signal terminal Vinit2, and the third initial signal terminal Vinit3 in Figure 1. The shielding portion 81 can shield the noise influence of other signals on the driving transistor T3.

[0208] As shown in Figures 4, 7, and 14, the first conductive layer may include: a first conductive portion 11, a second gate line G2, an enable signal line EM, a first reset signal line Re1, and a second reset signal line Re2. The second gate line G2 can be used to provide the second gate drive signal terminal in Figure 1; the enable signal line EM can be used to provide the enable signal terminal in Figure 1; the first reset signal line Re1 can be used to provide the first reset signal terminal in Figure 1; and the second reset signal line Re2 can be used to provide the second reset signal terminal in Figure 1. The orthographic projection of the second gate line G2 on the base substrate, the orthographic projection of the enable signal line EM on the base substrate, the orthographic projection of the first reset signal line Re1 on the base substrate, and the orthographic projection of the second reset signal line Re2 on the base substrate can all extend along the row direction X. The orthographic projection of the second gate line G2 on the base substrate covers the orthographic projection of the fourth active portion 74 on the base substrate, and a portion of the structure of the second gate line G2 is used to form the gate of the fourth transistor T4. The orthographic projection of the enable signal line EM on the substrate overlaps the orthographic projection of the fifth active portion 75 and the orthographic projection of the sixth active portion 76 on the substrate. Portions of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the first reset signal line Re1 on the substrate overlaps the orthographic projection of the first active portion 71 on the substrate. Portions of the first reset signal line Re1 can be used to form the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 on the substrate overlaps the orthographic projection of the seventh active portion 77 and the orthographic projection of the eighth active portion 78 on the substrate. Portions of the second reset signal line Re2 can be used to form the gates of the seventh transistor T7 and the eighth transistor T8, respectively. The orthographic projection of the first conductive portion 11 on the substrate overlaps the orthographic projection of the third active portion 73 on the substrate. The first conductive portion 11 can be used to form the gate of the drive transistor T3 and can also serve as the first electrode of the capacitor C. In the same pixel driving circuit, the orthographic projection of the first conductive portion 11 on the substrate is located between the orthographic projection of the first reset signal line Re1 on the substrate and the orthographic projection of the second gate line G2 on the substrate. The orthographic projection of the enable signal line EM on the substrate is located on a side of the orthographic projection of the second gate line G2 on the substrate away from the orthographic projection of the first conductive portion 11 on the substrate. The orthographic projection of the second reset signal line Re2 on the substrate is located on a side of the orthographic projection of the enable signal line EM on the substrate away from the orthographic projection of the first conductive portion 11 on the substrate. The display panel can use the first conductive layer as a mask to perform conductor processing on the first active layer, that is, the area of ​​the first active layer covered by the first conductive layer can form the channel region of the transistor, and the area of ​​the first active layer not covered by the first conductive layer forms a conductor structure.

[0209] As shown in Figures 4, 8, and 15, the second conductive layer may include: a third gate line 2G1, a second conductive portion 22, and a third initial signal line Vinit3. The orthographic projection of the third gate line 2G1 on the substrate extends along the row direction X, and the third gate line 2G1 can be used to provide the first gate drive signal terminal in Figure 1. The orthographic projection of the second conductive portion 22 on the substrate can at least partially overlap with the orthographic projection of the first conductive portion 11 on the substrate, and the second conductive portion 22 is used to form the second electrode of the capacitor C. The second conductive layer may also include a second connecting portion 23, and adjacent second conductive portions 22 in the row direction X can be connected via the second connecting portion 23. The third initial signal line Vinit3 can be used to provide the third initial signal terminal Vinit3 in Figure 1, and the orthographic projection of the third initial signal line Vinit3 on the substrate can extend along the row direction X. The orthographic projection of the third initial signal line Vinit3 on the substrate is located between the orthographic projection of the second reset signal line Re2 in the pixel drive circuit of the current row and the orthographic projection of the second reset signal line Re2 in the pixel drive circuit of the next adjacent row on the substrate. This configuration can reduce the parasitic capacitance between the third initial signal line Vinit3 and the enable signal line EM, the second conductive portion 22 and other structures, thereby improving the display effect of the display panel.

[0210] As shown in Figures 4, 9, and 16, the second active layer may include an active portion 9, and the active portion 9 may include: a second active portion 92, a twentieth active portion 920 connected to both ends of the second active portion 92, and a twenty-first active portion 921. The second active portion 92 is used to form the channel region of the second transistor T2. The second active layer can be formed of indium gallium zinc oxide, and accordingly, the second transistor T2 can be an N-type metal oxide thin film transistor. The orthographic projection of the third gate line 2G1 on the base substrate can cover the orthographic projection of the second active portion 92 on the base substrate, and a partial structure of the third gate line 2G1 can be used to form the bottom gate of the second transistor T2. In addition, the twentieth active portion 920, the second active portion 92, and the twenty-first active portion 921 can be distributed in the row direction X.

[0211] As shown in Figures 4, 10, and 17, the third conductive layer may include a first gate line 3G1 and a second initial signal line Vinit2. The orthographic projection of the first gate line 3G1 on the base substrate and the orthographic projection of the second initial signal line Vinit2 on the base substrate may both extend along the row direction X. The first gate line 3G1 may be used to provide the first gate drive signal terminal in Figure 1. The first gate line 3G1 includes a third main portion 3G13 and a fifth raised portion 3G15 connected to one side of the third main portion 3G13 in the column direction. The orthographic projection of the third main portion 3G13 on the base substrate extends along the row direction X. The orthographic projection of the fifth raised portion 3G15 on the base substrate covers the orthographic projection of the second active portion 92 on the base substrate. Part of the structure of the fifth raised portion 3G15 may be used to form the top gate of the second transistor T2. At the same time, the first gate line 3G1 may be connected to the third gate line 2G1 through a via located in the frame area of ​​the display panel. The second initial signal line Vinit2 may be used to provide the second initial signal terminal in Figure 1. As shown in Figures 4, 10, and 17, two adjacent rows of pixel driver circuit rows PH in the same pixel driver circuit row group CP can share the same second initial signal line Vinit2. The orthographic projection of the second initial signal line Vinit2 on the substrate substrate is at least partially located between the orthographic projections of two adjacent third initial signal lines Vinit3 in the same pixel driver circuit row group CP on the substrate substrate. This arrangement can reduce the parasitic cell between the third initial signal line Vinit3 and the second initial signal line Vinit2 by reducing the overlapping area between the third initial signal line Vinit3 and the second initial signal line Vinit2, thereby reducing signal interference between the third initial signal line Vinit3 and the second initial signal line Vinit2. As shown in Figures 4, 10, and 17, the second initial signal line Vinit2 can include a first main portion Vinit21, a first raised portion Vinit221, and a second raised portion Vinit222. The first raised portion Vinit221 and the second raised portion Vinit222 are respectively connected to both sides of the first main portion Vinit21 in the column direction Y. The orthographic projection of the first main portion Vinit21 on the substrate can extend along the row direction X and be located between the orthographic projections of two adjacent third initial signal lines Vinit3 in the same pixel driver circuit row group CP. In two pixel driver circuit rows that share the same second initial signal line Vinit2, the first main portion Vinit21 connects the two pixel driver circuit rows via the first raised portion Vinit221 and the second raised portion Vinit222.

[0212] In addition, the display panel can use the third conductive layer as a mask to conduct the second active layer, that is, the area of ​​the second active layer covered by the third conductive layer can form the channel region of the transistor, and the area of ​​the second active layer not covered by the third conductive layer forms a conductor structure.

[0213] As shown in Figures 4, 11, and 18, the fourth conductive layer may include a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, a seventh bridge portion 47, an eighth bridge portion 48, a ninth bridge portion 49, a first initial signal line Vinit1, and a first fan-out line FIPH. The first bridge portion 41 may be connected to the twentieth active portion 720 and the first conductive portion 11 through vias, respectively, to connect the first electrode of the second transistor T2 and the gate of the driving transistor T3. The second bridge portion 42 may be connected to the twenty-first active portion 721, the tenth active portion 710, and the thirteenth active portion 713 through vias, respectively, to connect the second electrode of the second transistor T2, the second electrode of the first transistor T1, and the first electrode of the sixth transistor T6. The third bridge portion 43 can be connected to the eleventh active portion 711, the sixteenth active portion 716, and the eighteenth active portion 718 through vias, respectively, to connect the second electrode of the fourth transistor T4, the second electrode of the eighth transistor T8, the second electrode of the fifth transistor T5, and the first electrode of the driving transistor T3. The fourth bridge portion 44 can be connected to the twelfth active portion 712 through a via to connect the first electrode of the fourth transistor T4. The fifth bridge portion 45 can be connected to the seventeenth active portion 717 through a via to connect the first electrode of the fifth transistor. The sixth bridge portion 46 can be connected to the nineteenth active portion 719 and the third initial signal line Vinit3 through vias, respectively, to connect the first electrode of the eighth transistor T8 and the third initial signal terminal. The seventh bridge portion 47 can be connected to the fourteenth active portion 714 through a via to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The eighth bridge portion 48 can be connected to the second initial signal line Vinit2 and the fifteenth active portion 715 through vias, thereby connecting the first electrode and the second initial signal terminal of the seventh transistor T7. The ninth bridge portion 49 is connected to two adjacent second conductive portions 22 in the row direction X through vias to reduce the resistance of the second conductive portions 22 in the row direction X.

[0214] The first initial signal line Vinit1 can be used to provide the first initial signal terminal shown in Figure 1. The orthographic projection of the first initial signal line Vinit1 on the substrate extends along the row direction X. Furthermore, in the same pixel driving circuit, the orthographic projection of the first initial signal line Vinit1 on the substrate is located on a side of the orthographic projection of the first reset signal line Re1 on the substrate that is away from the orthographic projection of the first conductive portion 11 on the substrate. This arrangement can reduce the parasitic capacitance of the first initial signal line Vinit1 and other AC signal lines, such as the enable signal line EM and the first reset signal line Re1, thereby improving the voltage stability of the first initial signal line Vinit1. An AC signal line is a signal line that outputs an AC signal.

[0215] In this exemplary embodiment, as shown in Figures 4, 11, and 18, two adjacent pixel driving circuit rows PH located in different pixel driving circuit row groups CP share the same first initial signal line Vinit1. This setting can also reduce the number of wirings and vias in the display panel, thereby improving the manufacturing yield of the display panel.

[0216] As shown in Figures 4, 11 and 18, the orthographic projection of the first fan-out line FIPH on the substrate can extend along the row direction X. The first fan-out line FIPH can be used as a row direction fan-out line connecting the data line in the FIP (Fanout In Pixel).

[0217] In this exemplary embodiment, the square resistance of the fourth conductive layer can be smaller than the square resistance of the first conductive layer, the second conductive layer, and the third conductive layer. In this exemplary embodiment, the first initial signal line Vinit1 is set in the fourth conductive layer. This setting can reduce the voltage difference of the first initial signal line Vinit1 at different positions of the display panel, thereby improving the display uniformity of the display panel.

[0218] As shown in Figures 4 and 12, the fifth conductive layer may include a tenth bridge portion 510, a data line Da, a first power line VDD, and a second fan-out line FIPV. The orthographic projection of the data line Da on the base substrate, the orthographic projection of the first power line VDD on the base substrate, and the orthographic projection of the second fan-out line FIPV on the base substrate may all extend along the column direction Y. The data line Da is used to provide the data signal terminal shown in Figure 1, and the first power line VDD is used to provide the first power terminal shown in Figure 1. The data line Da may be connected to the fourth bridge portion 44 via a via to connect the data signal terminal to the first electrode of the fourth transistor T4. There may be multiple first power lines VDD, and the orthographic projections of the multiple first power lines VDD on the base substrate extend along the column direction Y and are spaced apart along the row direction X. The first power line VDD may be connected to the ninth bridge portion 49, which intersects with its orthographic projection on the base substrate, via a via. The first power line VDD, the second conductive portion connected in the row direction X, and the ninth bridge portion 49 can form a grid structure. This arrangement can reduce voltage differences on the first power line at different locations on the display panel, thereby improving the display uniformity of the display panel. In addition, the first power line VDD can also be connected to the fifth bridge portion 45 through a via to connect the first power terminal and the first electrode of the fifth transistor T5.

[0219] The second fan-out line FIPV can be used as a column-direction fan-out line connecting the data line in the FIP (Fanout In Pixel, fan-out area in the pixel). A first fan-out line and a second fan-out line can also be provided in the non-fan-out area of ​​the display panel, and in the non-fan-out area, the second fan-out line FIPV can be connected to the first fan-out line FIPH whose orthographic projection on the substrate intersects with the second fan-out line FIPV through a via. The first fan-out line FIPH and the second fan-out line FIPV can form a grid structure, which can be connected to the common electrode layer in the display panel through a via. The common electrode layer can serve as the second electrode of the light-emitting unit. This arrangement can reduce the resistance of the common electrode layer, thereby reducing the voltage difference of the common electrode layer at different positions of the display panel, thereby improving the display uniformity of the display panel.

[0220] The tenth bridge portion 510 can be connected to the seventh bridge portion 47 through a via hole to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The tenth bridge portion 510 can also be connected to the pixel electrode in the pixel electrode layer through a via hole. The pixel electrode layer can be located on the side of the fifth conductive layer away from the base substrate. The pixel electrode can be used to form the first electrode of the light-emitting unit.

[0221] As shown in FIG19 , a partial cross-sectional view of the display panel shown in FIG4 taken along the dotted line CC is shown. The display panel may further include a first insulating layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a fifth insulating layer 105, a first dielectric layer 106, and a first planar layer 108. The base substrate 100, the shielding layer, the first insulating layer 101, the first active layer, the second insulating layer 102, the first conductive layer, the third insulating layer 103, the second conductive layer, the fourth insulating layer 104, the second active layer, the fifth insulating layer 105, the third conductive layer, the first dielectric layer 106, the fourth conductive layer, the first planar layer 108, and the fifth conductive layer are stacked in sequence. The first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be a single-layer structure or a multi-layer structure. The material of the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride. The first dielectric layer 106 can be a silicon nitride layer. The material of the first planar layer 108 can be an organic material, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), etc. The base substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence. The barrier layer can be an inorganic material. The material of the first conductive layer, the second conductive layer, and the third conductive layer can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a laminated conductive layer. The fourth and fifth conductive layers may be made of metal materials, such as molybdenum, aluminum, copper, titanium, or niobium, or an alloy thereof, or a molybdenum / titanium alloy or laminate, or a titanium / aluminum / titanium laminate. The square resistance of any of the fourth and fifth conductive layers may be less than the square resistance of any of the first, second, and third conductive layers.

[0222] In addition, the display panel may further include a pixel electrode layer located on the side of the fifth conductive layer facing away from the substrate, a light-emitting unit layer located on the side of the pixel electrode layer facing away from the substrate, and a common electrode layer located on the side of the light-emitting unit layer facing away from the substrate. The light-emitting unit layer may include a light-emitting material layer, a hole transport layer and an electron transport layer located on both sides of the light-emitting material layer, an electron injection layer located on the side of the electron transport layer away from the light-emitting material layer, and a hole injection layer located on the side of the hole transport layer away from the light-emitting material layer. Holes generated at the anode enter the light-emitting material layer through the hole injection layer and the hole transport layer, and electrons generated at the cathode enter the light-emitting material layer through the electron injection layer and the electron transport layer. When the electrons and holes meet in the light-emitting material layer, energy excitons are generated, thereby exciting light-emitting molecules in the light-emitting material layer to produce visible light.

[0223] FIG20 is an equivalent circuit diagram of another exemplary embodiment of a display panel according to the present disclosure. Compared to the display panel shown in FIG3 , the display panel shown in FIG20 also includes: a substrate, a pixel driving circuit row group CP, and a light-emitting unit OLED. The pixel driving circuit row group CP includes two adjacent pixel driving circuit rows PH in the column direction. The pixel driving circuit row PH includes a plurality of pixel driving circuits Pix distributed in the row direction X. The pixel driving circuit Pix is ​​used to drive the light-emitting unit OLED. The pixel driving circuit Pix includes a seventh transistor T7. A first electrode of the seventh transistor T7 is connected to a second initial signal line Vinit2. A second electrode of the seventh transistor T7 is connected to a first electrode of the light-emitting unit OLED. A gate of the seventh transistor T7 is formed by a portion of a second reset signal line. The orthogonal projection of the second reset signal line on the substrate extends along the row direction X. The orthogonal projections of two adjacent pixel driving circuit rows PH in the same pixel driving circuit row group CP on the substrate are mirror-symmetrically arranged about a first symmetry axis, which extends along the row direction X. The two adjacent pixel driving circuit rows in the same pixel driving circuit row group CP share the same second initial signal line Vinit2.

[0224] In this exemplary embodiment, the second initial signal line Vinit2 may form a first symmetry axis, that is, the orthographic projections of two adjacent pixel driving circuit rows PH in the same pixel driving circuit row group CP on the substrate are mirror-symmetrically arranged about the second initial signal line Vinit2.

[0225] As shown in Figure 20, the pixel driving circuit also includes a driving transistor T3 and a first transistor T1. The first electrode of the first transistor T1 is connected to the first initial signal line Vinit1, and the second electrode of the first transistor T1 is connected to the second electrode of the driving transistor T3. The display panel includes multiple rows of pixel driving circuit row groups CP, and the multiple rows of pixel driving circuit row groups CP are distributed in the column direction Y. Two adjacent pixel driving circuit rows PH located in different pixel driving circuit row groups CP share the same first initial signal line Vinit1.

[0226] As shown in FIG20 , the structure of the pixel driving circuit Pix may be as shown in FIG1 . Accordingly, the second initial signal line Vinit2 may be used to provide the second initial signal terminal in FIG1 , and the first initial signal line Vinit1 may be used to provide the first initial signal terminal in FIG1 .

[0227] As shown in FIG20 , the orthographic projections of two adjacent pixel driving circuits Pix in the same pixel driving circuit row PH on the substrate may be mirror-symmetric about a second symmetry axis extending along the column direction Y. This arrangement may also improve the integration of the display panel.

[0228] As shown in Figure 20, two adjacent pixel driving circuit rows PH in the same pixel driving circuit row group CP can share the same third initial signal line. This setting can reduce the number of wiring and vias in the display panel, thereby improving the manufacturing yield of the display panel.

[0229] It should be understood that in other exemplary embodiments, the pixel driving circuit Pix may also have other structures. For example, the pixel driving circuit Pix may not include the eighth transistor T8. For another example, one or more of the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be N-type transistors, and the second transistor T2 may be a P-type transistor. For another example, the second electrode of the first transistor T1 may be directly connected to the node N.

[0230] Furthermore, in other exemplary embodiments, the orthographic projections of two adjacent pixel driving circuit rows PH in the same pixel driving circuit row group CP on the substrate may also be partially mirror-symmetrically arranged about the first symmetry axis. Similarly, the orthographic projections of two adjacent pixel driving circuits Pix in the same pixel driving circuit row PH on the substrate may also be at least partially mirror-symmetrically arranged about the second symmetry axis.

[0231] The display panel shown in Figure 20 may include a base substrate, a blocking layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer stacked in sequence. Among them, an insulating layer may be provided between the above-mentioned adjacent layers. As shown in Figures 21-35, Figure 21 is a structural layout of an exemplary embodiment of the display panel disclosed herein, Figure 22 is a structural layout of the blocking layer in Figure 21, Figure 23 is a structural layout of the first active layer in Figure 21, Figure 24 is a structural layout of the first conductive layer in Figure 21, Figure 25 is a structural layout of the second conductive layer in Figure 21, Figure 26 is a structural layout of the second active layer in Figure 21, Figure 27 is a structural layout of the third conductive layer in Figure 21, Figure 28 is a structural layout of the fourth conductive layer in Figure 21, Figure 29 is a structural layout of the fifth conductive layer in Figure 21, and Figure 30 is a structural layout of the blocking layer and the first active layer in Figure 21. Figure 31 is the structural layout of the blocking layer, the first active layer, and the first conductive layer in Figure 21, Figure 32 is the structural layout of the blocking layer, the first active layer, the first conductive layer, and the second conductive layer in Figure 21, Figure 33 is the structural layout of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in Figure 21, Figure 34 is the structural layout of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in Figure 21, and Figure 35 is the structural layout of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in Figure 21.

[0232] As shown in Figures 21-35, the orthographic projections of two adjacent rows of pixel driving circuits PH in the same pixel driving circuit row group CP on the substrate can be at least partially mirror-symmetrically arranged about the first symmetry axis AA; the orthographic projections of two adjacent rows of pixel driving circuits in the same pixel driving circuit row PH on the substrate can be at least partially mirror-symmetrically arranged about the second symmetry axis BB.

[0233] 21 , 22 , and 30 , the shielding layer may include a plurality of shielding portions 81 , which are distributed in an array in the row direction X and the column direction Y. It should be understood that in other exemplary embodiments, the display panel may not include a shielding layer.

[0234] As shown in Figures 21, 23, 31 and 32, the first active layer may include: a first active portion 71, a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, a seventh active portion 77, an eighth active portion 78, a ninth active portion 79, a tenth active portion 710, an eleventh active portion 711, a twelfth active portion 712, a thirteenth active portion 713, a fourteenth active portion 714, a fifteenth active portion 715, a sixteenth active portion 716, a seventeenth active portion 717, an eighteenth active portion 718 and a nineteenth active portion 719. The first active portion 71 is used to form the channel region of the first transistor T1; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 can be used to form the channel region of the eighth transistor T8; the ninth active portion 79 is connected to the end of the first active portion 71 away from the third active portion 73, and in two adjacent pixel driving circuit rows sharing the same first initial signal line Vinit1, the ninth active portion 79 is connected to the two adjacent pixel driving circuit rows. The first active portion 71 is connected to the first active portion 71; the tenth active portion 710 is connected between the first active portion 71 and the third active portion 73; the eleventh active portion 711 is connected between the third active portion 73 and the fourth active portion 74; the twelfth active portion 712 is connected to the end of the fourth active portion 74 away from the third active portion 73; the thirteenth active portion 713 is connected to the end of the sixth active portion away from the seventh active portion 77; the fourteenth active portion 714 is connected between the sixth active portion 76 and the seventh active portion 77; the fifteenth active portion 715 is connected to the end of the seventh active portion 77 away from the sixth active portion 76; the sixteenth active portion 716 and the seventeenth active portion 717 are connected to both ends of the fifth active portion 75; the eighteenth active portion 718 and the nineteenth active portion 719 are connected to both ends of the eighth active portion 78. In this exemplary embodiment, the first active layer can be formed of polysilicon material, and accordingly, the first transistor T1, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type low-temperature polysilicon thin film transistors.

[0235] In this exemplary embodiment, as shown in Figures 21, 23, 31, and 32, the third active portion 73 is "L"-shaped. It should be understood that in other exemplary embodiments, the third active portion 73 can also be other shapes. For example, the third active portion 73 can also be "J"-shaped, "I"-shaped, etc.

[0236] It should be noted that in other exemplary embodiments, adjacent shielding portions in the row direction X can be connected by connecting portions located in the shielding layer, and adjacent shielding portions in the column direction Y can be connected by connecting portions located in the shielding layer. This arrangement can form a grid structure of the shielding layer. The shielding layer can also be connected to a stable power supply terminal. For example, the shielding layer can be connected to stable voltage terminals such as the first power supply terminal VDD, the first initial signal terminal Vinit1, the second initial signal terminal Vinit2, and the third initial signal terminal Vinit3 in Figure 1. The shielding portion 81 can shield the noise effects of other signals on the driving transistor T3.

[0237] As shown in Figures 21, 24, and 32, the first conductive layer may include: a first conductive portion 11, a second gate line G2, an enable signal line EM, a first reset signal line Re1, and a second reset signal line Re2. The second gate line G2 can be used to provide the second gate drive signal terminal in Figure 1; the enable signal line EM can be used to provide the enable signal terminal in Figure 1; the first reset signal line Re1 can be used to provide the first reset signal terminal in Figure 1; and the second reset signal line Re2 can be used to provide the second reset signal terminal in Figure 1. The orthographic projection of the second gate line G2 on the base substrate, the orthographic projection of the enable signal line EM on the base substrate, the orthographic projection of the first reset signal line Re1 on the base substrate, and the orthographic projection of the second reset signal line Re2 on the base substrate can all extend along the row direction X. The orthographic projection of the second gate line G2 on the base substrate covers the orthographic projection of the fourth active portion 74 on the base substrate, and a portion of the structure of the second gate line G2 is used to form the gate of the fourth transistor. The orthographic projection of the enable signal line EM on the substrate overlaps the orthographic projection of the fifth active portion 75 and the orthographic projection of the sixth active portion 76 on the substrate. Portions of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the first reset signal line Re1 on the substrate overlaps the orthographic projection of the first active portion 71 on the substrate. Portions of the first reset signal line Re1 can be used to form the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 on the substrate overlaps the orthographic projection of the seventh active portion 77 and the orthographic projection of the eighth active portion 78 on the substrate. Portions of the second reset signal line Re2 can be used to form the gates of the seventh transistor T7 and the eighth transistor T8, respectively. The orthographic projection of the first conductive portion 11 on the substrate overlaps the orthographic projection of the third active portion 73 on the substrate. The first conductive portion 11 can be used to form the gate of the drive transistor T3 and can also serve as the first electrode of the capacitor C. In the same pixel driving circuit, the orthographic projection of the first conductive portion 11 on the substrate is located between the orthographic projection of the first reset signal line Re1 on the substrate and the orthographic projection of the second gate line G2 on the substrate. The orthographic projection of the enable signal line EM on the substrate is located on a side of the orthographic projection of the second gate line G2 on the substrate away from the orthographic projection of the first conductive portion 11 on the substrate. The orthographic projection of the second reset signal line Re2 on the substrate is located on a side of the orthographic projection of the enable signal line EM on the substrate away from the orthographic projection of the first conductive portion 11 on the substrate. The display panel can use the first conductive layer as a mask to perform conductor processing on the first active layer, that is, the area of ​​the first active layer covered by the first conductive layer can form the channel region of the transistor, and the area of ​​the first active layer not covered by the first conductive layer forms a conductor structure.

[0238] As shown in Figures 21, 25, and 33, the second conductive layer may include: a third gate line 2G1, a second conductive portion 22, and a third initial signal line Vinit3. The orthographic projection of the third gate line 2G1 on the base substrate extends along the row direction X, and the third gate line 2G1 can be used to provide the first gate drive signal terminal in Figure 1. The orthographic projection of the second conductive portion 22 on the base substrate may at least partially overlap with the orthographic projection of the first conductive portion 11 on the base substrate, and the second conductive portion 22 is used to form the second electrode of the capacitor C. The second conductive layer may also include a second connecting portion 23, and the second conductive portions 22 adjacent in the row direction X can be connected by the second connecting portion 23. The third initial signal line Vinit3 can be used to provide the third initial signal terminal Vinit3 in Figure 1, and the orthographic projection of the third initial signal line Vinit3 on the base substrate may extend along the row direction X. The orthographic projection of the third initial signal line Vinit3 on the substrate is at least partially located between the orthographic projection of the second reset signal line Re2 in the pixel drive circuit of the current row and the orthographic projection of the second reset signal line Re2 in the pixel drive circuit of the next adjacent row. This arrangement can reduce parasitic capacitance between the third initial signal line Vinit3 and structures such as the enable signal line EM and the second conductive portion 22, thereby improving the display effect of the display panel. In addition, two adjacent rows of pixel drive circuits in the same repeating unit can share the same third initial signal line Vinit3. This arrangement can reduce the number of traces and vias in the display panel, thereby improving the integration, pixel density, and manufacturing yield of the display panel. As shown in Figures 21, 25, and 33, the third initial signal line Vinit3 may include: a second main portion Vinit32, a third raised portion Vinit33, and a fourth raised portion Vinit34. The orthographic projection of the second main portion Vinit32 on the substrate may extend along the row direction X. The third raised portion Vinit33 and the fourth raised portion Vinit34 are respectively located on either side of the second main portion Vinit32 in the column direction Y. The orthographic projection of the second main portion Vinit32 on the substrate is located between the orthographic projection of the second reset signal line Re2 in the pixel driving circuit of the current row and the orthographic projection of the second reset signal line Re2 in the pixel driving circuit of the next adjacent row. The third initial signal line Vinit3 may be connected to two pixel driving circuit rows PH that share the third initial signal line Vinit3 via the third raised portion Vinit33 and the fourth raised portion Vinit34.

[0239] As shown in Figures 21, 26, and 34, the second active layer may include an active portion 9, and the active portion 9 may include: a second active portion 92, a twentieth active portion 920 connected to both ends of the second active portion 92, and a twenty-first active portion 921. The second active portion 92 is used to form the channel region of the second transistor T2. The second active layer can be formed of indium gallium zinc oxide, and accordingly, the second transistor T2 can be an N-type metal oxide thin film transistor. The orthographic projection of the third gate line 2G1 on the base substrate can cover the orthographic projection of the second active portion 92 on the base substrate, and a partial structure of the third gate line 2G1 can be used to form the bottom gate of the second transistor T2. In addition, the twentieth active portion 920, the second active portion 92, and the twenty-first active portion 921 can be distributed in the row direction X.

[0240] As shown in Figures 21, 27, and 35, the third conductive layer may include a first gate line 3G1 and a second initial signal line Vinit2. The orthographic projection of the first gate line 3G1 on the base substrate and the orthographic projection of the second initial signal line Vinit2 on the base substrate may both extend along the row direction X. The first gate line 3G1 may be used to provide the first gate drive signal terminal in Figure 1. The first gate line 3G1 includes a third main portion 3G13 and a fifth raised portion 3G15 connected to one side of the third main portion 3G13 in the column direction. The orthographic projection of the third main portion 3G13 on the base substrate extends along the row direction X. The orthographic projection of the fifth raised portion 3G15 on the base substrate covers the orthographic projection of the second active portion 92 on the base substrate. Part of the structure of the fifth raised portion 3G15 may be used to form the top gate of the second transistor T2. At the same time, the first gate line 3G1 may be connected to the third gate line 2G1 through a via located in the frame area of ​​the display panel. The second initial signal line Vinit2 may be used to provide the second initial signal terminal in Figure 1. As shown in Figures 21, 27, and 35, the orthographic projection of the second initial signal line Vinit2 on the substrate at least partially overlaps with the orthographic projection of the third initial signal line Vinit3 on the substrate. This arrangement can improve the transmittance of the display panel. As shown in Figures 21, 27, and 35, the second initial signal line Vinit2 can include a first main portion Vinit21, a first raised portion Vinit221, and a second raised portion Vinit222. The first raised portion Vinit221 and the second raised portion Vinit222 are respectively connected to either side of the first main portion Vinit21 in the column direction. The orthographic projection of the first main portion Vinit21 on the substrate can extend along the row direction X and at least partially overlap with the orthographic projection of the third initial signal line Vinit3 on the substrate. In the two pixel drive circuit rows that share the same second initial signal line Vinit2, the first main portion Vinit21 connects to the two pixel drive circuit rows PH via the first raised portion Vinit221 and the second raised portion Vinit222.

[0241] In addition, the display panel can use the third conductive layer as a mask to conduct the second active layer, that is, the area of ​​the second active layer covered by the third conductive layer can form the channel region of the transistor, and the area of ​​the second active layer not covered by the third conductive layer forms a conductor structure.

[0242] As shown in Figures 21, 28, and 36, the fourth conductive layer may include a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, a seventh bridge portion 47, an eighth bridge portion 48, a ninth bridge portion 49, a first initial signal line Vinit1, a first fan-out line FIPH, and an eleventh bridge portion 411. The first bridge portion 41 may be connected to the twentieth active portion 720 and the first conductive portion 11 through vias, respectively, to connect the first electrode of the second transistor T2 and the gate of the driving transistor T3. The second bridge portion 42 may be connected to the twenty-first active portion 721, the tenth active portion 710, and the thirteenth active portion 713 through vias, respectively, to connect the second electrode of the second transistor T2, the second electrode of the first transistor T1, and the first electrode of the sixth transistor T6. The third bridge portion 43 can be connected to the eleventh active portion 711, the sixteenth active portion 716, and the eighteenth active portion 718 through vias, respectively, to connect the second electrode of the fourth transistor T4, the second electrode of the eighth transistor T8, the second electrode of the fifth transistor T5, and the first electrode of the driving transistor T3. The fourth bridge portion 44 can be connected to the twelfth active portion 712 through a via to connect the first electrode of the fourth transistor T4. The fifth bridge portion 45 can be connected to the seventeenth active portion 717 through a via to connect the first electrode of the fifth transistor. The sixth bridge portion 46 can be connected to the nineteenth active portion 719 and the third initial signal line Vinit3 through vias, respectively, to connect the first electrode of the eighth transistor T8 and the third initial signal terminal. The seventh bridge portion 47 can be connected to the fourteenth active portion 714 through a via to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The eighth bridge portion 48 can be connected to the second initial signal line Vinit2 and the fifteenth active portion 715 through vias, thereby connecting the first electrode and the second initial signal terminal of the seventh transistor T7. The ninth bridge portion 49 can be connected to the second conductive portion 22 through a via. The eleventh bridge portion 411 can be connected to the third initial signal line Vinit3 through a via.

[0243] The first initial signal line Vinit1 can be used to provide the first initial signal terminal shown in Figure 1. The orthographic projection of the first initial signal line Vinit1 on the substrate extends along the row direction X. Furthermore, in the same pixel driving circuit, the orthographic projection of the first initial signal line Vinit1 on the substrate is located on a side of the orthographic projection of the first reset signal line Re1 on the substrate that is away from the orthographic projection of the first conductive portion 11 on the substrate. This arrangement can reduce the parasitic capacitance of the first initial signal line Vinit1 and other AC signal lines, such as the enable signal line EM and the first reset signal line Re1, thereby improving the voltage stability of the first initial signal line Vinit1. An AC signal line is a signal line that outputs an AC signal.

[0244] In this exemplary embodiment, as shown in Figures 21, 28, and 36, two adjacent pixel driving circuit rows PH located in different pixel driving circuit row groups CP share the same first initial signal line Vinit1. This setting can also reduce the number of wirings and vias in the display panel, thereby improving the manufacturing yield of the display panel.

[0245] As shown in Figures 21, 28, and 37, the orthographic projection of the first fan-out line FIPH on the substrate can extend along the row direction X. The first fan-out line FIPH can be used as a row direction fan-out line connecting the data line in the FIP (Fanout In Pixel).

[0246] In this exemplary embodiment, the square resistance of the fourth conductive layer can be smaller than the square resistances of the first, second, and third conductive layers. This exemplary embodiment arranges the first initial signal line Vinit1 in the fourth conductive layer, thereby reducing voltage differences across the first initial signal line Vinit1 at different locations on the display panel, thereby improving display uniformity across the display panel. Similarly, this exemplary embodiment arranges the second initial connection line 4Vinit2 in the fourth conductive layer, thereby reducing voltage differences across the second initial signal line Vinit2 at different locations on the display panel, thereby improving display uniformity across the display panel.

[0247] As shown in Figures 21 and 29, the fifth conductive layer may include a tenth bridge portion 510, a data line Da, a first power line VDD, a second fan-out line FIPV, a first initial connection line 5Vinit1, and a third initial connection line 5Vinit3. The orthographic projections of the data line Da, the first power line VDD, the second fan-out line FIPV, the first initial connection line 5Vinit1, and the third initial connection line 5Vinit3 on the substrate may all extend along the column direction Y. The data line Da is used to provide the data signal terminal shown in Figure 1, and the first power line VDD is used to provide the first power terminal shown in Figure 1. The data line Da may be connected to the fourth bridge portion 44 via a via to connect the data signal terminal to the first electrode of the fourth transistor T4. There may be multiple first power lines VDD, with their orthographic projections on the substrate extending along the column direction Y and spaced apart along the row direction X. The first power line VDD may be connected to the ninth bridge portion 49, where its orthographic projection on the substrate intersects, via a via. The first power line VDD and the second conductive portion 22 connected in the row direction X can form a grid structure. This arrangement can reduce the voltage difference on the first power line at different positions on the display panel, thereby improving the display uniformity of the display panel. In addition, the first power line VDD can also be connected to the fifth bridge portion 45 through a via to connect the first power terminal and the first electrode of the fifth transistor T5.

[0248] The second fan-out line FIPV can be used as a column-direction fan-out line connecting the data line in the FIP (Fanout In Pixel, fan-out area in the pixel). A first fan-out line and a second fan-out line can also be provided in the non-fan-out area of ​​the display panel. In the non-fan-out area, the second fan-out line FIPV can be connected to the first fan-out line FIPH intersecting therewith through a via. The first fan-out line FIPH and the second fan-out line FIPV can form a grid structure. The grid structure can be connected to the common electrode layer in the display panel through the via. The common electrode layer can serve as the second electrode of the light-emitting unit. This arrangement can reduce the resistance of the common electrode layer, thereby reducing the voltage difference of the common electrode layer at different positions of the display panel, thereby improving the display uniformity of the display panel.

[0249] The first initial connection line 5Vinit1 can be connected to the first initial signal line Vinit1 that intersects with its orthographic projection on the base substrate through a via. This setting can enable the first initial signal line to form a grid structure. The initial signal line of the grid structure has a smaller resistance, thereby reducing the voltage difference of the first initial signal line at different positions of the display panel, thereby improving the display uniformity of the display panel.

[0250] The third initial connection line 5Vinit3 can be connected to the eleventh bridge portion 411 via a via to connect to the third initial signal line Vinit3, whose orthographic projection on the substrate intersects. This arrangement can form a grid structure of the third initial signal lines. The initial signal lines in this grid structure have a low resistance, thereby reducing the voltage difference between the third initial signal lines at different positions on the display panel, thereby improving the display uniformity of the display panel. It should be understood that in other exemplary embodiments, the display panel may not be provided with the eleventh bridge portion 411, and the third initial connection line 5Vinit3 may be directly connected to the third initial signal line Vinit3 via a via.

[0251] The tenth bridge portion 510 can be connected to the seventh bridge portion 47 through a via hole to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The tenth bridge portion 510 can also be connected to the pixel electrode in the pixel electrode layer through a via hole. The pixel electrode layer can be located on the side of the fifth conductive layer away from the base substrate. The pixel electrode can be used to form the first electrode of the light-emitting unit.

[0252] FIG36 is a partial cross-sectional view of the display panel shown in FIG21 taken along the dotted line CC. The display panel may further include a first insulating layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a fifth insulating layer 105, a first dielectric layer 106, and a first planar layer 108. The base substrate 100, the shielding layer, the first insulating layer 101, the first active layer, the second insulating layer 102, the first conductive layer, the third insulating layer 103, the second conductive layer, the fourth insulating layer 104, the second active layer, the fifth insulating layer 105, the third conductive layer, the first dielectric layer 106, the fourth conductive layer, the first planar layer 108, and the fifth conductive layer are stacked in sequence. The first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be a single-layer structure or a multi-layer structure. The material of the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride. The first dielectric layer 106 can be a silicon nitride layer. The material of the first planar layer 108 can be an organic material, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), etc. The base substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence. The barrier layer can be an inorganic material. The material of the first conductive layer, the second conductive layer, and the third conductive layer can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a laminated conductive layer. The material of the fourth conductive layer and the fifth conductive layer may include a metal material, for example, one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum / titanium alloy or a laminate, or a conductive layer such as a titanium / aluminum / titanium laminate. The square resistance of any one of the fourth conductive layer and the fifth conductive layer may be smaller than the square resistance of any one of the first conductive layer, the second conductive layer, and the third conductive layer. In addition, the display panel may further include a pixel electrode layer located on the side of the sixth conductive layer facing away from the base substrate, a light-emitting unit layer located on the side of the pixel electrode layer facing away from the base substrate, and a common electrode layer located on the side of the light-emitting unit layer facing away from the base substrate. The light-emitting unit layer may include a light-emitting material layer, and the holes generated by the anode of the light-emitting unit and the electrons generated by the cathode may generate energy excitons when they meet in the light-emitting material layer, thereby exciting the light-emitting molecules in the light-emitting material layer to generate visible light.

[0253] In this exemplary embodiment, the display panel shown in FIG3 may also have other layout structures. As shown in FIG37-51, FIG37 is a structural layout diagram of another exemplary embodiment of the display panel disclosed herein, FIG38 is a structural layout diagram of the shielding layer in FIG37, FIG39 is a structural layout diagram of the first active layer in FIG37, FIG40 is a structural layout diagram of the first conductive layer in FIG37, FIG41 is a structural layout diagram of the second conductive layer in FIG37, FIG42 is a structural layout diagram of the second active layer in FIG37, FIG43 is a structural layout diagram of the third conductive layer in FIG37, FIG44 is a structural layout diagram of the fourth conductive layer in FIG37, FIG45 is a structural layout diagram of the fifth conductive layer in FIG37, and FIG46 is a structural layout diagram of the shielding layer and the first active layer in FIG37. Figure 47 is the structural layout of the blocking layer, the first active layer, and the first conductive layer in Figure 37, Figure 48 is the structural layout of the blocking layer, the first active layer, the first conductive layer, and the second conductive layer in Figure 37, Figure 49 is the structural layout of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in Figure 37, Figure 50 is the structural layout of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in Figure 37, and Figure 51 is the structural layout of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in Figure 37.

[0254] As shown in Figures 37-51, the orthographic projections of two adjacent rows of pixel driving circuits PH in the same pixel driving circuit row group CP on the substrate are at least partially mirror-symmetrically arranged about the first symmetry axis AA; the orthographic projections of two adjacent rows of pixel driving circuits in the same pixel driving circuit row PH on the substrate are at least partially mirror-symmetrically arranged about the second symmetry axis BB.

[0255] 37 , 38 , and 46 , the shielding layer may include a plurality of shielding portions 81 , which are distributed in an array in the row direction X and the column direction Y. It should be understood that in other exemplary embodiments, the display panel may not include a shielding layer.

[0256] As shown in Figures 37, 39, 46 and 47, the first active layer may include: a first active portion 71, a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, a seventh active portion 77, an eighth active portion 78, a ninth active portion 79, a tenth active portion 710, an eleventh active portion 711, a twelfth active portion 712, a thirteenth active portion 713, a fourteenth active portion 714, a fifteenth active portion 715, a sixteenth active portion 716, a seventeenth active portion 717, an eighteenth active portion 718 and a nineteenth active portion 719. The first active portion 71 is used to form the channel region of the first transistor T1; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 can be used to form the channel region of the eighth transistor T8; the ninth active portion 79 is connected to the end of the first active portion 71 away from the third active portion 73, and in two adjacent pixel driving circuit rows sharing the same first initial signal line Vinit1, the ninth active portion 79 is connected to the two adjacent pixel driving circuit rows. The first active portion 71 is connected to the first active portion 71; the tenth active portion 710 is connected between the first active portion 71 and the third active portion 73; the eleventh active portion 711 is connected between the third active portion 73 and the fourth active portion 74; the twelfth active portion 712 is connected to the end of the fourth active portion 74 away from the third active portion 73; the thirteenth active portion 713 is connected to the end of the sixth active portion away from the seventh active portion 77; the fourteenth active portion 714 is connected between the sixth active portion 76 and the seventh active portion 77; the fifteenth active portion 715 is connected to the end of the seventh active portion 77 away from the sixth active portion 76; the sixteenth active portion 716 and the seventeenth active portion 717 are connected to both ends of the fifth active portion 75; the eighteenth active portion 718 and the nineteenth active portion 719 are connected to both ends of the eighth active portion 78. In this exemplary embodiment, the first active layer can be formed of polysilicon material, and accordingly, the first transistor T1, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type low-temperature polysilicon thin film transistors.

[0257] In this exemplary embodiment, as shown in Figures 37, 39, 46, and 47, the third active portion 73 is "L"-shaped. It should be understood that in other exemplary embodiments, the third active portion 73 can also be other shapes. For example, the third active portion 73 can also be "J"-shaped, "I"-shaped, etc.

[0258] It should be noted that in other exemplary embodiments, adjacent shielding portions 81 in the row direction X can be connected by connecting portions located in the shielding layer, and adjacent shielding portions 81 in the column direction Y can be connected by connecting portions located in the shielding layer. This arrangement can form a grid structure of the shielding layer. The shielding layer can also be connected to a stable power supply terminal. For example, the shielding layer can be connected to stable voltage terminals such as the first power supply terminal VDD, the first initial signal terminal Vinit1, the second initial signal terminal Vinit2, and the third initial signal terminal Vinit3 in Figure 1. The shielding portion 81 can shield the noise influence of other signals on the driving transistor T3.

[0259] As shown in Figures 37, 40, and 47, the first conductive layer may include: a first conductive portion 11, a second gate line G2, an enable signal line EM, a first reset signal line Re1, and a second reset signal line Re2. The second gate line G2 can be used to provide the second gate drive signal terminal in Figure 1; the enable signal line EM can be used to provide the enable signal terminal in Figure 1; the first reset signal line Re1 can be used to provide the first reset signal terminal in Figure 1; and the second reset signal line Re2 can be used to provide the second reset signal terminal in Figure 1. The orthographic projection of the second gate line G2 on the substrate, the orthographic projection of the enable signal line EM on the substrate, the orthographic projection of the first reset signal line Re1 on the substrate, and the orthographic projection of the second reset signal line Re2 on the substrate can all extend along the row direction X. The orthographic projection of the second gate line G2 on the substrate covers the orthographic projection of the fourth active portion 74 on the substrate, and a portion of the structure of the second gate line G2 is used to form the gate of the fourth transistor T4. The orthographic projection of the enable signal line EM on the substrate overlaps the orthographic projection of the fifth active portion 75 and the orthographic projection of the sixth active portion 76 on the substrate. Portions of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the first reset signal line Re1 on the substrate overlaps the orthographic projection of the first active portion 71 on the substrate. Portions of the first reset signal line Re1 can be used to form the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 on the substrate overlaps the orthographic projection of the seventh active portion 77 and the orthographic projection of the eighth active portion 78 on the substrate. Portions of the second reset signal line Re2 can be used to form the gates of the seventh transistor T7 and the eighth transistor T8, respectively. The orthographic projection of the first conductive portion 11 on the substrate overlaps the orthographic projection of the third active portion 73 on the substrate. The first conductive portion 11 can be used to form the gate of the drive transistor T3 and can also serve as the first electrode of the capacitor C. In the same pixel driving circuit, the orthographic projection of the first conductive portion 11 on the substrate is located between the orthographic projection of the first reset signal line Re1 on the substrate and the orthographic projection of the second gate line G2 on the substrate. The orthographic projection of the enable signal line EM on the substrate is located on a side of the orthographic projection of the second gate line G2 on the substrate away from the orthographic projection of the first conductive portion 11 on the substrate. The orthographic projection of the second reset signal line Re2 on the substrate is located on a side of the orthographic projection of the enable signal line EM on the substrate away from the orthographic projection of the first conductive portion 11 on the substrate. The display panel can use the first conductive layer as a mask to perform conductor processing on the first active layer, that is, the area of ​​the first active layer covered by the first conductive layer can form the channel region of the transistor, and the area of ​​the first active layer not covered by the first conductive layer forms a conductor structure.

[0260] As shown in Figures 37, 41, and 48, the second conductive layer may include: a third gate line 2G1, a second conductive portion 22, and a third initial signal line Vinit3. The orthographic projection of the third gate line 2G1 on the substrate extends along the row direction X, and the third gate line 2G1 can be used to provide the first gate drive signal terminal in Figure 1. The orthographic projection of the second conductive portion 22 on the substrate can at least partially overlap with the orthographic projection of the first conductive portion 11 on the substrate, and the second conductive portion 22 is used to form the second electrode of the capacitor C. The second conductive layer may also include a second connecting portion 23, and adjacent second conductive portions 22 in the row direction X can be connected via the second connecting portion 23. The third initial signal line Vinit3 can be used to provide the third initial signal terminal Vinit3 in Figure 1, and the orthographic projection of the third initial signal line Vinit3 on the substrate can extend along the row direction X. The orthographic projection of the third initial signal line Vinit3 on the substrate is located between the orthographic projection of the second reset signal line Re2 in the pixel drive circuit of the current row and the orthographic projection of the second reset signal line Re2 in the pixel drive circuit of the next adjacent row on the substrate. This configuration can reduce the parasitic capacitance between the third initial signal line Vinit3 and the enable signal line EM, the second conductive portion 22 and other structures, thereby improving the display effect of the display panel.

[0261] As shown in Figures 37, 42, and 49, the second active layer may include an active portion 9, which may include: a second active portion 92, a twentieth active portion 920 connected to both ends of the second active portion 92, and a twenty-first active portion 921. The second active portion 92 is used to form the channel region of the second transistor T2. The second active layer may be formed of indium gallium zinc oxide, and accordingly, the second transistor T2 may be an N-type metal oxide thin film transistor. The orthographic projection of the third gate line 2G1 on the substrate may cover the orthographic projection of the second active portion 92 on the substrate, and a portion of the structure of the third gate line 2G1 may be used to form the bottom gate of the second transistor T2. In addition, the twentieth active portion 920, the second active portion 92, and the twenty-first active portion 921 may be distributed in the row direction X.

[0262] As shown in Figures 37, 43, and 50, the third conductive layer may include a first bridge portion 31, a second bridge portion 32, a third bridge portion 33, a sixth bridge portion 36, a seventh bridge portion 37, a first gate line 3G1, and a second initial signal line Vinit2. The orthographic projection of the first gate line 3G1 and the orthographic projection of the second initial signal line Vinit2 on the substrate may both extend along the row direction X. The first gate line 3G1 can be used to provide the first gate drive signal terminal in Figure 1. The first gate line 3G1 includes a third main portion 3G13 and a fifth raised portion 3G15 connected to one side of the third main portion 3G13 in the column direction. The orthographic projection of the third main portion 3G13 on the substrate extends along the row direction X. The orthographic projection of the fifth raised portion 3G15 on the substrate covers the orthographic projection of the second active portion 92 on the substrate. Part of the structure of the fifth raised portion 3G15 can be used to form the top gate of the second transistor T2. At the same time, the first gate line 3G1 can be connected to the third gate line 2G1 through a via located in the frame area of ​​the display panel. The second initial signal line Vinit2 can be used to provide the second initial signal terminal in Figure 1. As shown in Figures 4, 10, and 17, two adjacent rows of pixel drive circuit rows PH in the same pixel drive circuit row group CP can share the same second initial signal line Vinit2. The orthographic projection of the second initial signal line Vinit2 on the substrate is at least partially located between the orthographic projections of two adjacent third initial signal lines Vinit3 on the substrate in the same pixel driver circuit row group CP. This arrangement can reduce the parasitic cell between the third initial signal line Vinit3 and the second initial signal line Vinit2 by reducing the overlapping area between the third initial signal line Vinit3 and the second initial signal line Vinit2, thereby reducing signal interference between the third initial signal line Vinit3 and the second initial signal line Vinit2. As shown in Figures 37, 43, and 50, the second initial signal line Vinit2 may include a first main portion Vinit21, a first raised portion Vinit221, and a second raised portion Vinit222. The first raised portion Vinit221 and the second raised portion Vinit222 are respectively connected to opposite sides of the first main portion Vinit21 in the column direction Y. The orthographic projection of the first main portion Vinit21 on the substrate can extend along the row direction X and be located between the orthographic projections of two adjacent third initial signal lines Vinit3 on the substrate in the same pixel driver circuit row group CP. In the two rows of pixel driving circuits sharing the same second initial signal line Vinit2, the first main portion Vinit21 is connected to the fifteenth active portion 715 in the two rows of pixel driving circuits through the first protrusion Vinit221 and the second protrusion Vinit222 via holes.

[0263] As shown in Figures 37, 43, and 50, the first bridge portion 31 may include a main portion 311 and an extension portion 312. The main portion 311 is connected to the gate of the driving transistor T3 and the first electrode of the second transistor T2 via vias, respectively. The orthographic projection of the extension portion 312 on the substrate at least partially overlaps the orthographic projection of the second conductive portion 22 on the substrate. The main portion includes a first side 3111, and the extension portion 312 includes a second side 3122. The first side 3111 and the second side 3122 are connected, and the angle between the orthographic projection of the first side 3111 on the substrate and the orthographic projection of the second side 3122 on the substrate is less than 180°. For example, the angle between the orthographic projection of the first side 3111 on the substrate and the orthographic projection of the second side 3122 on the substrate can be equal to 80°, 90°, 95°, etc. This configuration can increase the capacitance of the capacitor C, thereby maintaining a more stable voltage value at the node N in the pixel driving circuit, thereby improving the brightness stability of the light-emitting unit within a frame period.

[0264] As shown in Figures 37, 43, and 50, the first bridge portion 31 can be connected to the 20th active portion 720 and the first conductive portion 11 through vias, respectively, to connect the first electrode of the second transistor T2 and the gate of the driving transistor T3. The second bridge portion 32 can be connected to the 21st active portion 721, the 10th active portion 710, and the 13th active portion 713 through vias, respectively, to connect the second electrode of the second transistor T2, the second electrode of the first transistor T1, and the first electrode of the sixth transistor T6. The third bridge portion 33 can be connected to the 11th active portion 711, the 16th active portion 716, and the 18th active portion 718 through vias, respectively, to connect the second electrode of the fourth transistor T4, the second electrode of the eighth transistor T8, the second electrode of the fifth transistor T5, and the first electrode of the driving transistor T3. The sixth bridge portion 36 can be connected to the 19th active portion 719 and the third initial signal line Vinit3 through vias, respectively, to connect the first electrode of the eighth transistor T8 and the third initial signal terminal. The seventh bridge portion 37 may be connected to the fourteenth active portion 714 through a via hole to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 .

[0265] In addition, the display panel can use the third conductive layer as a mask to conduct the second active layer, that is, the area of ​​the second active layer covered by the third conductive layer can form the channel region of the transistor, and the area of ​​the second active layer not covered by the third conductive layer forms a conductor structure.

[0266] As shown in Figures 37, 44, and 51, the fourth conductive layer may include a fourth bridge portion 44, a fifth bridge portion 45, a ninth bridge portion 49, a twelfth bridge portion 412, a first initial signal line Vinit1, a first fan-out line FIPH, a second gate connection line 4G2, and a first gate connection line 4G1. The fourth bridge portion 44 may be connected to the twelfth active portion 712 via a via to connect to the first electrode of the fourth transistor T4. The fifth bridge portion 45 may be connected to the seventeenth active portion 717 via a via to connect to the first electrode of the fifth transistor. The ninth bridge portion 49 may be connected to the second conductive portion 22 via a via. The twelfth bridge portion 412 may be connected to the seventh bridge portion 37 via a via.

[0267] The first initial signal line Vinit1 can be used to provide the first initial signal terminal shown in Figure 1. The orthographic projection of the first initial signal line Vinit1 on the substrate extends along the row direction X. Furthermore, in the same pixel driving circuit, the orthographic projection of the first initial signal line Vinit1 on the substrate is located on a side of the orthographic projection of the first reset signal line Re1 on the substrate that is away from the orthographic projection of the first conductive portion 11 on the substrate. This arrangement can reduce the parasitic capacitance of the first initial signal line Vinit1 and other AC signal lines, such as the enable signal line EM and the first reset signal line Re1, thereby improving the voltage stability of the first initial signal line Vinit1. An AC signal line is a signal line that outputs an AC signal.

[0268] In this exemplary embodiment, as shown in Figures 37, 44, and 51, two adjacent pixel driving circuit rows PH located in different pixel driving circuit row groups CP share the same first initial signal line Vinit1. This setting can also reduce the number of wiring and vias in the display panel, thereby improving the manufacturing yield of the display panel.

[0269] As shown in Figures 37, 44, and 51, the orthographic projection of the first fan-out line FIPH on the substrate can extend along the row direction X. The first fan-out line FIPH can be used as a row direction fan-out line connecting the data line in the FIP (Fanout In Pixel).

[0270] As shown in Figures 37, 44, and 51, the orthographic projection of the first gate connection line 4G1 on the base substrate can extend along the row direction X, and the first gate connection line 4G1 can be connected to the first gate line 3G1 through a via. The orthographic projection of the second gate connection line 4G2 on the base substrate can extend along the row direction X, and the second gate connection line 4G2 can be connected to the second gate line G2 through a via. In this exemplary embodiment, the square resistance of the fourth conductive layer can be smaller than the square resistance of the first conductive layer, the second conductive layer, and the third conductive layer. In this exemplary embodiment, the first gate connection line 4G1 and the second gate connection line 4G2 are arranged in the fourth conductive layer. This arrangement can greatly reduce the resistance of the first gate line 3G1 and the second gate line G2, thereby improving the response speed of the corresponding transistor.

[0271] As shown in Figures 37 and 45, the fifth conductive layer may include a tenth bridge portion 510, a data line Da, a first power line VDD, and a second fan-out line FIPV. The orthographic projections of the data line Da, the first power line VDD, and the second fan-out line FIPV on the substrate may all extend along the column direction Y. The data line Da is used to provide the data signal terminal shown in Figure 1, and the first power line VDD is used to provide the first power terminal shown in Figure 1. The data line Da may be connected to the fourth bridge portion 44 via a via to connect the data signal terminal to the first electrode of the fourth transistor T4. There may be multiple first power lines VDD, with their orthographic projections on the substrate extending along the column direction Y and spaced apart along the row direction X. The first power line VDD may be connected to the ninth bridge portion 49, where its orthographic projection on the substrate intersects, via a via. The first power line VDD and the second conductive portion 22 connected in the row direction X may form a grid structure. This arrangement can reduce voltage differences on the first power line at different locations on the display panel, thereby improving display uniformity. In addition, the first power line VDD may also be connected to the fifth bridge portion 45 through a via hole to connect the first power terminal and the first electrode of the fifth transistor T5.

[0272] The second fan-out line FIPV can be used as a column-direction fan-out line connecting the data line in the FIP (Fanout In Pixel, fan-out area in the pixel). A first fan-out line and a second fan-out line can also be provided in the non-fan-out area of ​​the display panel, and in the non-fan-out area, the second fan-out line FIPV can be connected to the first fan-out line FIPH whose orthographic projection on the substrate intersects with the second fan-out line FIPV through a via. The first fan-out line FIPH and the second fan-out line FIPV can form a grid structure, which can be connected to the common electrode layer in the display panel through a via. The common electrode layer can serve as the second electrode of the light-emitting unit. This arrangement can reduce the resistance of the common electrode layer, thereby reducing the voltage difference of the common electrode layer at different positions of the display panel, thereby improving the display uniformity of the display panel.

[0273] The tenth bridge portion 510 can be connected to the twelfth bridge portion 412 through a via hole to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The tenth bridge portion 510 can also be connected to the pixel electrode in the pixel electrode layer through a via hole. The pixel electrode layer can be located on the side of the fifth conductive layer away from the base substrate. The pixel electrode can be used to form the first electrode of the light-emitting unit.

[0274] As shown in Figure 52, a partial cross-sectional view of the display panel shown in Figure 37 is taken along the dotted line CC. The display panel may further include a first insulating layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a fifth insulating layer 105, a first dielectric layer 106, and a first planar layer 108. The base substrate 100, the shielding layer, the first insulating layer 101, the first active layer, the second insulating layer 102, the first conductive layer, the third insulating layer 103, the second conductive layer, the fourth insulating layer 104, the second active layer, the fifth insulating layer 105, the third conductive layer, the first dielectric layer 106, the fourth conductive layer, the first planar layer 108, and the fifth conductive layer are stacked in sequence. The first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be a single-layer structure or a multi-layer structure. The material of the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride. The first dielectric layer 106 can be a silicon nitride layer. The material of the first planar layer 108 can be an organic material, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), etc. The base substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence. The barrier layer can be an inorganic material. The material of the first conductive layer, the second conductive layer, and the third conductive layer can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a laminated conductive layer. The fourth and fifth conductive layers may be made of metal materials, such as molybdenum, aluminum, copper, titanium, or niobium, or an alloy thereof, or a molybdenum / titanium alloy or laminate, or a titanium / aluminum / titanium laminate. The square resistance of any of the fourth and fifth conductive layers may be less than the square resistance of any of the first, second, and third conductive layers.

[0275] In addition, the display panel may further include a pixel electrode layer located on the side of the fifth conductive layer away from the base substrate, a light emitting unit layer located on the side of the pixel electrode layer away from the base substrate, and a common electrode layer located on the side of the light emitting unit layer away from the base substrate.

[0276] It should be understood that in other exemplary embodiments, the pixel driving circuit Pix in the display panel shown in Figures 3 and 20 may also have other structures. For example, the pixel driving circuit Pix may not include the eighth transistor T8. For another example, one or more of the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be N-type transistors, and the second transistor T2 may be a P-type transistor. For another example, the second electrode of the first transistor T1 may be directly connected to the node N.

[0277] It should be noted that, as shown in Figures 4, 18, 21, 35, 37, and 51, the black squares drawn on the side of the fourth conductive layer facing away from the substrate represent vias connecting the fourth conductive layer to other layers on the side facing the substrate; the black squares drawn on the side of the fifth conductive layer facing away from the substrate represent vias connecting the fifth conductive layer to other layers on the side facing the substrate. Different vias represented by black squares in different positions can penetrate different insulating layers.

[0278] In addition, in the display panels shown in Figures 4, 21, and 37, when one or more of the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are N-type transistors, the channel region of the N-type transistor can be located in the second active layer, the bottom gate of the N-type transistor can be located in the second conductive layer, and the top gate of the N-type transistor can be located in the third conductive layer. When the second transistor T2 is a P-type transistor, the channel region of the second transistor T2 can be located in the first active layer, and the gate of the second transistor can be located in the first conductive layer.

[0279] In the display panels shown in Figures 4, 21, and 37, in the same pixel driving circuit, the first active portion 71 and the third active portion 73 can be connected in the same layer. This arrangement can reduce the number of via bridges and improve the stability of the connection between the first active portion 71 and the third active portion 73.

[0280] In the display panels shown in Figures 4, 21, and 37, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 may also be located in other conductive layers. For example, the first initial signal line Vinit1 may also be located in the second conductive layer or the third conductive layer, the second initial signal line Vinit2 may also be located in the second conductive layer or the fourth conductive layer, and the third initial signal line Vinit3 may also be located in the third conductive layer or the fourth conductive layer.

[0281] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematics. In addition, qualifiers such as first and second are only used to limit different structure names, and they do not have a specific order meaning. The same structural layer can be formed by the same composition process. In this exemplary embodiment, the orthographic projection of a certain structure on the substrate extends in a certain direction, which can be understood as the orthographic projection of the structure on the substrate extending in a straight line or bending along that direction.

[0282] This exemplary embodiment also provides a display device, which includes the above-mentioned display panel. The display device can be a mobile phone, a tablet computer, a television, or other display device.

[0283] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0284] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0285] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A display panel, wherein: The display panel includes: substrate; a pixel driving circuit row group, the pixel driving circuit row group including two adjacent pixel driving circuit rows in the column direction, the pixel driving circuit rows including a plurality of pixel driving circuits distributed in the row direction; a light-emitting unit, the pixel driving circuit being used to drive the light-emitting unit, the pixel driving circuit comprising a seventh transistor, a first electrode of the seventh transistor being connected to a second initial signal line, a second electrode of the seventh transistor being connected to a first electrode of the light-emitting unit, a gate of the seventh transistor being formed by a portion of a second reset signal line, an orthographic projection of the second reset signal line on the substrate extending along a row direction; In which, the orthographic projections of two adjacent rows of pixel driving circuit rows in the same pixel driving circuit row group on the substrate are at least partially mirror-symmetrically arranged about a first symmetry axis, the first symmetry axis extends along the row direction, and the two adjacent rows of pixel driving circuit rows in the same pixel driving circuit row group share the same second initial signal line.

2. The display panel according to claim 1, wherein The second initial signal line forms the first symmetry axis, and the orthographic projections of two adjacent pixel driving circuit rows in the same pixel driving circuit row group on the substrate are at least partially mirror-symmetrically arranged about the second initial signal line.

3. The display panel according to claim 1, wherein: The pixel driving circuit further includes a driving transistor and a fifth transistor, wherein a first electrode of the fifth transistor is connected to the first power line, and a second electrode of the fifth transistor is connected to the first electrode of the driving transistor; The display panel further includes: a first conductive portion, wherein the first conductive portion is used to form a gate of the driving transistor; an enable signal line, an orthographic projection of the enable signal line on the substrate extending along a row direction, and a partial structure of the enable signal line being used to form a gate of the fifth transistor; In the same pixel driving circuit, an orthographic projection of the second reset signal line on the base substrate is located on a side of the orthographic projection of the enable signal line on the base substrate away from an orthographic projection of the first conductive portion on the base substrate; An orthographic projection of the second initial signal line on the base substrate is at least partially located between two adjacent second reset signal lines in the same pixel driving circuit row group.

4. The display panel according to claim 1, wherein: The second initial signal line includes: a first main body portion, wherein an orthographic projection of the first main body portion on the base substrate extends along a row direction; a first raised portion; a second protrusion, wherein the first protrusion and the second protrusion are respectively connected to two sides of the first main body in a column direction; In the two rows of pixel driving circuits that share the same second initial signal line, the first main body connects the two rows of pixel driving circuits via the first protrusion and the second protrusion.

5. The display panel according to claim 1, wherein: The pixel driving circuit further includes a driving transistor and a second transistor, wherein a first electrode of the second transistor is connected to a gate of the driving transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor; The display panel further includes: a first active layer located on one side of the base substrate, the first active layer comprising a third active portion, the third active portion being used to form a channel region of the driving transistor; a first conductive layer, located on a side of the first active layer facing away from the base substrate, the first conductive layer comprising a first conductive portion, an orthographic projection of the first conductive portion on the base substrate covering an orthographic projection of the third active portion on the base substrate, and the first conductive portion being used to form a gate of the driving transistor; a second active layer, located on a side of the first conductive layer facing away from the substrate, the second active layer comprising a second active portion, the second active portion being used to form a channel region of the second transistor; a third conductive layer, located on a side of the second active layer facing away from the base substrate, the third conductive layer comprising a first gate line, an orthographic projection of the first gate line on the base substrate extending along a row direction and covering an orthographic projection of the second active portion on the base substrate, and a portion of the first gate line forming a top gate of the second transistor; Wherein, the third conductive layer further includes the second initial signal line. The display panel according to claim 1 , wherein: The pixel driving circuit further includes a driving transistor and a first transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to a second electrode of the driving transistor; The display panel includes a plurality of pixel driving circuit row groups, the plurality of pixel driving circuit row groups are distributed in a column direction, and two adjacent pixel driving circuit rows in different pixel driving circuit row groups share the same first initial signal line.

7. The display panel according to claim 6, wherein: The display panel further includes: a first conductive portion, wherein the first conductive portion is used to form a gate of the driving transistor; a first reset signal line, wherein an orthographic projection of the first reset signal line on the substrate extends along a row direction, and a portion of the first reset signal line is used to form a gate of the first transistor; The orthographic projection of the first reset signal line on the base substrate is located on a side where the orthographic projection of the first conductive portion on the base substrate is away from the orthographic projection of the second reset signal line on the base substrate; In two adjacent pixel driving circuit rows sharing the same first initial signal line, the orthographic projection of the first initial signal line on the substrate is at least partially located between the orthographic projections of the first reset signal lines in the two adjacent pixel driving circuit rows on the substrate.

8. The display panel according to claim 7, wherein: The display panel further includes: a first active layer located on one side of the base substrate, the first active layer comprising a first active portion and a ninth active portion, the first active portion being used to form a channel region of the first transistor, and in two adjacent pixel driving circuit rows sharing the same first initial signal line, the ninth active portion being connected between two first active portions in the two adjacent pixel driving circuit rows; The first initial signal line is connected to the ninth active portion through a via hole.

9. The display panel according to claim 6, wherein: The pixel driving circuit further includes a second transistor, wherein a first electrode of the second transistor is connected to the gate electrode of the driving transistor, and a second electrode of the second transistor is connected to the second electrode of the driving transistor; The display panel further includes: a first active layer, located on one side of the base substrate, wherein at least a portion of the first active layer is used to form a channel region of the driving transistor; a first conductive layer, located on a side of the first active layer facing away from the base substrate, wherein at least a portion of the first conductive layer is used to form a gate of the driving transistor; a second active layer, located on a side of the first conductive layer facing away from the substrate, wherein at least a portion of the second active layer is used to form a channel region of the second transistor; a third conductive layer, located on a side of the second active layer facing away from the substrate, wherein at least a portion of the third conductive layer is used to form a top gate of the second transistor; The fourth conductive layer is located on a side of the third conductive layer away from the base substrate, and the fourth conductive layer includes the first initial signal line.

10. The display panel according to claim 1, wherein The pixel driving circuit further includes a driving transistor and an eighth transistor, wherein a first electrode of the eighth transistor is connected to the third initial signal line, and a second electrode of the eighth transistor is connected to the first electrode of the driving transistor; Two adjacent rows of pixel driving circuits in the same pixel driving circuit row group share the same third initial signal line.

11. The display panel according to claim 10, wherein: The third initial signal line includes: a second main body portion, wherein an orthographic projection of the second main body portion on the base substrate extends along a row direction; a third raised portion; a fourth protrusion, wherein the third protrusion and the fourth protrusion are respectively connected to two sides of the second main body in the column direction; In the two pixel driving circuit rows that share the same third initial signal line, the second main body portion connects the two pixel driving circuit rows via the third protrusion and the fourth protrusion.

12. The display panel according to claim 10, wherein: An orthographic projection of the third initial signal line on the base substrate and an orthographic projection of the second initial signal line on the base substrate at least partially overlap.

13. The display panel according to claim 10, wherein: The pixel driving circuit further includes a second transistor, wherein a first electrode of the second transistor is connected to the gate electrode of the driving transistor, and a second electrode of the second transistor is connected to the second electrode of the driving transistor; The display panel further includes: a first active layer, located on one side of the base substrate, wherein at least a portion of the first active layer is used to form a channel region of the driving transistor; a first conductive layer, located on a side of the first active layer facing away from the base substrate, wherein at least a portion of the first conductive layer is used to form a gate of the driving transistor; a second active layer, located on a side of the first conductive layer facing away from the substrate, wherein at least a portion of the second active layer is used to form a channel region of the second transistor; a third conductive layer, located on a side of the second active layer facing away from the substrate, wherein at least a portion of the third conductive layer is used to form a top gate of the second transistor; Wherein, the third conductive layer includes the third initial signal line.

14. The display panel according to claim 1, wherein: The pixel driving circuit further includes a driving transistor and a second transistor, wherein a first electrode of the second transistor is connected to a gate of the driving transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor; The display panel further includes: a first active layer, located on one side of the base substrate, wherein at least a portion of the first active layer is used to form a channel region of the driving transistor; a first conductive layer, located on a side of the first active layer facing away from the base substrate, wherein at least a portion of the first conductive layer is used to form a gate of the driving transistor; a second active layer, located on a side of the first conductive layer facing away from the substrate, wherein at least a portion of the second active layer is used to form a channel region of the second transistor; a third conductive layer, located on a side of the second active layer facing away from the substrate, wherein at least a portion of the third conductive layer is used to form a top gate of the second transistor; The third conductive layer further includes a first bridge portion, and the first bridge portion is connected to the gate of the driving transistor and the first electrode of the second transistor through via holes.

15. The display panel according to claim 14, wherein: The pixel driving circuit further comprises a capacitor, a first electrode of the capacitor is connected to the gate of the driving transistor, and a second electrode of the capacitor is connected to the first power line; The first conductive layer includes a first conductive portion, the first conductive portion is used to form a gate of the driving transistor, and the first conductive portion is multiplexed as a first electrode of the capacitor; The display panel further includes: a second conductive layer located between the third conductive layer and the first conductive layer, the second conductive layer comprising a second conductive portion, an orthographic projection of the second conductive portion on the base substrate at least partially overlapping with an orthographic projection of the first conductive portion on the base substrate, the second conductive portion being used to form a second electrode of the capacitor; The first bridge portion includes a main portion and an extension portion, the main portion is connected to the gate of the driving transistor and the first electrode of the second transistor through a via, and the orthographic projection of the extension portion on the base substrate and the orthographic projection of the second conductive portion on the base substrate at least partially overlap; The main body includes a first side, the extension includes a second side, the first side is connected to the second side, and an angle between an orthographic projection of the first side on the base substrate and an orthographic projection of the second side on the base substrate is less than 180°.

16. The display panel according to claim 1, wherein The pixel driving circuit further includes a driving transistor and a second transistor, wherein a first electrode of the second transistor is connected to a gate of the driving transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor; The display panel further includes: a first active layer, located on one side of the base substrate, wherein at least a portion of the first active layer is used to form a channel region of the driving transistor; a first conductive layer, located on a side of the first active layer facing away from the base substrate, wherein at least a portion of the first conductive layer is used to form a gate of the driving transistor; a second active layer, located on a side of the first conductive layer facing away from the substrate, wherein at least a portion of the second active layer is used to form a channel region of the second transistor; a third conductive layer, located on a side of the second active layer facing away from the substrate, wherein at least a portion of the third conductive layer is used to form a top gate of the second transistor; The third conductive layer further includes a second bridge portion, and the second bridge portion is connected to the second electrode of the second transistor and the second electrode of the driving transistor through via holes.

17. The display panel according to claim 1, wherein: The pixel driving circuit further includes a driving transistor, a second transistor, a fifth transistor, and an eighth transistor, wherein a first electrode of the second transistor is connected to the gate of the driving transistor, a second electrode of the second transistor is connected to the second electrode of the driving transistor, a first electrode of the fifth transistor is connected to the first power line, a second electrode of the fifth transistor is connected to the first electrode of the driving transistor, a first electrode of the eighth transistor is connected to the third initial signal line, and a second electrode of the eighth transistor is connected to the first electrode of the driving transistor; The display panel further includes: a first active layer, located on one side of the base substrate, wherein at least a portion of the first active layer is used to form a channel region of the driving transistor; a first conductive layer, located on a side of the first active layer facing away from the base substrate, wherein at least a portion of the first conductive layer is used to form a gate of the driving transistor; a second active layer, located on a side of the first conductive layer facing away from the substrate, wherein at least a portion of the second active layer is used to form a channel region of the second transistor; a third conductive layer, located on a side of the second active layer facing away from the substrate, wherein at least a portion of the third conductive layer is used to form a top gate of the second transistor; a third conductive layer, located on one side of the substrate, the third conductive layer comprising a first gate line, a portion of the first gate line being used to form a top gate of the second transistor; The third conductive layer further includes a third bridge portion, and the third bridge portion is connected to the first electrode of the driving transistor, the second electrode of the fifth transistor, and the second electrode of the eighth transistor through via holes.

18. The display panel according to claim 1, wherein: The pixel driving circuit further includes a driving transistor and a second transistor, wherein a first electrode of the second transistor is connected to a gate of the driving transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor; The display panel further includes: a third conductive layer, located on one side of the substrate, the third conductive layer comprising a first gate line, a portion of the first gate line being used to form a top gate of the second transistor; A fourth conductive layer is located on a side of the third conductive layer away from the base substrate, the fourth conductive layer includes a first gate connection line, the orthographic projection of the first gate connection line on the base substrate extends along the row direction, and the first gate connection line is connected to the first gate line through one or more vias.

19. The display panel according to claim 1, wherein: The pixel driving circuit further includes a driving transistor, a second transistor, and a fourth transistor, wherein a first electrode of the second transistor is connected to a gate of the driving transistor, a second electrode of the second transistor is connected to a second electrode of the driving transistor, a first electrode of the fourth transistor is connected to a data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor; The display panel further includes: a first active layer located on one side of the base substrate, the first active layer comprising a fourth active portion, the fourth active portion being used to form a channel region of the fourth transistor; a first conductive layer located on a side of the first conductive layer facing away from the base substrate, the first conductive layer comprising a second gate line, an orthographic projection of the second gate line on the base substrate covering an orthographic projection of the fourth active portion on the base substrate, and a portion of the second gate line forming a gate of the fourth transistor; a second active layer, located on a side of the first conductive layer away from the substrate, wherein a portion of the second active layer is used to form a channel region of the second transistor; a third conductive layer, located on a side of the second active layer facing away from the substrate, wherein a portion of the third conductive layer is used to form a top gate of the second transistor; A fourth conductive layer is located on a side of the third conductive layer away from the base substrate, the fourth conductive layer includes a second gate connection line, the orthographic projection of the second gate connection line on the base substrate extends along the row direction, and the second gate connection line is connected to the second gate line through one or more vias.

20. The display panel according to claim 1, wherein The pixel driving circuit further includes a driving transistor and a second transistor, wherein a first electrode of the second transistor is connected to a gate of the driving transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor; The display panel further includes: a first active layer, located on one side of the base substrate, wherein at least a portion of the first active layer is used to form a channel region of the driving transistor; a first conductive layer, located on a side of the first active layer facing away from the base substrate, wherein at least a portion of the first conductive layer is used to form a gate of the driving transistor; a second active layer located on a side of the first conductive layer facing away from the base substrate, the second active layer comprising a second active portion, and a twentieth active portion and a twenty-first active portion connected to both ends of the second active portion in a row direction, the second active portion being used to form a channel region of the second transistor, the twentieth active portion being used to form a first electrode of the second transistor, and the twenty-first active portion being used to form a second electrode of the second transistor; A third conductive layer is located on a side of the second active layer facing away from the base substrate, the third conductive layer includes a first gate line, the first gate line includes a third main body portion and a fifth protrusion portion connected to one side of the third main body portion in the column direction, the orthographic projection of the third main body portion on the base substrate extends along the row direction, and the orthographic projection of the fifth protrusion portion on the base substrate covers the orthographic projection of the second active portion on the base substrate.

21. The display panel according to claim 1, wherein The pixel driving circuit further includes a driving transistor, a fourth transistor, and a fifth transistor, wherein a first electrode of the fifth transistor is connected to a first power line, a second electrode of the fifth transistor is connected to the first electrode of the driving transistor, a first electrode of the fourth transistor is connected to a data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor; The display panel further includes: a first active layer, the first active layer including a third active portion, a fourth active portion, and a fifth active portion, the third active portion being used to form a channel region of the driving transistor, the fourth active portion being used to form a channel region of the fourth transistor, and the fifth active portion being used to form a channel region of the fifth transistor; a first conductive layer, located on a side of the first active layer facing away from the base substrate, the first conductive layer comprising a first conductive portion, a second gate line, and an enable signal line, an orthographic projection of the second gate line on the base substrate extending in a row direction and covering an orthographic projection of the fourth active portion on the base substrate, a portion of the second gate line being used to form a gate of the fourth transistor, an orthographic projection of the enable signal line on the base substrate extending in a row direction and covering an orthographic projection of the fifth active portion on the base substrate, and a portion of the enable signal line being used to form a gate of the fifth transistor; Wherein, in the same pixel driving circuit, the orthographic projection of the second gate line on the base substrate is located between the orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the enable signal line on the base substrate.

22. The display panel according to claim 1, wherein The pixel driving circuit further includes a driving transistor and a first transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to a second electrode of the driving transistor; The display panel further includes: a first active layer located on one side of the base substrate, the first active layer comprising a third active portion and a first active portion, the third active portion being used to form a channel region of the driving transistor, and the first active portion being used to form a channel region of the first transistor; In the same pixel driving circuit, the first active portion and the third active portion are connected in the same layer.

23. The display panel according to claim 1, wherein: Orthographic projections of two adjacent pixel driving circuits in the same pixel driving circuit row on the substrate are at least partially mirror-symmetrically arranged about a second symmetry axis, and the second symmetry axis extends along the column direction.

24. The display panel according to claim 1, wherein The pixel driving circuit further includes: driver transistor; a first transistor, wherein a first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to a second electrode of the driving transistor; a second transistor, wherein a first electrode of the second transistor is connected to the gate electrode of the driving transistor, and a second electrode of the second transistor is connected to the second electrode of the driving transistor; a fourth transistor, wherein a first electrode of the fourth transistor is connected to the data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor; a fifth transistor, wherein a first electrode of the fifth transistor is connected to the first power line, and a second electrode of the fifth transistor is connected to the first electrode of the driving transistor; a sixth transistor, wherein a first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and a second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit; an eighth transistor, wherein a first electrode of the eighth transistor is connected to the third initial signal line, and a second electrode of the eighth transistor is connected to the first electrode of the driving transistor; a capacitor, wherein a first electrode of the capacitor is connected to the gate of the driving transistor, and a second electrode of the capacitor is connected to the first power line; The first transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are P-type transistors, and the second transistor is an N-type transistor.

25. The display panel according to claim 24, wherein: The display panel further includes: a first active layer located on one side of the base substrate, wherein at least a portion of the first active layer is used to form channel regions of the first transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor; a first conductive layer, located on a side of the first active layer facing away from the base substrate, wherein at least a portion of the first conductive layer is used to form gates of the first transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor; a second active layer, located on a side of the first conductive layer facing away from the substrate, wherein at least a portion of the second active layer is used to form a channel region of the second transistor; The third conductive layer is located on a side of the second active layer away from the substrate. At least a portion of the structure of the third conductive layer is used to form a top gate of the second transistor.

26. A display device, wherein: The display device comprises the display panel according to any one of claims 1 to 25.

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