Display panel and manufacturing method therefor

Abstract

A display panel of the present invention may comprise: a base layer; a pixel defining layer disposed on the base layer and having a light-emitting opening defined therein; a partition disposed on the pixel defining layer and having a partition opening defined therein that overlaps the light-emitting opening; a plurality of light-emitting elements, each including an anode, a light-emitting pattern, and a cathode in contact with the partition, and disposed in the light-emitting opening and the partition opening; a plurality of lower encapsulation inorganic patterns covering each of the plurality of light-emitting elements; and a common inorganic layer covering the plurality of lower encapsulation inorganic patterns, and filling the space between the partition and the plurality of lower encapsulation inorganic patterns.

Description

Display panel and method for manufacturing the same

[0001] The present invention relates to a display panel and a method for manufacturing a display panel, and more particularly, to a display panel with improved display quality.

[0002] Display devices such as televisions, monitors, smartphones, and tablets that provide images to users include display panels that display images. Various display panels are being developed, including liquid crystal display panels, organic light emitting display panels, electro-wetting display panels, and electrophoretic display panels.

[0003] An organic light emitting display panel may include an anode, a cathode, and a light emitting pattern. The light emitting pattern may be separated for each light emitting region, and the cathode may provide a common voltage to each light emitting region.

[0004] The present invention aims to provide a display panel with improved display quality and a method for manufacturing the same in a display panel that forms a light-emitting element without using a metal mask.

[0005] According to one embodiment of the present invention, a display panel may include a base layer, a pixel defining film disposed on the base layer and defining a light emitting opening, a partition wall disposed on the pixel defining film and defining a partition wall opening overlapping the light emitting opening, an anode, a light emitting pattern, and a cathode contacting the partition wall, respectively, and may include a plurality of light emitting elements disposed within the light emitting opening and the partition wall opening, a plurality of lower encapsulating inorganic patterns covering each of the plurality of light emitting elements, and a common inorganic film covering the plurality of lower encapsulating inorganic patterns and filling a space between the partition wall and the plurality of lower encapsulating inorganic patterns.

[0006] The plurality of light-emitting elements may include first light-emitting elements, second light-emitting elements, and third light-emitting elements that each emit different colors, and the plurality of lower encapsulating inorganic patterns may include first lower encapsulating inorganic patterns covering the first light-emitting elements, second lower encapsulating inorganic patterns covering the second light-emitting elements, and third lower encapsulating inorganic patterns covering the third light-emitting elements.

[0007] The above common inorganic film can cover the dried first to third lower bag inorganic patterns.

[0008] The display panel may further include first additional bag weapon patterns covering the dried first lower bag weapon patterns, second additional bag weapon patterns covering the dried second lower bag weapon patterns, and third additional bag weapon patterns covering the dried third lower bag weapon patterns.

[0009] The above common weapon film can cover the first to third additional bag weapon patterns.

[0010] The above common weapon membrane has an internal region defined, and the internal region may be empty.

[0011] The above inner region may have a shape that surrounds the light-emitting opening on a plane.

[0012] A portion of the above inner region may overlap with the plurality of lower bag weapon patterns on a plane.

[0013] Each of the plurality of lower bag weapon patterns may include an upper surface, first side surfaces extending from the upper surface in the thickness direction of the base layer, lower surfaces extending from the first side surfaces toward the center of the anode in a plane, and second side surfaces extending from the lower surfaces in the thickness direction of the base layer.

[0014] The above common inorganic film can cover the upper surface, the first side surfaces, the lower surfaces, and the second side surfaces of each of the plurality of dried lower bag inorganic patterns.

[0015] The above common inorganic membrane may include an inorganic material.

[0016] The common inorganic film may include at least one of silicon nitride (SiNx) or silicon oxynitride (SiON).

[0017] The above display panel may further include an encapsulating organic film covering the common inorganic film and an upper encapsulating inorganic film covering the encapsulating organic film.

[0018] A method for manufacturing a display panel according to an embodiment of the present invention may include the steps of providing a preliminary display panel including a base layer, a pixel defining film disposed on the base layer, and a preliminary barrier rib disposed on the pixel defining film, forming a barrier rib having a barrier rib opening defined from the preliminary barrier rib, etching the pixel defining film to form a light-emitting opening overlapping the barrier rib opening on a plane, forming a light-emitting element and a lower encapsulating inorganic pattern covering the light-emitting element within the light-emitting opening and the barrier rib opening, and drying an outer surface of the barrier rib and the lower encapsulating inorganic pattern.

[0019] The step of forming the lower encapsulating inorganic pattern may include a step of forming a first light-emitting element and a first lower encapsulating inorganic pattern covering the first light-emitting element, a step of forming a second light-emitting element and a second lower encapsulating inorganic pattern covering the second light-emitting element, and a step of forming a third light-emitting element and a third lower encapsulating inorganic pattern covering the third light-emitting element.

[0020] The method for manufacturing the display panel may further include a step of forming a common inorganic film covering the first to third lower encapsulating inorganic patterns.

[0021] The method for manufacturing the display panel may further include a step of forming an additional encapsulating weapon pattern covering the lower encapsulating weapon pattern.

[0022] The step of drying the outer surface of the partition wall and the first lower encapsulating inorganic pattern may include, after the step of forming the first light-emitting element and the first lower encapsulating inorganic pattern, a step of drying the outer surface of the partition wall and the outer surface of the first lower encapsulating inorganic pattern, after the step of forming the second light-emitting element and the second lower encapsulating inorganic pattern, a step of drying the outer surface of the partition wall and the outer surface of the second lower encapsulating inorganic pattern, after the step of forming the third light-emitting element and the third lower encapsulating inorganic pattern, and a step of drying the outer surface of the partition wall and the outer surface of the third lower encapsulating inorganic pattern, and the step of forming the additional encapsulating inorganic pattern covering the lower encapsulating inorganic pattern may include, after the step of forming the first additional encapsulating inorganic pattern covering the first lower encapsulating inorganic pattern, a step of forming a second additional encapsulating inorganic pattern covering the second lower encapsulating inorganic pattern, and a step of forming a third additional encapsulating inorganic pattern covering the third lower encapsulating inorganic pattern. It may include a forming step.

[0023] The method for manufacturing the display panel may further include a step of forming a common inorganic film covering the first to third additional bag inorganic patterns.

[0024] According to one embodiment of the present invention, a display panel includes a base layer, a pixel defining film disposed on the base layer and having a light-emitting opening defined therein, a partition wall disposed on the pixel defining film and having a partition wall opening overlapping the light-emitting opening defined therein, an anode, a light-emitting pattern, and a cathode contacting the partition wall, respectively, a plurality of light-emitting elements disposed within the light-emitting opening and the partition wall opening, and a plurality of lower encapsulating inorganic patterns covering each of the plurality of light-emitting elements, wherein only an inorganic material may be disposed between the lower encapsulating inorganic pattern and an upper surface of the partition wall.

[0025] As described above, organic matter that absorbs moisture between the lower encapsulation inorganic pattern and the barrier rib can be removed, and any remaining moisture can be removed through a drying process. Therefore, the phenomenon of foreign matter entering through moisture between the lower encapsulation inorganic pattern and the barrier rib can be reduced or eliminated. As a result, pixel defects (e.g., dark spots and pixel shrinkage) in the display panel caused by foreign matter can be reduced or eliminated.

[0026] In addition, in the past, the sealing organic film was thickened to control the thin film sealing layer to have a low dielectric constant, but since the internal region is defined in the common inorganic film of the present invention, the common inorganic film can have a low dielectric constant close to 1. Therefore, the thickness of the sealing organic film of the present invention can be reduced, and the touch sensitivity can be improved by reducing the thickness of the sealing organic film.

[0027] FIG. 1A is a perspective view of a display device according to one embodiment of the present invention.

[0028] Figure 1b is an exploded perspective view of a display device according to one embodiment of the present invention.

[0029] Figure 2 is a cross-sectional view of a display module according to one embodiment of the present invention.

[0030] Figure 3 is a plan view of a display panel according to one embodiment of the present invention.

[0031] FIG. 4 is an enlarged plan view of a portion of a display area of ​​a display panel according to one embodiment of the present invention.

[0032] Figure 5 is a cross-sectional view taken along the line II' of Figure 3.

[0033] Fig. 6 is a cross-sectional view taken along the II-II' cutting line of Fig. 4.

[0034] FIGS. 7A to 8E are cross-sectional views illustrating some of the steps of a method for manufacturing a display panel according to one embodiment of the present invention.

[0035] Fig. 9 is a cross-sectional view taken along the II-II' cutting line of Fig. 4.

[0036] In this specification, when it is said that a component (or region, layer, portion, etc.) is “on,” “connected to,” or “coupled to” another component, it means that it can be directly disposed / connected / coupled to the other component, or a third component may be disposed between them.

[0037] Identical drawing numbers indicate identical components. Furthermore, in the drawings, the thicknesses, proportions, and dimensions of the components are exaggerated for the purpose of effectively illustrating the technical content. "And / or" encompasses any combination of one or more of the associated components.

[0038] While terms such as "first" and "second" may be used to describe various components, these components should not be limited by these terms. These terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a "second component," and similarly, a second component may also be referred to as a "first component." Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0039] Additionally, terms such as "below," "lower," "above," and "upper" are used to describe the relationships between components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0040] It should be understood that terms such as "include" or "have" are intended to specify the presence of a feature, number, step, operation, component, part or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0041] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. Furthermore, terms defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an overly idealistic or overly formal sense unless explicitly defined herein.

[0042] In this specification, the expression "at least one of a, b, or c" may mean a only, b only, c only, both a and b, both a and c, both b and c, or all of a, b, and c, or a combination thereof. Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0043] FIG. 1a is a perspective view of a display device (DD) according to one embodiment of the present invention, and FIG. 1b is an exploded perspective view of a display device (DD) according to one embodiment of the present invention.

[0044] In one embodiment, the display device (DD) may be a large electronic device, such as a television, monitor, or outdoor billboard. Furthermore, the display device (DD) may be a small or medium-sized electronic device, such as a personal computer, a laptop computer, a personal digital assistant, an automobile navigation unit, a game console, a smartphone, a tablet, or a camera. However, this is merely exemplary, and other display devices may be employed without departing from the spirit of the present invention. In FIGS. 1A and 1B , the display device (DD) is exemplarily illustrated as a smartphone.

[0045] Referring to FIGS. 1A and 1B, the display device (DD) can display an image (IM) in a third direction (DR3) on a display surface (FS) parallel to each of the first direction (DR1) and the second direction (DR2). The image (IM) can include a still image as well as a moving image. In FIG. 1A, a clock window and icons are shown as examples of the image (IM). The display surface (FS) on which the image (IM) is displayed can correspond to the front surface of the display device (DD).

[0046] In this embodiment, the front (or upper surface) and the back (or lower surface) of each member are defined based on the direction in which the image (IM) is displayed. The front and the back face each other in a third direction (DR3), and the normal direction of each of the front and the back may be parallel to the third direction (DR3). Meanwhile, the directions indicated by the first to third directions (DR1, DR2, DR3) are relative concepts and may be converted into other directions. In this specification, "on a plane" may mean when viewed from the third direction (DR3).

[0047] A display device (DD) may include a window (WP), a display module (DM), and a housing (HAU). The window (WP) and the housing (HAU) may be combined with each other to form the exterior of the display device (DD).

[0048] The window (WP) may include an optically transparent insulating material. For example, the window (WP) may include glass or plastic. The front surface of the window (WP) may define a display surface (FS) of the display device (DD). The display surface (FS) may include a transmissive area (TA) and a bezel area (BZA). The transmissive area (TA) may be an optically transparent area. For example, the transmissive area (TA) may be an area having a visible light transmittance of about 90% or more.

[0049] The bezel area (BZA) may be an area having relatively low light transmittance compared to the transmissive area (TA). The bezel area (BZA) may define the shape of the transmissive area (TA). The bezel area (BZA) may be adjacent to the transmissive area (TA) and may surround the transmissive area (TA). However, this is merely an example, and the bezel area (BZA) of the window (WP) may be omitted. The window (WP) may include at least one functional layer selected from the group consisting of an anti-fingerprint layer, a hard coating layer, and an anti-reflection layer, and is not limited to any one embodiment.

[0050] A display module (DM) may be positioned at the bottom of a window (WP). The display module (DM) may be configured to substantially generate an image (IM). The image (IM) generated by the display module (DM) is displayed on the display surface (IS) of the display module (DM) and is externally visible to a user through a transparent area (TA).

[0051] A display module (DM) may include a display area (DA) and a non-display area (NDA). The display area (DA) may be an area activated by an electrical signal. The non-display area (NDA) may be adjacent to the display area (DA). The non-display area (NDA) may surround the display area (DA). The non-display area (NDA) is an area covered by a bezel area (BZA) and may not be visible from the outside.

[0052] The housing (HAU) can be combined with a window (WP). The housing (HAU) can be combined with the window (WP) to provide a predetermined internal space. A display module (DM) can be accommodated in the internal space.

[0053] The housing (HAU) may comprise a relatively rigid material. For example, the housing (HAU) may comprise a plurality of frames and / or plates made of glass, plastic, or metal, or a combination thereof. The housing (HAU) can reliably protect the components of the display device (DD) housed within the internal space from external impact.

[0054] FIG. 2 is a cross-sectional view of a display module (DM) according to one embodiment of the present invention.

[0055] Referring to FIG. 2, the display module (DM) may include a display panel (DP) and an input sensor (INS). Although not separately illustrated, the display device (DD, see FIG. 1a) according to an embodiment of the present invention may further include a protective member disposed on the lower surface of the display panel (DP) or an anti-reflection member and / or a window member disposed on the upper surface of the input sensor (INS).

[0056] The display panel (DP) may be an emissive display panel. However, this is merely an example and is not particularly limited thereto. For example, the display panel (DP) may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer in the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer in the inorganic light-emitting display panel may include quantum dots, quantum rods, or micro LEDs. Hereinafter, the display panel (DP) is described as an organic light-emitting display panel.

[0057] A display panel (DP) may include a base layer (BL), a circuit element layer (DP-CL) disposed on the base layer (BL), a display element layer (DP-OLED), and a thin film encapsulation layer (TFE). An input sensor (INS) may be directly disposed on the thin film encapsulation layer (TFE). In this specification, "configuration A is directly disposed on configuration B" means that no adhesive layer is disposed between configuration A and configuration B.

[0058] The base layer (BL) may include at least one plastic film. The base layer (BL) may include a flexible substrate such as a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite material substrate. The display area (DA) and non-display area (NDA) described in Fig. 1b may be defined identically in the base layer (BL).

[0059] A circuit element layer (DP-CL) may include at least one insulating layer and circuit elements. The insulating layer includes at least one inorganic layer and at least one organic layer. The circuit elements include signal lines, pixel driving circuits, etc.

[0060] The display element layer (DP-OLED) may include a barrier layer and a light-emitting element. The light-emitting element may include an anode, an intermediate layer, and a cathode.

[0061] A thin film encapsulation (TFE) layer may include multiple thin films. Some thin films may be positioned to improve optical efficiency, and some thin films may be positioned to protect the organic light-emitting diodes.

[0062] The input sensor (INS) obtains coordinate information of an external input. The input sensor (INS) may have a multilayer structure. The input sensor (INS) may include a single-layer or multi-layer conductive layer. In addition, the input sensor (INS) may include a single-layer or multi-layer insulating layer. The input sensor (INS) may detect an external input using a capacitive method. However, this is exemplary and is not limited thereto. For example, in another embodiment, the input sensor (INS) may detect an external input using an electromagnetic induction method or a pressure detection method. Meanwhile, in another embodiment of the present invention, the input sensor (INS) may be omitted.

[0063] Figure 3 is a plan view of a display panel according to one embodiment of the present invention. In this specification, "plan view" may mean a drawing viewed in the thickness direction of the substrate layer (BL) (i.e., the third direction DR3).

[0064] Referring to FIG. 3, a display panel (DP) may define a display area (DA) and a non-display area (NDA) surrounding the display area (DA). The display panel (DP) may include pixels (PX) and signal lines (SGL) electrically connected to the pixels (PX). The display panel (DP) may include a driving circuit (GDC) and a pad portion (PLD). The display area (DA) and the non-display area (NDA) may be distinguished by the arrangement of pixels (PX). The pixels (PX) may be arranged in the display area (DA). The driving circuit (GDC) and the pad portion (PLD) may be arranged in the non-display area (NDA).

[0065] The pixels (PX) can be arranged in a first direction (DR1) and a second direction (DR2). The pixels (PX) can include a plurality of pixel rows extending in the first direction (DR1) and arranged in the second direction (DR2) and a plurality of pixel columns extending in the second direction (DR2) and arranged in the first direction (DR1).

[0066] The signal lines (SGL) may include gate lines (GL), data lines (DL), a power line (PL), and a control signal line (CSL). Each of the gate lines (GL) may be connected to a corresponding pixel among the pixels (PX), and each of the data lines (DL) may be connected to a corresponding pixel among the pixels (PX). The power line (PL) may be electrically connected to the pixels (PX). The control signal line (CSL) may be connected to a driving circuit (GDC) to provide control signals to the driving circuit (GDC).

[0067] The driver circuit (GDC) may include a gate driver circuit. The gate driver circuit may generate gate signals and sequentially output the generated gate signals to gate lines (GL). The gate driver circuit may further output another control signal to the pixel driver circuit.

[0068] The pad portion (PLD) may be a portion to which a flexible printed circuit board is connected. The pad portion (PLD) may include pixel pads (D-PD), and the pixel pads (D-PD) may be pads for connecting the flexible printed circuit board to a display panel (DP). Each of the pixel pads (D-PD) may be connected to a corresponding signal line among the signal lines (SGL). The pixel pads (D-PD) may be connected to corresponding pixels (PX) through the signal lines (SGL). In addition, any one pixel pad among the pixel pads (D-PD) may be connected to a driving circuit (GDC).

[0069] Additionally, the pad portion (PLD) may further include input pads. The input pads may be pads for connecting the flexible circuit board to the input sensor (INS, see FIG. 2). However, the present invention is not limited thereto, and in another embodiment, the input pads may be arranged on the input sensor (INS, see FIG. 2) and connected to a separate circuit board from the pixel pads (D-PD). Alternatively, the input sensor (INS, see FIG. 2) may be omitted, and may not further include input pads.

[0070] Fig. 4 is an enlarged plan view of a portion of a display area (DA) of a display panel (DP, see Fig. 2) according to one embodiment of the present invention. Fig. 4 illustrates a plan view of a display module (DM, see Fig. 1b) as viewed from the display surface (IS, see Fig. 1b) of the display module (DM), and shows the arrangement of light-emitting areas (PXA-R, PXA-G, PXA-B).

[0071] Referring to FIG. 4, the display area (DA) may include first to third light-emitting areas (PXA-R, PXA-G, PXA-B) and a peripheral area (NPXA) surrounding the first to third light-emitting areas (PXA-R, PXA-G, PXA-B). The first to third light-emitting areas (PXA-R, PXA-G, PXA-B) may each correspond to areas where light provided from light-emitting elements is emitted. The first to third light-emitting areas (PXA-R, PXA-G, PXA-B) may be distinguished according to the color of light emitted toward the outside of the display module (DM, see FIG. 2).

[0072] The first to third light-emitting regions (PXA-R, PXA-G, PXA-B) can provide first to third color lights having different colors, respectively. For example, the first color light can be red light, the second color light can be green light, and the third color light can be blue light. However, examples of the first to third color lights are not necessarily limited to the above examples.

[0073] Each of the first to third light-emitting regions (PXA-R, PXA-G, PXA-B) can be defined as a region where the upper surface of the anode is exposed by a light-emitting opening described later. The peripheral region (NPXA) sets a boundary between the first to third light-emitting regions (PXA-R, PXA-G, PXA-B) and can prevent color mixing between the first to third light-emitting regions (PXA-R, PXA-G, PXA-B).

[0074] Each of the first to third light-emitting areas (PXA-R, PXA-G, PXA-B) may be provided in multiple numbers and may be repeatedly arranged in a predetermined arrangement within the display area (DA). For example, the first and third light-emitting areas (PXA-R, PXA-B) may be arranged alternately along the first direction (DR1) to form a 'first group'. The second light-emitting areas (PXA-G) may be arranged along the first direction (DR1) to form a 'second group'. Each of the 'first group' and the 'second group' may be provided in multiple numbers, and the 'first groups' and the 'second groups' may be arranged alternately along the second direction (DR2).

[0075] One second light-emitting region (PXA-G) can be spaced apart from one first light-emitting region (PXA-R) or one third light-emitting region (PXA-B) in a fourth direction (DR4). The fourth direction (DR4) can be defined as a direction between the first and second directions (DR1, DR2).

[0076] Meanwhile, FIG. 4 is an example of an arrangement form of the first to third light-emitting regions (PXA-R, PXA-G, PXA-B), but is not limited thereto and may be arranged in various forms. In one embodiment, the first to third light-emitting regions (PXA-R, PXA-G, PXA-B) may have a PENTILETM arrangement form as illustrated in FIG. 4. Alternatively, in another embodiment, the first to third light-emitting regions (PXA-R, PXA-G, PXA-B) may have a Stripe arrangement form or a Diamond (Diamond PixelTM) arrangement form.

[0077] The first to third light-emitting regions (PXA-R, PXA-G, PXA-B) may have various shapes on a plane. For example, the first to third light-emitting regions (PXA-R, PXA-G, PXA-B) may have shapes such as a polygon, a circle, or an ellipse. Fig. 4 illustrates, by way of example, the first and third light-emitting regions (PXA-R, PXA-B) having a square shape (or a rhombus shape) on a plane and the second light-emitting region (PXA-G) having an octagonal shape.

[0078] The first to third light-emitting regions (PXA-R, PXA-G, PXA-B) may have the same shape on a plane, or at least some of them may have different shapes. Fig. 4 illustrates, by way of example, the first and third light-emitting regions (PXA-R, PXA-B) having the same shape on a plane, and the second light-emitting region (PXA-G) having a different shape from the first and third light-emitting regions (PXA-R, PXA-B).

[0079] At least some of the first to third light-emitting regions (PXA-R, PXA-G, PXA-B) may have different areas on a plane. In one embodiment, the area of ​​the first light-emitting region (PXA-R) that emits red light may be larger than the area of ​​the second light-emitting region (PXA-G) that emits green light, and may be smaller than the area of ​​the third light-emitting region (PXA-B) that emits blue light. However, the relationship between the sizes of the areas between the first to third light-emitting regions (PXA-R, PXA-G, PXA-B) according to the light-emitting color is not limited thereto, and may vary depending on the design of the display module (DM, see FIG. 2). In addition, the first to third light-emitting regions (PXA-R, PXA-G, PXA-B) may also have the same areas on a plane.

[0080] Meanwhile, the shape, area, arrangement, etc. of the first to third light-emitting regions (PXA-R, PXA-G, PXA-B) of the display module (DM, see FIG. 2) of the present invention can be designed in various ways depending on the color of the emitted light or the size and configuration of the display module (DM, see FIG. 2), and is not limited to the embodiment illustrated in FIG. 4.

[0081] Fig. 5 is a cross-sectional view of a display panel taken along line I-I' of Fig. 3. In describing Fig. 5, reference will be made to Fig. 2, and descriptions of the same reference numerals will be omitted. Fig. 5 is an enlarged view of one light-emitting area (PXA) within a display area (DA, see Fig. 4), and the light-emitting area (PXA) of Fig. 5 may correspond to any one of the first to third light-emitting areas (PXA-R, PXA-G, PXA-B) of Fig. 4.

[0082] Referring to FIG. 5, the display panel (DP) may include a base layer (BL), a circuit element layer (DP-CL), a display element layer (DP-OLED), and a thin film encapsulation layer (TFE).

[0083] A display panel (DP) may include a plurality of insulating layers and semiconductor patterns, conductive patterns, signal lines, etc. The insulating layers, semiconductor layers, and conductive layers are formed by coating, deposition, etc. Thereafter, the insulating layers, semiconductor layers, and conductive layers can be selectively patterned by photolithography and etching. In this way, semiconductor patterns, conductive patterns, signal lines, etc. included in the circuit element layer (DP-CL) and the display element layer (DP-OLED) can be formed.

[0084] A circuit element layer (DP-CL) may be disposed on a base layer (BL). The circuit element layer (DP-CL) may include a buffer layer (BFL), a transistor (TR1), a signal transmission region (SCL), first to fifth insulating layers (10, 20, 30, 40, 50), an electrode (EE), and a plurality of connection electrodes (CNE1, CNE2).

[0085] A buffer layer (BFL) may be disposed on a base layer (BL). The buffer layer (BFL) may enhance bonding strength between the base layer (BL) and the semiconductor pattern. The buffer layer (BFL) may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0086] A semiconductor pattern may be arranged on a buffer layer (BFL). The semiconductor pattern may include polysilicon. However, the present invention is not limited thereto, and in another embodiment, the semiconductor pattern may include amorphous silicon or a metal oxide. FIG. 5 only illustrates some of the semiconductor patterns as an example, and further semiconductor patterns may be arranged in a plurality of light-emitting regions (PXA-R, PXA-G, PXA-B, see FIG. 4). The semiconductor patterns may be arranged in a specific pattern across the plurality of light-emitting regions (PXA-R, PXA-G, PXA-B). The semiconductor pattern may have different electrical properties depending on whether it is doped. The semiconductor pattern may include a first region having a high doping concentration and a second region having a low doping concentration. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a first region doped with a P-type dopant.

[0087] The first region is more conductive than the second region and essentially functions as an electrode or signal line. The second region may essentially correspond to the active (or channel) region of the transistor. In other words, a portion of the semiconductor pattern may be the active region of the transistor, another portion may be the source or drain of the transistor, and still another portion may be the conductive region.

[0088] The source (S), active (A), and drain (D) of the transistor (TR1) can be formed from a semiconductor pattern. FIG. 5 illustrates a portion of a signal transmission region (SCL) formed from a semiconductor pattern. Although not shown separately, the signal transmission region (SCL) can be connected to the drain (D) of the transistor (TR1) on a plane.

[0089] The first to fifth insulating layers (10, 20, 30, 40, 50) may be disposed on a buffer layer (BFL). The first to fifth insulating layers (10, 20, 30, 40, 50) may be inorganic layers or organic layers.

[0090] A first insulating layer (10) may be disposed on a buffer layer (BFL). The first insulating layer (10) may cover a source (S), an active (A), a drain (D), and a signal transmission region (SCL) of a transistor (TR1) disposed on the buffer layer (BFL). A gate (G) of the transistor (TR1) may be disposed on the first insulating layer (10). A second insulating layer (20) may be disposed on the first insulating layer (10) to cover the gate (G). An electrode (EE) may be disposed on the second insulating layer (20). A third insulating layer (30) may be disposed on the second insulating layer (20) to cover the electrode (EE).

[0091] The first connection electrode (CNE1) may be disposed on the third insulating layer (30). The first connection electrode (CNE1) may be connected to the signal transmission region (SCL) through a contact hole (CNT-1) penetrating the first to third insulating layers (10, 20, 30). The fourth insulating layer (40) may be disposed on the third insulating layer (30) to cover the first connection electrode (CNE1). The fourth insulating layer (40) may be an organic layer.

[0092] The second connection electrode (CNE2) may be disposed on the fourth insulating layer (40). The second connection electrode (CNE2) may be connected to the first connection electrode (CNE1) through a contact hole (CNT-2) penetrating the fourth insulating layer (40). The fifth insulating layer (50) may be disposed on the fourth insulating layer (40) to cover the second connection electrode (CNE2). The fifth insulating layer (50) may be an organic layer.

[0093] The display element layer (DP-OLED) may be disposed on the circuit element layer (DP-CL). The display element layer (DP-OLED) may include a light emitting element (ED), a sacrificial pattern (SP), a pixel defining layer (PDL), and a barrier rib (PW).

[0094] The light-emitting element (ED) may include an anode (AE, or first electrode), a light-emitting pattern (EP), and a cathode (CE, or second electrode). The light-emitting element (ED) may be disposed within a light-emitting opening (OP-E) and a partition opening (OP-P), which will be described later.

[0095] The anode (AE) may be disposed on the fifth insulating layer (50) of the circuit element layer (DP-CL). The anode (AE) may be a transparent electrode, a semi-transparent electrode, or a reflective electrode. The anode (AE) may be connected to the second connection electrode (CNE2) by a connection contact hole (CNT-3) defined by penetrating the fifth insulating layer (50). Therefore, the anode (AE) may be electrically connected to the signal transmission region (SCL) through the first and second connection electrodes (CNE1, CNE2), and may be electrically connected to a corresponding circuit element. The anode (AE) may include a single-layer or multi-layer structure. The anode (AE) may include a plurality of layers including ITO and Ag. For example, the anode (AE) may include a layer including ITO (hereinafter, a lower ITO layer), a layer including Ag disposed on the lower ITO layer (hereinafter, an Ag layer), and a layer including ITO disposed on the Ag layer (hereinafter, an upper ITO layer).

[0096] A sacrificial pattern (SP) may be positioned between an anode (AE) and a pixel defining layer (PDL). The sacrificial pattern (SP) may define (or have) a sacrificial opening (OP-S) that exposes a portion of the upper surface of the anode (AE). The sacrificial opening (OP-S) may overlap in a plane with an emission opening (OP-E) described below.

[0097] A pixel defining layer (PDL) may be disposed on a fifth insulating layer (50) of a circuit element layer (DP-CL). A light-emitting opening (OP-E) may be defined (or may have) in the pixel defining layer (PDL). The light-emitting opening (OP-E) may correspond to the anode (AE), and the pixel defining layer (PDL) may expose at least a portion of the anode (AE) through the light-emitting opening (OP-E).

[0098] In addition, the light-emitting aperture (OP-E) may correspond to the sacrificial aperture (OP-S) of the sacrificial pattern (SP). According to the present embodiment, the upper surface of the anode (AE) may be spaced apart from the pixel defining layer (PDL) in cross section with the sacrificial pattern (SP) interposed therebetween, thereby protecting the anode (AE) from damage during the process of forming the light-emitting aperture (OP-E).

[0099] On a plane, the area of ​​the light-emitting aperture (OP-E) may be smaller than the area of ​​the sacrificial aperture (OP-S). That is, the inner surface of the pixel defining layer (PDL) defining the light-emitting aperture (OP-E) may be closer to the center of the anode (AE) than the inner surface of the sacrificial pattern (SP) defining the sacrificial opening (OP-S). However, this is not limited to this, and in another embodiment, the inner surface of the sacrificial pattern (SP) defining the sacrificial opening (OP-S) may be substantially aligned with the inner surface of the pixel defining layer (PDL) defining the light-emitting aperture (OP-E). In this case, the light-emitting area (PXA) may be viewed as the area of ​​the anode (AE) exposed from the corresponding sacrificial opening (OP-S).

[0100] The pixel defining layer (PDL) may include an inorganic insulating material. For example, it may include silicon nitride (SiNx, or silicon nitride). The pixel defining layer (PDL) may be positioned between the anode (AE) and the barrier wall (PW), thereby blocking the anode (AE) and the barrier wall (PW) from being electrically connected to each other.

[0101] The light-emitting pattern (EP) may be disposed on the anode (AE). The light-emitting pattern (EP) may include an emitting layer including a light-emitting material. The light-emitting pattern (EP) may further include a hole injection layer (HIL) and a hole transport layer (HTL) disposed between the anode (AE) and the emitting layer, and may further include an electron transport layer (ETL) and an electron injection layer (EIL) disposed on the emitting layer. The light-emitting pattern (EP) may also be referred to as an 'organic layer' or an 'intermediate layer'.

[0102] The light emitting pattern (EP) can be patterned by a tip portion defined in the barrier rib (PW). This will be described in detail later in the description of the method for manufacturing a display panel. The light emitting pattern (EP) can be arranged inside the sacrificial opening (OP-S) and the light emitting opening (OP-E). However, this is merely an example, and the light emitting pattern (EP) can be arranged inside at least one opening among the sacrificial opening (OP-S), the light emitting opening (OP-E), and the barrier rib opening (OP-P). The light emitting pattern (EP) can cover a portion of the upper surface of the pixel defining layer (PDL).

[0103] The cathode (CE) may be disposed on the light-emitting pattern (EP). The cathode (CE) may be patterned by a tip portion defined in the partition wall (PW). At least a portion of the cathode (CE) may be disposed in the partition wall opening (OP-P). In Fig. 5, the cathode (CE) is exemplarily illustrated as being disposed within the light-emitting opening (OP-E) and the partition wall opening (OP-P), but is not limited thereto. For example, in another embodiment, the cathode (CE) may be disposed only within the partition wall opening (OP-P).

[0104] The cathode (CE) may extend along the first inner surface of the first barrier layer (L1), and an end of the cathode (CE) may be in contact with the first barrier layer (L1). In FIG. 5, the cathode (CE) is exemplarily illustrated as being in contact with the first inner surface of the first barrier layer (L1) and the inner surface of the pixel defining layer (PDL), but is not limited thereto. For example, in another embodiment, the cathode (CE) may be formed in contact only with the first inner surface of the first barrier layer (L1).

[0105] The cathode (CE) may be conductive. The cathode (CE) may be formed of various conductive materials, such as metals, transparent conductive oxides (TCOs), or conductive polymers. For example, the cathode (CE) may include silver (Ag), magnesium (Mg), lead (Pb), copper (Cu), or compounds thereof.

[0106] In one embodiment of the present invention, the display element layer (DP-OLED) may further include a capping pattern (CP). The capping pattern (CP) may be disposed within the partition wall opening (OP-P) and may be disposed on the cathode (CE). The capping pattern (CP) may be patterned by a tip portion defined in the partition wall (PW). In one embodiment, the capping pattern (CP) may be omitted.

[0107] A barrier rib (PW) may be disposed on a pixel defining layer (PDL). A barrier rib opening (OP-P) may be defined in the barrier rib (PW). The barrier rib opening (OP-P) may overlap the emission aperture (OP-E) in a plane and expose at least a portion of the anode (AE).

[0108] The partition wall (PW) may include a plurality of sequentially stacked layers. For example, the partition wall (PW) may include a first partition wall layer (L1) and a second partition wall layer (L2). The first partition wall layer (L1) may be disposed on a pixel defining layer (PDL), and the second partition wall layer (L2) may be disposed on the first partition wall layer (L1). As illustrated in FIG. 5, the thickness of the first partition wall layer (L1) may be greater than the thickness of the second partition wall layer (L2), but is not limited thereto.

[0109] Each of the first barrier layer (L1) and the second barrier layer (L2) may include a conductive material. For example, the conductive material may include a metal, a transparent conductive oxide (TCO), or a combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy. The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide.

[0110] The partition wall (PW) may have an undercut shape in cross section. At least one of the plurality of layers of the partition wall (PW) may be sunken compared to the other layers, and thus the partition wall (PW) may include a tip portion. For example, the first partition wall layer (L1) may have an undercut shape with respect to the second partition wall layer (L2). The second partition wall layer (L2) may protrude toward the light-emitting opening (OP-E) more than the first partition wall layer (L1) to form a tip portion. A portion protruding from the first partition wall layer (L1) toward the light-emitting area (PXA) may be defined as a tip portion within the partition wall (PW). That is, the second inner surface of the second partition wall layer (L2) may be closer to the center of the anode (AE) than the first inner surface of the first partition wall layer (L1).

[0111] In Fig. 5, the first inner side of the first barrier layer (L1) and the second inner side of the second barrier layer (L2) are exemplarily illustrated as being perpendicular to the upper surface of the pixel defining layer (PDL), but this is not limited thereto. For example, in another embodiment, the barrier layer (PW) may have a tapered shape or a reverse tapered shape.

[0112] The bulkhead (PW) can receive a driving voltage, and accordingly, the cathode (CE) is electrically connected to the bulkhead (PW) and can receive the driving voltage.

[0113] A thin film encapsulation layer (TFE) may be disposed on a display element layer (DP-OLED). The thin film encapsulation layer (TFE) may include a lower encapsulation inorganic pattern (LIL), a common inorganic film (CLIL), an encapsulation organic film (OL), and an upper encapsulation inorganic film (UIL).

[0114] The lower encapsulating inorganic pattern (LIL) may correspond to (or overlap) the light-emitting opening (OP-E). The lower encapsulating inorganic pattern (LIL) may be arranged on the capping pattern (CP) to cover the light-emitting element (ED). A portion of the lower encapsulating inorganic pattern (LIL) may be formed within the partition opening (OP-P), and another portion of the lower encapsulating inorganic pattern (LIL) may be formed on the partition wall (PW).

[0115] The lower encapsulation inorganic pattern (LIL) may include an upper surface (U_LIL), first side surfaces (S1_LIL), lower surfaces (B_LIL), and second side surfaces (S2_LIL). The first side surfaces (S1_LIL) may extend from the upper surface (U_LIL) in a thickness direction of the base layer (BL) (e.g., in a direction opposite to the third direction (DR3)). The lower surfaces (B_LIL) may extend from the first side surfaces (S1_LIL) toward the center of the anode (AE). The second side surfaces (S2_LIL) may extend from the lower surfaces (B_LIL) in a thickness direction of the base layer (BL) (e.g., in a direction opposite to the third direction (DR3)).

[0116] The common inorganic film (CLIL) can cover the lower encapsulating inorganic pattern (LIL) and fill the space between the partition wall (PW) and the lower encapsulating inorganic pattern (LIL). At this time, the space between can be defined by the lower surface (B_LIL), the second side surface (S2_LIL), and the upper surface of the second partition wall layer. The common inorganic film (CLIL) can cover the dried lower encapsulating inorganic pattern (LIL). For example, the common inorganic film (CLIL) can cover the lower encapsulating inorganic pattern (LIL) when the outer surface of the lower encapsulating inorganic pattern (LIL) is dried and no residual moisture exists.

[0117] An internal region (ES) can be defined in the common inorganic layer (CLIL). The internal region (ES) can be an empty space formed during the common inorganic layer (CLIL) deposition process. For example, the internal region (ES) can be filled with a gas. The internal region (ES) can have a shape surrounding the light-emitting opening (OP-E) on a plane. A part of the internal region (ES) can overlap the lower encapsulating inorganic pattern (LIL) on a plane, and the internal region (ES) can overlap the partition wall (PW) on a plane. That is, the internal region (ES) is formed between the lower encapsulating inorganic pattern (LIL) and the partition wall (PW) and can overlap the lower encapsulating inorganic pattern (LIL) and the partition wall (PW) on a plane.

[0118] The common inorganic film (CLIL) can cover the upper surface (U_LIL), first side surfaces (S1_LIL), lower surfaces (B_LIL), and second side surfaces (S2_LIL) of the lower encapsulating inorganic pattern (LIL). That is, the common inorganic film (CLIL) can be formed by covering the outer surface of the lower encapsulating inorganic pattern (LIL) and surrounding the inner region (ES).

[0119] The common inorganic layer (CLIL) may include an inorganic material. For example, the common inorganic layer (CLIL) may include at least one of silicon nitride (SiNx) or silicon oxynitride (SiON). That is, only an inorganic material may exist between the lower encapsulating inorganic pattern (LIL) and the upper surface of the barrier wall (PW).

[0120] An encapsulating organic film (OL) may be disposed on a common inorganic film (CLIL). The encapsulating organic film (OL) may cover the common inorganic film (CLIL) and provide a flat upper surface. An upper encapsulating inorganic film (UIL) may be disposed on the encapsulating organic film (OL). The lower encapsulating inorganic pattern (LIL), the common inorganic film (CLIL), and the upper encapsulating inorganic film (UIL) may protect the display element layer (DP-OLED) from moisture / oxygen, and the encapsulating organic film (OL) may protect the display element layer (DP-OLED) from foreign substances such as dust particles.

[0121] Although FIG. 5 illustrates, by way of example, that the thin film encapsulation layer (TFE) includes a lower encapsulation inorganic pattern (LIL), a common inorganic film (CLIL), an encapsulation organic film (OL), and an upper encapsulation inorganic film (UIL), the present invention is not limited thereto. For example, in another embodiment, the thin film encapsulation layer (TFE) may further include additional encapsulation inorganic patterns (ALIL1, ALIL2, ALIL3, see FIG. 9) positioned between the lower encapsulation inorganic pattern (LIL) and the common inorganic film (CLIL). This will be described in detail later with reference to FIG. 9.

[0122] According to the present invention, organic substances that absorb moisture between the lower encapsulation inorganic pattern (LIL) and the barrier wall (PW) can be removed, and any remaining moisture can be removed through a drying process. Accordingly, the phenomenon of foreign substances entering through moisture between the lower encapsulation inorganic pattern (LIL) and the barrier wall (PW) can be reduced or eliminated. As a result, pixel defects (e.g., dark spots and pixel shrinkage) in the display panel caused by foreign substances can be effectively reduced or eliminated.

[0123] In addition, in the past, the thin film encapsulation layer (TFE) was controlled to have a low dielectric constant by thickening the encapsulation organic film (OL), but since the internal region (ES) is defined in the common inorganic film (CLIL) of the present invention, the common inorganic film (CLIL) can have a low dielectric constant close to a dielectric constant of 1. Therefore, the thickness of the encapsulation organic film (OL) of the present invention can be reduced, and the touch sensitivity can be effectively improved by reducing the thickness of the encapsulation organic film (OL).

[0124] Fig. 6 is a cross-sectional view taken along the line II-II' of Fig. 4. Fig. 6 is an enlarged view of one first light-emitting region (PXA-R), one second light-emitting region (PXA-G), and one third light-emitting region (PXA-B), and the description of one light-emitting region (PXA) of Fig. 5 can be equally applied to each of the first to third light-emitting regions (PXA-R, PXA-G, PXA-B) of Fig. 6. In describing Fig. 6, the same / similar reference numerals are used for the same / similar configurations as those described in Fig. 5, and duplicate descriptions are omitted.

[0125] Referring to FIG. 6, the display panel (DP) may include a base layer (BL), a circuit element layer (DP-CL), a display element layer (DP-OLED), and a thin film encapsulation layer (TFE). The display element layer (DP-OLED) may include light emitting elements (ED1, ED2, ED3), sacrificial patterns (SP1, SP2, SP3), a pixel defining layer (PDL), and a barrier rib (PW).

[0126] The light-emitting elements (ED1, ED2, ED3) may include a first light-emitting element (ED1), a second light-emitting element (ED2), and a third light-emitting element (ED3) that each emit different colors. The first light-emitting element (ED1), the second light-emitting element (ED2), and the third light-emitting element (ED3) may be provided in multiples. However, for convenience of explanation, they are expressed singly below.

[0127] The first light-emitting element (ED1) may include a first anode (AE1), a first light-emitting pattern (EP1), and a first cathode (CE1). The second light-emitting element (ED2) may include a second anode (AE2), a second light-emitting pattern (EP2), and a second cathode (CE2). The third light-emitting element (ED3) may include a third anode (AE3), a third light-emitting pattern (EP3), and a third cathode (CE3). The first to third anodes (AE1, AE2, AE3) may be provided as a plurality of patterns. In one embodiment, the first light-emitting pattern (EP1) may provide red light, the second light-emitting pattern (EP2) may provide green light, and the third light-emitting pattern (EP3) may provide blue light.

[0128] A pixel defining layer (PDL) may define first to third light-emitting openings (OP1-E, OP2-E, OP3-E). The first light-emitting opening (OP1-E) may expose at least a portion of the first anode (AE1). The second light-emitting opening (OP2-E) may expose at least a portion of the second anode (AE2). The third light-emitting opening (OP3-E) may expose at least a portion of the third anode (AE3).

[0129] In the present embodiment, the first light-emitting region (PXA-R) may be defined as a region exposed by the first light-emitting opening (OP1-E) on the upper surface of the first anode (AE1). The second light-emitting region (PXA-G) may be defined as a region exposed by the second light-emitting opening (OP2-E) on the upper surface of the second anode (AE2). The third light-emitting region (PXA-B) may be defined as a region exposed by the third light-emitting opening (OP3-E) on the upper surface of the third anode (AE3).

[0130] The sacrificial patterns (SP1, SP2, SP3) may include a first sacrificial pattern (SP1), a second sacrificial pattern (SP2), and a third sacrificial pattern (SP3). The first to third sacrificial patterns (SP1, SP2, SP3) may be disposed on the upper surfaces of the first to third anodes (AE1, AE2, AE3), respectively. The first to third sacrificial patterns (SP1, SP2, SP3) may have first to third sacrificial openings (OP1-S, OP2-S, OP3-S) that overlap the first to third light-emitting openings (OP1-E, OP2-E, OP3-E) on a plane, respectively.

[0131] In this embodiment, the partition wall (PW) may be defined with first to third light-emitting openings (OP1-E, OP2-E, OP3-E) and first to third partition wall openings (OP1-P, OP2-P, OP3-P) that overlap each other on a plane.

[0132] In the present embodiment, the first to third light-emitting patterns (EP1, EP2, EP3) and the first to third cathodes (CE1, CE2, CE3) may be physically separated by the second partition layer (L2) forming the tip portion and formed within the respective light-emitting openings (OP1-E, OP2-E, OP3-E) and partition openings (OP1-P, OP2-P, OP3-P). That is, the light-emitting elements (ED1, ED2, ED3) may be arranged within the partition openings (OP1-P, OP2-P, OP3-P) and the light-emitting openings (OP1-E, OP2-E, OP3-E). For example, the first light-emitting element (ED1) can be disposed within the first partition opening (OP1-P) and the first light-emitting opening (OP1-E), the second light-emitting element (ED2) can be disposed within the second partition opening (OP2-P) and the second light-emitting opening (OP2-E), and the third light-emitting element (ED3) can be disposed within the third partition opening (OP3-P) and the third light-emitting opening (OP3-E).

[0133] According to the present invention, a plurality of first light-emitting patterns (EP1) can be patterned and deposited in pixel units by the tip portion defined in the partition wall (PW). That is, the first light-emitting patterns (EP1) are commonly formed using an open mask, but can be easily divided into pixel units by the partition wall (PW).

[0134] On the other hand, when patterning the first light-emitting patterns (EP1) using a fine metal mask (FMM), a supporting spacer protruding from the conductive barrier rib must be provided to support the fine metal mask. In addition, since the fine metal mask is spaced apart from the base surface on which patterning is performed by the height of the barrier rib and the spacer, there may be limitations in implementing high resolution. In addition, since the fine metal mask comes into contact with the spacer, foreign substances may remain on the spacer after the patterning process of the first light-emitting patterns (EP1), or the spacer may be damaged by being imprinted by the fine metal mask. Accordingly, a defective display panel may be formed.

[0135] According to the present embodiment, by including a partition wall (PW), physical separation between light-emitting elements (ED1, ED2, ED3) can be easily achieved. Accordingly, current leakage or driving errors between adjacent light-emitting regions (PXA-R, PXA-G, PXA-B) can be prevented, and independent driving of each light-emitting element (ED1, ED2, ED3) can be enabled.

[0136] In particular, by patterning a plurality of first light-emitting patterns (EP1) without a mask that comes into contact with the internal structure within the display area (DA, see FIG. 1b), a display panel (DP) with improved process reliability due to a reduced defect rate can be provided. Since patterning is possible even without a separate support spacer protruding from the partition wall (PW), the area of ​​the light-emitting areas (PXA-R, PXA-G, PXA-B) can be miniaturized, thereby providing a display panel (DP) that is easy to implement with a high resolution.

[0137] In addition, when manufacturing a large-area display panel (DP), the process cost can be reduced by omitting the production of a large-area mask, and a display panel (DP) with improved process reliability can be provided because it is not affected by defects that may occur in a large-area mask. The description of the plurality of first light-emitting patterns (EP1) can be equally applied to the plurality of second and third light-emitting patterns (EP2, EP3).

[0138] The thin film encapsulation layer (TFE) may include lower encapsulation inorganic patterns (LIL), a common inorganic layer (CLIL), an encapsulation organic layer (OL), and an upper encapsulation inorganic layer (UIL).

[0139] The lower encapsulating inorganic patterns (LIL) may include a first lower encapsulating inorganic pattern (LIL1) covering a first light-emitting element (ED1), a second lower encapsulating inorganic pattern (LIL2) covering a second light-emitting element (ED2), and a third lower encapsulating inorganic pattern (LIL3) covering a third light-emitting element (ED3). The first to third lower encapsulating inorganic patterns (LIL1, LIL2, LIL3) may overlap the first to third light-emitting openings (OP1-E, OP2-E, OP3-E) on a plane, respectively. The first to third lower encapsulating inorganic patterns (LIL1, LIL2, LIL3) may be provided in a pattern form that is spaced apart from each other.

[0140] The common inorganic film (CLIL) covers the first to third lower encapsulating inorganic patterns (LIL1, LIL2, LIL3) and can fill a space between the partition wall (PW) and the first to third lower encapsulating inorganic patterns (LIL1, LIL2, LIL3). The common inorganic film (CLIL) can cover the dried first to third lower encapsulating inorganic patterns (LIL1, LIL2, LIL3). For example, the common inorganic film (CLIL) can cover the first to third lower encapsulating inorganic patterns (LIL1, LIL2, LIL3) in a state where the outer surfaces of the first to third lower encapsulating inorganic patterns (LIL1, LIL2, LIL3) are dried and no residual moisture exists.

[0141] The common inorganic layer (CLIL) may have internal regions (ES1, ES2, ES3) defined. The internal regions (ES1, ES2, ES3) may be empty regions formed during the common inorganic layer (CLIL) deposition process. For example, the internal regions (ES1, ES2, ES3) may be filled with gas. The internal regions (ES1, ES2, ES3) may include a first internal region (ES1), a second internal region (ES2), and a third internal region (ES3).

[0142] The first inner region (ES1) may have a shape that surrounds the first light-emitting opening (OP1-E) on a plane. A part of the first inner region (ES1) may overlap the first lower encapsulating inorganic pattern (LIL1) on a plane, and the first inner region (ES1) may overlap the partition wall (PW) on a plane. That is, the first inner region (ES1) is formed between the first lower encapsulating inorganic pattern (LIL1) and the partition wall (PW) and may overlap the first lower encapsulating inorganic pattern (LIL1) and the partition wall (PW) on a plane.

[0143] The second inner region (ES2) may have a shape that surrounds the second light-emitting opening (OP2-E) on a plane. A part of the second inner region (ES2) may overlap the second lower encapsulating inorganic pattern (LIL2) on a plane, and the second inner region (ES2) may overlap the partition wall (PW) on a plane. That is, the second inner region (ES2) is formed between the second lower encapsulating inorganic pattern (LIL2) and the partition wall (PW) and may overlap the second lower encapsulating inorganic pattern (LIL2) and the partition wall (PW) on a plane.

[0144] The third inner region (ES3) may have a shape that surrounds the third light-emitting opening (OP3-E) on a plane. A part of the third inner region (ES3) may overlap the third lower encapsulating inorganic pattern (LIL3) on a plane, and the third inner region (ES3) may overlap the partition wall (PW) on a plane. That is, the third inner region (ES3) is formed between the third lower encapsulating inorganic pattern (LIL3) and the partition wall (PW) and may overlap the third lower encapsulating inorganic pattern (LIL3) and the partition wall (PW) on a plane.

[0145] The common inorganic film (CLIL) can cover the upper surface (U_LIL, see FIG. 5), the first side surfaces (S1_LIL, see FIG. 5), the lower surfaces (B_LIL, see FIG. 5), and the second side surfaces (S2_LIL, see FIG. 5) of each of the first to third lower encapsulating inorganic patterns (LIL1, LIL2, LIL3). That is, the common inorganic film (CLIL) can be formed to cover the outer surfaces of the first to third lower encapsulating inorganic patterns (LIL1, LIL2, LIL3) and surround the first to third inner regions (ES1, ES2, ES3).

[0146] FIGS. 7A to 8E are cross-sectional views illustrating some of the steps of a method for manufacturing a display panel according to one embodiment of the present invention. In describing FIGS. 7A to 8E, reference will be made to FIGS. 1 to 6 to describe the same / similar components using the same / similar reference numerals, and any duplicate description will be omitted.

[0147] A method for manufacturing a display panel according to an embodiment of the present invention may include the steps of providing a preliminary display panel including a base layer, a pixel defining film disposed on the base layer, and a preliminary barrier rib disposed on the pixel defining film, forming a barrier rib having a barrier rib opening defined from the preliminary barrier rib, etching the pixel defining film to form a light-emitting opening overlapping the barrier rib opening on a plane, forming a light-emitting element and a lower encapsulating inorganic pattern covering the light-emitting element within the light-emitting opening and the barrier rib opening, and drying an outer surface of the barrier rib and the lower encapsulating inorganic pattern.

[0148] Hereinafter, a method of forming three light-emitting elements (ED1, ED2, ED3) and lower encapsulating inorganic patterns (LIL1, LIL2, LIL3) covering the light-emitting elements (ED1, ED2, ED3), a common inorganic film (CLIL), an encapsulating organic film (OL), and an upper encapsulating inorganic film (UIL) will be described with reference to FIGS. 7A to 8E. The display panel (DP) formed through FIGS. 7A to 8E may correspond to the display panel (DP) of FIG. 6.

[0149] Referring to FIG. 7A, a method for manufacturing a display panel of the present invention may include a step of providing a preliminary display panel (DP-I). The preliminary display panel (DP-I) ​​provided in the present embodiment may include a base layer (BL), a circuit element layer (DP-CL), first to third anodes (AE1, AE2, AE3), first to third preliminary sacrificial patterns (SP1-I, SP2-I, SP3-I), a pixel defining layer (PDL), and a preliminary barrier rib (PW-I). The preliminary barrier rib (PW-I) may include a first preliminary barrier rib layer (L1-I) and a second preliminary barrier rib layer (L2-I).

[0150] The circuit element layer (DP-CL) may be formed through a typical circuit element manufacturing process in which an insulating layer, a semiconductor layer, and a conductive layer are formed by coating, deposition, etc., and the insulating layer, semiconductor layer, and conductive layer are selectively patterned by photolithography and etching processes to form a semiconductor pattern, a conductive pattern, and a signal line, etc.

[0151] The first anode (AE1) and the first preliminary sacrificial pattern (SP1-I) may be formed by the same patterning process, the second anode (AE2) and the second preliminary sacrificial pattern (SP2-I) may be formed by the same patterning process, and the third anode (AE3) and the third preliminary sacrificial pattern (SP3-I) may be formed by the same patterning process. The pixel defining layer (PDL) may be disposed on the base layer (BL). The pixel defining layer (PDL) may cover all of the first to third anodes (AE1, AE2, AE3) and the first to third preliminary sacrificial patterns (SP1-I, SP2-I, SP3-I).

[0152] The first preliminary barrier layer (L1-I) may be disposed on a pixel defining layer (PDL). The first preliminary barrier layer (L1-I) may be formed by a deposition process of a conductive material. The second preliminary barrier layer (L2-I) may be disposed on the first preliminary barrier layer (L1-I). The second preliminary barrier layer (L2-I) may also be formed by a deposition process of a conductive material. The first preliminary barrier layer (L1-I) and the second preliminary barrier layer (L2-I) may include a metal, a transparent conductive oxide (TCO), or a combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy. The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide. In one embodiment of the present invention, the first preliminary barrier layer (L1-I) may include aluminum (Al), and the second preliminary barrier layer (L2-I) may include titanium (Ti), but the materials of the first preliminary barrier layer (L1-I) and the second preliminary barrier layer (L2-I) are not limited thereto.

[0153] Referring to FIG. 7b thereafter, the method for manufacturing a display panel of the present invention may include a step of forming a first photoresist layer (PR1) on a preliminary barrier rib (PW-I). The first photoresist layer (PR1) may be formed by forming a preliminary photoresist layer on the preliminary barrier rib (PW-I) and then patterning the preliminary photoresist layer using a photo mask. Through the patterning process, a first photo opening (OP-PR1), a second photo opening (OP-PR2), and a third photo opening (OP-PR3) may be formed in the first photoresist layer (PR1). The first photo opening (OP-PR1) may overlap the first anode (AE1), the second photo opening (OP-PR2) may overlap the second anode (AE2), and the third photo opening (OP-PR3) may overlap the third anode (AE3) on a plane.

[0154] Hereafter, referring to FIGS. 7c and 7d, the method for manufacturing a display panel of the present invention may include a step of forming a partition wall (PW) in which partition wall openings (OP1-P, OP2-P, OP3-P) are defined from a preliminary partition wall (PW-I, refer to FIG. 7b). The step of forming the partition wall (PW) may include a step of forming a first partition wall layer (L1) and a second partition wall layer (L2) in which partition wall openings (OP1-P, OP2-P, OP3-P) are defined by etching a first preliminary partition wall layer (L1-I) and a second preliminary partition wall layer (L2-I).

[0155] First, as illustrated in FIG. 7c, the first preliminary barrier layer (L1-I) and the second preliminary barrier layer (L2-I) are etched in a first etching step. The first photoresist layer (PR1) can be used as a mask to dry etch the first preliminary barrier layer (L1-I) and the second preliminary barrier layer (L2-I). A portion of the preliminary barrier layer (PW-I) that does not overlap the first photoresist layer (PR1) on a plane can be etched and removed. For example, a first preliminary partition wall opening (OP1-PI) may be formed in a portion that overlaps and is removed with the first photo opening (OP-PR1), a second preliminary partition wall opening (OP2-PI) may be formed in a portion that overlaps and is removed with the second photo opening (OP-PR2), and a third preliminary partition wall opening (OP3-PI) may be formed in a portion that overlaps and is removed with the third photo opening (OP-PR3).

[0156] The first dry etching process in the present embodiment can be performed in an etching environment in which the etching selectivity between the first preliminary barrier rib layer (L1-I) and the second preliminary barrier rib layer (L2-I) is substantially the same. Accordingly, the inner surface of the first preliminary barrier rib layer (L1-I) and the inner surface of the second preliminary barrier rib layer (L2-I) defining the preliminary barrier rib openings (OP1-PI, OP2-PI, OP3-PI) can be substantially aligned.

[0157] Thereafter, as illustrated in FIG. 7d, the step of secondary etching the first preliminary barrier layer (L1-I, see FIG. 7c) may be performed by wet etching the first preliminary barrier layer (L1-I) using the first photoresist layer (PR1) as a mask. Accordingly, a portion of the first preliminary barrier layer (L1-I) may be etched to form barrier openings (OP1-P, OP2-P, OP3-P). The barrier openings (OP1-P, OP2-P, OP3-P) may include a first barrier opening (OP1-P), a second barrier opening (OP2-P), and a third barrier opening (OP3-P). The first bulkhead opening (OP1-P) can be formed to overlap the first anode (AE1) on a plane, the second bulkhead opening (OP2-P) can be formed to overlap the second anode (AE2) on a plane, and the third bulkhead opening (OP3-P) can be formed to overlap the third anode (AE3) on a plane.

[0158] The secondary wet etching process in the present invention can be performed in an environment in which the etching selectivity between the first preliminary barrier layer (L1-I) and the second preliminary barrier layer (L2-I, see FIG. 7c) is high. Accordingly, the inner surface of the barrier wall (PW) defining the barrier openings (OP1-P, OP2-P, OP3-P) can have an undercut shape in cross-section. Specifically, since the etch rate of the first preliminary barrier layer (L1-I) with respect to the etching solution is greater than the etch rate of the second preliminary barrier layer (L2-I), the first preliminary barrier layer (L1-I) can be primarily etched. Accordingly, the first inner surface of the first barrier layer (L1) can be formed to be more recessed inward than the second inner surface of the second barrier layer (L2). A tip portion can be formed in the bulkhead (PW) by a portion of the second bulkhead layer (L2) that protrudes more than the first bulkhead layer (L1).

[0159] Thereafter, referring to FIG. 7e, the method for manufacturing a display panel of the present invention may include a step of etching a pixel defining layer (PDL) to form light-emitting openings (OP1-E, OP2-E, OP3-E) that overlap on a plane with the barrier rib openings (OP1-P, OP2-P, OP3-P).

[0160] The step of etching the pixel defining layer (PDL) can be performed by dry etching the pixel defining layer (PDL) using the first photoresist layer (PR1) and the barrier rib (PW, for example, the second barrier rib layer (L2)) as a mask. A portion of the pixel defining layer (PDL) that does not overlap with the first photoresist layer (PR1) and the barrier rib (PW) on a plane can be etched and removed. As a result, light-emitting openings (OP1-E, OP2-E, OP3-E) that overlap with the barrier rib openings (OP1-P, OP2-P, OP3-P) on a plane can be formed in the pixel defining layer (PDL). The light-emitting openings (OP1-E, OP2-E, OP3-E) may include a first light-emitting opening (OP1-E) that overlaps the first bulkhead opening (OP1-P) on a plane, a second light-emitting opening (OP2-E) that overlaps the second bulkhead opening (OP2-P) on a plane, and a third light-emitting opening (OP3-E) that overlaps the third bulkhead opening (OP3-P) on a plane.

[0161] Thereafter, referring to FIG. 7f, the method for manufacturing a display panel of the present invention may include a step of etching the first to third preliminary sacrificial patterns (SP1-I, SP2-I, SP3-I, refer to FIG. 7e) to form sacrificial patterns (SP1, SP2, SP3) in which sacrificial openings (OP1-S, OP2-S, OP3-S) overlapping with light-emitting openings (OP1-E, OP2-E, OP3-E) are defined, respectively.

[0162] The step of etching the first to third preliminary sacrificial patterns (SP1-I, SP2-I, SP3-I) may be performed by wet etching the first to third preliminary sacrificial patterns (SP1-I, SP2-I, SP3-I) using the first photoresist layer (PR1) and the barrier rib (PW, for example, the second barrier rib layer L2) as a mask. Parts of the first to third preliminary sacrificial patterns (SP1-I, SP2-I, SP3-I) that do not overlap with the first photoresist layer (PR1) and the barrier rib (PW) may be etched and removed. As a result, the sacrificial patterns (SP1, SP2, SP3) may be formed from the first to third preliminary sacrificial patterns (SP1-I, SP2-I, SP3-I).

[0163] The sacrificial patterns (SP1, SP2, SP3) may include a first sacrificial pattern (SP1), a second sacrificial pattern (SP2), and a third sacrificial pattern (SP3). A first sacrificial opening (OP1-S) may be formed in the first sacrificial pattern (SP1) and overlapped on a plane with a first light-emitting opening (OP1-E), a second sacrificial opening (OP2-S) may be formed in the second sacrificial pattern (SP2) and overlapped on a plane with a second light-emitting opening (OP2-E), and a third sacrificial opening (OP3-S) may be formed in the third sacrificial pattern (SP3) and overlapped on a plane with a third light-emitting opening (OP3-E).

[0164] The etching process of the sacrificial patterns (SP1, SP2, SP3) can be performed in an environment in which the etching selectivity between the sacrificial patterns (SP1, SP2, SP3) and the anodes (AE1, AE2, AE3) is high, thereby preventing the anodes (AE1, AE2, AE3) from being etched together. That is, by arranging the sacrificial patterns (SP1, SP2, SP3) having a higher etch rate than the anodes (AE1, AE2, AE3) between the pixel defining layer (PDL) and the anodes (AE1, AE2, AE3), the anodes (AE1, AE2, AE3) can be prevented from being etched together and damaged during the etching process.

[0165] Thereafter, referring to FIGS. 7g to 8b, the method for manufacturing a display panel of the present invention may include a step of forming light-emitting elements (ED1, ED2, ED3) and lower encapsulating inorganic patterns (LIL1, LIL2, LIL3) covering the light-emitting elements (ED1, ED2, ED3) within the light-emitting openings (OP1-E, OP2-E, OP3-E) and the partition openings (OP1-P, OP2-P, OP3-P) after removing the first photoresist layer (PR1, refer to FIG. 7f).

[0166] The step of forming the light-emitting elements (ED1, ED2, ED3) and the lower encapsulating inorganic pattern (LIL1, LIL2, LIL3) may include the step of forming the first light-emitting element (ED1) and the first lower encapsulating inorganic pattern (LIL1) covering the first light-emitting element (ED1), the step of forming the second light-emitting element (ED2) and the second lower encapsulating inorganic pattern (LIL2) covering the second light-emitting element (ED2), and the step of forming the third light-emitting element (ED3) and the third lower encapsulating inorganic pattern (LIL3) covering the third light-emitting element (ED3). The step of forming the first light-emitting element (ED1) and the first lower encapsulating inorganic pattern (LIL1) is described through FIGS. 7g to 7i, and the step of forming the second light-emitting element (ED2) and the second lower encapsulating inorganic pattern (LIL2) and the step of forming the third light-emitting element (ED3) and the third lower encapsulating inorganic pattern (LIL3) are described through FIGS. 8a to 8b.

[0167] Referring to FIG. 7g, the step of forming the first light-emitting element (ED1) may include the step of forming the first light-emitting pattern (EP1) and the step of forming the first cathode (CE1). The step of forming the first light-emitting pattern (EP1) may include a deposition process of the light-emitting layer. For example, the step of forming the first light-emitting pattern (EP1) may include the step of thermally evaporating the light-emitting layer. The light-emitting layers may be separated by tip portions formed in the partition walls (PW) and deposited inside the first to third partition wall openings (OP1-P, OP2-P, OP3-P) and on the partition walls (PW). The light-emitting layer formed inside the first partition wall opening (OP1-P) may form the first light-emitting pattern (EP1), and the light-emitting layers formed inside the second and third partition wall openings (OP2-P, OP3-P) and on the partition walls (PW) may form the first dummy layer (D1). That is, the first light-emitting pattern (EP1) can be formed to overlap the first partition opening (OP1-P) on the first anode (AE1) in a plane, and the first light-emitting pattern (EP1) can be formed to cover the first anode (AE1) and the pixel definition film (PDL).

[0168] The first dummy layer (D1) formed together in the step of forming the first light-emitting pattern (EP1) may include an organic material. For example, the first dummy layer (D1) may include the same material as the first light-emitting pattern (EP1). The first dummy layer (D1) may be formed simultaneously with the first light-emitting pattern (EP1) through a single process, and may be formed separately from the first light-emitting pattern (EP1) by the undercut shape of the partition wall (PW).

[0169] The step of forming the first cathode (CE1) may include a deposition process of a cathode layer. For example, the step of forming the first cathode (CE1) may include a step of sputtering the cathode layer. The cathode layer may be separated by a tip portion formed in the partition wall (PW) and deposited inside the first to third partition wall openings (OP1-P, OP2-P, OP3-P) and on the partition wall (PW). The cathode layer formed inside the first partition wall opening (OP1-P) may form the first cathode (CE1), and the cathode layers formed inside the second and third partition wall openings (OP2-P, OP3-P) and on the partition wall (PW) may form the second dummy layer (D2). That is, the first cathode (CE1) can be formed to overlap the first partition opening (OP1-P) on the first light-emitting pattern (EP1) in a plane, and the first cathode (CE1) can be formed to cover the first light-emitting pattern (EP1). In addition, the first cathode (CE1) can be formed to contact the inner surface of the first partition layer (L1) and extend along the inner surface of the first partition layer (L1).

[0170] The second dummy layer (D2) formed together with the first cathode (CE1) in the step of forming the first cathode (CE1) may include a conductive material. For example, the second dummy layer (D2) may include the same material as the first cathode (CE1). The second dummy layer (D2) may be formed simultaneously with the first cathode (CE1) through a single process, and may be formed separately from the first cathode (CE1) by the undercut shape of the partition wall (PW).

[0171] A first anode (AE1), a first light-emitting pattern (EP1), and a first cathode (CE1) can be sequentially stacked along a third direction (DR3). The first anode (AE1), the first light-emitting pattern (EP1), and the first cathode (CE1) can form a first light-emitting element (ED1).

[0172] The method for manufacturing a display panel of the present invention may include a step of forming a capping pattern (CP). The step of forming the capping pattern (CP) may include a deposition process of a capping pattern layer. The capping pattern layer may be separated by a tip portion formed in the partition wall (PW) and deposited inside the first to third partition wall openings (OP1-P, OP2-P, OP3-P) and on the partition wall (PW). The capping pattern layer formed inside the first partition wall opening (OP1-P) may form a capping pattern (CP), and the capping pattern layer formed inside the second and third partition wall openings (OP2-P, OP3-P) and on the partition wall (PW) may form a third dummy layer (D3).

[0173] The third dummy layer (D3) formed together with the capping pattern (CP) in the step of forming the capping pattern (CP) may include a conductive material. For example, the third dummy layer (D3) may include the same material as the capping pattern (CP). The third dummy layer (D3) may be formed simultaneously with the capping pattern (CP) through a single process, and may be formed separately from the capping pattern (CP) by the undercut shape of the partition wall (PW). In one embodiment of the present invention, the process of forming the capping pattern (CP) and the third dummy layer (D3) may be omitted.

[0174] Hereinafter, referring to FIG. 7h, the step of forming the first lower encapsulating inorganic pattern (LIL1) may include the step of depositing the first lower encapsulating inorganic layer (LIL1-I). The first lower encapsulating inorganic layer (LIL1-I) may be formed through a deposition process. In one embodiment, the first lower encapsulating inorganic layer (LIL1-I) may be formed through a chemical vapor deposition (CVD) process. The first lower encapsulating inorganic layer (LIL1-I) may be formed to cover the first cathode (CE1) (or, capping pattern (CP)) and the partition wall (PW). A portion of the first lower encapsulating inorganic layer (LIL1-I) may fill the first partition wall opening (OP1-P).

[0175] Thereafter, the method for manufacturing a display panel of the present invention may include a step of forming a second photoresist layer (PR2). In the step of forming the second photoresist layer (PR2), the second photoresist layer (PR2) may be formed by forming a preliminary photoresist layer and then patterning the preliminary photoresist layer using a photo mask. Through the patterning process, the second photoresist layer (PR2) may be formed in a pattern shape corresponding to the first light-emitting element (ED1).

[0176] Referring to FIG. 7i, the step of forming the first lower encapsulating inorganic pattern (LIL1) may include the step of removing a portion of the first lower encapsulating inorganic layer (LIL1-I, see FIG. 7h) that does not overlap with the first light-emitting element (ED1).

[0177] The step of removing a portion of the first lower encapsulating inorganic layer (LIL1-I) that does not overlap the first light-emitting element (ED1) may be performed by dry etching the first lower encapsulating inorganic layer (LIL1-I) using the second photoresist layer (PR2) as a mask. A portion of the first lower encapsulating inorganic layer (LIL1-I) that does not overlap the second photoresist layer (PR2) may be removed, and a first lower encapsulating inorganic pattern (LIL1) may be formed from a portion of the first lower encapsulating inorganic layer (LIL1-I) that is not etched.

[0178] Thereafter, the method for manufacturing a display panel of the present invention may include a step of removing dummy layers (D1, D2, D3). Among the dummy layers (D1, D2, D3), the second and third dummy layers (D2, D3) may be removed by wet etching, and among the dummy layers (D1, D2, D3), the first dummy layer (D1) may be removed by a stripper.

[0179] Thereafter, referring to FIG. 8a, the method for manufacturing a display panel of the present invention can form a second light-emitting element (ED2), a capping pattern (CP), and a second lower encapsulating inorganic pattern (LIL2) after removing the second photoresist layer (PR2, refer to FIG. 7i). The process of forming the second light-emitting element (ED2), the capping pattern (CP), and the second lower encapsulating inorganic pattern (LIL2) can be substantially the same as the process of forming the first light-emitting element (ED1), the capping pattern (CP), and the first lower encapsulating inorganic pattern (LIL1) described through FIGS. 7g to 7i.

[0180] Hereafter, referring to FIG. 8b, the method for manufacturing a display panel of the present invention can form a third light-emitting element (ED3), a capping pattern (CP), and a third lower encapsulating inorganic pattern (LIL3). The process of forming the third light-emitting element (ED3), the capping pattern (CP), and the third lower encapsulating inorganic pattern (LIL3) can be substantially the same as the process of forming the first light-emitting element (ED1), the capping pattern (CP), and the first lower encapsulating inorganic pattern (LIL1) described through FIGS. 7g to 7i.

[0181] Hereafter, referring to FIG. 8c, the method for manufacturing a display panel of the present invention may include a step of drying the outer surfaces of the partition wall (PW) and the lower encapsulating inorganic patterns (LIL1, LIL2, LIL3). The step of drying the outer surfaces of the partition wall (PW) and the lower encapsulating inorganic patterns (LIL1, LIL2, LIL3) may be a step of providing heat (HT) to the outer surfaces of the partition wall (PW) and the lower encapsulating inorganic patterns (LIL1, LIL2, LIL3) to evaporate residual moisture. As a result of the above process, moisture may not exist on the outer surfaces of the partition wall (PW) and the lower encapsulating inorganic patterns (LIL1, LIL2, LIL3).

[0182] According to the present invention, an organic material (the first dummy layer (D1) of FIG. 7i) that absorbs moisture between the lower encapsulating inorganic pattern (LIL) and the barrier wall (PW) can be removed, and any remaining moisture can be removed through a drying process. Accordingly, the phenomenon of foreign matter entering through moisture between the lower encapsulating inorganic pattern (LIL) and the barrier wall (PW) can be reduced or eliminated. As a result, pixel defects (dark spots, pixel shrinkage, etc.) of a display panel caused by foreign matter can be effectively reduced or eliminated.

[0183] Thereafter, referring to FIG. 8d, the method for manufacturing a display panel of the present invention may include a step of forming a common inorganic film (CLIL) covering the first to third lower encapsulating inorganic patterns (LIL1, LIL2, LIL3).

[0184] A common inorganic film (CLIL) can be formed to cover the dried first to third lower encapsulating inorganic patterns (LIL1, LIL2, LIL3). The common inorganic film (CLIL) can cover the upper surface (U_LIL, see FIG. 5), first side surfaces (S1_LIL, see FIG. 5), lower surfaces (B_LIL, see FIG. 5), and second side surfaces (S2_LIL, see FIG. 5) of each of the first to third lower encapsulating inorganic patterns (LIL1, LIL2, LIL3).

[0185] A common inorganic layer (CLIL) can fill the space between the partition wall (PW) and the first to third lower encapsulating inorganic patterns (LIL1, LIL2, LIL3). In the process of forming the common inorganic layer (CLIL), first to third internal regions (ES1, ES2, ES3), which are empty spaces, can be formed. The first internal region (ES1) is formed between the first lower encapsulating weapon pattern (LIL1) and the partition wall (PW) and can overlap the first lower encapsulating weapon pattern (LIL1) and the partition wall (PW) on a plane, the second internal region (ES2) is formed between the second lower encapsulating weapon pattern (LIL2) and the partition wall (PW) and can overlap the second lower encapsulating weapon pattern (LIL2) and the partition wall (PW) on a plane, and the third internal region (ES3) is formed between the third lower encapsulating weapon pattern (LIL3) and the partition wall (PW) and can overlap the third lower encapsulating weapon pattern (LIL3) and the partition wall (PW) on a plane. That is, the common inorganic film (CLIL) can be formed by covering the outer surfaces of the first to third lower bag inorganic patterns (LIL1, LIL2, LIL3) and surrounding the first to third internal regions (ES1, ES2, ES3).

[0186] In the past, the thin film encapsulation layer (TFE) was adjusted to have a low dielectric constant by thickening the encapsulation organic film (OL), but as the internal region (ES) is defined in the common inorganic film (CLIL) of the present invention, the common inorganic film (CLIL) can have a low dielectric constant close to 1. Therefore, the thickness of the encapsulation organic film (OL) of the present invention can be reduced, and the touch sensitivity can be improved by reducing the thickness of the encapsulation organic film (OL).

[0187] Hereafter, referring to FIG. 8e, the method for manufacturing a display panel of the present invention may include a step of forming an encapsulating organic film (OL) and an upper encapsulating inorganic film (UIL) to complete the display panel (DP). The encapsulating organic film (OL) may be formed by applying an organic material using an inkjet method, but is not limited thereto. The encapsulating organic film (OL) provides a planarized upper surface. Thereafter, the upper encapsulating inorganic film (UIL) may be formed by depositing an inorganic material. Through this, a display panel (DP) including a base layer (BL), a circuit element layer (DP-CL), a display element layer (DP-OLED), and a thin film encapsulating layer (TFE) may be formed.

[0188] Fig. 9 is a cross-sectional view taken along the line II-II' of Fig. 4. The cross-sectional view of Fig. 9 corresponds to the cross-sectional view of Fig. 6 and illustrates another embodiment of the present invention. In describing Fig. 9, identical / similar reference numerals are used for components identical / similar to those described in Figs. 5 and 6, and duplicate descriptions are omitted.

[0189] Referring to FIG. 9, the display panel (DPa) may include a base layer (BL), a circuit element layer (DP-CL), a display element layer (DP-OLED), and a thin film encapsulation layer (TFEa). The thin film encapsulation layer (TFEa) may include lower encapsulation inorganic patterns (LIL1, LIL2, LIL3), additional encapsulation inorganic patterns (ALIL1, ALIL2, ALIL3), a common inorganic film (CLILa), an encapsulation organic film (OL), and an upper encapsulation inorganic film (UIL).

[0190] The thin film encapsulation layer (TFEa) of FIG. 9 may further include additional encapsulation inorganic patterns (ALIL1, ALIL2, ALIL3) than the thin film encapsulation layer (TFE) of FIG. 6. The additional encapsulation inorganic patterns (ALIL1, ALIL2, ALIL3) may include a first additional encapsulation inorganic pattern (ALIL1), a second additional encapsulation inorganic pattern (ALIL2), and a third additional encapsulation inorganic pattern (ALIL3).

[0191] The first additional bag inorganic pattern (ALIL1) can cover the dried first lower bag inorganic pattern (LIL1), the second additional bag inorganic pattern (ALIL2) can cover the dried second lower bag inorganic pattern (LIL2), and the third additional bag inorganic pattern (ALIL3) can cover the dried third lower bag inorganic pattern (LIL3). For example, each of the first to third additional bag inorganic patterns (ALIL1, ALIL2, ALIL3) can cover the first to third lower bag inorganic patterns (LIL1, LIL2, LIL3) in a state where the outer surfaces of the first to third lower bag inorganic patterns (LIL1, LIL2, LIL3) are dried and no residual moisture exists.

[0192] The first to third additional bag weapon patterns (ALIL1, ALIL2, ALIL3) can overlap the first to third light-emitting openings (OP1-E, OP2-E, OP3-E) on a plane, respectively, and the first to third additional bag weapon patterns (ALIL1, ALIL2, ALIL3) can be provided in the form of patterns spaced apart from each other.

[0193] The common inorganic film (CLILa) may be arranged on the first to third additional encapsulating inorganic patterns (ALIL1, ALIL2, ALIL3) to cover the first to third additional encapsulating inorganic patterns (ALIL1, ALIL2, ALIL3). The description of the common inorganic film (CLILa) may be substantially the same as the description of the common inorganic film (CLIL) of FIG. 6. Although the internal regions (ES1, ES2, ES3, see FIG. 6) are not illustrated in FIG. 9, the internal regions (ES1, ES2, ES3) may be defined in the common inorganic film (CLILa) of FIG. 9.

[0194] The process for manufacturing the display panel (DPa) of FIG. 9 may differ in some respects from the process for manufacturing the display panel (DP) described in FIGS. 7A to 8E. The method for manufacturing the display panel (DPa) of FIG. 9 may further include a step of forming additional encapsulation inorganic patterns (ALIL1, ALIL2, ALIL3) covering the lower encapsulation inorganic patterns (LIL1, LIL2, LIL3). For example, between the step of removing the dummy layers (D1, D2, D3) of FIG. 7I and the step of forming the second light-emitting element (ED2) of FIG. 8A, the method may further include a step of drying the outer surface of the partition wall (PW) and the first lower encapsulation inorganic pattern (LIL1) and a step of forming the first additional encapsulation inorganic pattern (ALIL1) covering the first lower encapsulation inorganic pattern (LIL1).

[0195] In addition, the method for manufacturing the display panel (DPa) of FIG. 9 may further include a step of drying the outer surface of the partition wall (PW) and the second lower encapsulating inorganic pattern (LIL2) and a step of forming a second additional encapsulating inorganic pattern (ALIL2) covering the second lower encapsulating inorganic pattern (LIL2) between the step of forming the second light-emitting element (ED2) and the second lower encapsulating inorganic pattern (LIL2) of FIG. 8a and the step of forming the third light-emitting element (ED3) of FIG. 8b.

[0196] In addition, the method for manufacturing the display panel (DPa) of FIG. 9 may further include, after the step of forming the third light-emitting element (ED3) and the third lower encapsulating inorganic pattern (LIL3) of FIG. 8b, a step of drying the outer surface of the partition wall (PW) and the third lower encapsulating inorganic pattern (LIL3) and a step of forming a third additional encapsulating inorganic pattern (ALIL3) covering the third lower encapsulating inorganic pattern (LIL3).

[0197] In the method for manufacturing the display panel (DPa) of FIG. 9, the step of drying the outer surfaces of the partition wall (PW) and the lower encapsulating inorganic patterns (LIL1, LIL2, LIL3) of FIG. 8c may be omitted. In addition, the method for manufacturing the display panel (DPa) of FIG. 9 may include a step of forming a common inorganic film (CLILa) covering the first to third additional encapsulating inorganic patterns (ALIL1, ALIL2, ALIL3).

[0198] While the present invention has been described above with reference to preferred embodiments, those skilled in the art or possessing common knowledge in the art will appreciate that various modifications and variations can be made to the present invention without departing from the spirit and scope of the invention. Therefore, the technical scope of the present invention is not necessarily limited to the details set forth in the detailed description of the specification.

[0199] An organic light emitting display panel (OLED) may include lower encapsulating inorganic patterns covering light emitting elements. An organic material that absorbs moisture between the lower encapsulating inorganic pattern (LIL) and a barrier wall (PW) can be removed, and any remaining moisture can be removed through a drying process. Accordingly, the phenomenon of foreign matter entering through moisture between the lower encapsulating inorganic pattern (LIL) and the barrier wall (PW) can be reduced or eliminated. The invention relates to a display device with improved reliability, in which pixel defects (dark spots, pixel shrinkage, etc.) of a display panel caused by foreign matter are reduced or eliminated, and thus has high industrial applicability.

Claims

1. Base layer; A pixel defining film disposed on the base layer and having a light-emitting opening defined therein; A barrier rib having a barrier opening defined therein and arranged on the pixel defining film and overlapping the light-emitting opening on a plane; A plurality of light emitting elements each comprising an anode, a light emitting pattern, and a cathode in contact with the barrier wall, and arranged within the light emitting opening and the barrier wall opening; A plurality of lower encapsulating inorganic patterns covering each of the plurality of light-emitting elements; and A display panel comprising a common inorganic film covering the plurality of lower bag weapon patterns and filling a space between the partition and the plurality of lower bag weapon patterns.

2. In paragraph 1, The above plurality of light-emitting elements include first light-emitting elements, second light-emitting elements, and third light-emitting elements each emitting different colors, A display panel wherein the plurality of lower encapsulating inorganic patterns include first lower encapsulating inorganic patterns covering the first light-emitting elements, second lower encapsulating inorganic patterns covering the second light-emitting elements, and third lower encapsulating inorganic patterns covering the third light-emitting elements.

3. In paragraph 2, The above common weapon film is a display panel covering the dried first to third lower bag weapon patterns.

4. In paragraph 3, First additional bag weapon patterns covering the dried first lower bag weapon patterns; Second additional bag weapon patterns covering the dried second lower bag weapon patterns; and A display panel further comprising third additional bag weapon patterns covering the dried third lower bag weapon patterns.

5. In paragraph 4, The above common weapon film is a display panel covering the first to third additional bag weapon patterns.

6. In paragraph 1, A display panel having an internal area defined in the above common weapon film, wherein the internal area is an empty space.

7. In paragraph 6, A display panel having a shape in which the inner region surrounds the light-emitting opening on a plane.

8. In paragraph 6, A display panel in which a portion of the inner area overlaps with the plurality of lower bag weapon patterns on a plane.

9. In paragraph 1, Each of the above multiple lower bag weapon patterns, top surface; First side surfaces extending in the thickness direction of the base layer from the upper surface; The lower surfaces extending from the first side surfaces toward the center of the anode on a plane; and A display panel including second side surfaces extending in the thickness direction of the base layer from the above-described surfaces.

10. In paragraph 9, A display panel in which the common inorganic film covers the upper surface, the first side surfaces, the lower surfaces, and the second side surfaces of each of the plurality of dried lower bag inorganic patterns.

11. In paragraph 1, The above common inorganic film is a display panel containing an inorganic material.

12. In paragraph 1, A display panel wherein the common inorganic film comprises at least one of silicon nitride (SiNx) or silicon oxynitride (SiON).

13. In paragraph 1, A bag organic film covering the above common inorganic film; and A display panel further comprising an upper encapsulating inorganic film covering the above encapsulating organic film.

14. A step of providing a preliminary display panel including a base layer, a pixel defining film disposed on the base layer, and a preliminary barrier rib disposed on the pixel defining film; A step of forming a bulkhead having a bulkhead opening defined from the above-mentioned preliminary bulkhead; A step of etching the pixel definition film to form a light-emitting opening that overlaps the barrier rib opening on a plane; A step of forming a light-emitting element and a lower encapsulating inorganic pattern covering the light-emitting element within the light-emitting opening and the partition opening; and A method for manufacturing a display panel, comprising the step of drying the outer surface of the above bulkhead and the lower bag weapon pattern.

15. In paragraph 14, The step of forming the above lower bag weapon pattern is: A step of forming a first light-emitting element and a first lower encapsulating inorganic pattern covering the first light-emitting element; A step of forming a second light-emitting element and a second lower encapsulating inorganic pattern covering the second light-emitting element; and A method for manufacturing a display panel, comprising the step of forming a third light-emitting element and a third lower encapsulating inorganic pattern covering the third light-emitting element.

16. In paragraph 15, A method for manufacturing a display panel further comprising the step of forming a common inorganic film covering the first to third lower bag inorganic patterns.

17. In paragraph 15, A method for manufacturing a display panel further comprising the step of forming an additional bag weapon pattern covering the lower bag weapon pattern.

18. In paragraph 17, The step of forming the additional bag weapon pattern covering the lower bag weapon pattern is: After the step of forming the first light-emitting element and the first lower encapsulating inorganic pattern, the step of drying the outer surface of the partition wall and the first lower encapsulating inorganic pattern; A step of forming a first additional bag weapon pattern covering the first lower bag weapon pattern; After the step of forming the second light-emitting element and the second lower encapsulating inorganic pattern, the step of drying the outer surface of the partition wall and the second lower encapsulating inorganic pattern; A step of forming a second additional bag weapon pattern covering the second lower bag weapon pattern; After the step of forming the third light-emitting element and the third lower encapsulating inorganic pattern, the step of drying the outer surface of the partition wall and the third lower encapsulating inorganic pattern; and A method for manufacturing a display panel, comprising the step of forming a third additional bag weapon pattern covering the third lower bag weapon pattern.

19. In paragraph 18, A method for manufacturing a display panel further comprising the step of forming a common weapon film covering the first to third additional bag weapon patterns.

20. Base layer; A pixel defining film disposed on the base layer and having a light-emitting opening defined therein; A barrier rib having a barrier opening defined therein and arranged on the pixel defining film and overlapping the light-emitting opening on a plane; A plurality of light emitting elements each including an anode, a light emitting pattern, and a cathode in contact with the barrier wall, and arranged within the light emitting opening and the barrier wall opening; and Including a plurality of lower encapsulating weapon patterns covering each of the plurality of light-emitting elements, A method for manufacturing a display panel in which only an inorganic material is placed between the lower bag weapon pattern and the upper surface of the bulkhead.

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