Control circuit for asynchronous circuit, and asynchronous circuit

Abstract

This control circuit for an asynchronous circuit comprises a clock generation circuit (220) that outputs a clock (clk) of an expandable / contractable pulse width. The clock generation circuit (220) comprises a delay adjustment circuit (101) that delays an inputted clock (clk) by a delay amount and outputs the result, and a logic circuit (205) that outputs, as a clock (clk), a signal expressing the result of a logical operation between the output of the delay adjustment circuit (101), a request signal (req), and an acknowledgement signal (ack). The clock (clk) is supplied to a register.

Description

Control circuit of asynchronous circuit and asynchronous circuit

[0001] The present disclosure relates to a control circuit for an asynchronous circuit and an asynchronous circuit.

[0002] There are two circuit design methods: synchronous and asynchronous. In synchronous design, wiring delays are automatically adjusted to prevent violations of register setup time, hold time, recovery time, and removal time.

[0003] On the other hand, in an asynchronous design, it is necessary to manually adjust the wiring delay using a delay buffer, an inverter chain, etc. Also, in an asynchronous design, the operating cycle is not constant, so it is extremely difficult to adjust the delay between registers.

[0004] One of the advantages of adopting asynchronous design is that it does not generate dynamic power consumption during standby. This feature can be a key technology depending on the application or use, and is attracting attention in fields that are based on handshake-type communication, such as NoC (Network on Chip).

[0005] For example, a control circuit for an asynchronous circuit is known, as described in Patent Document 1. The control circuit for an asynchronous circuit described in Patent Document 1 is a control circuit 1i for an asynchronous circuit in which each of a plurality of circuit blocks 4i, each composed of an arithmetic circuit 2i and a control circuit 1i, executes a predetermined operation by exchanging handshake signals (ini, outi, etc.) with the other circuit blocks, and the control circuit 1i has an input terminal (ini terminal) for inputting a handshake signal from the previous stage, an output terminal (outi terminal) for outputting a handshake signal to the next stage, an operation execution control signal terminal (muxi terminal) for the arithmetic circuit, and a latch signal terminal (lati terminal) for latching the result of the operation execution of the arithmetic circuit, and each arithmetic circuit 2i operates, under control of the control circuit 1i, in an execution mode in which an operation is executed and in a standby mode in which no operation is executed, and in the standby mode When the corresponding signal states of the input terminal (ini terminal), output terminal (outi terminal), operation execution control signal terminal (muxi terminal), and latch signal terminal (lati terminal) are represented by "0," the control circuit 1i detects that the input terminal (ini terminal) signal from the previous stage has transitioned from "1" to "0," sets the signal state of the operation execution control signal terminal (muxi terminal) to "1," and executes the operation of the operation circuit, and further sets the signal states of the output terminal (outi terminal) and latch signal terminal (lati terminal) to "1," and after the operation is completed, transitions the signal state of the latch signal terminal (lati terminal) to "0" to hold the operation execution result, and further comprises means for transitioning the signal states of the operation execution control signal terminal (muxi terminal) and output terminal (outi terminal) to "0."

[0006] JP 2008-181170 A

[0007] However, the asynchronous circuit described in Patent Document 1 is not suitable for large-scale circuits because the control is complicated.

[0008] Therefore, an object of the present disclosure is to provide an asynchronous circuit suitable for large-scale circuits and a control circuit for the asynchronous circuit.

[0009] The control circuit of the asynchronous circuit of the present disclosure includes a clock generation circuit that outputs a clock with an expandable pulse width. The clock generation circuit includes a delay adjustment circuit that delays an input clock by a delay amount and outputs the delayed clock, and a logic circuit that outputs a signal representing the result of a logical operation between the output of the delay adjustment circuit, a request signal, and an acknowledgment signal as a clock. The clock is supplied to a register.

[0010] The control circuit for an asynchronous circuit disclosed herein includes a clock generation circuit that outputs a clock with an expandable pulse width. The clock generation circuit includes a first delay adjustment circuit that delays an input clock by a first delay amount and outputs the clock, and a logic circuit. The control circuit for the asynchronous circuit further includes a second delay adjustment circuit that delays a request signal by a second delay amount and outputs the request signal, a counter that counts the number of clocks, a comparator that activates an acknowledgement signal when the counter value is equal to a predetermined value, and a third delay adjustment circuit that delays the acknowledgement signal by a third delay amount and outputs the acknowledgement signal. The logic circuit outputs a signal representing the result of a logical operation between the outputs of the first delay adjustment circuit, the second delay adjustment circuit, and the third delay adjustment circuit as a clock. The clock is supplied to a register.

[0011] The asynchronous circuits and control circuits of the present disclosure may be suitable for large scale circuits.

[0012] 6 is a diagram illustrating an asynchronous circuit of a reference example. FIG. 7 is a conceptual diagram of a clock generation circuit 220 included in the control circuit of the asynchronous circuit of embodiment 1. FIG. 8 is a transition diagram of signals in the circuit of FIG. 2. FIG. 9 is a diagram illustrating an asynchronous circuit of embodiment 1. FIG. 10 is a diagram illustrating the transition of a clock clk and data in registers included in each of register groups RG1, RG2, and RG3. FIG. 11 is a conceptual diagram of a control circuit 200 of the asynchronous circuit of embodiment 2. FIG. 12 is a transition diagram of signals in the circuit of FIG. 6. FIG. 13 is a diagram illustrating an asynchronous circuit of embodiment 2. FIG. 14 is a diagram illustrating an operation of comparing a binary counter value with a predetermined value "7". FIG. 15 is a diagram illustrating an operation of comparing a Gray code counter value with a predetermined value "7". FIG. 16 is a diagram illustrating delay adjustment by a second delay adjustment circuit 212. FIG. 17 is a diagram illustrating an example in which delay adjustment by a third delay adjustment circuit 213 is not performed. FIG. 18 is a diagram illustrating delay adjustment by a third delay adjustment circuit 213. FIG. 19 is a diagram illustrating an asynchronous circuit of embodiment 3. FIG. 19 is a diagram illustrating data capture in a conventional SPI communication interface. Fig. 10 is a diagram for explaining data capture in the interface 302 of embodiment 3. Fig. 11 is a diagram for explaining CRC (Cyclic Redundancy Check) processing in a conventional SPI communication interface. Fig. 12 is a diagram for explaining CRC processing in the interface 302 of embodiment 3. Fig. 13 is a diagram showing the format of data transmitted from a master through a MOSI signal line.

[0013] Hereinafter, embodiments will be described with reference to the drawings. Embodiment 1 Fig. 1 is a diagram showing an asynchronous circuit of a reference example.

[0014] In the asynchronous design of the reference example, the propagation delay between register groups RG1, RG2, ... is managed using CL (ClickElement) 1, CL2, .... This method requires adjusting the skew between each bit at the point (e.g., PT2) where the processing results between register groups RG1, RG2, ... merge. The skew adjustment includes the propagation delay (max, min) of the clock path, the propagation delay (max, min) of the data path, the setup time of register groups RG1, RG2, ..., and the hold time of register groups RG1, RG2, .... The timing requirements of all merged data must be met, and this delay adjustment is performed by inserting delay adjustment circuits DL1, DL2, ... between CL1, CL2, ..., or the like.

[0015] This method is not a problem for pipeline processing where data flows in a fixed direction, but when values ​​from later stages of the pipeline are used in earlier stages, or when processing results from other CLs (ClickElements) are merged, delay adjustment becomes complicated, making the design difficult.

[0016] The following embodiment can facilitate such an asynchronous design: Figure 2 is a conceptual diagram of a clock generation circuit 220 included in the control circuit of the asynchronous circuit of the first embodiment.

[0017] The clock generating circuit 220 outputs a clock clk having an expandable pulse width. The clock generating circuit 220 includes a control unit 201 and an oscillator 202.

[0018] The control unit 201 receives a request signal req and an acknowledgement signal ack from the outside, and sets the drive signal for driving the oscillator 202 to high level only when the request signal req is activated (high level) and the acknowledgement signal ack is inactivated (low level).

[0019] The oscillator 202 outputs a clock clk to the outside only when the drive signal from the control unit 201 is at a high level.

[0020] (Operation) FIG. 3 is a transition diagram of signals in the circuit of FIG.

[0021] When an external request signal req is set to high level, the control unit 201 sets the drive signal to high level, and the oscillator 202 outputs a clock clk when the drive signal is set to high level.

[0022] When an external acknowledge signal ack is set to high level, the control unit 201 sets the drive signal to low level. When the drive signal is set to low level, the oscillator 202 stops outputting the clock clk. After the acknowledge signal ack becomes high level, all signals in the asynchronous circuit are inactivated, so no dynamic power consumption occurs. All signals include data signals, control signals (including reset signals, enable signals, select signals, etc.), address signals, data bus signals, and interrupt signals.

[0023] 4 is a diagram showing the asynchronous circuit of the first embodiment. The asynchronous circuit includes register groups RG1, RG2, . . . , combinational circuits CM1, CM2, .

[0024] The clock clk is used to control the flow of data within the digital circuit and ensure data stability and timing. The clock clk is supplied to the register groups RG1, RG2, .... Each of the register groups RG1, RG2, ... comprises at least one register.

[0025] Data is read from or written into the register groups RG1, RG2, ... in synchronization with the rising or falling edge (or specific clock cycle) of the clock clk. The clock clk prevents data inconsistencies and conflicts and ensures signal timing. The clock clk propagates data from the register groups RG1, RG2, ... to the combinational circuits CM1, CM2, .... This ensures signal synchronization and reliability, and allows accurate data processing.

[0026] Combinational circuits CM1, CM2, ... are a type of digital circuit that immediately generates an output signal from an input signal. The operation of combinational circuits CM1, CM2, ... does not depend on timing information such as a clock (clk), because they apply a specific logic function to the input to generate an output.

[0027] Specifically, the combinational circuits CM1, CM2, ... perform the following processing: (1) Receiving Input Signals The combinational circuits CM1, CM2, ... receive a series of input signals. These input signals are usually represented by digital signals, and each input is represented by 1 or 0 (true / false value).

[0028] (2) Application of Logic Functions Combinational circuits CM1, CM2, ... apply a pre-designed logic function to the input signals. This function generates an output for each input combination. Logic functions are constructed using basic logic gates (AND, OR, NOT, etc.) to calculate the output according to the combination conditions.

[0029] (3) Generation of Output Signals Combinational circuits CM1, CM2, ... generate output signals calculated based on logic functions, which are supplied to other components in the digital circuit or to external devices depending on the purpose of the combinational circuits.

[0030] (4) No timing dependency: Combinational circuits are timing independent, so they instantly generate new outputs whenever there is a change in the input signals, which is very useful when combinational circuits are used for data processing and logic operations.

[0031] Combinational circuits CM1, CM2, ... are composed of logic gates, decoders, encoders, multiplexers, arithmetic logic units (ALUs), etc. These circuits are important in data processing and control, and are fundamental elements of logic design and digital circuits.

[0032] The asynchronous circuit of the first embodiment includes a control circuit 100 in place of CL1, CL2, . . . and delay adjustment circuits DL1, DL2, .

[0033] The control circuit 100 of the asynchronous circuit in Fig. 4 includes a clock generation circuit 220 that outputs a clock clk having an expandable pulse width. The clock generation circuit 220 includes a delay adjustment circuit 101 and an AND circuit 205. The AND circuit 205 and the delay adjustment circuit 101 in Fig. 4 are circuits that embody the control unit 201 and oscillator 202 in Fig. 2.

[0034] The delay adjustment circuit 101 outputs a delayed clock clkd obtained by delaying the clock clk output from the AND circuit 205 by a delay amount d.

[0035] The AND circuit 205 outputs the logical product of the request signal req, the inverted signal of the acknowledge signal ack, and the inverted signal of the delayed clock clkd as the clock clk.

[0036] The clock clk output from the clock generation circuit 220 is supplied to register groups RG1, RG2, .... The register groups RG1, RG2, ... output the data held therein to the subsequent combinational circuits CM1, CM2, ... at the timing of the rising edge of the clock clk.

[0037] (CTS) Synthesis and layout are performed with the output port PT of the clock clk as the starting point of CTS (Clock Tree Synthesis).

[0038] The CTS performs the following: (1) Generation of clock signals: A clock signal to be used in a digital circuit is generated. This clock signal must be synchronized with all parts of the digital circuit.

[0039] (2) Clock signal distribution: Clock signals are distributed evenly within the digital circuit, allowing each part to operate at the correct timing and maintaining data integrity.

[0040] (3) Minimizing delays: The clock signal delay within the circuit is minimized to meet timing requirements, allowing data signals to be processed accurately.

[0041] (4) Noise Reduction: Noise generated during clock signal propagation is reduced to improve signal quality. This process includes clock gating, buffer placement, and wiring routing. The CTS must be carefully tuned to meet the timing requirements of the clock signal and optimize power consumption. More specifically, the following is performed:

[0042] (A) Logic Synthesis Logic synthesis is the first step in digital design. In this step, a gate-level logic circuit is generated from a logic description (usually written in an HDL language). Designers convert the design from a high-level synthesis language into a combination of concrete gates and flip-flops, and evaluate the quality and performance of the design at this stage.

[0043] (B) Post-Synthesis Layout Generation Post-synthesis layout generation generates the actual transistor and wiring placement and connection information based on the synthesized logic circuit. At this stage, the physical shape and size of the circuit are determined.

[0044] (C) Moving to the CTS starting point: Once the post-synthesis layout generation is complete, the CTS process begins. The starting point for CTS is the physical layout of the specific design. At this point, the location of each component (gate, flip-flop, etc.) in the circuit is determined, and the physical characteristics of the design are known.

[0045] (D) Clock Tree Design Design the clock tree. This involves planning the propagation path of the clock signal from the source of the clock signal (usually a clock generator) to each part and designing a method to distribute the clock signal evenly.

[0046] (E) Adding buffers and minimizing delays: Proper buffer (amplifier) ​​placement and proper timing adjustment are performed, which minimizes delays and enables accurate distribution of clock signals.

[0047] (F) Wire Routing: Connections between wires and buffers in the clock tree are made, forming the actual wires and physically implementing the design.

[0048] (G) Timing Analysis and Optimization: After the clock tree design and routing are complete, timing analysis such as Static Timing Analysis (STA) is performed and optimization is performed as needed to ensure that the timing requirements of the clock signal are met.

[0049] (Delay Adjustment) In the reference example, a plurality of delay adjustment circuits are required, whereas in this embodiment, delay adjustment can be performed with only one delay adjustment circuit.

[0050] FIG. 5 is a diagram showing the clock clk and the transition of data in the registers included in each of the register groups RG1, RG2, and RG3.

[0051] Here, the data delays DLAY1, DLAY2, and DLAY3 are the processing times of the combinational circuits CM0 (not shown), CM1, and CM2.

[0052] One cycle of clk is generated by the signal circulating twice through a closed loop formed by the delay adjustment circuit 101 and the AND circuit 205. The high level period and low level period of clk are the delay amount d of the delay adjustment circuit 101.

[0053] The delay amount d of the delay adjustment is adjusted to match the maximum data delay DMAX among the data delays DLAY1, DLAY2, . . . based on the results of STA (satisfying the setup constraint and the hold constraint).

[0054] 5, DMAX=DLAY2. Specifically, the following condition must be satisfied: Under certain temperature or voltage conditions, a setup violation may occur internally, causing the circuit to not operate as intended.

[0055] 2×d>DMAX (1) According to this embodiment, the number of locations where delay adjustment specific to asynchronous design is performed can be reduced (to one location), thereby reducing the power consumption of the asynchronous circuit. Furthermore, the asynchronous circuit and the control circuit for the asynchronous circuit according to this embodiment are suitable for large-scale circuits.

[0056] Second Embodiment In pipeline processing, the number of cycles from the occurrence of a request (activation of a request signal req) to the completion of processing is often known. In such cases, it is possible to generate an acknowledgement signal ack within the control circuit of the asynchronous control circuit. The control circuit of the asynchronous circuit of this embodiment has a function of generating an acknowledgement signal ack.

[0057] 6 is a conceptual diagram of a control circuit 200 of an asynchronous circuit according to embodiment 2. The control circuit 200 of the asynchronous circuit includes a clock generation circuit 220 that outputs a clock clk having an expandable pulse width, a counter 203, and a comparator 204. The clock generation circuit 220 includes a control unit 201 and an oscillator 202.

[0058] The control unit 201 receives a request signal req from the outside and receives an acknowledgement signal ack from the comparator 204. The control unit 201 sets the drive signal for driving the oscillator 202 to a high level only when the request signal req is activated (high level) and the acknowledgement signal ack is inactivated (low level).

[0059] The oscillator 202 outputs a clock clk to the counter 203 and to the outside only when the drive signal from the control unit 201 is at a high level.

[0060] The counter 203 counts the number of pulses of the clock clk output from the oscillator 202. The counter 203 outputs the number of pulses of the clock clk as a counter value. The counter 203 receives a request signal req. The counter 203 resets the counter value to 0 when the request signal req rises to a high level.

[0061] The comparator 204 compares the counter value (number of pulses of the clock clk) output from the counter 203 with a predetermined number of times, and outputs an acknowledgement signal ack based on the comparison result to the outside and the control unit 201.

[0062] The comparator 204 sets the acknowledgement signal ack to inactive (low level) when the counter value is less than a predetermined number of times, and sets the acknowledgement signal ack to active (high level) when the counter value is equal to the predetermined number of times.

[0063] (Operation) FIG. 7 is a transition diagram of signals in the circuit of FIG.

[0064] When an external request signal req is set to high level, the control unit 201 sets the drive signal to high level, and the counter 203 resets the count value to 0. When the drive signal is set to high level, the oscillator 202 outputs a clock clk.

[0065] The counter 203 counts the number of pulses of the clock clk and outputs the number of pulses of the clock clk as a counter value.

[0066] The comparator 204 sets the acknowledge signal ack to high level when the counter value is equal to a predetermined number of times. When the acknowledge signal ack is set to high level, the control unit 201 stops outputting the clock clk. After the acknowledge signal ack becomes high level, all signals in the asynchronous circuit are inactivated, so no dynamic power consumption is generated.

[0067] 8 is a diagram showing an asynchronous circuit according to the second embodiment. The asynchronous circuit according to the second embodiment includes a control circuit 200 instead of the control circuit 100 according to the first embodiment.

[0068] The control circuit 200 of the asynchronous circuit includes a clock generation circuit 220 that outputs a clock clk having an expandable pulse width, a counter 203, a comparator 204, a second delay adjustment circuit 212, and a third delay adjustment circuit 213. The clock generation circuit 220 includes a first delay adjustment circuit 211 and an AND circuit 205. The AND circuit 205 and the first delay adjustment circuit 211 in FIG. 8 are circuits that embody the control unit 201 and oscillator 202 in FIG. 6.

[0069] The AND circuit outputs the logical product of the delayed request signal reqd, the inverted signal of the delayed acknowledge signal ackd, and the inverted signal of the delayed clock clkd as the clock clk. The clock clk output from the clock generating circuit 220 is supplied to the register groups RG1, RG2, .

[0070] (Counter) The counter 203 counts the number of pulses of the clock clk output from the clock generation circuit 220. The counter 203 outputs the number of pulses of the clock clk as a counter value.

[0071] The counter 203 is configured by a Gray code counter. The request signal req is input to a reset terminal of the counter 203. The counter 203 resets the counter value to 0 in response to the request signal req rising to a high level.

[0072] 9 is a diagram illustrating the operation of comparing the value of the binary counter with a predetermined value "7." When a binary counter is used, glitches may occur due to skew between bits. Therefore, restrictions are imposed, such as limiting the value provided to the comparator 204 to a power of two.

[0073] 10 is a diagram illustrating the operation of comparing the value of the Gray code counter with a predetermined value of 7. By using the Gray code counter, the change to the next number is limited to a change of one bit, thereby suppressing the occurrence of glitches.

[0074] (First Delay Adjustment Circuit) The first delay adjustment circuit 211 delays the clock clk output from the AND circuit 205 by a first delay amount d1 and inputs the delayed clock clk to the AND circuit 205. The first delay adjustment circuit 211 is similar to the delay adjustment circuit of the first embodiment. Therefore, the first delay amount d1 is the same as the delay amount d described in the first embodiment.

[0075] (Second Delay Adjustment Circuit) When the request signal req changes to high level, the counter 203 is reset, so it is necessary to adjust the removal time.

[0076] 11 is a diagram for explaining delay adjustment by the second delay adjustment circuit 212. The second delay adjustment circuit 212 outputs a delayed request signal reqd, which is obtained by delaying the request signal req by a second delay amount d2, to the clock generation circuit 220. The second delay amount d2 is set to be equal to or greater than the removal time of the counter 203. When the delayed request signal reqd goes high, the clock generation circuit 220 starts outputting the clock clk.

[0077] (Third Delay Adjustment Circuit) FIG. 12 is a diagram for explaining an example in which there is no delay adjustment by the third delay adjustment circuit 213. In FIG.

[0078] If the delay adjustment by the third delay adjustment circuit 213 is not performed, the clock generation circuit 220 stops generating the clock clk and sets the clock clk to a low level when the ack goes high, which shortens the pulse width of the clock clk and causes part of the clock clk to be missing.

[0079] 13 is a diagram for explaining delay adjustment by the third delay adjustment circuit 213. The third delay adjustment circuit 213 outputs a delayed acknowledgement signal ackd, which is obtained by delaying the acknowledgement signal ack output from the comparator 204 by a third delay amount d3, to the outside and the clock generation circuit 2220.

[0080] When the delayed acknowledge signal ackd, which is delayed by the third delay amount d3 from the acknowledge signal ack, goes high, the clock generation circuit 220 stops generating the clock clk and sets the clock clk to low. To prevent the clock clk from being dropped (to ensure a minimum pulse width), the following condition must be satisfied among the first delay amount d1, the third delay amount d3, and the processing time dA by the counter 203 and the comparator 204:

[0081] d1×2>d3+dA>d1 (2) According to this embodiment, the number of locations where delay adjustment specific to asynchronous design is performed can be reduced (to three locations), thereby reducing the power consumption of the asynchronous circuit. Furthermore, the asynchronous circuit and its control circuit of this embodiment are suitable for large-scale circuits.

[0082] Embodiment 3 Figure 14 is a diagram showing an asynchronous circuit according to embodiment 3. In this embodiment, the asynchronous circuit is a slave that communicates with an external master.

[0083] The asynchronous circuit includes a control circuit 200 , an interface 302 , a register 303 , a buffer 304 , an AD converter 305 , and a sensor 306 .

[0084] The control circuit 200 is similar to the control circuit 200 of the second embodiment. The control circuit 200 is configured to supply a clock clk to the AD converter 305 and the buffer 304, receive a request signal req from the register 303, and output a delayed acknowledge signal ackd to the register 303.

[0085] The interface 302 is a serial peripheral interface (SPI) that communicates with an external master.

[0086] The register 303 is connected to the interface 302. The register 303 outputs a request signal req to the control circuit 200, and receives a delayed acknowledge signal ackd output from the control circuit 200. The register 303 outputs a start instruction signal to the AD converter 305.

[0087] The sensor 306 outputs analog data representing the detection result to the AD converter 305. When the clock clk is supplied, the AD converter 305 converts the analog data from the sensor 306 into digital data and outputs it to the buffer 304.

[0088] The buffer 304 stores the digital data output from the AD converter 305 when the clock clk is supplied.

[0089] (Operation) The operation of the asynchronous circuit according to the third embodiment will be described.

[0090] In accordance with the instruction signal included in the data received by SPI communication from the master, the interface 302 causes the register 303 to output a signal instructing the AD converter 305 to start, and also causes the register 303 to output an activated request signal req. However, at this point, the AD converter 305 and buffer 304 do not operate because they are not receiving a supply of clk.

[0091] When the control circuit 200 receives the activated request signal req, it starts supplying the clock clk to the AD converter 305 and the buffer 304 .

[0092] The AD converter 305 and the buffer 304 start operating as they receive the clock clk, and the AD converter 305 converts the analog data from the sensor 306 into digital data and outputs it to the buffer 304 .

[0093] When the number of clocks equals the predetermined value, the control circuit 200 activates the acknowledge signal ack and stops supplying the clock clk. Since the AD converter 305 and the buffer 304 do not receive the clock clk, they stop operating.

[0094] At any timing, in accordance with an instruction signal included in data received from the master via SPI communication, the interface 302 reads the state of the delayed acknowledge signal ackd stored in the register 303. When the register 303 receives an activated delayed acknowledge signal ackd, the interface 302 reads data from the buffer 304.

[0095] (Interface) The interface 302 will now be described.

[0096] It is desirable for the interface 302 to minimize dynamic power consumption during standby, so by selecting the SPI protocol in which the clock is stopped, further reductions in power consumption during standby can be expected.

[0097] FIG. 15 is a diagram for explaining data capture in a conventional SPI communication interface.

[0098] The interface receives the edge of the serial clock SCK in synchronization with the internal clock clk. The interface captures data on the MOSI (Master Out Slav In) signal line at the edge of the pulse following the internal clock clk pulse that it received in synchronization with. However, the internal clock clk must be constantly running, which is not suitable for power saving.

[0099] FIG. 16 is a diagram for explaining data capture in the interface 302 according to the third embodiment.

[0100] The interface 302 simultaneously receives data from the MOSI signal line and the serial clock SCK from the clock signal line.

[0101] The interface 302 captures data on the MOSI signal line at the edge of the serial clock SCK. In this embodiment, the internal clock clk does not need to be driven all the time, which makes it possible to reduce power consumption.

[0102] FIG. 17 is a diagram for explaining CRC (Cyclic Redundancy Check) processing in a conventional SPI communication interface.

[0103] After the reception of the data on the MOSI signal line is completed, the interface executes CRC processing of the captured data using the internal clock clk, and outputs the processing result to the register 303 .

[0104] On the other hand, in this embodiment, the interface 302 uses the serial clock SCK instead of the internal clock clk, but in SPI communication, the serial clock SCK is not supplied after data transmission and reception is completed, which causes a problem in that a clock for CRC processing of the capture data cannot be obtained.

[0105] Fig. 18 is a diagram for explaining CRC processing in interface 302 according to embodiment 3. Fig. 19 is a diagram showing the format of data transmitted from the master via the MOSI signal line.

[0106] After transmitting one byte of CRC data, the master transmits one byte of dummy data via the MOSI signal line and the serial clock SCK via the clock signal line. The interface 302 simultaneously receives the one byte of dummy data from the MOSI signal line and the serial clock SCK from the clock signal line. The interface 302 performs CRC processing on the captured data based on the serial clock SCK and outputs the processing result to the register 303.

[0107] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not by the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0108] 100, 200 Control circuit, 101, DL1 Delay adjustment circuit, 201 Control unit, 202 Oscillator, 203 Counter, 204 Comparator, 205 AND circuit, 211 First delay adjustment circuit, 212 Second delay adjustment circuit, 213 Third delay adjustment circuit, 220 Clock generation circuit, 302 Interface, 303 Register, 304 Buffer, 305 AD converter, 306 Sensor, CM1, CM2, CM3 Combination circuit, RG1, RG2, RG3 Register group.

Claims

1. A control circuit for an asynchronous circuit, comprising a clock generation circuit that outputs a clock with a variable pulse width, the clock generation circuit including a delay adjustment circuit that delays an input clock by a delay amount and outputs it, and a logic circuit that outputs, as the clock, a signal representing the result of a logical operation between the output of the delay adjustment circuit, a request signal, and an acknowledgement response signal, wherein the clock is supplied to a register.

2. The control circuit for an asynchronous circuit according to claim 1, wherein the asynchronous circuit includes a plurality of stages of registers to which the clock is supplied, and a plurality of combinational circuits each disposed between two of the registers of the plurality of stages of registers, and the delay amount is greater than the maximum value of the processing times of the plurality of combinational circuits.

3. A control circuit for an asynchronous circuit, comprising a clock generation circuit that outputs a clock with a variable pulse width, the clock generation circuit including a first delay adjustment circuit that delays an input clock by a first delay amount and outputs it, and a logic circuit, the control circuit for the asynchronous circuit further including a second delay adjustment circuit that delays a request signal by a second delay amount and outputs it, a counter that counts the number of the clocks, a comparator that activates an acknowledgement response signal when a value of the counter is equal to a determined value, and a third delay adjustment circuit that delays the acknowledgement response signal by a third delay amount and outputs it, the logic circuit outputting, as the clock, a signal representing the result of a logical operation between the output of the first delay adjustment circuit, the output of the second delay adjustment circuit, and the output of the third delay adjustment circuit, wherein the clock is supplied to a register.

4. The control circuit for an asynchronous circuit according to claim 3, wherein the asynchronous circuit includes a plurality of stages of registers to which the clock is supplied, and a plurality of combinational circuits each disposed between two of the registers of the plurality of stages of registers, and the first delay amount is greater than the maximum value of the processing times of the plurality of combinational circuits.

5. The control circuit for an asynchronous circuit according to claim 3 or 4, wherein the counter is a Gray code counter.

6. The control circuit for an asynchronous circuit according to any one of claims 3 to 5, wherein the request signal is input to a reset terminal of the counter, and the second delay amount is equal to or greater than a removal time of the counter.

7. The double of the first delay amount is greater than the sum of the third delay amount and the processing times of the counter and the comparator, and the sum of the third delay amount and the processing times of the counter and the comparator is greater than the first delay amount. The control circuit of the asynchronous circuit according to any one of claims 3 to 6.

8. A sensor, an ADC that ADC-converts analog data output from the sensor when a clock is supplied, a buffer that stores digital data output from the ADC when the clock is supplied, an interface that communicates with an external master, a register connected to the interface, and a control circuit of the asynchronous circuit according to any one of claims 3 to 7, configured to supply the clock to the ADC and the buffer, receive a request signal from the register, and output an acknowledgment response signal to the register. The interface outputs a signal instructing start from the register to the ADC according to an instruction signal included in data received from the master, and outputs a request signal activated from the register. The control circuit starts supplying the clock to the ADC and the buffer according to the activation of the request signal. When the number of clocks becomes equal to a determined value, the control circuit activates an acknowledgment response signal and stops supplying the clock. The interface reads data from the buffer when the register receives the activated acknowledgment response signal. Asynchronous circuit.

9. The interface is an SPI (Serial Peripheral Interface). The interface receives data and SCK (Serial Clock) from the master at the same time and captures the data by the SCK. The asynchronous circuit according to claim 8.

10. After receiving CRC (Cyclic Redundancy Check) from the master, the interface receives dummy data and SCK from the master at the same time, and performs CRC processing on the captured data based on the SCK. The asynchronous circuit according to claim 9.

Images