3D packaging interposer structure and forming method therefor, and packaged device

Abstract

A 3D packaging interposer structure and a forming method therefor, and a packaged device. The 3D packaging interposer structure comprises: a plurality of interposer substrates, each of which includes a functional chip region and an edge region, the edge region surrounding the functional chip region; and a plurality of conductive through-via structures, each of which runs through each interposer substrate except the top interposer substrate in the edge region and is electrically insulated from the functional chip region of each interposer substrate, wherein one or more RDL structures are formed on a surface of each interposer substrate, a first end of at least one RDL structure of each surface is electrically connected to at least one conductive through-via structure, and a second end of the RDL structure is configured to be electrically connected to a functional chiplet in the functional chip region. The present invention can realize three-dimensional packaging of various functional chiplets, reduce the requirements for the design of the functional chiplets and a wafer manufacturing process thereof, and effectively expand the application range of 3D packaging.

Description

3D packaging transfer structure and forming method thereof, and packaging device Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a 3D packaging transfer structure, a forming method thereof, and a packaging device. Background Art

[0002] As integrated circuits evolve towards ultra-large-scale integrated circuits (VLSIs), the circuit density within them is increasing, the number of components they contain is also increasing, and the demand for smaller components is also increasing. For multi-component architectures, 3D packaging technology is gaining increasing attention.

[0003] Existing 3D packaging technology allows bare functional chips with the same layout to be stacked together. For example, through-silicon via (TSV) technology can be used to vertically stack multiple bare dynamic random access memory (DRAM) chips to save space. Bare functional chips, also known as die or chiplet, are chips that can perform a specific function and are in their pre-packaged state.

[0004] However, in the existing technology, only bare functional chips of the same type and layout can be three-dimensionally packaged, which has too many restrictions and limited space savings, making it difficult to meet the complex, multi-functional, and high-packaging-density 3D heterogeneous integrated packaging requirements. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a 3D packaging transfer structure and its formation method, and a packaging device, which can realize the three-dimensional packaging of multiple bare functional chips, and reduce the design requirements of bare functional chips and their wafer manufacturing process requirements, effectively expand the application scope of 3D packaging, and facilitate the realization of complex, multi-functional, high-packaging-density 3D heterogeneous integrated packaging products.

[0006] To solve the above technical problems, an embodiment of the present invention provides a 3D packaging transfer structure, including: a multi-layer interposer substrate, each layer of the interposer substrate including a functional chip area and an edge area, the edge area surrounding the functional chip area; a plurality of through-conductive structures, each through-conductive structure penetrating each layer of the interposer substrate except the top layer of the interposer substrate in the edge area, and electrically insulated from the functional chip area of ​​each layer of the interposer substrate; wherein one or more RDL structures are formed on the surface of each layer of the interposer substrate, a first end of at least one RDL structure on each surface is electrically connected to at least one through-conductive structure, and a second end of the RDL structure is used to electrically connect to a bare functional chip in the functional chip area.

[0007] Optionally, each through-conductive structure includes: an intra-board conductive column, which passes through a single-layer intermediate substrate and is flush with the upper and lower surfaces of the intermediate substrate to which it belongs; a through-RDL structure, which is located on the upper surface and / or lower surface of the single-layer intermediate substrate and is electrically connected to the intra-board conductive column within the intermediate substrate to which it belongs; an inter-board conductive column, which is located between adjacent intermediate substrates and is electrically connected to the through-RDL structure of one layer of the intermediate substrates; a welding structure, which is located between adjacent intermediate substrates, one end of the welding structure is electrically connected to the inter-board conductive column, and the other end of the welding structure is electrically coupled to another intermediate substrate in the adjacent intermediate substrates; wherein the RDL structure is electrically connected to the corresponding through-conductive structure through the through-RDL structure.

[0008] Optionally, opposite surfaces of adjacent interposers both have the through RDL structure; and the other end of the soldering structure is electrically connected to the through RDL structure of another one of the adjacent interposers.

[0009] Optionally, the soldering structure includes: a solder ball for connecting to the inter-board conductive pillar; and a solder pad for electrically coupling to another adjacent interposer substrate.

[0010] Optionally, each through-conductive structure has a through-RDL structure on the lower surface of the underlying intermediate substrate, which is electrically connected to the on-board conductive column in the underlying intermediate substrate; each through-conductive structure also includes: a bottom solder ball, which is electrically connected to the through-RDL structure on the lower surface of the underlying intermediate substrate; wherein the area ratio of the bottom solder ball in the horizontal direction is greater than or equal to the area ratio of the through-conductive structure.

[0011] Optionally, in a direction perpendicular to the bottom interposer substrate, axes of the intra-board conductive pillars and inter-board conductive pillars included in each through-conductive structure are consistent.

[0012] Optionally, the RDL structure includes one or more RDL stacking layers, each RDL stacking layer includes an RDL dielectric layer and an RDL conductive layer; wherein, the RDL conductive layer in the bottom RDL stacking layer is electrically connected to the corresponding through-conductive structure, and the RDL conductive layer in the top RDL stacking layer is electrically connected to the pad of the external bare functional chip.

[0013] Optionally, the RDL structure further includes: an RDL pad formed on the surface of the top RDL stacking layer; wherein the RDL conductive layer in the top RDL stacking layer is electrically connected to the pad of the external bare functional chip through the RDL pad.

[0014] Optionally, the RDL structure includes: a fuse structure; wherein, when the fuse structure is in an on state, the bottom RDL stacking layer and the top RDL stacking layer are electrically connected; when the fuse structure is in an off state, the bottom RDL stacking layer and at least a portion of the top RDL stacking layer are electrically insulated.

[0015] Optionally, the fuse structure includes: an interconnect plug formed in the RDL dielectric layer, used to connect adjacent RDL conductive layers; wherein the interconnect plug can be blown when a fuse voltage is applied, and the fuse voltage is applied to both ends of the interconnect plug between the adjacent RDL conductive layers.

[0016] Optionally, the first part of the top RDL stacking layer is electrically connected to the pad of the external bare functional chip, and the second part of the top RDL stacking layer is electrically connected to the bottom RDL stacking layer; the fuse structure includes: a conductive line segment, an RDL conductive layer formed in the top RDL stacking layer; wherein, the conductive line segment can be disconnected by a cutting process; after the conductive line segment is disconnected, the first part of the top RDL stacking layer is electrically insulated from the second part of the top RDL stacking layer, and the bottom RDL stacking layer is electrically insulated from the first part of the top RDL stacking layer.

[0017] Optionally, the functional chip area of ​​each layer of the intermediate substrate has one or more pre-divided functional chip sub-areas, and each functional chip sub-area is used to place a predefined bare functional chip; the 3D packaging transfer structure also includes: a heat dissipation structure, at least a portion of the heat dissipation structure is located between adjacent functional chip sub-areas to perform heat dissipation treatment on the bare functional chip.

[0018] Optionally, the heat dissipation structure includes: a refrigerant pipeline located between the adjacent functional chip sub-areas and / or between adjacent intermediate substrates; and a pump connected to the refrigerant pipeline to allow the refrigerant to circulate in the refrigerant pipeline.

[0019] Optionally, the 3D packaging transfer structure further includes an interlayer support structure located between adjacent intermediate substrates and electrically insulated and coupled to the intermediate substrates.

[0020] Optionally, the material of the interlayer support structure is a thermally conductive material.

[0021] Optionally, the material of the intermediate substrate is selected from: silicon, germanium, glass, and organic polymer.

[0022] To solve the above technical problems, an embodiment of the present invention provides a packaging device, including: a 3D packaging adapter structure as described above, wherein at least a portion of the functional chip area of ​​the intermediate substrate is bonded with a bare functional chip; and a plastic insulation layer encapsulating the 3D packaging adapter structure and the bare functional chip.

[0023] Optionally, the bare functional chip includes a bare CPU chip and a non-CPU bare chip; wherein, the bare CPU chip and the non-CPU bare chip are respectively bonded to the upper surface and lower surface of the same intermediate layer intermediate substrate of the 3D packaging transfer structure, and the intermediate layer intermediate substrate includes: functional conductive columns passing through the intermediate layer intermediate substrate, for electrically connecting the bare CPU chip and the non-CPU bare chip; the non-CPU bare chip is selected from: bare GPU chip, bare SRAM chip, bare DRAM chip, bare logic control chip, bare sensor chip, bare MEMS chip, bare signal processing chip, bare power management chip, bare front-end chip.

[0024] Optionally, the bare functional chip includes a bare radio frequency chip; wherein the bare radio frequency chip is bonded to a functional chip region on a lower surface of a top-layer interposer substrate of the 3D packaging transfer structure.

[0025] To solve the above technical problems, an embodiment of the present invention provides a method for forming a 3D packaging transfer structure as described above, including: providing layers of intermediate substrates, wherein a portion of the through-conductive structure is formed on the lower surface and the upper surface of each layer of intermediate substrate; sequentially placing the intermediate layer of intermediate substrates above the previous layer of intermediate substrates, and connecting the portions between adjacent intermediate substrates through the through-conductive structure.

[0026] Optionally, a portion of the through-conductive structure formed on the lower surface and upper surface of each layer of the intermediate substrate includes: intra-board conductive pillars, which penetrate the single-layer intermediate substrate and are flush with the upper and lower surfaces of the intermediate substrate to which it belongs; through-RDL structures, which are located on the upper surface and / or lower surface of the single-layer intermediate substrate and are electrically connected to the intra-board conductive pillars in the intermediate substrate to which it belongs; and inter-board conductive pillars, which are located between adjacent intermediate substrates and are electrically connected to the through-RDL structures of one layer of the intermediate substrates; connecting portions between adjacent intermediate substrates through the through-conductive structure, including: electrically connecting adjacent intermediate substrates using a welding structure; wherein one end of the welding structure is used to connect to the inter-board conductive pillars, and the other end of the welding structure is used to electrically couple to another intermediate substrate in the adjacent intermediate substrates, and the RDL structure is electrically connected to the corresponding through-conductive structure through the through-RDL structure.

[0027] Optionally, each through-conductive structure has a through-RDL structure on the lower surface of the bottom interposer substrate, which is electrically connected to the on-board conductive column in the bottom interposer substrate; the method also includes: forming a bottom solder ball connected to the lower surface of the bottom interposer substrate; wherein the area ratio of the bottom solder ball in the horizontal direction is greater than or equal to the area ratio of the through-conductive structure.

[0028] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0029] In an embodiment of the present invention, a 3D packaging adapter structure is provided. The structure comprises an interposer substrate surrounding a functional chip region at its edge region, a through-conductive structure electrically insulated from the functional chip region disposed in the edge region, and a redistributed layer (RDL) structure electrically connected to both the through-conductive structure and the bare functional chip region. This structure enables the bare functional chip to be electrically connected to bare functional chips in the same or other layers via the RDL structure and the through-conductive structure, thereby enabling three-dimensional packaging of multiple bare functional chips. Compared to conventional three-dimensional packaging of bare functional chips of the same type and layout, the 3D packaging adapter structure in the embodiment of the present invention reduces the design requirements for bare functional chips and their wafer fabrication process, effectively expanding the application scope of 3D packaging and facilitating the realization of complex, multifunctional, and high-packaging-density 3D heterogeneous integrated packaging products. Furthermore, by disposing the through-conductive structure at the edge region, a more concentrated area of ​​space is reserved for the bare functional chips, improving the layout convenience of multiple bare functional chips. By electrically isolating the through-conductive structure from the functional chip regions of each layer of the interposer substrate, short circuits between functional chip regions can be prevented, thereby improving the reliability of electrical performance.

[0030] Furthermore, each through-conductive structure includes: an intra-board conductive column, a through-RDL structure, an inter-board conductive column, and a welding structure. The RDL structure is electrically connected to the corresponding through-conductive structure through the through-RDL structure. Compared with forming an integrated through-conductive structure, the above-mentioned scheme is adopted to form multi-layer substructures between and within the boards, which can reduce the process complexity and process cost on the basis of realizing the through-conductive function of the through-conductive structure.

[0031] Furthermore, the through-RDL structure is formed on opposing surfaces of adjacent interposers; the other end of the solder structure is electrically connected to the through-RDL structure of another adjacent interposer. Compared to forming a through-RDL structure on only one side of the interposer, this allows bare functional chips to be placed on both sides of the interposer, thereby improving the storage capacity of the 3D packaging adapter structure. Furthermore, by forming through-RDL structures on both sides of the interposer, bare functional chips can also be placed on both sides of the interposer. This, combined with the use of intra-board wiring, reduces wire length, lowers on-resistance, and improves electrical performance, effectively expanding the applicability of the 3D packaging adapter structure of the present invention.

[0032] Furthermore, each through-conductive structure also includes: a bottom solder ball, electrically connected to the through-RDL structure on the lower surface of the bottom intermediate substrate; wherein, the area ratio of the bottom solder ball in the horizontal direction is greater than or equal to the area ratio of the through-conductive structure, so that the size of the bottom solder ball can be flexibly set according to specific needs, such as setting the size of the bottom solder ball to be larger than the size of the solder ball inside the through-conductive structure, thereby improving the ease of use of the 3D packaging transfer structure, for example, in the process of connecting the 3D packaging transfer structure to the packaging substrate through the bottom solder ball, reducing process complexity and production cost.

[0033] Furthermore, in a direction perpendicular to the underlying intermediate substrate, the axes of the intra-board conductive columns and inter-board conductive columns contained in each through-conductive structure are consistent, so that a through-conductive structure with consistent position between the upper and lower layers can be formed in the edge area to increase the space in the central area reserved for the bare functional chip. In addition, through the consistent through-conductive structure in the same direction, the resistance of the through-conductive structure can be reduced as much as possible, thereby improving the electrical performance of the 3D packaging transfer structure.

[0034] Furthermore, the RDL structure includes: a fuse structure; wherein, when the fuse structure is in a conductive state, the bottom RDL stacking layer and the top RDL stacking layer are electrically conductive; when the fuse structure is in a disconnected state, the bottom RDL stacking layer and at least a portion of the top RDL stacking layer are electrically insulated, so that by setting the fuse structure, the RDL rewiring function can be realized, the electrical connection requirements of different bare functional chips can be adapted, the same intermediate substrate can be flexibly reused, and the cost can be reduced.

[0035] Furthermore, the 3D packaging transfer structure also includes: a heat dissipation structure, at least a portion of which is located between adjacent functional chip sub-areas to perform heat dissipation treatment on the bare functional chip, thereby effectively ensuring the normal operation and reliability of each bare functional chip by dissipating the heat of the bare functional chip.

[0036] Furthermore, the 3D packaging transfer structure also includes an interlayer support structure located between adjacent interposers and electrically insulated and coupled to the interposers. This structure effectively supports the adjacent interposers and improves the stability and reliability of the 3D packaging transfer structure. Furthermore, the electrically insulated coupling between the interlayer support structure and the interposer prevents short circuits between functional chip regions, improving electrical reliability.

[0037] Furthermore, the packaged device includes the above-mentioned 3D package transfer structure, wherein at least a portion of the functional chip area of ​​the intermediate substrate is bonded with a bare functional chip, and also includes a plastic insulation layer, which encapsulates the 3D package transfer structure and the bare functional chip, thereby forming a complete packaged device after plastic encapsulation, and then delivered to the user, thereby improving the stability and reliability of the packaged device during the use phase.

[0038] Furthermore, the bare functional chips include a bare CPU chip and a non-CPU bare chip; wherein the bare CPU chip and the non-CPU bare chip are respectively bonded to the upper and lower surfaces of the same intermediate layer interposer substrate in the 3D packaging adapter structure, and the intermediate layer interposer substrate includes functional conductive pillars that penetrate the intermediate layer interposer substrate to electrically connect the bare CPU chip and the non-CPU bare chip. This solution allows the bare functional chips to be placed on both sides of the interposer substrate, thereby reducing wire length, lowering on-resistance, and improving electrical performance through intra-board wiring, effectively increasing the processing efficiency and performance of the CPU bare chip.

[0039] Furthermore, the bare functional chip includes a bare RF chip, which is bonded to the functional chip region on the bottom surface of the top interposer substrate of the 3D package transfer structure. This solution allows the bare RF chip to be used to implement antenna functionality, and by properly positioning it on the bottom surface of the top interposer substrate, the antenna's RF transceiver performance is enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] FIG1 is a bottom view of a 3D package transfer structure according to an embodiment of the present invention;

[0041] FIG2 is a schematic cross-sectional view of the structure along the cutting line A1-A2 of FIG1;

[0042] FIG3 is a schematic cross-sectional view of the structure along the cutting line B1-B2 of FIG1;

[0043] FIG4 is a schematic cross-sectional view of another 3D packaging transfer structure according to an embodiment of the present invention;

[0044] FIG5 is a schematic cross-sectional view of an RDL structure according to an embodiment of the present invention;

[0045] FIG6 is a schematic cross-sectional view of another 3D packaging transfer structure according to an embodiment of the present invention;

[0046] 7 is a schematic cross-sectional view of a packaging device according to an embodiment of the present invention;

[0047] FIG8 is a flow chart of a method for forming a 3D packaging transfer structure according to an embodiment of the present invention.

[0048] Description of reference numerals:

[0049] Interposer substrate 100, through-conductive structure 110, RDL structure 120, bare functional chip 130, top-layer interposer substrate 101, middle-layer interposer substrate 102, bottom-layer interposer substrate 103, intra-board conductive pillars 111, through-RDL structure 112, inter-board conductive pillars 113, welding structure 114, solder balls 1141, solder pads 1142, bottom-layer solder balls 115, RDL stacking layer 121, RDL dielectric layer 1211, RDL conductive layer 1212, interconnect plugs 1213, RDL pads 122, heat dissipation structure 116, interlayer support structure 117, plastic insulation layer 118, and packaging substrate 119. DETAILED DESCRIPTION

[0050] As mentioned above, in existing three-dimensional packaging technology, bare functional chips with the same layout can be stacked together. For example, through silicon via (TSV) technology can be used to stack multiple DRAM bare functional chips in a vertical direction to save space.

[0051] Research has found that through-silicon via (TSV) technology is a vertical electrical interconnection technology that creates vertical conductions between chips and between wafers. By filling conductive materials, vertical electrical interconnection of through-silicon vias (TSVs) is achieved. Since only bare functional chips of the same type and layout can meet the consistency of conduction positions, the existing through-silicon via (TSV) technology can only perform three-dimensional packaging on bare functional chips of the same type and layout, which saves limited space and is difficult to meet the complex, multi-functional, high-packaging-density 3D heterogeneous integrated packaging requirements.

[0052] In an embodiment of the present invention, a 3D packaging adapter structure is provided. The structure comprises an interposer substrate surrounding a functional chip region in an edge region, a through-conductive structure electrically insulated from the functional chip region disposed in the edge region, and an RDL structure electrically connected to both the through-conductive structure and the bare functional chip in the functional chip region. This structure enables the bare functional chip to be electrically connected to bare functional chips in the same or other layers via the RDL structure and the through-conductive structure, thereby enabling three-dimensional packaging of multiple bare functional chips. Compared to the prior art practice of three-dimensionally packaging bare functional chips of the same type and layout, the 3D packaging adapter structure in the embodiment of the present invention can reduce the design and wafer manufacturing process requirements for bare functional chips, effectively expanding its scope of application. Furthermore, by disposing the through-conductive structure in the edge region, a more concentrated space area can be reserved for the bare functional chips, improving the layout convenience of multiple bare functional chips. By electrically insulating the through-conductive structure from the functional chip regions of each layer of the interposer substrate, short circuits between functional chip regions can be prevented, thereby improving the reliability of electrical performance.

[0053] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0054] 1 to 3 , FIG1 is a bottom view schematic diagram of a 3D packaging transfer structure in an embodiment of the present invention, FIG2 is a cross-sectional structural schematic diagram along cutting line A1 - A2 of FIG1 , and FIG3 is a cross-sectional structural schematic diagram along cutting line B1 - B2 of FIG1 .

[0055] As shown in the figure, the 3D package interposer structure may include a multi-layer interposer substrate 100 and a plurality of through-conductive structures 110 .

[0056] Each layer of the interposer substrate 100 may include a functional chip region and an edge region, wherein the edge region surrounds the functional chip region.

[0057] Each through conductive structure 110 penetrates through each layer of the interposer substrate 100 except the top interposer substrate 101 in the edge region and is electrically insulated from the functional chip region of each layer of the interposer substrate 100 .

[0058] Furthermore, the material of the interposer substrate 100 may be selected from: silicon, germanium, glass, and organic polymer.

[0059] Specifically, the interposer substrate 100 can be made of semiconductor materials, and existing wafer fabrication processes can be used to fabricate through-silicon vias (TSVs) and RDL structures therein, effectively controlling costs and improving applicability. For example, the interposer substrate 100 can be made of silicon, germanium, or other materials such as silicon germanium, silicon carbide, silicon nitride, and gallium nitride.

[0060] The interposer substrate 100 may be made of glass, thereby reducing high-frequency signal loss and improving high-frequency transmission characteristics. For example, it may be silicon-based glass (such as silicon dioxide SiO2), or other silicate glass materials.

[0061] The material of the interposer substrate 100 may be an organic polymer, such as polyimide. Since the polymer is an organic high molecular material, it has better comprehensive performance, high temperature resistance of over 400°C, no obvious melting point, and high insulation performance, which can better meet usage requirements.

[0062] It should be noted that although FIG3 illustrates the number of intermediate interposer substrates 102 as two, in practice, there is no limitation on the number of intermediate interposer substrates 102. For example, it can be 0 (i.e., only the top interposer substrate 101 and the bottom interposer substrate 103), 1, or any other number greater than or equal to 3.

[0063] Furthermore, one or more RDL structures 120 may be formed on the surface of each layer of the intermediate substrate 100, and the first end of at least one RDL structure 120 on the surface of each intermediate substrate 100 is electrically connected to at least one through-conductive structure 110, and the second end of the RDL structure 120 is used to be electrically connected to the bare functional chip 130 in the functional chip area.

[0064] The bare functional chip 130 and the RDL structure 120 may be connected using any suitable process, such as a thermocompression bonding (TCB) process using microbumps and pads, or a low-temperature direct bonding (DBI) process using Cu-Cu pads.

[0065] Here, electrical connection is used to indicate electrical conduction, and may be, for example, a direct electrical connection (also referred to as bonding and electrical conduction), or an indirect electrical connection (also referred to as electrical coupling).

[0066] The bare functional chip 130 is used to represent an external bare chip for realizing a predetermined function, which is a die or chiplet that has not been packaged, such as a die with a pad but not connected to a lead frame.

[0067] It should be particularly pointed out that by adopting the bare functional chip 130, it is only necessary to align the input / output (I / O) pads of the bare functional chip 130 with the I / O pads on the RDL structure 120 of the 3D packaging transfer structure one-to-one, so as to achieve electrical connection between the bare functional chip 130 and the RDL structure 120, as well as electrical connection with the through-conductive structure. Compared with the existing technical solution of making through silicon vias (TSVs) in the bare functional chip 130, it is not required to make through silicon vias (TSVs) separately for the bare functional chip 130, and it can avoid the need to pre-make TSVs in functional wafers due to stacking, and avoid the adverse effect of invalid wafer area caused by the keep-out zone (KOZ) set around the TSV, thereby increasing the effective circuit area of ​​the wafer, reducing the complexity of the front-end wafer manufacturing process, and improving the wafer yield and quality reliability, accelerating the speed from design to completion of new products, and effectively saving the production cost of the bare functional chip 130.

[0068] In other words, the 3D packaging transfer structure of the embodiment of the present invention effectively reduces the complexity of designing and manufacturing the bare functional chip 130 , and can be designed and manufactured according to a normal single chip without the need for through silicon vias (TSVs).

[0069] In an embodiment of the present invention, a 3D packaging transfer structure is provided, which includes an intermediate substrate 100 with an edge region surrounding the functional chip region, a through-conductive structure 110 electrically insulated from the functional chip region, and an RDL structure 120 electrically connected to the through-conductive structure 110 and to a bare functional chip 130 in the functional chip region. The bare functional chip 130 can be electrically connected to the bare functional chip 130 in the same layer or other layers through the RDL structure 120 and the through-conductive structure 110, thereby realizing three-dimensional packaging of multiple bare functional chips 130. Compared with the three-dimensional packaging of bare functional chips 130 of the same type and the same layout in the prior art, the 3D packaging transfer structure in the embodiment of the present invention can reduce the design and manufacturing requirements for the bare functional chip 130, thereby effectively expanding the scope of application. In addition, by setting the through-conductive structure 110 in the edge area, a more concentrated space area can be reserved for the bare functional chip 130, thereby improving the layout convenience of multiple bare functional chips 130; by electrically insulating the through-conductive structure 110 from the functional chip areas of each layer of the intermediate substrate 100, short circuit problems between functional chip areas can be prevented, thereby improving the reliability of electrical performance.

[0070] The through-conductive structure 110 can be formed in various ways according to specific circumstances, for example, an integrated structure similar to a through-silicon via (TSV) can be formed, or a multi-layer substructure can be formed between or within boards.

[0071] 4 , which is a schematic cross-sectional view of another 3D packaging transfer structure according to an embodiment of the present invention.

[0072] The other 3D packaging transfer structure is formed by forming a through conductive structure 110 through multiple layers of sub-structures between boards and within boards.

[0073] Each through-conductive structure 110 may include: an intra-board conductive pillar 111, which passes through a single-layer interposer substrate 100 and is flush with the upper and lower surfaces of the interposer substrate 100 to which it belongs; a through-RDL structure 112, which is located on the upper surface and / or lower surface of the single-layer interposer substrate 100 and is electrically connected to the intra-board conductive pillar 111 within the interposer substrate 100 to which it belongs; an inter-board conductive pillar 113, which is located between adjacent interposers 100 and is electrically connected to the through-RDL structure 112 of one layer of the interposer substrate 100; a welding structure 114, which is located between adjacent interposers 100, one end of the welding structure 114 is electrically connected to the inter-board conductive pillar 113, and the other end of the welding structure 114 is electrically coupled to another interposer substrate 100 in the adjacent interposers 100; wherein the RDL structure 120 is electrically connected to the corresponding through-conductive structure 110 through the through-RDL structure 112.

[0074] It should be noted that although the conductive pillars 111 can be designed to be flush with the upper and lower surfaces of the interposer substrate 100 , in actual manufacturing, a deviation within a preset error range may be allowed.

[0075] By designing the through RDL structure 112 to be located on the upper surface and / or lower surface of the single-layer interposer substrate 100 , the through RDL structure 112 can be formed on only one side of the interposer substrate 100 or on both sides of the interposer substrate 100 according to specific circumstances.

[0076] Furthermore, the through RDL structures 112 are formed on opposite surfaces of adjacent interposer substrates 100 ; and the other end of the solder structure 114 is electrically connected to the through RDL structure 112 of another one of the adjacent interposer substrates 100 .

[0077] In this embodiment of the present invention, the other end of the solder structure 114 is electrically connected to the through-RDL structure 112 of another adjacent interposer substrate 100. Compared to forming through-RDL structure 112 on only one side of the interposer substrate 100, this allows bare functional chips 130 to be placed on both sides of the interposer substrate 100, thereby improving the accommodating capacity of the 3D packaging adapter structure. Furthermore, by forming through-RDL structure 112 on both sides of the interposer substrate 100, bare functional chips 130 can be placed on both sides of the interposer substrate 100. This, through intra-board wiring, reduces wire length, lowers on-resistance, and improves electrical performance, effectively expanding the applicability of the 3D packaging adapter structure of this embodiment of the present invention.

[0078] In a specific implementation, the RDL structure 120 may be electrically connected to the corresponding through-conductive structure 110 through the through-RDL structure 112 .

[0079] More specifically, the RDL structure 120 and a portion or all of the through-RDL structure 112 located on the same surface of the interposer substrate 100 may be formed using the same process, thereby improving process efficiency and device quality.

[0080] In an embodiment of the present invention, each through-conductive structure 110 includes: an intra-board conductive column 111, a through-RDL structure 112, an inter-board conductive column 113 and a welding structure 114. The RDL structure 120 is electrically connected to the corresponding through-conductive structure 110 through the through-RDL structure 112. Compared with forming an integrated through-conductive structure 110, the above-mentioned scheme is adopted to form multi-layer substructures between and within the boards, which can reduce the process complexity and process cost on the basis of realizing the through-conductive function of the through-conductive structure 110.

[0081] Furthermore, the soldering structure 114 may include: a solder ball 1141 for connecting to the inter-board conductive pillar 113 ; and a solder pad 1142 for electrically coupling to another interposer 100 in the adjacent interposer 100 .

[0082] The solder balls 1141 may be metal balls, and the solder pads 1142 may be metal blocks.

[0083] In the embodiment of the present invention, by providing the solder balls 1141 and the solder pads 1142 as the soldering structures 114 , the process cost can be effectively controlled.

[0084] It should be noted that in one specific implementation of the present invention, each layer of interposer substrate 100 and its intra-board conductive pillars 111, through-RDL structures 112, and inter-board conductive pillars 113 can be prefabricated separately, with adjacent interposer substrates 100 electrically connected via soldering structures 114. Compared to bonding, gluing, or threaded connections, soldering structures 114 can improve the stability and reliability of the 3D package transfer structure.

[0085] Furthermore, the pad 1142 electrically coupled to the interposer substrate 100 may be electrically connected to the through RDL structure 112 .

[0086] In a specific implementation, by using solder balls 1141 to connect with the inter-board conductive pillars 113, the connection tightness can be improved; by using pads 1142 to connect with the through-RDL structure 112, compared with using solder balls 1141 to connect with the through-RDL structure 112, the solution of an embodiment of the present invention can improve the reliability of the welding structure 114 and the through-RDL structure 112.

[0087] Furthermore, each through-conductive structure 110 has a through-RDL structure 112 on the lower surface of the underlying interposer substrate 103, which is electrically connected to the on-board conductive column 113 in the underlying interposer substrate 103; each through-conductive structure 110 may also include: a bottom solder ball 115, which is connected to the through-RDL structure 112 on the lower surface of the underlying interposer substrate 103; wherein the area ratio of the bottom solder ball 115 in the horizontal direction is greater than or equal to the area ratio of the through-conductive structure 110.

[0088] The horizontal area ratio of the bottom solder balls 115 may represent the ratio of the sum of the maximum horizontal cross-sectional areas of the bottom solder balls 115 to the area of ​​the entire bottom interposer substrate 103 . The maximum horizontal cross-sectional area may be, for example, the cross-sectional area passing through the center point of the bottom solder balls 115 .

[0089] The area ratio of the through conductive structure 110 is used to indicate the ratio of the cross-sectional area of ​​the through conductive structure 110 in the horizontal direction to the area of ​​the entire bottom interposer substrate 103 .

[0090] The area ratio of the bottom solder balls 115 in the horizontal direction can be determined according to the size of the bottom solder balls 115 or the number of the bottom solder balls 115. The larger the size of the bottom solder balls 115 and the greater the number of the bottom solder balls 115, the greater the area ratio of the bottom solder balls 115 in the horizontal direction.

[0091] As shown in FIG. 4 , the size of the bottom solder ball 115 is larger than the cross-sectional size of the through conductive structure 110 , and the area ratio of the bottom solder ball 115 is greater than or equal to the area ratio of the through conductive structure 110 .

[0092] Specifically, RDL can be used to lead the through-conductive structures 110 to further distances to connect to the bottom solder balls 115, thereby increasing the area ratio and providing more electrical channels for non-data access (such as various power supply access, etc.).

[0093] In an embodiment of the present invention, the area ratio of the bottom solder ball 115 in the horizontal direction is greater than or equal to the area ratio of the through conductive structure 110, so that the size of the bottom solder ball 115 can be flexibly set according to specific needs. For example, the size of the bottom solder ball 115 can be set to be larger than the size of the solder ball 1141 inside the through conductive structure 110, thereby improving the ease of use of the 3D packaging transfer structure. For example, in the process of connecting the 3D packaging transfer structure to the packaging substrate through the bottom solder ball 115, the process complexity and production cost are reduced.

[0094] Furthermore, in a direction perpendicular to the bottom interposer substrate 103 , the axes of the intra-board conductive pillars 111 and the inter-board conductive pillars 113 included in each through-conductive structure 110 are aligned.

[0095] In the case where the 3D package transfer structure is placed on a horizontal plane, the direction perpendicular to the bottom interposer substrate 103 can be regarded as the vertical direction.

[0096] The axis can be understood as a straight line around which an object or a three-dimensional figure rotates or can be imagined to rotate. For example, the axis lines of each intra-board conductive column 111 and inter-board conductive column 113 included in each through-conductive structure 110 can be on the same straight line.

[0097] In a specific implementation, the axes of the intra-board conductive columns 111 and the inter-board conductive columns 113 included in each through-conductive structure 110 are consistent, so that a through-conductive structure 110 with consistent positions between the upper and lower layers can be formed in the edge area to increase the space in the central area reserved for the bare functional chip 130. In addition, through the consistent through-conductive structure 110 in the same direction, the resistance of the through-conductive structure 110 can be reduced as much as possible, thereby improving the electrical performance of the 3D packaging transfer structure.

[0098] 5 , which is a schematic cross-sectional view of an RDL structure according to an embodiment of the present invention.

[0099] The RDL structure 120 may be formed on the upper surface and / or the lower surface of the interposer substrate 100 (ie, formed on one side or both sides).

[0100] In FIG. 5 , an example is used in which both the upper surface and the lower surface of the intermediate layer interposer substrate 102 have the RDL structure 120 .

[0101] Specifically, the RDL structure 120 may include one or more RDL stacking layers 121, and each RDL stacking layer 121 may include an RDL dielectric layer 1211 and an RDL conductive layer 1212; wherein, the RDL conductive layer 1212 in the bottom RDL stacking layer 121 is electrically connected to the corresponding through-conductive structure 110, and the RDL conductive layer 1212 in the top RDL stacking layer 121 is electrically connected to the pad of the external bare functional chip 130 (refer to Figure 2).

[0102] Furthermore, the RDL dielectric layer 1211 may further include an interconnect plug 1213 for connecting adjacent RDL conductive layers 1212 .

[0103] In an embodiment of the present invention, the RDL structure 120 includes an RDL dielectric layer 1211 and an RDL conductive layer 1212. The RDL structure 120 can change the circuit contact positions (such as I / O pads) of the original design. For example, the contact positions can be changed through a metal wiring process and a bump process, thereby achieving the effect of circuit redistribution to realize electrical connection between related bare functional chips.

[0104] Furthermore, the RDL structure 120 may also include: an RDL pad 122 formed on the surface of the top RDL stacking layer 121; wherein the RDL conductive layer 1212 in the top RDL stacking layer 121 is electrically connected to the pad of the external bare functional chip 130 through the RDL pad 122.

[0105] In an embodiment of the present invention, by setting an RDL pad 122 on the surface of the top RDL stacking layer 121, electrical connection with the pad of the external bare functional chip 130 can be achieved, thereby providing the user with a 3D packaging transfer structure that does not include a bare functional chip 130. The user can add appropriate bare functional chips 130 according to specific needs, thereby further improving the application scope of the 3D packaging transfer structure in the embodiment of the present invention.

[0106] Furthermore, the RDL structure 120 may include: a fuse structure; wherein, when the fuse structure is in an on state, the bottom RDL stacking layer 121 and the top RDL stacking layer 121 are electrically connected; when the fuse structure is in an off state, the bottom RDL stacking layer 121 and at least a portion of the top RDL stacking layer 121 are electrically insulated.

[0107] In an embodiment of the present invention, electrical conduction or electrical insulation is achieved between the bottom RDL stacking layer 121 and the top RDL stacking layer 121 by setting the fuse structure to an on state or an off state. Therefore, by setting the fuse structure, the RDL rewiring function can be more flexibly achieved, the electrical connection requirements of different bare functional chips can be adapted, and the same intermediate substrate 110 can be flexibly reused to reduce costs.

[0108] In a specific embodiment, the fuse structure may include: an interconnect plug 1213, formed in the RDL dielectric layer 1211, for connecting adjacent RDL conductive layers 1212; wherein, the interconnect plug 1213 can be fused when a fuse voltage is applied, and the fuse voltage is applied to both ends of the interconnect plug between the adjacent RDL conductive layers 1212.

[0109] The interconnect plug 1213 encircled by a dotted circle as shown in the figure can be blown when a blow voltage is applied, wherein the blow voltage can be applied to the RDL conductive layer 1212 at both ends of the interconnect plug.

[0110] In an embodiment of the present invention, by applying a fusing voltage at both ends of the interconnect plug 1213 between the adjacent RDL conductive layers 1212, the interconnect plug 1213 electrically connected to the upper RDL conductive layer 1212 can be fused, thereby disconnecting the electrical connection between the bottom RDL stacking layer 121 and the top RDL stacking layer 121, thereby improving the convenience of rewiring.

[0111] Furthermore, the interconnect plug 1213 used as a fuse structure may be a top-layer interconnect plug.

[0112] The top interconnect plug may be the interconnect plug 1213 of the top RDL stack layer 121 , and may be located in a layer below the top RDL conductive layer 1212 (eg, the RDL dielectric layer 1211 of the top RDL stack layer 121 ).

[0113] In the embodiment of the present invention, by using the top interconnect plug as the interconnect plug 1213 of the fuse structure, a voltage can be applied to the top RDL conductive layer 1212 of the top RDL stack layer 121 , thereby improving the convenience of the fuse operation.

[0114] In another specific embodiment, the first part of the top RDL stacking layer 121 is electrically connected to the pad of the external bare functional chip 130, and the second part of the top RDL stacking layer 121 is electrically connected to the bottom RDL stacking layer 121; the fuse structure may include: a conductive line segment, an RDL conductive layer 1212 formed in the top RDL stacking layer 121; wherein the conductive line segment can be disconnected by a cutting process; after the conductive line segment is disconnected, the first part of the top RDL stacking layer 121 is electrically insulated from the second part of the top RDL stacking layer 121, and the bottom RDL stacking layer 121 is electrically insulated from the first part of the top RDL stacking layer 121.

[0115] The conductive line segments encircled by the dotted circles in the figure can be disconnected by a cutting process.

[0116] Furthermore, a focused ion beam (FIB) process can be used to use an electric lens to focus the ion beam into a very small size of micro-dissection technology, and the conductive line segments can be disconnected by bombardment.

[0117] In an embodiment of the present invention, the conductive line segments of the RDL conductive layer 1212 in the top RDL stacking layer 121 are disconnected through a cutting process, and the electrical connection between the RDL traces of the RDL conductive layer 1212 in the same layer of the RDL stacking layer 121 can be disconnected, so that the first part of the top RDL stacking layer 121 is electrically insulated from the second part of the top RDL stacking layer 121, which is equivalent to electrically insulating the bottom RDL stacking layer 121 from the first part of the top RDL stacking layer 121, thereby disconnecting the electrical connection between the through conductive structure 110 and the bare functional chip 130, effectively improving the convenience of rewiring.

[0118] 6, which is a schematic cross-sectional view of another 3D package transfer structure according to an embodiment of the present invention, the differences between FIG6 and FIG2 are described below.

[0119] In another 3D package transfer structure shown in FIG. 6 , the functional chip area of ​​each interposer substrate 100 may have one or more pre-divided functional chip sub-areas, each of which is used to place a predefined bare functional chip 130 .

[0120] The 3D packaging transfer structure may further include a heat dissipation structure 116 , at least a portion of which is located between adjacent functional chip sub-regions to dissipate heat for the bare functional chip 130 .

[0121] In an embodiment of the present invention, at least a portion of the heat dissipation structure 116 is located between adjacent functional chip sub-regions to perform heat dissipation treatment on the bare functional chip 130, thereby effectively ensuring the normal operation and reliability of each bare functional chip 130 by dissipating heat for the bare functional chip 130.

[0122] In a specific embodiment, the heat dissipation structure 116 may include: a refrigerant pipeline (not shown), located between the adjacent functional chip sub-areas, and / or, located between adjacent intermediate substrates 100; a pump (not shown), connected to the refrigerant pipeline to allow the refrigerant to circulate in the refrigerant pipeline.

[0123] Specifically, the refrigerant may be a liquid refrigerant, and the liquid refrigerant may include water, silicone oil, and mineral oil.

[0124] In the embodiment of the present invention, by adopting a pump, the refrigerant can be circulated in the refrigerant pipeline, so the heat dissipation effect of the heat dissipation structure 116 can be effectively improved by adopting liquid refrigerant.

[0125] The refrigerant pipelines between the adjacent functional chip sub-regions may be represented by the schematic diagram of the heat dissipation structure 116 shown in FIG. 6 , for example.

[0126] It should be noted that, in a specific embodiment, the refrigerant pipeline may be added as a whole only after each layer of the intermediate substrates 100 is formed, aligned and placed, and connected between adjacent intermediate substrates 100 through the through-conductive structure 110.

[0127] In another specific embodiment, the refrigerant pipelines of each layer can be added separately when forming each layer of the intermediate substrate 100, and then the refrigerant pipelines of each layer can be connected in the process of aligning and placing the next intermediate substrate 100 on top of the previous intermediate substrate 100 and connecting the parts between adjacent intermediate substrates 100 by penetrating the conductive structure 110.

[0128] It is understandable that in the embodiment of the present invention, there is no limitation on the specific implementation of the refrigerant pipeline.

[0129] In another specific embodiment, a heat conducting member, such as a metal sheet, may be placed between adjacent functional chip sub-regions and / or between adjacent interposer substrates 100 .

[0130] Furthermore, the thermal conductivity of the heat-conducting element can be greater than a preset thermal conductivity threshold. Since thermal conductivity reflects the thermal conductivity of a substance, it refers to the amount of heat transferred through a unit heat-conducting surface per unit time per unit temperature gradient (temperature drops by 1K within a length of 1m). Therefore, by adopting a heat-conducting element with a larger thermal conductivity, better heat conduction and heat dissipation effects can be achieved.

[0131] In yet another 3D package transfer structure shown in FIG. 6 , the 3D package transfer structure may further include: an interlayer support structure 117 located between adjacent interposer substrates 100 and electrically insulated and coupled to the interposer substrates 100 .

[0132] In this embodiment of the present invention, interlayer support structure 117 is located between adjacent interposer substrates 100 and is electrically insulated and coupled to the interposer substrates 100. This effectively supports the adjacent interposer substrates 100, improving the stability and reliability of the 3D package transfer structure. Furthermore, the electrically insulated coupling between interlayer support structure 117 and interposer substrate 110 prevents short circuits between functional chip regions, improving electrical reliability.

[0133] Furthermore, the material of the interlayer support structure 117 is a thermally conductive material.

[0134] Furthermore, the thermal conductivity of the interlayer support structure 117 can be greater than a preset thermal conductivity threshold. Since thermal conductivity reflects the thermal conductivity of a material, better interlayer heat conduction and outward heat dissipation effects can be obtained by adopting an interlayer support structure 117 with a larger thermal conductivity.

[0135] 7 , which is a schematic cross-sectional view of a packaging device according to an embodiment of the present invention.

[0136] As shown in FIG. 7 , the packaged device may include a 3D package conversion structure (eg, the 3D package transfer structure described above and shown in FIG. 1 to FIG. 6 ), wherein at least a portion of the functional chip region of the interposer substrate 100 may be bonded with a bare functional chip 130 .

[0137] The packaged device may further include an underfill (not shown) filled between the intermediate layers; and a plastic insulation layer 118 encapsulating the 3D package transfer structure and the bare functional chip 130 .

[0138] The material of the plastic insulation layer 118 may be, for example, epoxy molding compound (EMC); the bottom filler (not shown) may be selected from liquid epoxy resin, deformable gel, silicone rubber, etc., or a combination thereof.

[0139] In an embodiment of the present invention, the 3D package transfer structure and the bare functional chip 130 are encapsulated by the plastic insulation layer 118, thereby forming a complete packaged device after plastic encapsulation, which can then be delivered to the user, thereby improving the stability and reliability of the packaged device during use.

[0140] The bottom solder balls 115 can be connected to an external package substrate 119, allowing the plastic insulation layer 118 of the packaged device to encapsulate the bottom solder balls 115 and protect the 3D package transfer structure in combination with the package substrate 119. The metal wires on the lower surface of the package substrate 119 are connected to large solder balls (e.g., with a diameter of several hundred microns), forming a BGA package functional module that can be bonded to a PCB board.

[0141] In other words, the 3D package transfer structure disclosed in the embodiment of the present invention may include the package substrate 119 and the metal wires on its lower surface, and may also include large-sized solder balls.

[0142] Furthermore, the bare functional chip 130 may include a bare central processing unit (CPU) chip and a non-CPU bare chip; the non-CPU bare chip may be selected from: a bare graphics processing unit (GPU) chip, a bare static random access memory (SRAM) chip, a bare dynamic random access memory (DRAM) chip, a bare logic control chip, a bare sensor chip, a bare micro-electro-mechanical system (MEMS) chip, a bare signal processing chip, a bare power management chip, a bare front-end chip, etc.

[0143] Among them, the bare front-end chip may include, for example, a power amplifier (PA), a low-noise amplifier (LNA), a filter (Filter), a radio frequency switch (Switch), etc.

[0144] 6 , the bare CPU chip and the non-CPU bare chip can be respectively bonded to the upper and lower surfaces of the same intermediate layer interposer substrate of the 3D packaging transfer structure, and the intermediate layer interposer substrate includes: functional conductive columns passing through the intermediate layer interposer substrate for electrically connecting the bare CPU chip and the non-CPU bare chip.

[0145] As shown in FIG6 , bare functional chips are bonded to the right sides of the upper and lower surfaces of the first intermediate layer interposer substrate, which may be a bare CPU chip and a non-CPU bare chip respectively. The intermediate layer interposer substrate may include functional conductive pillars.

[0146] In an embodiment of the present invention, the bare CPU chip and the non-CPU bare chip are bonded to the top and bottom surfaces of the same interposer substrate in the 3D package adapter structure, respectively. The interposer substrate includes functional conductive posts that penetrate the interposer substrate to electrically connect the bare CPU chip and the non-CPU bare chip. This solution allows bare functional chips to be placed on both sides of the interposer substrate. This reduces wire length, lowers on-resistance, improves electrical performance, and enhances high-frequency transmission performance, effectively increasing the processing efficiency and performance of the CPU bare chip.

[0147] Furthermore, the bare functional chip 130 may include a bare radio frequency chip; wherein the bare radio frequency chip may be bonded to a functional chip region on the lower surface of the top interposer substrate of the 3D packaging transfer structure.

[0148] In an embodiment of the present invention, the bare RF chip is bonded to the functional chip area on the lower surface of the top-layer intermediate substrate of the 3D packaging adapter structure. The bare RF chip can be set to realize the antenna function, and the RF transceiver effect of the antenna can be improved by setting it in an appropriate position, that is, the lower surface of the top-layer intermediate substrate.

[0149] The package in Figure 7 can also be used as a standalone end product, such as a single personal computer (PC), a standalone wearable product, a standalone industrial control module, a standalone artificial intelligence (AI) module, and a high-performance computing (HPC) module.

[0150] 8 is a flow chart of a method for forming a 3D package transfer structure according to an embodiment of the present invention. The method for forming a 3D package transfer structure may include steps S81 to S82, each of which is described below.

[0151] Step S81 : providing interposer substrates of various layers, wherein a portion of the through conductive structure is formed on the lower surface and the upper surface of each interposer substrate.

[0152] Specifically, each layer of the interposer substrate and a portion of the through conductive structure thereof may be pre-manufactured separately.

[0153] Step S82: sequentially aligning and placing the intermediate interposer substrates on top of the previous interposer substrate, and connecting the portions between adjacent interposer substrates through the through conductive structures.

[0154] In an embodiment of the present invention, by pre-fabricating each layer of intermediate substrates and a portion of their through-conductive structures, adjacent intermediate substrates can be electrically connected, so that the bare functional chip can be electrically connected to the bare functional chip in the same layer or other layers through the RDL structure and the through-conductive structure, thereby realizing three-dimensional packaging of multiple bare functional chips. Compared with the three-dimensional packaging of bare functional chips of the same type and the same layout in the prior art, the use of the 3D packaging transfer structure in the embodiment of the present invention can reduce the requirements for the bare functional chip and effectively expand the scope of application.

[0155] It should be noted that a 3D packaging transfer structure in an embodiment of the present invention may include a multi-layer intermediate layer intermediate substrate and a single-layer bottom intermediate substrate. In this case, the upper surface of the top intermediate layer intermediate substrate can also be electrically connected to the bare functional chip.

[0156] In this case, the intermediate interposer substrates can be aligned and placed sequentially on top of the previous interposer substrate, and connections can be made between adjacent interposer substrates through the through-conductive structures.

[0157] Another 3D packaging transfer structure according to an embodiment of the present invention may include a single top interposer substrate, one or more middle interposer substrates, and a single bottom interposer substrate. In this case, the top surface of the top interposer substrate cannot be electrically connected to a bare functional chip.

[0158] In this case, the middle interposer substrates can be aligned and placed on the previous interposer substrate, and the top interposer substrate can be aligned and placed on the topmost middle interposer substrate, and the through conductive structures can be used to connect adjacent interposers.

[0159] Furthermore, a portion of the through-conductive structure formed on the lower and upper surfaces of each layer of the intermediate substrate includes: intra-board conductive pillars, which penetrate the single-layer intermediate substrate and are flush with the upper and lower surfaces of the intermediate substrate to which it belongs; through-RDL structures, which are located on the upper and / or lower surfaces of the single-layer intermediate substrate and are electrically connected to the intra-board conductive pillars within the intermediate substrate to which it belongs; and inter-board conductive pillars, which are located between adjacent intermediate substrates and are electrically connected to the through-RDL structures of one layer of the intermediate substrates; the step of connecting the portions between adjacent intermediate substrates through the through-conductive structure may include: electrically connecting the adjacent intermediate substrates using a welding structure; wherein one end of the welding structure is used to connect to the inter-board conductive pillars, and the other end of the welding structure is used to electrically couple to another intermediate substrate in the adjacent intermediate substrates, and the RDL structure is electrically connected to the corresponding through-conductive structure through the through-RDL structure.

[0160] In the embodiment of the present invention, by forming multi-layer substructures between boards and within boards, the process complexity and process cost can be reduced on the basis of realizing the through-conducting function of the through-conducting structure.

[0161] Furthermore, each through-conductive structure has a through-RDL structure on the lower surface of the bottom interposer substrate, which is electrically connected to the on-board conductive pillars in the bottom interposer substrate; the method also includes: forming a bottom solder ball connected to the lower surface of the bottom interposer substrate; wherein the area ratio of the bottom solder ball in the horizontal direction is greater than or equal to the area ratio of the through-conductive structure.

[0162] In an embodiment of the present invention, if the area ratio of the bottom solder ball in the horizontal direction is greater than or equal to the area ratio of the through-conductive structure, the size of the bottom solder ball can be flexibly set according to specific needs, such as setting the size of the bottom solder ball to be larger than the size of the solder ball inside the through-conductive structure, thereby improving the ease of use of the 3D packaging transfer structure, for example, in the process of connecting the 3D packaging transfer structure to the packaging substrate through the bottom solder ball, reducing the process complexity and production cost.

[0163] It should be understood that the term "and / or" as used herein simply describes an association between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " as used herein indicates that the related objects are in an "or" relationship.

[0164] The term "plurality" used in the embodiments of the present application refers to two or more.

[0165] The first, second, etc. descriptions appearing in the embodiments of this application are only used for illustration and distinction of the description objects. There is no order, nor does it indicate a special limitation on the number in the embodiments of this application, and cannot constitute any limitation on the embodiments of this application.

[0166] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A 3D packaging interposer structure, characterized in that, Comprising: A multi-layer interposer substrate, each layer of the interposer substrate including a functional chip region and an edge region, the edge region surrounding the functional chip region; A plurality of through-conductive structures, each through-conductive structure penetrating through each layer of the interposer substrate except the top layer of the interposer substrate in the edge region and being electrically insulated from the functional chip regions of each layer of the interposer substrate; Wherein, one or more RDL structures are formed on the surface of each layer of the interposer substrate, a first end of at least one RDL structure on each surface being electrically connected to at least one through-conductive structure, and a second end of the RDL structure being used for electrically connecting to a bare functional chip in the functional chip region.

2. The 3D packaging interposer structure according to claim 1, wherein Each through-conductive structure includes: An in-plane conductive pillar, penetrating through a single layer of the interposer substrate and being flush with the upper and lower surfaces of the belonging interposer substrate; A through-RDL structure, located on the upper surface and / or the lower surface of a single layer of the interposer substrate and being electrically connected to the in-plane conductive pillar in the belonging interposer substrate; An inter-plane conductive pillar, located between adjacent interposer substrates and being electrically connected to the through-RDL structure of one of the interposer substrates; A welding structure, located between adjacent interposer substrates, one end of the welding structure being electrically connected to the inter-plane conductive pillar, and the other end of the welding structure being electrically coupled to another interposer substrate among the adjacent interposer substrates; Wherein, the RDL structure is electrically connected to the corresponding through-conductive structure through the through-RDL structure.

3. The 3D packaging interposer structure according to claim 2, wherein The opposite surfaces of adjacent interposer substrates both have the through-RDL structures; The other end of the welding structure is electrically connected to the through-RDL structure of another interposer substrate among the adjacent interposer substrates.

4. The 3D packaging interposer structure according to claim 2 or 3, characterized in that, The welding structure includes: A solder ball, used for connecting to the inter-plane conductive pillar; A pad, used for electrically coupling to another interposer substrate among the adjacent interposer substrates.

5. The 3D packaging interposer structure according to claim 2, wherein Each through-conductive structure has a through-RDL structure on the lower surface of the bottom layer of the interposer substrate, which is electrically connected to the in-plane conductive pillar in the bottom layer of the interposer substrate; Each through-conductive structure further includes: A bottom solder ball, electrically connected to the through-RDL structure on the lower surface of the bottom layer of the interposer substrate; Wherein, the area ratio of the bottom solder ball in the horizontal direction is greater than or equal to the area ratio of the through-conductive structure.

6. The 3D packaging interconnection structure according to claim 2, wherein In a direction perpendicular to the bottom layer of the interposer substrate, the axes of the respective in-plane conductive pillars and inter-plane conductive pillars included in each through-conductive structure are consistent.

7. The 3D packaging interposer structure according to claim 1, characterized in that, The RDL structure includes one or more RDL stacked layers, each RDL stacked layer including an RDL dielectric layer and an RDL conductive layer; Wherein, the RDL conductive layer in the bottom RDL stacked layer is electrically connected to the corresponding through-conductive structure, and the RDL conductive layer in the top RDL stacked layer is electrically connected to the pad of an external bare functional chip.

8. The 3D packaging interposer structure according to claim 7, wherein The RDL structure further includes: An RDL pad, formed on the surface of the top RDL stacked layer; Wherein, the RDL conductive layer in the top RDL stacked layer is electrically connected to the pad of an external bare functional chip through the RDL pad.

9. The 3D packaging interposer structure according to claim 7, wherein, The RDL structure includes: A fusing structure; Wherein, when the fusing structure is in a conductive state, electrical conduction exists between the bottom RDL stacked layer and the top RDL stacked layer; When the fusing structure is in a disconnected state, electrical insulation is provided between at least a portion of the bottom RDL stack layer and the top RDL stack layer.

10. The 3D packaging interposer structure according to claim 9, wherein The fusing structure includes: Interconnect plugs formed in the RDL dielectric layer for connecting adjacent RDL conductive layers; Among them, the interconnect plugs can be fused when a fusing voltage is applied, and the fusing voltage is applied across both ends of the interconnect plugs between adjacent RDL conductive layers.

11. The 3D packaging interposer structure according to claim 9, wherein A first portion of the top RDL stack layer is electrically connected to the pads of the external bare functional chip, and a second portion of the top RDL stack layer is electrically connected to the bottom RDL stack layer; The fusing structure includes: Conductive line segments formed in the RDL conductive layer of the top RDL stack layer; Among them, the conductive line segments can be disconnected by a cutting process; After the conductive line segments are disconnected, electrical insulation is provided between the first portion and the second portion of the top RDL stack layer, and electrical insulation is provided between the bottom RDL stack layer and the first portion of the top RDL stack layer.

12. The 3D packaging interposer structure according to claim 1, wherein Each functional chip region of each interposer substrate has one or more pre-divided functional chip sub-regions, and each functional chip sub-region is used to place a predefined bare functional chip; The 3D package interposer structure further includes: A heat dissipation structure, at least a portion of which is located between adjacent functional chip sub-regions to dissipate heat from the bare functional chips.

13. The 3D packaging interposer structure according to claim 12, wherein The heat dissipation structure includes: Refrigerant pipelines located between adjacent functional chip sub-regions and / or between adjacent interposer substrates; A pump connected to the refrigerant pipelines to circulate the refrigerant in the refrigerant pipelines.

14. The 3D packaging interposer structure according to claim 1, wherein The 3D package interposer structure further includes: An interlayer support structure located between adjacent interposer substrates and electrically insulated and coupled to the interposer substrates.

15. The 3D package interposer structure according to claim 14, wherein The material of the interlayer support structure is a thermally conductive material.

16. The 3D packaging interposer structure according to claim 1, wherein The material of the interposer substrate is selected from: silicon, germanium, glass, organic polymers.

17. An encapsulation device, characterized in that, It includes: The 3D package interposer structure according to any one of claims 1 to 16, wherein at least a portion of the functional chip region of the interposer substrate is bonded with a bare functional chip; A plastic encapsulation insulating layer encapsulating the 3D package interposer structure and the bare functional chips.

18. The encapsulated device according to claim 17, wherein The bare functional chips include bare CPU chips and non-CPU bare chips; Among them, the bare CPU chips and the non-CPU bare chips are respectively bonded to the upper surface and the lower surface of the same layer of the middle interposer substrate of the 3D package interposer structure, and this layer of the middle interposer substrate includes: Functional conductive posts passing through this layer of the middle interposer substrate for electrically connecting the bare CPU chips and the non-CPU bare chips; The non-CPU bare chips are selected from: bare GPU chips, bare SRAM chips, bare DRAM chips, bare logic control chips, bare sensor chips, bare MEMS chips, bare signal processing chips, bare power management chips, bare front-end chips.

19. The encapsulated device according to claim 17, wherein The bare functional chips include bare radio frequency chips; Among them, the bare radio frequency chip is bonded to the functional chip area on the lower surface of the top - layer interposer substrate of the 3D packaging interposer structure.

20. A method for forming a 3D packaging interposer structure according to any one of claims 1 to 16, characterized in that, Including: Providing each layer of interposer substrate, with a part of the through - via conductive structure formed on the lower surface and the upper surface of each layer of interposer substrate; Aligning and placing the intermediate - layer interposer substrate above the previous - layer interposer substrate in sequence, and connecting the parts between adjacent interposer substrates through the through - via conductive structure.

21. The method according to claim 20, characterized in that, A part of the through - via conductive structure formed on the lower surface and the upper surface of each layer of interposer substrate includes: in - plane conductive vias, penetrating through a single - layer interposer substrate and flush with the upper and lower surfaces of the belonging interposer substrate, through - via RDL structures, located on the upper surface and / or the lower surface of the single - layer interposer substrate and electrically connected to the in - plane conductive vias in the belonging interposer substrate, inter - plane conductive vias, located between adjacent interposer substrates and electrically connected to the through - via RDL structure of one of the interposer substrates; Connecting the parts between adjacent interposer substrates through the through - via conductive structure includes: Electrically connecting adjacent interposer substrates using a welding structure; Among them, one end of the welding structure is used to connect to the inter - plane conductive via, the other end of the welding structure is used to be electrically coupled to another interposer substrate among adjacent interposer substrates, and the RDL structure is electrically connected to the corresponding through - via conductive structure through the through - via RDL structure.

22. The method according to claim 21, wherein Each through - via conductive structure has a through - via RDL structure on the lower surface of the bottom - layer interposer substrate, which is electrically connected to the in - plane conductive vias in the bottom - layer interposer substrate; The method further includes: Forming bottom solder balls connected to the lower surface of the bottom - layer interposer substrate; Among them, the area ratio of the bottom solder balls in the horizontal direction is greater than or equal to the area ratio of the through - via conductive structure.

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