Power semiconductor apparatus and power conversion apparatus

Abstract

A power semiconductor apparatus (1) comprises a power semiconductor device (10) and a main wiring part (110) electrically connected to the power semiconductor device (10). The power semiconductor device (10) includes: a semiconductor substrate (21) including a first surface (S1) and a second surface (S2) on the side opposite from the first surface (S1); a first main electrode (23) provided on the first surface (S1) of the semiconductor substrate (21); a second main electrode (25) provided on the second surface (S2) of the semiconductor substrate (21); and a terminal structure (22) provided on the first surface (S1) of the semiconductor substrate (21). The main wiring part (110) is electrically connected to the first main electrode (23) and is disposed on the side of the first main electrode (23) that is away from the second main electrode (25). At least part of a portion of the main wiring part (110) facing the terminal structure (22) does not pass through an insulation layer between the terminal structure (22) and the main wiring part (110).

Description

Power semiconductor device and power conversion device

[0001] The present disclosure relates to a power semiconductor device and a power conversion device.

[0002] For example, in the semiconductor device described in Japanese Patent Laid-Open No. 2013-89948 (Patent Document 1), a pole called a connector separates the semiconductor device from the wiring.

[0003] JP 2013-89948 A

[0004] However, when the wiring itself serves as part of the heat dissipation path, increasing the distance between the semiconductor device and the wiring means an increase in thermal resistance. In the semiconductor device described in the above publication, the thermal resistance of the poles called connectors and the bonding layers above and below them is added to the semiconductor device, hindering heat dissipation.

[0005] The present disclosure has been made in view of the above-mentioned problems, and its object is to provide a power semiconductor device and a power conversion device that achieve high heat dissipation properties.

[0006] The power semiconductor device of the present disclosure includes a power semiconductor device and a main wiring portion electrically connected to the power semiconductor device. The power semiconductor device includes a semiconductor substrate including a first surface and a second surface opposite the first surface, a first main electrode provided on the first surface of the semiconductor substrate, a second main electrode provided on the second surface of the semiconductor substrate, and a termination structure provided on the first surface of the semiconductor substrate. The main wiring portion is electrically connected to the first main electrode and is located on the opposite side of the first main electrode from the second main electrode. At least a portion of the main wiring portion facing the termination structure does not have an insulating layer between it and the termination structure.

[0007] According to the power semiconductor device of the present disclosure, high heat dissipation properties can be achieved.

[0008] 5 is a schematic cross-sectional view of a power semiconductor device in embodiment 1. FIG. 6 is a schematic top view and a schematic cross-sectional view from the surface of the power semiconductor device in embodiment 1. FIG. 7 is a schematic cross-sectional view of a power semiconductor device using a thermally conductive resin insulating layer in embodiment 1. FIG. 8 is a schematic cross-sectional view of a power semiconductor device using an exterior case in embodiment 1. FIG. 9 is a schematic cross-sectional view of a 2-in-1 package power semiconductor device in embodiment 1. FIG. 10 is a circuit diagram when the power semiconductor device in FIG. 5 is a MOS-FET. FIG. 11 is a schematic cross-sectional view of a power semiconductor device applied to mounting in which the back surface of the power semiconductor device in embodiment 1 is on the mounting substrate side. FIG. 12 is a schematic cross-sectional view of a power semiconductor device in embodiment 2. FIG. 13 is an enlarged view of an end of a power semiconductor device in embodiment 2. FIG. 14 is a schematic view of the cross-sectional shape of a groove in embodiment 2. FIG. 15 is an enlarged view of an end of a power semiconductor device in embodiment 3. FIG. 16 is an enlarged view of an end of a power semiconductor device in a modified example of embodiment 3. FIG. 17 is a schematic cross-sectional view of a power semiconductor device in embodiment 4. FIG. 18 is a block diagram schematically showing the configuration of a power conversion device in embodiment 5.

[0009] The power semiconductor device of the embodiment will be described below with reference to the drawings. In each drawing, the same or similar components are designated by the same reference numerals. Furthermore, each drawing merely shows the concept, and the dimensional ratios in the drawings have no particular meaning.

[0010] First Embodiment. The configuration of a power semiconductor device 1 according to the first embodiment will be described with reference to Figures 1 and 2. Figure 1 is a schematic cross-sectional view of the power semiconductor device 1 in the first embodiment. Also, Figure 2 is a schematic top view and cross-sectional view of a power semiconductor device 10 in the first embodiment from the surface. Figure 1 corresponds to the cross-section AA' of Figure 2 (upside down). Detailed structure and protective films of the power semiconductor device 10 are omitted in both Figures 1 and 2. The same applies to the following drawings.

[0011] The power semiconductor device 1 includes a power semiconductor device 10. The power semiconductor device 10 includes a semiconductor substrate 21, a termination structure 22, a first main electrode 23 through which a main current flows, a control electrode 24 that controls the main current, and a second main electrode 25 through which the main current flows. The control electrode 24 is not necessary in a diode or the like that does not have the function of controlling the main current.

[0012] The semiconductor substrate 21 includes a first surface S1 and a second surface S2 opposite to the first surface S1. The first main electrode 23 is provided on the first surface S1 of the semiconductor substrate 21. The second main electrode 25 is provided on the second surface S2 of the semiconductor substrate 21. The termination structure 22 is provided on the first surface S1 of the semiconductor substrate 21.

[0013] The material of the semiconductor substrate 21 is a semiconductor such as silicon (Si), silicon carbide (SiC), gallium nitride, or gallium oxide, and is not limited to a specific material. In the power semiconductor device 10, heat is mainly generated near the first main electrode 23, so the structure of the present disclosure, which draws heat from the surface close to the heat source, is particularly suitable for gallium oxide-based semiconductors, which have low thermal conductivity and do not easily transfer heat to the back surface. In this embodiment, for example, the semiconductor substrate 21 is a gallium oxide-based semiconductor.

[0014] The basic structure of the power semiconductor device 10 is called a vertical type, in which the main current flows between the front and back surfaces, i.e., in the thickness direction of the semiconductor substrate 21. The power semiconductor device 10 functions as a diode or a transistor. The basic structure of the transistor is not limited to specific structures such as an insulated gate bipolar transistor (IGBT) or a metal oxide semiconductor field effect transistor (MOS-FET). Furthermore, the electrode material is preferably a material with good electrical and thermal conductivity, such as aluminum (Al), aluminum alloy, copper (Cu), copper alloy, a bilayer aluminum / copper structure, or a multilayer structure containing gold (Au) or silver (Ag). A diffusion prevention layer, such as titanium (Ti), may be included in part of the electrode. A nickel (Ni) silicide underlayer may be used to establish ohmic contact with the semiconductor substrate 21. A thin layer of a precious metal, such as gold (Au), may be disposed on the surface layer to prevent electrode oxidation and improve electrode adhesion. In the present disclosure, there are no particular restrictions on the electrode material. The control electrode 24 may be located anywhere inside the termination structure 22 of the power semiconductor device 10, but is preferably located at the edge of the power semiconductor device 10 because the control wiring would block part of the heat dissipation path. Possible electrode shapes include a rectangle, an ellipse (including a circle), a combination of an ellipse and a rectangle, or a hexagon. In the present disclosure, there are no particular restrictions on the location or shape of the control electrode 24.

[0015] The substrate on which the power semiconductor device 10 is mounted will now be described. The mounting substrate 103 includes a conductive portion 100, an insulating substrate 42, and a lower electrode 52. The conductive portion 100 is preferably made of a material with good electrical and thermal conductivity, such as copper, copper alloy, aluminum, or aluminum alloy. The insulating substrate 42 may be made of, for example, a ceramic primarily composed of silicon nitride (Si-N) or aluminum nitride (Al-N), which are highly thermally conductive, but is not limited to these materials. In this application, the lower electrode 52 must function as a current-blocking electrode but must be highly thermally conductive, and the linear expansion coefficients of the upper and lower electrodes must be matched to suppress warping. Therefore, the lower electrode 52 is typically made of the same material as the conductive portion 100, such as copper, aluminum, or an alloy thereof, but is not limited to these materials. The conductive portion 100, insulating substrate 42, and lower electrode 52 of the mounting substrate 103 are bonded to each other using a direct bonding method, an active metal brazing (AMB) method, or the like.

[0016] The power semiconductor device 1 includes a main wiring portion 110 electrically connected to the power semiconductor device 10. The main wiring portion 110 is electrically connected to the first main electrode 23 and is disposed on the opposite side of the first main electrode 23 from the second main electrode 25. At least a portion of the portion of the main wiring portion 110 facing the termination structure 22 does not have an insulating layer between it and the termination structure 22. The main wiring portion 110 and the termination structure 22 are at least partially continuous. At least a portion of the termination structure 22 forms a part of the current path and the heat dissipation path. In this embodiment, at least a portion of the region where the main wiring portion 110 and the termination structure 22 face each other is filled with a conductor without any gaps. Specifically, at least a portion of the region where the main wiring portion 110 and the termination structure 22 face each other is filled with the first main electrode 23 and the bonding material 31a without any gaps.

[0017] The power semiconductor device 1 includes a control wiring section 120 electrically connected to the power semiconductor device 10. The mounting substrate 103 represents the entire integrated mounting substrate of the control wiring section 120 and the main wiring section 110 having the upper electrode, which is the conductive section 100, the insulating substrate 42, and the lower electrode 52.

[0018] In this embodiment, the mounting substrate 103 is described as a substrate generally called a ceramic insulating circuit board, but it may also be one that uses a thermally conductive resin insulating layer 41 as shown in FIG. 3, or may have another structure. The material of the support plate 51 is preferably a highly thermally conductive material, specifically copper, copper alloy, aluminum, aluminum alloy, etc. The mounting substrate 102 is the entire integrated mounting substrate of the main wiring section 110 and the control wiring section 120, which has the thermally conductive resin insulating layer 41 and the support plate 51. The sealing structure of FIG. 3 is generally created by transfer molding using epoxy resin.

[0019] The bonding material 31a electrically and mechanically connects the first main electrode 23 to the portion 13 of the mounting substrate 103 facing the first main electrode 23. The bonding material 31b electrically and mechanically connects the control electrode 24 to the portion 14 of the mounting substrate 103 facing the control electrode 24. While solder is a common bonding material, it increases thermal resistance, which is roughly determined by thermal conductivity, bonding thickness, and cross-sectional area, making it unsuitable for the present disclosure. As an example of the bonding material 31a, a sintered material using fine particles of silver or copper, etc., is suitable for the present disclosure because it achieves low thermal resistance through a thin bonding thickness and high thermal conductivity. There are no particular requirements for pressure or no pressure, or for the process temperature or temperature profile. Furthermore, bonding may be achieved by liquid phase diffusion bonding using Cu-Sn (tin), etc., which allows for a thin bonding thickness. Because the bonding thickness is proportional to the thermal resistance, it is preferable for the bonding thickness to be at least 0.2 mm, preferably 0.1 mm or less. The distance between the main wiring portion 110 and the termination structure 22 is approximately the same as the bonding thickness, and is therefore preferably at least less than 0.2 mm, and more preferably 0.1 mm or less, as with the bonding thickness. The above description is about the bonding material 31 a, and it is not necessarily required for the bonding material 31 b connected to the control electrode 24, which generates less heat than the first main electrode 23 and the second main electrode 25, but it is preferable that the same bonding material and bonding thickness be used in the manufacturing process.

[0020] The main circuit wiring 53 connected to the first main electrode 23 via the conductive portion 100 of the mounting substrate 103, the control wiring 54 connected to the control electrode 24, and the main circuit wiring 55 connected to the second main electrode 25 are connected via bonding materials 32a, 32b, and 32c, respectively. While the main circuit wiring 55 connected to the second main electrode 25 is depicted as a lead frame in this embodiment, it may be made of aluminum or copper wire. In this case, the bonding material 32c is not required because the main circuit wiring 55 is bonded to the second main electrode 25 via wire bonding. While solder is typically used for the bonding materials 32a, 32b, and 32c, solder remelting may occur depending on the process temperature or temperature profile during mounting of the power semiconductor device 1 of the present disclosure to a power converter. From the perspective of long-term reliability of the connection, solder is not necessarily optimal. Other bonding materials similar to the bonding material 31a may be used, or direct bonding such as ultrasonic bonding or laser welding without a bonding material may also be used. In the case of direct bonding, no bonding material is used, so the main circuit wiring 53 is in direct contact with the connection portion 12 of the mounting board 103. In addition, in order to reduce the parasitic inductance Ls of the main circuit, it is desirable to arrange the main circuit wiring 53 and the main circuit wiring 55 as parallel plates as possible.

[0021] Furthermore, termination structure 22 desirably has a field plate structure that is not affected by the electric field from conductive portion 100 that forms part of main circuit wiring 53 that is continuous with first main electrode 23. Insulating material 26 forms part of termination structure 22. In addition to silicon oxide, examples of materials for insulating material 26 include high-dielectric-constant materials such as hafnium oxide and tantalum oxide, but there are no particular restrictions as long as it can withstand the manufacturing process and can ensure insulation and insulation reliability.

[0022] 1, the only electrode other than the first main electrode 23 is the control electrode 24, but there may be one or more electrodes other than the control electrode 24. Also, like a diode, there may be no electrode other than the first main electrode 23. Examples of wiring other than the control line include a line at the same potential as the first main electrode 23, a current sense line, and a temperature sense line that is wiring from an on-chip diode.

[0023] Sealing with the sealing material 91 is typically achieved by transfer molding with epoxy resin, or by potting silicone gel or liquid epoxy resin around the outer periphery of an outer case 202 made of thermoplastic resin, as shown in FIG. 4 . The base plate 201 is preferably made of a highly thermally conductive material such as copper, copper alloy, aluminum, aluminum alloy, or AlSiC. The bonding material 33 bonds the mounting substrate 103 to the base plate 201, and is preferably a highly thermally conductive material such as the aforementioned bonding material 31a, in addition to solder. The bonding material 34 bonds the outer case 202 to the base plate 201. However, since electrical and thermal functionality are not important, a material commonly referred to as an adhesive may be used as long as there is no gap between the outer case 202 and the base plate 201 and mechanical reliability is ensured. Furthermore, integrating the base plate 201 and mounting substrate 103 is preferable because it eliminates the thermal resistance of the bonding material. Other methods for forming the sealing material include compression molding or sheet-like sealing materials.

[0024] Although not shown in FIGS. 1 , 3 , and 4 , a cooler is typically provided on the mounting substrate 103, the mounting substrate 102, and the base plate 201 opposite the mounting surface on which the power semiconductor device 10 is mounted. Coolers can be liquid-cooled or air-cooled. The thermal connection between the mounting substrate 103 and the cooler can be achieved by mechanically fastening them using a material generally known as a TIM (Thermal Interface Material), which has almost no mechanical bonding strength, or by bonding them using solder or a material similar to the bonding material 31a, also known as direct bonding. Furthermore, a structure in which the conductive portion 100, which constitutes the entire or part of the cooler, the thermally conductive resin insulating layer 41, and the cooler are integrated in the area corresponding to the support plate 51 in FIG. 3 is desirable from the perspective of heat dissipation because there is no thermal resistance generated in the TIM or bonding material.

[0025] Although this embodiment shows the case where there is one power semiconductor device 10, multiple power semiconductor devices 10 (in this example, a so-called 2-in-1 package) may be mounted in series as shown in FIG. 5, with an upper arm and a lower arm. FIG. 6 shows a circuit diagram of the power semiconductor device 10 in FIG. 5 when it is a MOS-FET. To reduce the parasitic inductance Ls of the main circuit, it is desirable to arrange the P wiring 56, AC wiring 57, and N wiring 58 as parallel plates as much as possible. Each arm may also be composed of multiple power semiconductor devices 10. Multiple power semiconductor devices 10 may also be arranged in a direction perpendicular to the paper surface, or the three phases U, V, and W may be mounted on a single mounting board 103. There is no particular limit to the number of power semiconductor devices 10 mounted.

[0026] In this embodiment, the power semiconductor device 1 is described as being configured in what is commonly called flip-chip mounting, in which the front surface of the power semiconductor device 10 faces the mounting substrate. However, the power semiconductor device 1 can also be configured in a manner in which the back surface of the power semiconductor device 10 faces the mounting substrate, as shown in FIG. 7 . By arranging coolers on both sides, double-sided cooling can be achieved. Note that the use of the entire integrated mounting substrate of the main wiring portion, including the insulating substrate 42 and the lower electrode 52, as the mounting substrate 104 is merely an example; any substrate configuration, including a non-insulated configuration, is conceivable for the power semiconductor device 1 as long as the conductive portion 100 is a good conductor. Similarly, various configurations and arrangements are conceivable for the main circuit wiring 53, control wiring 54, and main circuit wiring 55, including wires.

[0027] Next, the effects of the power semiconductor device 1 in the first embodiment will be described. According to the power semiconductor device 1 in the first embodiment, at least a part of the portion of the main wiring portion 110 facing the termination structure 22 does not have an insulating layer between it and the termination structure 22. This makes it possible to enhance heat dissipation from the first surface S1 of the semiconductor substrate 21. In other words, it is possible to reduce thermal resistance. Therefore, it is possible to achieve high heat dissipation.

[0028] According to the power semiconductor device 1 of the first embodiment, the main wiring portion 110 and at least a portion of the termination structure 22 are continuous, and at least a portion of the termination structure 22 forms a part of the current path and the heat dissipation flow path. Therefore, the heat dissipation flow path can be expanded to an area greater than that of the first main electrode 23, thereby enhancing heat dissipation from the first surface S1 of the semiconductor substrate 21.

[0029] According to the power semiconductor device 1 of the first embodiment, the distance between the main wiring portion 110 and the termination structure 22 is less than 0.2 mm. By shortening the distance between the first main electrode 23 and the main wiring portion 110, heat dissipation from the first surface S1 of the semiconductor substrate 21 can be improved.

[0030] According to power semiconductor device 1 of the first embodiment, termination structure 22 has a field plate structure. Since the field plate structure is not affected by conductive portion 100 that forms part of main circuit wiring 53 that is continuous with first main electrode 23, heat dissipation from first surface S1 of semiconductor substrate 21 can be improved by shortening the distance between first main electrode 23 and main wiring portion 110.

[0031] According to the power semiconductor device 1 of the first embodiment, the semiconductor substrate 21 is a gallium oxide semiconductor. Gallium oxide semiconductors have low thermal conductivity and do not easily transfer heat to the back surface side, making them suitable for a structure that draws heat from the front surface close to the heat source.

[0032] Embodiment 2. Another embodiment of the power semiconductor device 1 according to the present disclosure will be described. Figure 8 is a schematic cross-sectional view of the power semiconductor device 1 according to embodiment 2 of the present disclosure. In this embodiment, a groove 61 is provided in the main wiring portion 110. The groove 61 in the mounting substrate 103 is provided along the outer periphery of the termination structure 22 of the power semiconductor device 10 so as to face the termination structure 22. The rest is the same as in Figure 1. The power semiconductor device 10 has a side surface 27.

[0033] Here, one step in the manufacturing process for the power semiconductor device 1 according to the present disclosure will be described. This step, commonly referred to as die bonding or die attach, involves placing bonding material 31a and bonding material 31b on a mounting substrate 103 and bonding the power semiconductor device 10 by heating or other processes. During this process, there is a risk that the bonding material 31a may protrude to the periphery. FIG. 9 shows an enlarged view of the edge of the power semiconductor device. FIG. 9(b) is a partial enlarged view of FIG. 8, and FIG. 9(a) shows the case where the bonding material 31a has protruded. The second main electrode 25, through which the main current flows, and the side surface 27 of the power semiconductor device 10 are essentially at the same potential. Because the bonding material 31a is a good conductor, the first main electrode 23 and the second main electrode 25 are short-circuited. A groove 61 is provided in the mounting substrate 103 to prevent the bonding material 31a from protruding. 8, the cross-sectional shape of the groove 61 is rectangular, but it may also be a trapezoid, a combination of a trapezoid and a rectangle, an ellipse, a combination of an ellipse and a rectangle, or the like, as shown in FIGS. 10(a) to 10(d). It is desirable that the groove sidewall on the side closer to the power semiconductor device 10 moves away from the power semiconductor device 10 in the depth direction, because this increases the cross-sectional area of ​​the heat flow from the power semiconductor device 10. In other words, if the sidewall of the groove 61 is vertical, the cross-sectional area is constant, but if the sidewall of the groove 61 widens like a trapezoid, the cross-sectional area increases, thereby reducing the thermal resistance.

[0034] Next, the effects of the power semiconductor device 1 according to the second embodiment will be described. According to the power semiconductor device 1 according to the second embodiment, the grooves 61 are provided so as to face each other along the outer periphery of the termination structure 22 of the power semiconductor device 10. Therefore, the grooves 61 can suppress the creeping up of the bonding material 31a. Therefore, the first main electrode 23 and the second main electrode 25 can be prevented from being short-circuited.

[0035] Embodiment 3. Another embodiment of the power semiconductor device 1 according to the present disclosure will be described. FIG. 11 is a cross-sectional schematic diagram of the end portion of the power semiconductor device 1 according to embodiment 3 of the present disclosure. The power semiconductor device 10 includes an insulating material 28. The insulating material 28 is formed on a side surface 27 of the power semiconductor device 10. In this embodiment, the insulating material 28 is formed around the entire periphery of the side surface 27. The rest is the same as FIG. 1 . The insulating material 28 may be an oxide such as silicon oxide or aluminum oxide, a nitride such as silicon nitride or aluminum nitride, glass, or a resin such as polyimide or epoxy. For example, the insulating material 28 may be formed by masking the termination structure and depositing a film by chemical vapor deposition (CVD), physical vapor deposition (PVD) such as sputtering or evaporation, spraying, or by applying a resin or the like. This improves the reliability of the withstand voltage and also improves the tolerance to concerns such as the overflow of the bonding material 31a shown in FIG. 9( a). In other words, the insulating material 28 can prevent the first main electrode 23 and the second main electrode 25 from shorting out even if the bonding material 31 a creeps up.

[0036] The insulating material 28 does not necessarily need to cover the vicinity of the second main electrode 25, but should be at least 0.05 mm or more in the thickness direction of the semiconductor substrate 21, and preferably 0.1 mm or more.

[0037] A modification of this embodiment will be described with reference to Fig. 12. As shown in Fig. 12, an inclined portion 27b is provided at the end of the power semiconductor device. A vertical portion 27a and an inclined portion 27b are provided on the side surface 27 of the power semiconductor device 10. In this embodiment, the inclined portion 27b is formed around the entire periphery of the side surface 27. The inclined portion 27b further improves the ease of forming the insulating material 28 and the insulation reliability.

[0038] Next, a description will be given of the effects of the power semiconductor device 1 according to the third embodiment. According to the power semiconductor device 1 according to the third embodiment, the insulating material 28 is formed on the side surface 27 of the power semiconductor device 10. This makes it possible to improve the dielectric strength.

[0039] According to the power semiconductor device 1 of the third embodiment, the inclined portion 27b is provided on the side surface 27 of the power semiconductor device 10. This makes it possible to improve the dielectric strength.

[0040] Fourth Embodiment Another embodiment of the power semiconductor device 1 according to the present disclosure will be described. Fig. 13 is a cross-sectional schematic diagram of the power semiconductor device 1 according to the fourth embodiment of the present disclosure. The power semiconductor device 1 includes an underfill resin 81. The underfill resin 81 is disposed in the gap between the power semiconductor device 10 and the main wiring portion 110. The underfill resin 81 fills the local gap between the power semiconductor device 10 and the mounting substrate 103. The rest is the same as Fig. 1 .

[0041] The die bonding process described in the second embodiment creates localized voids between the power semiconductor device 10 and the mounting substrate 103. Because the bonding material 31a is formed so as not to protrude as shown in FIG. 9A, voids are created at the edges of the power semiconductor device 10. Furthermore, voids inevitably occur around the control electrode 24. This is because, without the voids, the first main electrode 23 and the control electrode 24 would be short-circuited. However, in subsequent processes, the back surface or the second main electrode 25 is inevitably exposed to mechanical stress. Gallium oxide, in particular, has cleavage planes, which raise concerns about cracks and chips originating from the void edges. Filling the voids with underfill resin 81 after the die bonding process eliminates cracks and chips originating from the void edges in subsequent processes, thereby improving reliability.

[0042] Next, a description will be given of the effects of the power semiconductor device 1 in embodiment 4. According to the power semiconductor device 1 in embodiment 4, the underfill resin 81 is disposed in the gap between the power semiconductor device 10 and the main wiring portion 110. Gallium oxide has a cleavage plane and is prone to cracking, so mechanical support by the underfill resin 81 can reduce breakage during the manufacturing process.

[0043] Fifth Embodiment In a fifth embodiment, the power semiconductor device 1 according to any one of the first to fourth embodiments is applied to a power conversion device. Although the present disclosure is not limited to a specific power conversion device, a case in which the present disclosure is applied to a three-phase inverter will be described as the fifth embodiment.

[0044] 14 is a block diagram showing the configuration of a power conversion system to which the power conversion device 300 is applied. The power conversion system shown in FIG.

[0045] The power supply 410 is a DC power supply that supplies DC power to the power conversion device 300. The power supply 410 can be configured from various sources. For example, the power supply 410 can be configured from a DC system, a solar cell, or a storage battery. The power supply 410 may be configured from a rectifier circuit connected to an AC system or an AC / DC converter. The power supply 410 may be configured from a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0046] The load 420 is a three-phase electric motor driven by AC power supplied from the power conversion device 300. The load 420 is not limited to a specific application. The load 420 is an electric motor mounted on various electrical devices. The load 420 is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0047] The power conversion device 300 is a three-phase inverter connected between a power supply 410 and a load 420. The power conversion device 300 converts DC power supplied from the power supply 410 into AC power and supplies the AC power to the load 420. As shown in Fig. 14 , the power conversion device 300 has a main conversion circuit 301 that converts DC power into AC power and outputs it, and a control circuit 303 that outputs a control signal for controlling the main conversion circuit 301 to the main conversion circuit 301.

[0048] The following describes in detail the configuration of the power conversion device 300. The main conversion circuit 301 has a switching element and a free wheel diode (not shown). The main conversion circuit 301 converts DC power supplied from the power source 410 into AC power by switching the switching element, and supplies the AC power to the load 420.

[0049] There are various specific circuit configurations for the main conversion circuit 301, but the main conversion circuit 301 according to the fifth embodiment is a two-level three-phase half-bridge circuit, and is composed of six switching elements and six freewheeling diodes connected in anti-parallel to each switching element. Note that the freewheeling diodes are not essential for transistors with a freewheeling diode function, such as MOS transistors with a body diode or RC-IGBTs with a built-in diode. Furthermore, the switching elements themselves may be composed of multiple transistors.

[0050] At least one of the switching elements and freewheel diodes of the main conversion circuit 301 is a switching element or a freewheel diode included in a semiconductor device 302 corresponding to the power semiconductor device 1 of any of the first to fourth embodiments. The six switching elements are connected in series in groups of two switching elements to form upper and lower arms. Each upper and lower arm forms one phase (U phase, V phase, W phase) of the full bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 301, are connected to a load 420.

[0051] The main conversion circuit 301 has a drive circuit (not shown) that drives each switching element. This drive circuit may be built into the semiconductor device 302, or may be configured separately from the semiconductor device 302. This drive circuit generates drive signals that drive the switching elements of the main conversion circuit 301, and supplies them to the control electrodes of the switching elements of the main conversion circuit 301.

[0052] Specifically, this drive circuit outputs a drive signal to turn the switching element on and a drive signal to turn the switching element off to the control electrode of each switching element in accordance with a control signal from a control circuit 303 (described later). When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element. When maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or lower than the threshold voltage of the switching element.

[0053] The control circuit 303 controls the switching elements of the main conversion circuit 301 so that the desired power is supplied to the load 420. Specifically, it calculates the time (on time) that each switching element of the main conversion circuit 301 should be in the on state based on the power to be supplied to the load 420. For example, the main conversion circuit 301 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. The control circuit 303 outputs control commands (control signals) to the drive circuit of the main conversion circuit 301 so that on signals and off signals are output to the switching elements that should be in the on state and off state, respectively, at each point in time. The drive circuit of the main conversion circuit 301 outputs on or off signals as drive signals to the control electrodes of each switching element in accordance with the control signals.

[0054] According to the power conversion device 300, the power semiconductor device according to any one of the first to fourth embodiments is applied as the semiconductor device 302 constituting the main conversion circuit 301, and therefore high heat dissipation properties of the semiconductor device 302 can be realized.

[0055] In the fifth embodiment, an example in which the present disclosure is applied to a two-level three-phase inverter has been described, but the present disclosure is not limited to this and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is described, but a three-level or multi-level power conversion device may also be used. In addition, when power is supplied to a single-phase load, the present disclosure may also be applied to a single-phase inverter. Furthermore, when power is supplied to a DC load or the like, the present disclosure may also be applied to a DC / DC converter or an AC / DC converter.

[0056] Furthermore, the power conversion device to which the present disclosure is applied is not limited to cases in which the above-mentioned load is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.

[0057] The above-described embodiments can be combined as appropriate. The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0058] 1 Power semiconductor device, 10 Power semiconductor device, 12 Connection portion, 13, 14 Portion, 21 Semiconductor substrate, 22 Termination structure, 23 First main electrode, 24 Control electrode, 25 Second main electrode, 26, 28 Insulating material, 27 Side, 27a Vertical portion, 27b Inclined portion, 31a, 31b, 32a, 32c, 33, 34 Bonding material, 41 Thermally conductive resin insulating layer, 42 Insulating substrate, 51 Support plate, 52 Lower electrode, 53, 55 Main circuit wiring, 54 Control wiring, 61 Groove, 81 Underfill resin, 91 Sealing material, 100 Conductive portion, 102, 103, 104 Mounting substrate, 110 Main wiring portion, 201 Base plate, 202 Outer case, S1 First surface, S2 Second surface.

Claims

1. A power semiconductor device comprising: a power semiconductor device; and a main wiring portion electrically connected to the power semiconductor device, wherein the power semiconductor device comprises: a semiconductor substrate including a first surface and a second surface opposite the first surface; a first main electrode provided on the first surface of the semiconductor substrate; a second main electrode provided on the second surface of the semiconductor substrate; and a termination structure provided on the first surface of the semiconductor substrate, wherein the main wiring portion is electrically connected to the first main electrode and is positioned on the opposite side of the first main electrode from the second main electrode, and at least a portion of the portion of the main wiring portion facing the termination structure does not have an insulating layer between it and the termination structure.

2. The power semiconductor device according to claim 1, wherein the main wiring portion and at least a portion of the termination structure are continuous, and at least a portion of the termination structure forms a part of a current path and a heat dissipation path.

3. The power semiconductor device according to claim 1 or 2, wherein the distance between the main wiring portion and the termination structure is less than 0.2 mm.

4. The power semiconductor device according to any one of claims 1 to 3, wherein the termination structure is a field plate structure.

5. The power semiconductor device according to any one of claims 1 to 4, wherein the semiconductor substrate is a gallium oxide-based semiconductor.

6. The power semiconductor device according to any one of claims 1 to 5, wherein grooves are provided in the main wiring portion, and the grooves are provided so as to face each other along the outer periphery of the termination structure.

7. The power semiconductor device according to any one of claims 1 to 6, wherein the power semiconductor device includes an insulating material, and the insulating material is formed on a side surface of the power semiconductor device.

8. The power semiconductor device according to claim 7, wherein said side surface of said power semiconductor device is provided with an inclined portion.

9. The power semiconductor device according to any one of claims 1 to 8, further comprising an underfill resin, said underfill resin being disposed in a gap between said power semiconductor device and said main wiring portion.

10. A power conversion device comprising the power semiconductor device according to any one of claims 1 to 9, a main conversion circuit that converts input power and outputs it, and a control circuit that outputs a control signal to the main conversion circuit to control the main conversion circuit.

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