Light-emitting device

Abstract

This light-emitting device comprises: a plurality of semiconductor light-emitting elements that have first and second electrode layers and a light-emitting layer and that emit light from the side of the second electrode layer; electrode pads for supplying power to the semiconductor light-emitting elements; and wiring that electrically connects the second electrode layers of the semiconductor light-emitting elements and the electrode pads. The semiconductor light-emitting elements include a semiconductor light-emitting element arranged in a first region less than a first distance from the electrode pad, and a semiconductor light-emitting element arranged in a second region of a first distance or more from the electrode pad. The wiring includes first and second wirings, the first wiring is in contact with the second electrode layer of each of the semiconductor light-emitting elements, the first and second wirings are not in contact with each other in the first region and are in contact with each other in the second region, and an end part, on the first region side, of a portion where the first wiring and the second wiring are in contact with each other is located between the semiconductor light-emitting elements adjacent to each other with a boundary between the first region and the second region interposed therebetween.

Description

Light-emitting device

[0001] The present invention relates to a light emitting device.

[0002] Light-emitting devices in which vertical cavity surface-emitting laser (VCSEL) elements are arranged two-dimensionally are being developed as light sources for LiDAR (Light Detection and Ranging) systems, 3D (Dimensional) sensors, etc. For example, in distance measuring devices, studies are being conducted to arrange VCSEL elements with a wide light-emitting diameter at a high density (narrow pitch) with the aim of increasing output and miniaturizing elements to improve distance measurement performance (sensitivity, resolution, extended distance measurement range, etc.).

[0003] The driving methods for the light source in a LiDAR system include a flash driving method, in which all light-emitting elements constituting the array are lit simultaneously to measure distances over a wide area, and a sequential driving method, in which multiple light-emitting regions constituting the array are lit in sequence. For example, in the sequential driving method, if the optical power density of some of the multiple light-emitting regions can be made equal to the optical power density of the entire element, it is possible to improve distance measurement performance.

[0004] Patent Document 1 discloses a surface-emitting laser array element in which the wiring for supplying current to the VCSEL element has a two-layer structure, and the wiring structure is changed depending on the light-emitting region, thereby improving the uniformity of the potential distribution across the entire array.

[0005] Japanese Patent Application Laid-Open No. 2017-216285

[0006] However, although the technology described in Patent Document 1 can improve the uniformity of the potential distribution over the entire array, there is a possibility that the reliability of the wiring may be reduced due to local current concentration depending on the driving conditions.

[0007] According to one disclosure of the present specification, there is provided a light emitting device comprising: a plurality of semiconductor light emitting elements, each having a first electrode layer, a second electrode layer, and a light emitting layer disposed between the first electrode layer and the second electrode layer, and emitting light from the side of the second electrode layer; electrode pads for supplying power to the plurality of semiconductor light emitting elements; and wiring electrically connecting the second electrode layer of each of the plurality of semiconductor light emitting elements to the electrode pad, wherein the plurality of semiconductor light emitting elements include semiconductor light emitting elements disposed in a first region that is less than a first distance from the electrode pad and semiconductor light emitting elements disposed in a second region that is the first distance or more from the electrode pad, the wiring having a first wiring and a second wiring, the first wiring being in contact with the second electrode layer of each of the plurality of semiconductor light emitting elements, the first wiring and the second wiring not being in contact with each other in the first region but being in contact with each other in the second region, and an end portion of the contact portion between the first wiring and the second wiring on the first region side being located between adjacent semiconductor light emitting elements across the boundary between the first region and the second region.

[0008] According to the present invention, in a light emitting device having a plurality of light emitting elements, it is possible to improve the uniformity of the light emission intensity while suppressing a decrease in the reliability of the wiring.

[0009] FIG. 1 is a plan view schematically illustrating a configuration of a light-emitting device according to the first embodiment. FIG. 2 is a cross-sectional view (part 1) illustrating a configuration of a light-emitting element constituting the light-emitting device according to the first embodiment. FIG. 3 is a cross-sectional view (part 2) illustrating a configuration of a light-emitting device according to the first embodiment. FIG. 4 is a cross-sectional view (part 4) illustrating a method of manufacturing a light-emitting device according to the first embodiment. FIG. 5 is a cross-sectional view (part 5) illustrating a method of manufacturing a light-emitting device according to the first embodiment. FIG. 6 is a cross-sectional view (part 6) illustrating a method of manufacturing a light-emitting device according to the first embodiment. 10A to 10C are cross-sectional views (part 8) illustrating the process of manufacturing the light-emitting device according to the first embodiment. FIG. 11B are cross-sectional views (part 9) illustrating the process of manufacturing the light-emitting device according to the first embodiment. FIG. 12A to 12C are cross-sectional views (part 10) illustrating the process of manufacturing the light-emitting device according to the first embodiment. FIG. 13A are cross-sectional views (part 1) illustrating the process of manufacturing a light-emitting element constituting the light-emitting device according to the second embodiment. FIG. 14B are cross-sectional views (part 1) illustrating the process of manufacturing a light-emitting device according to the third embodiment. FIG. 15A are cross-sectional views (part 2) illustrating the process of manufacturing a light-emitting device according to the third embodiment. FIG. 16A are cross-sectional views (part 3) illustrating the process of manufacturing a light-emitting device according to the fourth embodiment.FIG. 10 is a cross-sectional view (part 4) illustrating a process of manufacturing a light-emitting device according to a reference example of the fourth embodiment. FIG. 11 is a cross-sectional view (part 1) illustrating a process of manufacturing a light-emitting device according to the fourth embodiment. FIG. 12 is a cross-sectional view (part 2) illustrating a process of manufacturing a light-emitting device according to the fourth embodiment. FIG. 13 is a cross-sectional view (part 3) illustrating a process of manufacturing a light-emitting device according to the fourth embodiment. FIG. 14 is a cross-sectional view (part 5) illustrating a process of manufacturing a light-emitting device according to the fourth embodiment. FIG. 15 is a schematic plan view (part 1) illustrating an opening in an insulating layer in a light-emitting device according to the fourth embodiment. FIG. 16 is a schematic plan view (part 2) illustrating an opening in an insulating layer in a light-emitting device according to the fourth embodiment. FIG. 17 is a schematic plan view showing a general configuration of a light-emitting device according to a fifth embodiment. FIG. 18 is a schematic view showing the configuration and current path of anode wiring in a light-emitting device according to a fifth embodiment. FIG. 19 is a graph showing current distribution in a light-emitting device according to a fifth embodiment. FIG. 19 is a schematic view showing the configuration and current path of anode wiring in a light-emitting device according to a sixth embodiment. FIG. 19 is a graph showing current distribution in a light-emitting device according to a sixth embodiment. FIG. 10 is a cross-sectional view (part 1) showing an example of the configuration of a light-emitting element constituting a light-emitting device according to a seventh embodiment. FIG. 11 is a diagram showing constituent materials of a semiconductor layer and their resistance values. FIG. 12 is a graph showing the relationship between the area of ​​a non-oxidized portion of a current confinement layer and the element resistance. FIG. 13 is a cross-sectional view (part 2) showing an example of the configuration of a light-emitting element constituting a light-emitting device according to a seventh embodiment. FIG. 14 is a graph showing the relationship between the width of an opening connecting a transparent conductive film to the light-emitting element and the element resistance. FIG. 15 is a graph (part 1) showing the current distribution in a light-emitting device according to a seventh embodiment. FIG. 16 is a graph (part 2) showing the current distribution in a light-emitting device according to a seventh embodiment. FIG. 17 is a diagram showing the element resistance of a light-emitting element in a light-emitting device of Example 11. FIG. 18 is a graph showing the current distribution in a light-emitting device according to an eighth embodiment. FIG. 19 is a diagram showing various electrical characteristics of light-emitting devices of Examples 12 and 13 and Comparative Example 9. FIG. 19 is a cross-sectional view (part 1) showing the general configuration of a light-emitting device according to a ninth embodiment. FIG. 19 is a plan view (part 1) showing an example of the configuration of a light-emitting device according to a tenth embodiment. FIG. 19 is a plan view (part 2) showing an example of the configuration of a light-emitting device according to a tenth embodiment. FIG. 19 is a block diagram showing the general configuration of a distance measuring device according to an eleventh embodiment. FIG. 23 is a block diagram (part 1) showing a configuration example of a moving body according to a twelfth embodiment.FIG. 22 is a block diagram (part 2) showing an example configuration of a moving body according to a twelfth embodiment. FIG. 23 is a schematic plan view showing a schematic configuration of a light-emitting device according to a first reference embodiment. FIG. 24 is a schematic cross-sectional view (part 1) showing a schematic configuration of a light-emitting device according to a first reference embodiment. FIG. 25 is a schematic cross-sectional view (part 2) showing a schematic configuration of a light-emitting device according to a first reference embodiment. FIG. 26 is a graph showing current distribution in a light-emitting device according to a first reference embodiment. FIG. 27 is a schematic plan view showing a schematic configuration of a light-emitting device according to a second reference embodiment. FIG. 28 is a schematic cross-sectional view (part 1) showing a schematic configuration of a light-emitting device according to a second reference embodiment. FIG. 29 is a schematic cross-sectional view (part 2) showing a schematic configuration of a light-emitting device according to a second reference embodiment. FIG. 29 is a graph showing current distribution in a light-emitting device according to a second reference embodiment. FIG. 21 is a diagram (part 1) explaining the relationship between the width and spacing of an emission port and the anode wiring width. FIG. 22 is a diagram (part 2) explaining the relationship between the width and spacing of an emission port and the anode wiring width. FIG. 23 is a diagram (part 3) explaining the relationship between the width and spacing of an emission port and the anode wiring width. FIG. 24 is a diagram showing the results of calculations of the wiring width ratio and the current density ratio when the configuration of the anode wiring is changed.

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the following embodiments do not limit the invention according to the claims. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate identical or similar components, and redundant explanations are omitted as appropriate. Furthermore, each drawing is merely for the purpose of explaining the structure or configuration, and the dimensions of each illustrated component do not necessarily reflect the actual dimensions.

[0011] [First Embodiment] A light-emitting device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 8J. FIG. 1 is a plan view showing the general configuration of a light-emitting device according to this embodiment. FIG. 2 is a cross-sectional view showing the general configuration of a light-emitting element constituting the light-emitting device according to this embodiment. FIGS. 3 and 4 are cross-sectional views showing the general configuration of a light-emitting device according to this embodiment. FIG. 5 is a schematic diagram showing the configuration of anode wiring and current paths in a light-emitting device according to this embodiment. FIG. 6 is a graph showing current distribution in the light-emitting device according to this embodiment. FIG. 7 is a diagram showing the results of calculation of the current density ratio when the configuration of anode wiring of the light-emitting device according to this embodiment is changed. FIGS. 8A to 8J are cross-sectional views showing steps in a manufacturing method for a light-emitting device according to this embodiment.

[0012] The light emitting device according to the present embodiment is a surface-emitting type light emitting device having a plurality of light emitting elements arranged two-dimensionally. Each of the plurality of light emitting elements is configured by a VCSEL element. Fig. 1 shows a schematic plan view of the light emitting device according to the present embodiment as viewed from the light emitting surface side.

[0013] 1, the light-emitting device 100 according to this embodiment includes a substrate 10, a plurality of VCSEL elements 20, a plurality of anode wirings 70, and a plurality of anode electrode pads 90. The substrate 10 may be a compound semiconductor substrate 22 (described later) or a support substrate on which the compound semiconductor substrate 22 is mounted. For convenience of the following explanation, the surface of the substrate 10 on which the plurality of VCSEL elements 20 are arranged is assumed to be a plane parallel to the XY plane. The direction of light emission from the plurality of VCSEL elements 20 is assumed to be the Z direction.

[0014] The VCSEL elements 20 are arranged in a matrix along the X and Y directions. As an example, assume that 40 VCSEL elements 20 are arranged in the X direction and 40 in the Y direction, for a total of 1,600 VCSEL elements 20, are arranged on the substrate 10. To simplify the drawing, only a portion of these VCSEL elements 20 is shown in FIG. 1 . In the following description, the positional relationship of the components may be expressed by assuming that the X direction is the row direction and the Y direction is the column direction.

[0015] An anode wiring 70 is arranged in each column of the VCSEL element array. That is, a plurality of anode wirings 70 extending in the Y direction are arranged in the X direction on the substrate 10. As an example, it is assumed here that 40 anode wirings 70, corresponding to the number of VCSEL elements arranged in the X direction, are arranged on the substrate 10. Each of the plurality of anode wirings 70 connects in parallel the anodes of the 40 VCSEL elements 20 arranged in the corresponding column.

[0016] The anode electrode pad 90 is an electrode for connecting a connection member, such as a gold (Au) wire or a metal bump, for electrically connecting an external device (not shown) to the light emitting device 100. The anode electrode pad 90 is electrically connected to one end (the upper side in FIG. 1 ) of each of the plurality of anode wirings 70. Here, as an example, it is assumed that 40 anode electrode pads 90, corresponding to the number of anode wirings 70 arranged in the X direction, are arranged on the substrate 10.

[0017] This allows the drive current supplied from the anode electrode pads 90 of each column to be supplied in parallel to the 40 VCSEL elements arranged in the corresponding column via the anode wiring 70 of the corresponding column.

[0018] Here, the region that is less than a predetermined distance from the anode electrode pad 90 is referred to as region 110, and the VCSEL element 20 disposed in region 110 is referred to as VCSEL element 20A. Furthermore, the region that is at least a predetermined distance from the anode electrode pad 90 is referred to as region 112, and the VCSEL element 20 disposed in region 112 is referred to as VCSEL element 20B. For example, line B-B' shown by the two-dot chain line in Figure 1 is the boundary between region 110 and region 112. Boundary line B-B' is located in the region between VCSEL element 20A and VCSEL element 20B that are adjacent in the Y direction.

[0019] FIG. 2 shows a schematic cross-sectional view of a VCSEL element 20 constituting the light-emitting device 100. As shown in FIG. 2 , the VCSEL element 20 may be composed of a compound semiconductor substrate 22, a lower DBR (Distributed Bragg Reflector) layer 24, a resonator portion 26 including an active layer 28, an upper DBR layer 30, and a contact layer 34. The lower DBR layer 24, the resonator portion 26, the upper DBR layer 30, and the contact layer 34 are compound semiconductor epitaxial layers epitaxially grown in this order on the compound semiconductor substrate 22. The upper DBR layer 30 may be provided with a current confinement layer 32 for confining the path of current injected into the active layer 28. The inner portion surrounded by the current confinement layer 32 constitutes the light-emitting portion of the VCSEL element 20. Although the layers constituting the VCSEL device 20 are depicted in FIG. 2 as being in direct contact with each other, other functional layers may be provided between any of the layers.

[0020] The contact layer 34, upper DBR layer 30, and resonator portion 26 are processed into a plurality of mesa structures 36, each having a rectangular shape in a plan view, thereby forming a plurality of VCSEL elements 20, each including one mesa structure 36. The compound semiconductor substrate 22 and lower DBR layer 24 are components common to the plurality of VCSEL elements 20. The planar shape of the VCSEL element 20 (mesa structure 36) is not particularly limited, and may be a shape other than rectangular, for example, circular. Note that in this specification, a planar view refers to a view from the light emission direction (Z direction) of the VCSEL element 20.

[0021] An insulating layer 42 is provided on the top surface and sidewall portions of the mesa structure 36, as well as on the lower DBR layer 24 exposed by processing the contact layer 34, upper DBR layer 30, and resonator portion 26 into the mesa structure 36. An anode wiring 70 made of a metal material is provided on the insulating layer 42. The insulating layer 42 not only provides electrical isolation between the anode wiring 70 and the sidewall portions of the mesa structure 36 and the lower DBR layer 24, but also serves as a protective film to prevent deterioration of the semiconductor surface, such as the sidewall portions of the mesa structure 36. The insulating layer 42 is provided with an opening 44 that has a frame-like shape in plan view and reaches the mesa structure 36. This allows the anode wiring 70 to be electrically connected to the contact layer 34 through the opening 44. The anode wiring 70 is also provided with a rectangular emission port 72 that overlaps with the top surface of the mesa structure 36 in plan view. Light generated by the VCSEL device 20 is emitted from this emission port 72. A cathode electrode 60 common to the plurality of VCSEL elements 20 is provided on the back surface side of the compound semiconductor substrate 22 .

[0022] Although the emission wavelength of the VCSEL element 20 is not particularly limited, this embodiment assumes that the VCSEL element 20 emits light in the 940 nm band. In this case, the compound semiconductor substrate 22 may be, for example, an n-type GaAs substrate. The lower DBR layer 24 may be, for example, an Al 1100 Å (Al 2 O 3 ) layer having an optical film thickness of ¼λc. ０．１ Ga ０．９ As layer and Al ０．９ Ga ０．１The resonator section 26 may be constructed by stacking 35 pairs of layers, each including an n-type layer and an As layer. Here, λc is the center wavelength of the high reflection band of the lower DBR layer 24, which is 940 nm in this embodiment. The resonator section 26 may be constructed of a pin junction consisting of an n-type layer, an undoped spacer section, and a p-type layer. The undoped spacer section may be provided with, for example, three active layers 28. Each active layer 28 may be constructed of, for example, a multiple quantum well including four quantum well layers, each of which has an 8 nm thick InGaAs well layer sandwiched between 10 nm thick AlGaAs barrier layers. In this case, the resonator section 26 includes a total of 12 quantum well layers. The n-type layer may be constructed of n-type GaAs layers, the p-type layer may be constructed of p-type GaAs layers, and the remaining portions of the undoped spacer section may be constructed of undoped GaAs layers. The upper DBR layer 30 may be constructed of, for example, an AlGaAs layer having an optical thickness of ¼ λc. ０．１ GaAs layer and Al ０．９ The upper DBR layer 30 may be configured by stacking 20 pairs of layers, each of which is a stack of a GaAs layer. ０．９８ Ga ０．０２ A current confinement layer 32 is provided, which is formed by oxidizing a portion of the As layer. The current confinement layer 32 has a non-oxidized portion in the center of the mesa structure 36 and an oxidized portion near the sidewall of the mesa structure 36. As a result, the current injected into the VCSEL element 20 flows only through the non-oxidized portion, and therefore, only the portion of the VCSEL element 20 that overlaps with the center of the mesa structure 36 in plan view oscillates as a laser. The contact layer 34 has a thickness of 50 nm and a carrier concentration of 1×10 １９ cm －３ This improves the electrical contact between the upper DBR layer 30 and the anode wiring 70.

[0023] Fig. 3 is a cross-sectional view taken along lines III1-III1' and III2-III2' in Fig. 1. Fig. 4 is a cross-sectional view taken along lines IV1-IV1' and IV2-IV2' in Fig. 1. The cross-sectional view taken along line III1-III1' in Fig. 3 and the cross-sectional view taken along line IV1-IV1' in Fig. 4 are cross-sectional views taken on a plane parallel to the Y-Z plane passing through the anode electrode pad 90. The cross-sectional view taken along line III2-III2' in Fig. 3 is a cross-sectional view taken on a plane parallel to the Y-Z plane passing through the injection port 72. The cross-sectional view taken along line IV2-IV2' in Fig. 4 is a cross-sectional view taken on a plane parallel to the Y-Z plane passing through a portion of the opening 44 extending in the Y direction.

[0024] In this embodiment, the anode wiring 70 is composed of a wiring 46 and a wiring 52 that is composed of a wiring layer located above the wiring layer that constitutes the wiring 46. The anode electrode pad 90 is also composed of the wiring 52.

[0025] An insulating layer 50 is provided in a portion of the region between the wiring 46 and the wiring 52. More specifically, the insulating layer 50 disposed between the wiring layer constituting the wiring 46 and the wiring layer constituting the wiring 52 is provided in the region 110 but not in the region 112. In other words, there is no electrical path connecting the wiring 46 and the wiring 52 in the region extending from the anode electrode pad 90 to the region 110. On the other hand, in the region 112, the wiring 46 and the wiring 52 are stacked directly without an insulating layer therebetween, and are physically and electrically connected throughout the entire region 112.

[0026] 3 and 4 , the end of the insulating layer 50 on the side of region 112 is located in the region between the mesa structure 36 of the VCSEL device 20A and the mesa structure 36 of the VCSEL device 20B. In other words, the electrical connection portion between the wiring 46 and the wiring 52 at the boundary 140 between the regions 110 and 112 is located in the region between the mesa structure 36 of the VCSEL device 20A and the mesa structure 36 of the VCSEL device 20B. As a result, the width in the X direction of the electrical connection portion between the wiring 46 and the wiring 52 at the boundary 140 between the regions 110 and 112 is equal to the width in the X direction of the anode wiring 70.

[0027] The anode side (contact layer 34) of both VCSEL elements 20A and 20B is in contact with wiring 46. However, the anode wiring 70 at the connection portion with VCSEL element 20A is configured with a single-layer structure of wiring 46, whereas the anode wiring 70 at the connection portion with VCSEL element 20B is configured with a layered structure (layered wiring) of wiring 46 and wiring 52. The same is true for the other VCSEL elements 20A and 20B not shown in FIGS.

[0028] 3 and 4 , the anode electrode pad 90 has a single-layer structure of the wiring 52, but the anode electrode pad 90 does not necessarily have to have a single-layer structure of the wiring 52 and may be formed of multiple electrode layers. The anode electrode pad 90 only needs to be configured to selectively supply an externally supplied current to the wiring 52 in the region 110. For example, the anode electrode pad 90 configured with the wiring 46 may be connected to the wiring 52 in the region 110. Furthermore, in the configuration examples of FIGS. 3 and 4 , the wiring 46 does not extend to the layer below the anode electrode pad 90, but the wiring 46 may be configured to extend to the layer below the anode electrode pad 90 together with the insulating layer 50.

[0029] 5 is a schematic diagram visually illustrating the configuration of the anode wiring 70 and the flow of current supplied from the anode electrode pad 90. In FIG. 5, the first VCSEL element 20A from the anode electrode pad 90 side is １ , the second VCSEL element 20A ２ , the (n-1)th VCSEL element 20A ｎ－１ , the nth VCSEL element 20B ｎ , the (n+1)th VCSEL element 20B ｎ＋１ The boundary 140 between the region 110 and the region 112 is the (n-1)th VCSEL element 20A. ｎ－１ and the n-th VCSEL element 20B ｎ It is assumed to be located between

[0030] 5, resistance R1 is the wiring resistance between the VCSEL elements 20 in the wiring 46, and resistance R2 is the wiring resistance between the VCSEL elements 20 in the wiring 52. Resistance R12 is the wiring resistance between the VCSEL elements 20 in the laminated film of the wiring 46 and the wiring 52 (the parallel resistance of resistances R1 and R2). Resistance R10 is the wiring resistance equivalent to half of resistance R1, and resistance R20 is the wiring resistance equivalent to half of resistance R2. Resistance R120 is the wiring resistance equivalent to half of resistance R12 (the parallel resistance of resistances R10 and R20).

[0031] By configuring the anode electrode pad 90 and the anode wiring 70 in this manner, the current I supplied from the anode electrode pad 90 to the anode wiring 70 １ First, the current I flows in the −Y direction through the region 110 via the wiring 52 and reaches the boundary 140 between the region 110 and the region 112. Then, the current I １ is a current I that flows in the Y direction in the region 110, turning back via the wiring 46. ２１ and a current I flows in the −Y direction through the region 112 via the stacked film of the wiring 46 and the wiring 52. ２２ The current I flows through the wiring 46 in the Y direction. ２１ is supplied to the VCSEL element 20A disposed in the region 110. A current I flows in the −Y direction through the laminated film of the wiring 46 and the wiring 52. ２２ is supplied to the VCSEL element 20B disposed in the region 112. This makes it possible to supply current to all of the VCSEL elements 20A and 20B connected to the anode wiring 70.

[0032] 6 is a graph showing the results of calculations of the current values ​​flowing through each of multiple VCSEL elements 20 connected to a common anode electrode pad 90. The horizontal axis indicates the number of the VCSEL elements 20 counted from the anode electrode pad 90 side, and the vertical axis indicates the current value flowing through each VCSEL element 20. The solid line indicates the calculation results for the light-emitting device of this embodiment (Example 1), and the dashed line indicates the calculation results for the light-emitting device of the first reference embodiment described below (Reference Example 1).

[0033] In Example 1, it is assumed that 40 VCSEL elements 20 are connected to one anode electrode pad 90, and a boundary portion 140 is provided between the 16th and 17th VCSEL elements 20 from the anode electrode pad 90 side. In the calculation, the interval between the light-emitting points of the VCSEL elements 20 is 30 μm, the width of the non-oxidized portion of the current confinement layer 32 of the VCSEL element 20 is 17.3 μm, the thickness and width of the wiring 46 and wiring 52 are 1 μm and 6 μm, respectively, and the amount of current injected into the anode electrode pad 90 is 2.4 A.

[0034] In the light-emitting device of this embodiment, as described above, current is supplied to each VCSEL element 20 through the wiring 46 from the boundary 140 between the regions 110 and 112. Therefore, the current values ​​are highest in the 16th VCSEL element 20A and the 17th VCSEL element 20B, which are adjacent to the boundary 140. The current values ​​flowing through the VCSEL elements 20 become increasingly smaller from the 16th VCSEL element 20A toward the first VCSEL element 20A, and from the 17th VCSEL element 20B toward the 40th VCSEL element 20B. As a result, the current distribution in the light-emitting device of this embodiment has a mountain shape, as shown by the solid line in FIG. 6 . The ratio of the minimum to the maximum current values ​​(minimum / maximum) at the 40 light-emitting points was 0.71. If the minimum current value required for the light-emitting operation of one VCSEL element 20 is 0.06 A, the minimum current value that needs to be injected from one anode electrode pad 90 to which 40 VCSEL elements 20 are connected is 2.8 A, and the power consumption in this case is 23.5 W.

[0035] In contrast, in the light-emitting device of the first reference embodiment, the VCSEL elements 20 closer to the anode electrode pad 90 have a higher current value, and the VCSEL elements 20 farther from the anode electrode pad 90 have a lower current value. The ratio of the minimum to the maximum current values ​​at the 40 light-emitting points was 0.24. If the minimum current value required for the light-emitting operation of one VCSEL element 20 is 0.06 A, then the minimum current value that needs to be injected from one anode electrode pad 90 to which 40 VCSEL elements 20 are connected is 4.7 A, and the power consumption in this case is 45.1 W.

[0036] Therefore, according to the light emitting device of this embodiment, it is possible to suppress the variation in the current value supplied to the multiple VCSEL elements 20 connected to one anode electrode pad 90 and reduce power consumption more than the light emitting device of the first reference embodiment.

[0037] Furthermore, in the light-emitting device of this embodiment, as described above, the boundary 140 between the region 110 and the region 112 is located in the region between the mesa structure 36 of the VCSEL element 20A and the mesa structure 36 of the VCSEL element 20B. That is, the X-direction width of the electrical connection between the wiring 46 and the wiring 52 at the boundary 140 is equal to the X-direction width of the anode wiring 70. Therefore, in the light-emitting device of this embodiment, the current density at the boundary 140, where the current value is maximum, can be reduced compared to the light-emitting device of the second reference embodiment described below. This suppresses deterioration of the anode wiring 70 due to electromigration, and a highly durable light-emitting device can be realized.

[0038] Figure 7 summarizes the results of calculations of the wiring width ratio and current density ratio when the configuration of the anode wiring 70 is changed. In Figure 7, Example 2 shows the results when the pitch between the VCSEL elements 20 is 30 μm and the opening diameter of the emission port 72 is 10 μm in the configuration of Figure 47A (described later). Example 3 shows the results when the pitch between the VCSEL elements 20 is 30 μm and the opening diameter of the emission port 72 is 17 μm (high optical power density) in the configuration of Figure 47B (described later). Example 4 shows the results when the pitch between the VCSEL elements 20 is 30 μm, the opening diameter of the emission port 72 is 10 μm, and the separation width between the anode wirings 70 is 3 μm (sequential drive mode) in the configuration of Figure 47C (described later). Example 5 shows the results (high optical power density + sequential driving mode) when the pitch between the VCSEL elements 20 is 30 μm, the opening diameter of the emission port 72 is 17 μm, and the separation width between the anode wirings 70 is 3 μm in the configuration shown in FIG. 47C described below.

[0039] 7, the current density ratio is the ratio of the maximum current density to the area of ​​the injection hole 72 when the current density is constant, and is shown as a value based on Reference Example 4 described later. This current density ratio is 0.67 for Example 2, 1.93 for Example 3, 0.74 for Example 4, and 2.14 for Example 5. The current density ratio for the first reference embodiment is the ratio of the current density of Examples 2, 3, 4, and 5 to Reference Examples 4, 5, 6, and 7 described later, and is 0.67 for Example 1, 0.43 for Example 3, 0.63 for Example 4, and 0.37 for Example 5.

[0040] 7, the current density at the boundary portion 140 in Examples 2, 3, 4, and 5 is lower than the current density in Reference Examples 4, 5, 6, and 7. That is, in this embodiment, when the anode wiring 70 has any of the configurations shown in Figures 47A to 47C, it is found that the effect of suppressing electromigration is higher than in the second reference embodiment described later.

[0041] In this embodiment, a boundary 140 is provided between the 16th and 17th VCSEL elements 20 from the anode electrode pad 90 side, and it is desirable to appropriately set the location of the boundary 140 so that the current value between the VCSEL elements 20 becomes small.

[0042] Next, a method for manufacturing the light emitting device according to this embodiment will be described with reference to Figures 8A to 8J. Note that, although the method for manufacturing the light emitting device according to this embodiment will be described focusing on the portion where VCSEL element 20A and VCSEL element 20B are adjacent to each other, other portions can also be manufactured using a similar process.

[0043] First, an n-type GaAs substrate, for example, is prepared as the compound semiconductor substrate 22. Next, the lower DBR layer 24, the resonator section 26, the upper DBR layer 30 including a selective oxidation layer, and the contact layer 34 are grown in this order on the compound semiconductor substrate 22 by metal organic chemical vapor deposition or molecular beam epitaxy to form a compound semiconductor epitaxial layer. The lower DBR layer 24 is made of, for example, n-type Al. ０．１ Ga ０．９ As layer and n-type Al ０．９ Ga ０．１The resonator section 26 may be constructed by repeatedly stacking a predetermined number of layers, each of which includes an n-type layer, an undoped spacer section, and a p-type layer. The undoped spacer section may be provided with, for example, three active layers 28. Each active layer 28 may be constructed with, for example, a multiple quantum well including four quantum well layers, each of which has an 8-nm-thick InGaAs well layer sandwiched between 10-nm-thick AlGaAs barrier layers. In this case, the resonator section 26 includes a total of 12 quantum well layers. The n-type layer may be constructed with an n-type GaAs layer, the p-type layer may be constructed with a p-type GaAs layer, and the remaining portions of the undoped spacer section may be constructed with undoped GaAs layers. The upper DBR layer 30 may be constructed with, for example, a p-type AlGaAs layer. ０．１ Ga ０．９ As layer and p-type Al ０．９ Ga ０．１ The selective oxidation layer can be formed by repeatedly stacking a predetermined number of layers of p-type Al and As layers. ０．９８ The contact layer 34 may be formed of, for example, a p-type GaAs layer.

[0044] Next, silicon oxide is deposited on the contact layer 34 by, for example, plasma CVD to form a hard mask 38 made of the silicon oxide layer (FIG. 8A).

[0045] Next, the hard mask 38 is patterned into a shape according to the planar layout of the mesa structure 36 using photolithography and wet etching (FIG. 8B).

[0046] Next, the contact layer 34, the upper DBR layer 30, and the resonator portion 26 are dry-etched using the hard mask 38 as a mask, and the contact layer 34, the upper DBR layer 30, and the resonator portion 26 are processed into the mesa structure 36. At this time, the compound semiconductor epitaxial layer is etched at least until the active layer 28 of the resonator portion 26 is divided into each VCSEL element 20. It is more preferable that the etching of the compound semiconductor epitaxial layer reaches a portion of the lower DBR layer 24.

[0047] The shape of the mesa structure 36, particularly its sidewall angle, is desirably selected appropriately depending on the specifications and performance required of the light-emitting device 100, manufacturing process considerations, and the like. For example, if it is desired to arrange the light-emitting points (VCSEL elements 20) at high density, it is preferable to make the sidewall angle closer to vertical. If there is a concern that a mesa step may cause a discontinuity in the film formed on the side surface of the mesa structure 36, such as an insulating layer or wiring layer, which may adversely affect device characteristics, it is preferable that the sidewall angle be smaller than vertical.

[0048] Next, heat treatment is performed in a water vapor atmosphere to form the p-type Al selective oxidation layer. ０．９８ The GaAs layer is partially oxidized from the sidewall portion of the mesa structure 36 to form the current confinement layer 32 (FIG. 8C).

[0049] Next, photolithography is used to form a resist film 40 that covers the regions between the mesa structures 36 and exposes at least a portion of the hard mask 38 (FIG. 8D). Next, using the resist film 40 as a mask, the hard mask 38 is removed by wet etching using, for example, a diluted hydrofluoric acid solution (FIG. 8E). Next, the resist film 40 is removed by, for example, ashing (FIG. 8F).

[0050] Next, silicon oxide is deposited by, for example, plasma CVD to form the insulating layer 42. Next, the insulating layer 42 is patterned using photolithography and dry etching to form an opening 44 in the insulating layer 42 that reaches the contact layer 34.

[0051] Next, a resist film (not shown) is formed using photolithography to cover areas other than the area where the wiring 46 is to be formed, and a metal film is deposited over the entire surface by vacuum deposition. After that, the metal film in the unnecessary areas is removed together with the resist film by lift-off, thereby forming the wiring 46 with an opening 48 on the top surface of the mesa structure 36 ( FIG. 8G ).

[0052] Next, silicon oxide is deposited using, for example, plasma CVD to form an insulating layer 50 made of silicon oxide. Next, photolithography is used to form a resist film (not shown) that covers the regions where the VCSEL elements 20A and 20B are to be formed, the openings 48, and exposes the remaining regions where the VCSEL elements 20B are to be formed. Next, using this resist film as a mask, the insulating layer 50 is etched by, for example, wet etching using a diluted hydrofluoric acid solution, to remove the insulating layer 50 from the regions where the VCSEL elements 20B are to be formed, excluding the openings 48. Next, the resist film is removed by, for example, ashing ( FIG. 8H ).

[0053] Next, a resist film (not shown) is formed using photolithography to cover areas other than the area where the wiring 52 is to be formed, and a metal film is deposited over the entire surface by vacuum deposition. The unnecessary metal film is then removed together with the resist film by lift-off, thereby forming the wiring 52 with an opening 54 on the top surface of the mesa structure 36. In this manner, the anode wiring 70 including the wiring 46 and the wiring 52 is formed ( FIG. 8I ). The emission port 72 of the anode wiring 70 is located in the area where the opening 48 and the opening 54 overlap.

[0054] Next, the back surface of the compound semiconductor substrate 22 opposite to the compound semiconductor epitaxial layer is polished, and a cathode electrode 60 is formed on the polished surface, thereby forming the VCSEL element 20A arranged in the region 110 and the VCSEL element 20B arranged in the region 112 ( FIG. 8J ).

[0055] In this manner, in this embodiment, the in-plane uniformity of the current distribution can be improved, thereby reducing the power input to the VCSEL element array and improving the in-plane uniformity of the light emission intensity. Furthermore, the variation in the current density injected into each VCSEL element can be reduced, thereby suppressing the variation in the lifespan of each VCSEL element. Furthermore, the highest current value injected into each VCSEL element in the VCSEL element array can be reduced, thereby extending the lifespan of the light-emitting device.

[0056] Therefore, according to this embodiment, in a light emitting device having a plurality of light emitting elements, it is possible to improve the uniformity of the light emission intensity while suppressing a decrease in the reliability of wiring and the like.

[0057] In addition to VCSEL elements, semiconductor light-emitting elements such as LEDs and edge-emitting lasers are also widely used in light-emitting devices. However, the occurrence of current variations described above is a problem specific to VCSEL elements and does not occur in LEDs or edge-emitting lasers.

[0058] First, in the case of LEDs, the current density injected into the light-emitting portion is at least one order of magnitude lower than that of VCSEL elements, and the current flowing through the wiring is small even if the area of ​​the light-emitting portion is the same, so electromigration is not a problem. Furthermore, when increasing the light output of an LED, it is easier in terms of design and manufacturing to increase the light-emitting area of ​​a single light-emitting portion than to increase the number of light-emitting points as in the case of VCSEL elements. Therefore, LEDs cannot be configured with multiple light-emitting portions and wiring arranged between them as in the case of VCSEL elements. A typical example of this is a white LED used for lighting, which has a chip size of more than 1 mm and a single light-emitting point, achieving a light output of more than 1 W.

[0059] In the case of an edge-emitting laser, the laser light is output from the chip edge, so the light-emitting surface and the electrode surface are separate surfaces. Therefore, unlike a VCSEL element, an edge-emitting laser does not have a configuration in which the opening for light emission and the wiring are provided on the same plane, and the above-mentioned problem does not occur.

[0060] An example of a semiconductor device in which a large number of semiconductor elements are arranged in a two-dimensional array and wiring is provided on the same surface is a CMOS image sensor, whose wiring is matrix wiring for independently reading signals from each pixel.

[0061] Therefore, unlike a VCSEL element array, in which multiple semiconductor elements are connected in parallel to one wiring, a CMOS image sensor has a different wiring configuration from a VCSEL element array. As a result, in a CMOS image sensor, the problems of wiring resistance due to the length of the wiring and the location where the current density is maximum differ from those in a VCSEL element array, and the countermeasures also differ.

[0062] [Second Embodiment] A light emitting device according to a second embodiment of the present invention will be described with reference to Fig. 9. Components similar to those in the light emitting device according to the first embodiment are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 9 is a cross-sectional schematic diagram showing the general configuration of a light emitting element constituting the light emitting device according to this embodiment.

[0063] The light-emitting device 100 according to this embodiment is similar to the light-emitting device according to the first embodiment, except for the configuration of the VCSEL element 20. That is, as shown in FIG. 9 , each of the VCSEL elements 20 in the light-emitting device 100 according to this embodiment further includes a spacer layer 64 including a saturable absorbing layer 66 between the lower DBR layer 24 and the resonator portion 26. Furthermore, the barrier layers sandwiching the quantum well layer of the active layer 28 are configured to be GaAs layers or AlGaAs layers with a narrow band gap, so that the barrier layers can also function as carrier accumulation layers. A VCSEL element having a saturable absorbing layer is described, for example, in Japanese Patent Application Laid-Open No. 2022-176886.

[0064] More specifically, the spacer layer 64 may be composed of, for example, an undoped GaAs layer. The saturable absorbing layer 66 may be composed of, for example, a multiple quantum well including three quantum well layers, each of which has an 8-nm-thick InGaAs well layer sandwiched between 10-nm-thick AlGaAs barrier layers. The resonator section 26 may be composed of a pin junction consisting of an n-type layer, an undoped spacer section, and a p-type layer. Each of the active layers 28 disposed in the undoped spacer section may be composed of, for example, a multiple quantum well including four quantum well layers, each of which has an 8-nm-thick InGaAs well layer sandwiched between 10-nm-thick GaAs barrier layers. The n-type layer may be composed of an n-type GaAs layer, the p-type layer may be composed of a p-type GaAs layer, and the remaining portions of the undoped spacer section may be composed of undoped GaAs layers. In this embodiment, the saturable absorbing layer 66 is disposed between the lower DBR layer 24 and the resonator section 26, but the present invention is not limited to this and may be disposed between the upper DBR layer 30 and the lower DBR layer 24. For example, the saturable absorbing layer 66 may be disposed in the upper DBR layer 30, in the lower DBR layer 24, or between the upper DBR layer 30 and the lower DBR layer 24.

[0065] Other aspects of the VCSEL element 20 may be the same as those of the light-emitting device according to the first embodiment. By configuring the VCSEL element 20 in this manner, it is possible to emit optical pulses having short, high peak power. Hereinafter, a VCSEL element that emits optical pulses having short, high peak power will be referred to as a high peak power VCSEL element.

[0066] High-peak VCSEL elements have the advantage of being able to output extremely short, high-peak pulses of light of several hundred picoseconds at the start of oscillation. For example, when applied to a light source device in a LiDAR system, improvements in ranging distance and ranging accuracy can be expected. On the other hand, high-peak VCSEL elements also have the advantage that the timing of the pulsed light generated at the start of oscillation depends on the current density. If there is variation in current density among the VCSEL elements, the light emission timing of each VCSEL element will differ. As a result, the overall light emission time of the VCSEL element array will be wider than the width of the pulsed light of a single high-peak VCSEL element, potentially eliminating the benefits of applying high-peak VCSEL elements to a LiDAR system.

[0067] In this regard, the light emitting device 100 of the first embodiment can reduce non-uniformity in the current supplied to each VCSEL element 20 in the VCSEL element array. Therefore, when high peak power VCSEL elements are used as the VCSEL elements 20, it is possible to suppress variations in the oscillation start timing of each VCSEL element and fully utilize the characteristics of high peak power VCSEL elements, that is, to emit optical pulses that are short and have a high peak power.

[0068] For example, when the minimum current density of the VCSEL element 20 is 20 kA / cm ２ When the injected current value is adjusted so as to be equal to or greater than this, in the second reference embodiment (reference example 2), the maximum current density for each VCSEL element 20 is 47.8 kA / cm ２ In contrast, in this embodiment, when the value of the current injected into the VCSEL element 20 is adjusted in the same manner, the maximum current density is 29.1 kA / cm ２ As a result, the difference in pulse delay time between the VCSEL elements 20 can be reduced compared to the second reference embodiment.

[0069] As described above, according to this embodiment, in a light emitting device having a plurality of light emitting elements, it is possible to improve the uniformity of the light emission intensity while suppressing a decrease in the reliability of wiring, etc. Furthermore, according to this embodiment, it is possible to suppress non-uniformity in the oscillation start timing and an increase in the optical pulse width in a VCSEL element array while making use of the characteristics of each high peak VCSEL element.

[0070] [Third Embodiment] A light-emitting device according to a third embodiment of the present invention will be described with reference to FIGS. 10 to 14. Components similar to those in the light-emitting devices according to the first or second embodiment are designated by the same reference numerals, and their descriptions will be omitted or simplified. FIGS. 10 and 11 are cross-sectional views showing the general configuration of a light-emitting element constituting the light-emitting device according to this embodiment. FIG. 10 corresponds to the cross-sectional views taken along lines III1-III1' and III2-III2' in FIG. 1. FIG. 11 corresponds to the cross-sectional views taken along lines IV1-IV1' and IV2-IV2' in FIG. 1. FIG. 12 is a schematic diagram showing the configuration of the anode wiring and the current path in the light-emitting device according to this embodiment. FIG. 13 is a graph showing the current distribution in the light-emitting device according to this embodiment. FIG. 14 is a graph showing the relationship between the resistance value of the resistor section and current variation.

[0071] The light emitting device 100 according to this embodiment is similar to the light emitting device according to the first embodiment, except for the configuration of the anode electrode pad 90 and the configuration of the connection between the anode electrode pad 90 and the VCSEL element 20A closest to the anode electrode pad 90. That is, the anode electrode pad 90 in this embodiment is configured with a layered structure of a wiring 46 and a wiring 52, as shown in Figures 10 and 11. Furthermore, the anode electrode pad 90 and the wiring 46 connected to the VCSEL element 20A closest to the anode electrode pad 90 are connected via a resistor 150. The resistor 150 can be configured with the wiring 46, for example.

[0072] 12 is a circuit diagram visually showing the flow of current supplied from the anode electrode pad 90. In FIG. 12, the first VCSEL element 20A from the anode electrode pad 90 side is １ , the second VCSEL element 20A ２ , the (n-1)th VCSEL element 20A ｎ－１ , the nth VCSEL element 20B ｎ , the (n+1)th VCSEL element 20B ｎ＋１ The boundary 140 between the region 110 and the region 112 is the (n-1)th VCSEL element 20A. ｎ－１ and the n-th VCSEL element 20B ｎIt is located between.

[0073] In FIG. 12 , resistor R9 is the wiring resistance in resistor portion 150 of wiring 46. Resistors R1, R2, R10, R20, R120, and R12 are the same as those in FIG. 5 . The resistance value of resistor R9 is set to a value greater than the resistance values ​​of resistors R1 and R2. Note that the resistance value of resistor R9 can be increased in resistor portion 150 by narrowing the wiring width of wiring 46, increasing the wiring length of wiring 46, reducing the thickness of wiring 46, or constructing wiring 46 from a metal material with high resistance, or by any combination of these. Note that the configuration of the first embodiment can also be said to be a case in which the resistance value of resistor R9 is so large that the current flowing through resistor R9 in the configuration of this embodiment is negligible.

[0074] By configuring the anode wiring 70 in this manner, the current I supplied from the anode electrode pad 90 to the anode wiring 70 ０ is the current I flowing in the −Y direction through the region 110 via the wiring 52. １ and a current I3 that flows in the −Y direction through the region 110 via the wiring 46. １ When the current I reaches the boundary 140, it turns back via the wiring 46 and flows in the Y direction through the region 110. ２１ and a current I flows in the −Y direction through the region 112 via the stacked film of the wiring 46 and the wiring 52. ２２ Current I ２１ and current I ３ is supplied to the VCSEL element 20A disposed in the region 110. ２２ is supplied to the VCSEL element 20B disposed in the region 112. This makes it possible to supply current to all of the VCSEL elements 20A and 20B connected to the anode wiring 70.

[0075] 13 is a graph showing the results of calculations of the current values ​​flowing through each of multiple VCSEL elements 20 connected to a common anode electrode pad 90. The horizontal axis represents the number of the VCSEL elements 20 counted from the anode electrode pad 90 side, and the vertical axis represents the current value flowing through each VCSEL element 20. The solid line represents the calculation results for the light-emitting device of this embodiment (Example 6), and the dashed line represents the calculation results for the light-emitting device of the first reference embodiment described below (Reference Example 2).

[0076] Here, it is assumed that 40 VCSEL elements 20 are connected to one anode electrode pad 90, and a boundary 140 is provided between the 29th and 30th VCSEL elements 20 from the anode electrode pad 90 side. In the calculation, the spacing between the light-emitting points of the VCSEL elements 20 is 30 μm, the width of the non-oxidized portion of the current confinement layer 32 of the VCSEL elements 20 is 17.3 μm, the thickness and width of the wiring 46 and wiring 52 are 1 μm and 6 μm, respectively, and the amount of current injected into the anode electrode pad 90 is 2.4 A. The resistance value of resistor R9 is set to 10 times the resistance values ​​of resistors R1 and R2.

[0077] In the light-emitting device of this embodiment, current is supplied not only from the boundary 140 but also from the VCSEL elements 20 closer to the anode electrode pad 90. Therefore, overall, the VCSEL elements 20 closer to the anode electrode pad 90 tend to have higher current values, and the VCSEL elements 20 farther from the anode electrode pad 90 tend to have lower current values. Furthermore, current is supplied also from the boundary 140, which prevents a decrease in the current value in the VCSEL elements 20 farther from the anode electrode pad 90. The ratio of the minimum to the maximum current values ​​at the 40 light-emitting points was 0.563.

[0078] This value is smaller than 0.71 (Reference Example 3) in the case of the light-emitting device according to the second reference embodiment, which will be described later. This is because current is supplied from the anode electrode pad 90 to the VCSEL element 20 that is close to the anode electrode pad 90 via the resistor portion 150. On the other hand, this value is larger than 0.24 (Reference Example 1) and 0.43 (Reference Example 2) in the case of the light-emitting device according to the first reference embodiment, which will be described later. This shows that supplying current from the boundary portion 140 also makes it possible to suppress variations in the current value injected into each VCSEL.

[0079] Furthermore, if the minimum current value required for the light-emitting operation of one VCSEL element 20 is 0.06 A, the minimum current value that needs to be injected from one anode electrode pad 90 to which 40 VCSEL elements 20 are connected is 2.8 A, and the power consumption in this case is 18.8 W.

[0080] Therefore, according to the light-emitting device of this embodiment, it is possible to reduce the variation in the current value supplied to the multiple VCSEL elements 20 connected to one anode electrode pad 90 and reduce power consumption more than in the light-emitting device of the first reference embodiment.

[0081] 14 is a graph showing the relationship between the variation in the current value injected into each VCSEL and the resistance value of the resistor section 150. The vertical axis represents the ratio (minimum value / maximum value) of the current value of the VCSEL element 20 with the smallest current value to the current value of the VCSEL element 20 with the largest current value among the multiple VCSEL elements 20 connected to one anode wiring 70. The horizontal axis represents the magnification of the resistance value of the resistor section 150 with respect to a predetermined reference value. In FIG. 14, the resistance value between the anode electrode pad 90 and the VCSEL element 20 closest to it in a second reference embodiment (second reference example) described below is used as the reference value, and is represented by the plot with a black circle.

[0082] 14 , the variation in the current value injected into each VCSEL decreases as the resistance value of the resistor section 150 increases (the ratio of minimum value to maximum value approaches 1). It is desirable to appropriately set the resistance value of the resistor section 150 so as to reduce the variation in the current value between the VCSEL elements 20, taking into consideration the location of the boundary section 140.

[0083] The ratio between the minimum and maximum values ​​of the current flowing through the VCSEL element 20 is smaller in this embodiment than in the first embodiment, and the effect of this embodiment in terms of reducing current variations is smaller than that of the first embodiment. However, this embodiment also has the advantage of being able to alleviate current concentration at the boundary 140 between the regions 110 and 112, which is another advantageous effect not obtained in the first embodiment.

[0084] The current flowing from wiring 52 to wiring 46 at boundary 140 and concentrating on the edge passes through resistor R20, so the degree of concentration on the edge can be compared by comparing the current value of resistor R20 (the ratio of the current concentrating on the edge of boundary 140). Comparing the current value flowing through resistor R20, it was 1.13 A in the first embodiment and 0.43 A in this embodiment. In other words, this embodiment can mitigate the current concentrating on the edge.

[0085] Even in the configuration of the first embodiment, in which the current density is lower than in the second reference embodiment, it is preferable to apply this embodiment when the number of VCSEL elements 20 is so large or the drive current value is so large that the durability of the boundary portion 140 is insufficient. In this case, by adjusting the resistance value of resistor R9, it is possible to control the ratio between the minimum and maximum values ​​of the current flowing through the VCSEL elements 20 and the degree of current concentration at the edges.

[0086] As described above, according to this embodiment, in a light emitting device having a plurality of light emitting elements, it is possible to improve the uniformity of the light emission intensity while suppressing a decrease in the reliability of wiring and the like.

[0087] [Fourth Embodiment] A light emitting device and a manufacturing method thereof according to a fourth embodiment of the present invention will be described with reference to Figs. 15 to 19. Components similar to those in the light emitting devices according to the first to third embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 15 is a graph showing current distribution in the light emitting device according to this embodiment. Figs. 16A to 16D are cross-sectional views showing steps in a manufacturing method for a light emitting device according to a reference example of this embodiment. Figs. 17A to 17E are cross-sectional views showing steps in a manufacturing method for a light emitting device according to this embodiment. Figs. 18 and 19 are schematic plan views showing openings in an insulating layer in a light emitting device according to this embodiment.

[0088] One method for reducing the variation in the value of the current supplied to the VCSEL element 20 is to increase the film thickness of the wiring 46, 52. In the first embodiment, the wiring 46, 52 is formed by vapor deposition. However, the film thickness that can be formed by vapor deposition using the lift-off method is limited to a few microns, depending on the width between the wiring and the photoresist used. In this regard, if plating is used to form the wiring 46, 52, it is possible to form the wiring 46, 52 with a film thickness of about 10 μm, which can further reduce the variation in the value of the current supplied to the VCSEL element 20.

[0089] 15 is a graph showing the results of calculations of the current values ​​flowing through each of the multiple VCSEL elements 20 connected to a common anode electrode pad 90. The horizontal axis indicates the number of the VCSEL elements 20 counted from the anode electrode pad 90 side, and the vertical axis indicates the current value flowing through each VCSEL element 20. The solid line indicates the calculation results for the light-emitting device of this embodiment, and the dashed line indicates the calculation results for the light-emitting device of the first reference example described below.

[0090] The calculations assume that 40 VCSEL elements 20 are connected to one anode electrode pad 90. The spacing between the light-emitting points of the VCSEL elements 20 is 30 μm, the width of the non-oxidized portion of the current confinement layer 32 of the VCSEL elements 20 is 17.3 μm, the width of the anode wiring 70 is 6 μm, and the amount of current injected into the anode electrode pad 90 is 2.4 A. The solid line represents the calculation results (Example 7) for the first embodiment, where the boundary 140 is located between the ninth and tenth VCSEL elements 20 from the anode electrode pad 90 side, the wiring 46 is 1 μm thick, and the wiring 52 is 9 μm thick. The dashed line represents the calculation results (Example 8) for the first embodiment, where the anode wiring 70 is 10 μm thick.

[0091] In both configurations, the thickness of the anode wiring 70 was 10 μm, but when comparing the ratio of the minimum value to the maximum value of the current flowing through the VCSEL element 20, it was 0.81 in Reference Example 4 and 0.88 in Example 7, and an improvement similar to the calculation results shown in the first embodiment was observed.

[0092] One method for improving the electromigration resistance of the anode wiring 70 is to use copper (Cu) instead of gold (Au) as the wiring material. By using copper instead of gold as the wiring material, the electromigration resistance can be improved by approximately 10 times. However, because copper oxidizes more easily than gold, when copper is used for the anode wiring 70, it is preferable to cover its surface with a metal that is less susceptible to oxidation, such as gold.

[0093] However, when copper is used as the wiring material in a configuration similar to that of the first embodiment, the following problems may arise. A typical manufacturing method when copper is used as the wiring material in a configuration similar to that of the first embodiment will be described with reference to FIGS.

[0094] First, the insulating layer 42, the wiring 46, the insulating layer 50, etc. are formed in the same manner as in the manufacturing method of the light-emitting device according to the first embodiment shown in Figures 8A to 8H. Next, copper is deposited on the entire surface by, for example, sputtering to form a seed layer 52a made of copper (Figure 16A).

[0095] Next, a resist film 56 is formed by photolithography to expose the region where the wiring 52 is to be formed and to cover the other regions (FIG. 16B).

[0096] Next, using the resist film 56 as a mask, a plating layer 52b made of copper is grown on the seed layer 52a by electrolytic plating (FIG. 16C).

[0097] Next, the resist film 56 is removed by, for example, ashing, and then the seed layer 52a in the portion covered with the resist film 56 is removed by wet etching using an acid etchant, with the plating layer 52b as a mask, thereby forming the wiring 52 made of a laminated film of the seed layer 52a and the plating layer 52b (FIG. 16C).

[0098] At this time, in the region where the VCSEL element 20B is formed, the wiring 46, the seed layer 52a, and the plating layer 52b are simultaneously exposed to the etchant at the peripheral portion 58 of the bottom of the opening 54. If the ionization tendencies of the metal materials constituting the wiring 46, the seed layer 52a, and the plating layer 52b differ, corrosion of some of the metals may occur due to galvanic action during etching.

[0099] When copper is used as the wiring material for the wiring 46 to improve electromigration resistance, a layered structure in which a gold film is provided on a copper film may be used to prevent the copper surface from oxidizing. Furthermore, when copper is also used for the wiring 52, the dissimilar metals of copper and gold are simultaneously exposed to the etchant during wet etching to remove the seed layer 52a. In particular, since the wiring 46 is a layer that directly supplies current to the VCSEL element 20, corrosion of the wiring 46 may adversely affect the characteristics of the VCSEL element 20.

[0100] Next, a method for manufacturing the light emitting device according to this embodiment will be described with reference to FIGS. 17A to 17E.

[0101] First, the insulating layer 42, the wiring 46, the insulating layer 50, etc. are formed in the same manner as in the manufacturing method of the light-emitting device according to the first embodiment shown in Figures 8A to 8H. At this time, the insulating layer 50 disposed in the region where the VCSEL element 20B is to be formed is formed so that it extends from within the opening 48 onto the edge of the wiring 46 and overlaps the entire region where the opening 54 is to be formed in plan view (Figure 17A).

[0102] Next, copper is deposited on the entire surface by, for example, sputtering to form a seed layer 52a made of copper (FIG. 17B).

[0103] Next, a resist film 56 is formed by photolithography to expose the region where the wiring 52 is to be formed and to cover the other regions. Next, using the resist film 56 as a mask, a plating layer 52b made of copper is grown on the seed layer 52a by electrolytic plating (FIG. 17C).

[0104] Next, the resist film 56 is removed by, for example, ashing, and then the seed layer 52a in the portion covered with the resist film 56 is removed by wet etching using an acid etchant, with the plating layer 52b as a mask. This forms the wiring 52 made of a laminated film of the seed layer 52a and the plating layer 52b (FIG. 17D). At this time, the wiring 46 is protected by the insulating layer 50, so that the wiring 46 can be prevented from being corroded by the etchant.

[0105] Next, the back surface of compound semiconductor substrate 22 opposite to the compound semiconductor epitaxial layer is polished, and cathode electrode 60 is formed on the polished surface, thereby forming VCSEL element 20A arranged in region 110 and VCSEL element 20B arranged in region 112 ( FIG. 17E ).

[0106] In the VCSEL element 20B, current is supplied from the wiring 52 to the wiring 46 through an opening 62 provided in the insulating layer 50. The position of this opening 62 will be explained using Figures 18 and 19. Figure 18 is a plan view showing the general configuration of the light-emitting device according to this embodiment. Figure 19 is an enlarged view of the vicinity of the boundary line B-B' in Figure 18.

[0107] This embodiment differs from the first embodiment in that openings 62 are provided in the insulating layer 50 at the boundary between the region 110 and the region 112 and between the VCSEL elements 20 in the region 112 .

[0108] The openings 62 are preferably set so that the width Lx satisfies the relationship of the following formula (1), where P is the pitch of the injection holes 72, Ls is the width of the injection holes 72, Lx is the width of the openings 62 in the X direction, and Lh is the spacing between the anode wirings 70. Lx>P-Lh-Ls (1)

[0109] By setting the width Lx of the opening 62 as expressed by Equation (1), the wiring width at the boundary 140 can be made wider than in the second reference embodiment described later, thereby reducing the current density at the boundary 140. In this embodiment, the opening 62 is provided between adjacent VCSEL elements 20 in the Y direction, but the location of the opening 62 is not limited thereto. The opening 62 need not overlap with an area where no wiring 52 is provided in a plan view, and at least a portion of the opening 62 may be provided between adjacent VCSEL elements 20 in the X direction. Furthermore, the opening 62 does not necessarily need to be provided in a flat area between adjacent mesa structures 36; at least a portion of the opening 62 may overlap the sidewall or top surface of the mesa structure 36. In particular, by increasing the area of ​​the opening 62 at the boundary between the region 110 and the region 112, the current density at the boundary 140 can be reduced.

[0110] It should be noted that when the wiring 52 is formed by vapor deposition as shown in the first embodiment, there is a possibility that the variation in current value will be greater compared to when the wiring 52 is formed by plating as in the present embodiment. However, if plating is not used, the opening 62 does not need to be provided, and therefore it is possible to further reduce the current density at the boundary portion 140. It is desirable to select an appropriate method for manufacturing the wirings 46, 52 that make up the anode wiring 70 depending on the characteristics required of the light-emitting device 100, etc.

[0111] As described above, according to this embodiment, in a light emitting device having a plurality of light emitting elements, it is possible to improve the uniformity of the light emission intensity while suppressing a decrease in the reliability of wiring and the like.

[0112] [Fifth Embodiment] A light-emitting device according to a fifth embodiment of the present invention will be described with reference to Figs. 20 to 22. Components similar to those in the light-emitting devices according to the first to fourth embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 20 is a plan view showing the general configuration of the light-emitting device according to this embodiment. Fig. 21 is a schematic diagram showing the configuration of the anode wiring and the current path in the light-emitting device according to this embodiment. Fig. 22 is a graph showing the current distribution in the light-emitting device according to this embodiment.

[0113] In the first to fourth embodiments, the anode wiring 70 is described as being composed of two layers of wiring 46 and 52. However, the anode wiring 70 does not necessarily have to be composed of two layers, and can be composed of three or more layers of wiring. In this embodiment, the anode wiring 70 is described as being composed of three layers of wiring.

[0114] 20 , in the light emitting device 100 according to the present embodiment, regions 120, 122, 124, and 126 are defined according to the distance from the anode electrode pad 90. The regions 120, 122, 124, and 126 are spaced further from the anode electrode pad 90 in this order. In FIG. 20 , line B1-B1′ is the boundary between region 122 and region 124, line B2-B2′ is the boundary between region 120 and region 122, and line B3-B3′ is the boundary between region 124 and region 126.

[0115] In the light-emitting device 100 of this embodiment, the anode wiring 70 includes a wiring 46 formed of a first wiring layer, a wiring 52 formed of a second wiring layer above the first wiring layer, and a wiring 76 formed of a third wiring layer above the second wiring layer. The insulating layer disposed between the first wiring layer and the second wiring layer is insulating layer 50, and the insulating layer disposed between the second wiring layer and the third wiring layer is insulating layer 74. The insulating layer 50 is disposed in at least regions 122 and 124, and the insulating layer 74 is disposed in at least regions 120 and 122.

[0116] The VCSEL element 20A is disposed in the region 120. The anode of the VCSEL element 20A is in contact with the wiring 52 / 46, which is formed by directly stacking the wiring 46 and the wiring 52. The wiring 76 is disposed on the wiring 52 / 46 via the insulating layer 74. In other words, the wiring 46, the wiring 52, the insulating layer 74, and the wiring 76 are stacked in this order in the region 120.

[0117] A VCSEL element 20B is disposed in region 122. A wiring 46 is in contact with the anode of the VCSEL element 20B. A wiring 52 is disposed on wiring 46 with an insulating layer 50 interposed therebetween. A wiring 76 is disposed on wiring 52 with an insulating layer 74 interposed therebetween.

[0118] That is, in the region 122, the wiring 46, the insulating layer 50, the wiring 52, the insulating layer 74, and the wiring 76 are stacked in this order.

[0119] A VCSEL element 20C is disposed in region 124. A wiring 46 is in contact with the anode of the VCSEL element 20C. A wiring 76 / 52, in which a wiring 52 and a wiring 76 are stacked directly on top of each other, is disposed on top of the wiring 46 with an insulating layer 50 interposed therebetween. That is, in region 124, the wiring 46, insulating layer 50, and wiring 76 / 52 are stacked in this order.

[0120] The VCSEL element 20D is disposed in the region 126. The anode of the VCSEL element 20D is in contact with a wiring 76 / 52 / 46 formed by directly stacking a wiring 46, a wiring 52, and a wiring 76. In other words, the wiring 46, the wiring 52, and the wiring 76 are stacked in this order in the region 126.

[0121] The wiring 76 is connected to the wiring 52 and the wiring 76 / 52 at a boundary 140 which is the boundary between the region 122 and the region 124. The wiring 52 is connected to the wiring 52 / 46 and the wiring 46 at a boundary 142 which is the boundary between the region 120 and the region 122. The wiring 76 / 52 is connected to the wiring 46 and the wiring 76 / 52 / 46 at a boundary 144 which is the boundary between the region 124 and the region 126. Note that the boundaries 140, 142, and 144 are arranged in the region between adjacent VCSEL elements 20, similar to the boundary 140 in the first to fourth embodiments.

[0122] 21 , resistor R1 is the wiring resistance between the VCSEL elements 20 in wiring 46, resistor R2 is the wiring resistance between the VCSEL elements 20 in wiring 52, and resistor R3 is the wiring resistance between the VCSEL elements 20 in wiring 76. Resistor R10 is the wiring resistance equivalent to half of resistor R1, resistor R20 is the wiring resistance equivalent to half of resistor R2, and resistor R30 is the wiring resistance equivalent to half of resistor R3. Resistor R12 is the wiring resistance between the VCSEL elements 20 in wiring 52 / 46 (the parallel resistance of resistors R1 and R2). Resistor R23 is the wiring resistance between the VCSEL elements 20 in wiring 76 / 52 (the parallel resistance of resistors R2 and R3). Resistor R120 is the wiring resistance equivalent to half of resistor R12 (the parallel resistance of resistors R10 and R20), and resistor R230 is the wiring resistance equivalent to half of resistor R23 (the parallel resistance of resistors R10 and R20). Resistor R123 (not shown) is the wiring resistance (parallel resistance of resistors R1, R2, and R3) between the VCSEL elements 20 in wiring 76 / 52 / 46. Resistor R1230 is the wiring resistance (parallel resistance of resistors R10 and R230) equivalent to half of resistor R123.

[0123] By configuring the anode electrode pad 90 and the anode wiring 70 in this manner, the current supplied from the anode electrode pad 90 to the anode wiring 70 first flows in the −Y direction through the regions 120 and 122 via the wiring 76 and reaches the boundary 140. The current that reaches the boundary 140 then splits into a current that flows in the Y direction through the region 122, turning back via the wiring 52, and a current that flows in the −Y direction through the region 124 via the wiring 76 / 52. The current flowing in the Y direction through the wiring 52 splits at the boundary 142 into a current that flows in the Y direction through the region 120 via the wiring 52 / 46 and a current that flows in the −Y direction through the region 122, turning back via the wiring 46. The current flowing through the wiring 76 / 52 splits at the boundary 144 into a current that flows in the Y direction through the region 124, turning back via the wiring 46, and a current that flows in the −Y direction through the region 126 via the wirings 76 / 52 / 46. This makes it possible to supply current to all of the VCSEL elements 20A, 20B, 20C, and 20D connected to the anode wiring 70.

[0124] 22 is a graph showing the results of calculations of the current values ​​flowing through each of the multiple VCSEL elements 20 connected to a common anode electrode pad 90. The horizontal axis indicates the number of the VCSEL element 20 counted from the anode electrode pad 90 side, and the vertical axis indicates the current value flowing through each VCSEL element 20.

[0125] Here, the number of VCSEL elements 20 connected to one anode electrode pad 90 was set to 40. Boundary 140 was set between the eleventh and twelfth VCSEL elements 20 from the anode electrode pad 90 side. Boundary 142 was set between the ninth and tenth VCSEL elements 20 from the anode electrode pad 90 side. Boundary 144 was set between the twenty-third and twenty-fourth VCSEL elements 20 from the anode electrode pad 90 side. In the calculation, the following conditions were set: the spacing between the light-emitting points of the VCSEL elements 20 was 30 μm, the width of the non-oxidized portion of the current confinement layer 32 of each VCSEL element 20 was 17.3 μm, the thicknesses of the wiring 46 and wiring 52 were 1 μm, the thickness of wiring 76 was 8 μm, and the widths of the wirings 46, 52, and 76 were 6 μm. The amount of current injected into the anode electrode pad 90 was set to 2.4 A.

[0126] In the light-emitting device of this embodiment (Example 8), the current value was high at the boundaries 142 and 144, resulting in an M-shaped distribution as shown by the solid line in Fig. 22. The ratio of the minimum to the maximum current values ​​at the 40 light-emitting points was 0.943, which means that the variation in current values ​​was reduced more than in the fourth embodiment.

[0127] In the above calculation example, the wiring 76 was assumed to be a thick wiring formed by plating, but the method for forming the wiring 76 is not particularly limited, and a vapor deposition method may be used as in the first embodiment.

[0128] In addition, in this embodiment, an example has been shown in which only the wiring 76 of the three wirings 46, 52, and 76 constituting the anode wiring 70 is directly connected to the anode electrode pad 90, but the connection between the anode electrode pad 90 and the wirings 46, 52, and 76 is not limited to this example. For example, as in the third embodiment, the wiring 46 and the wiring 52 may be connected to the anode electrode pad directly or via a resistor.

[0129] As described above, according to this embodiment, in a light emitting device having a plurality of light emitting elements, it is possible to improve the uniformity of the light emission intensity while suppressing a decrease in the reliability of wiring and the like.

[0130] [Sixth Embodiment] A light-emitting device according to a sixth embodiment of the present invention will be described with reference to Figures 23 and 24. Components similar to those in the light-emitting devices according to the first to fifth embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Figure 23 is a plan view showing the general configuration of the light-emitting device according to this embodiment. Figure 24 is a graph showing current distribution in the light-emitting device according to this embodiment.

[0131] In the first to fourth embodiments, the anode wiring 70 is configured with two layers of wiring 46 and 52, and in the fifth embodiment, the anode wiring 70 is configured with three layers of wiring 46, 52, and 76. In this embodiment, the anode wiring 70 is configured with four layers of wiring.

[0132] In the light emitting device 100 according to this embodiment, regions 130, 131, 132, 133, 134, 135, 136, and 137 are defined according to the distance from the anode electrode pad 90. The regions 130, 131, 132, 133, 134, 135, 136, and 137 are spaced further from the anode electrode pad 90 in this order.

[0133] In the light-emitting device 100 of this embodiment, the anode wiring 70 includes wiring 46 formed from the first wiring layer, wiring 52 formed from the second wiring layer, wiring 76 formed from the third wiring layer, and wiring 80 formed from the fourth wiring layer above the third wiring layer.

[0134] The insulating layer disposed between the first wiring layer and the second wiring layer is insulating layer 50, the insulating layer disposed between the second wiring layer and the third wiring layer is insulating layer 74, and the insulating layer disposed between the third wiring layer and the fourth wiring layer is insulating layer 78. Insulating layer 50 is disposed in at least regions 131, 132, 135, and 136, insulating layer 74 is disposed in at least regions 132, 133, 134, and 135, and insulating layer 78 is disposed in at least regions 130, 131, 132, and 133.

[0135] A VCSEL element 20A is disposed in region 130. The anode of the VCSEL element 20A is in contact with wiring 76 / 52 / 46, which is formed by directly stacking wirings 46, 52, and 76. A wiring 80 is disposed on the wirings 76 / 52 / 46 with an insulating layer 78 interposed therebetween.

[0136] That is, in the region 130, the wiring 46, the wiring 52, the wiring 76, the insulating layer 78, and the wiring 80 are stacked in this order.

[0137] A VCSEL element 20B is disposed in region 131. Wiring 46 is in contact with the anode of VCSEL element 20B. Wiring 76 / 52, in which wiring 52 and 76 are directly stacked with insulating layer 50 interposed therebetween, is disposed on wiring 46. Wiring 80 is disposed on wiring 76 / 52 with insulating layer 78 interposed therebetween. In other words, wiring 46, insulating layer 50, wiring 52, wiring 76, insulating layer 78, and wiring 80 are stacked in this order in region 131.

[0138] A VCSEL element 20C is disposed in region 132. A wiring 46 is in contact with the anode of the VCSEL element 20C. A wiring 52 is disposed on wiring 46 with an insulating layer 50 interposed therebetween. A wiring 76 is disposed on wiring 52 with an insulating layer 74 interposed therebetween.

[0139] A wiring 80 is disposed on the wiring 76 via an insulating layer 78. That is, in the region 132, the wiring 46, the insulating layer 50, the wiring 52, the insulating layer 74, the wiring 76, the insulating layer 78, and the wiring 80 are stacked in this order.

[0140] A VCSEL element 20D is disposed in region 133. Wiring 52 / 46, which is formed by directly stacking wiring 46 and 52, is in contact with the anode of the VCSEL element 20D. Wiring 76 is disposed on wiring 52 / 46 with an insulating layer 74 interposed therebetween. Wiring 80 is disposed on wiring 76 with an insulating layer 78 interposed therebetween. In other words, wiring 46, wiring 52, insulating layer 74, wiring 76, insulating layer 78, and wiring 80 are stacked in this order in region 133.

[0141] A VCSEL element 20E is disposed in region 134. The anode of the VCSEL element 20E is in contact with wiring 52 / 46, which is formed by directly stacking wirings 46 and 52. Wiring 80 / 76, which is formed by directly stacking wirings 76 and 80 with an insulating layer 74 interposed therebetween, is disposed on wiring 52 / 46. In other words, in region 134, wiring 46, wiring 52, insulating layer 74, wiring 76, and wiring 80 are stacked in this order.

[0142] A VCSEL element 20F is disposed in region 135. A wiring 46 is in contact with the anode of the VCSEL element 20F. A wiring 52 is disposed on wiring 46 with an insulating layer 50 interposed therebetween. A wiring 80 / 76 is disposed on wiring 52, in which wirings 76 and 80 are directly stacked with an insulating layer 74 interposed therebetween. In other words, in region 135, wiring 46, insulating layer 50, wiring 52, insulating layer 74, wiring 76, and wiring 80 are stacked in this order.

[0143] A VCSEL element 20G is disposed in region 136. A wiring 46 is in contact with the anode of the VCSEL element 20G. A wiring 80 / 76 / 52 is disposed on top of the wiring 46, in which wirings 52, 76, and 80 are stacked directly with an insulating layer 50 interposed therebetween. In other words, in region 136, wiring 46, insulating layer 50, wiring 52, wiring 76, and wiring 80 are stacked in this order.

[0144] The VCSEL element 20H is disposed in the region 137. The anode of the VCSEL element 20H is provided with a wiring 80 / 76 / 52 / 46, in which the wirings 46, 52, 76, and 80 are stacked in series. That is, in the region 136, the wiring 46, wiring 52, wiring 76, and wiring 80 are stacked in this order.

[0145] Wiring 80 is connected to wiring 76 and wiring 80 / 76 at boundary 140, which is the boundary between region 133 and region 134. Wiring 76 is connected to wiring 76 / 52 and wiring 52 at boundary 141, which is the boundary between region 131 and region 132. Wiring 80 / 76 is connected to wiring 52 and wiring 80 / 76 / 52 at boundary 142, which is the boundary between region 135 and region 136. Wiring 76 / 52 is connected to wiring 76 / 52 / 46 and wiring 46 at boundary 143, which is the boundary between region 130 and region 131.

[0146] The wiring 52 arranged in the region 132 is connected to the wiring 46 and the wiring 52 / 46 at the boundary 144 between the region 132 and the region 133. The wiring 52 arranged in the region 135 is connected to the wiring 52 / 46 and the wiring 46 at the boundary 145 between the region 134 and the region 135. The wiring 80 / 76 / 52 is connected to the wiring 46 and the wiring 80 / 76 / 52 / 46 at the boundary 146 between the region 136 and the region 137. Note that the boundaries 140, 141, 142, 143, 144, 145, and 146 are arranged in the region between the adjacent VCSEL elements 20, similar to the boundary 140 in the first to fourth embodiments.

[0147] 23 , resistor R1 is the wiring resistance between the VCSEL elements 20 in wiring 46, and resistor R2 (not shown) is the wiring resistance between the VCSEL elements 20 in wiring 52. Resistor R3 is the wiring resistance between the VCSEL elements 20 in wiring 76, and resistor R4 is the wiring resistance between the VCSEL elements 20 in wiring 80. Resistor R10 is the wiring resistance equivalent to half of resistor R1, resistor R20 is the wiring resistance equivalent to half of resistor R2, R30 is the wiring resistance equivalent to half of resistor R3, and resistor R40 is the wiring resistance equivalent to half of resistor R4. Resistor R12 is the wiring resistance between the VCSEL elements 20 in wiring 52 / 46 (the parallel resistance of resistors R1 and R2). Resistor R23 (not shown) is the wiring resistance between the VCSEL elements 20 in wiring 76 / 52 (the parallel resistance of resistors R2 and R3). Resistor R34 is the wiring resistance between the VCSEL elements 20 in wiring 80 / 76 (the parallel resistance of resistors R3 and R4). Resistor R123 (not shown) is the wiring resistance between the VCSEL elements 20 in wiring 76 / 52 / 46 (the parallel resistance of resistors R1, R2, and R3). Resistor R234 (not shown) is the wiring resistance between the VCSEL elements 20 in wiring 80 / 76 / 52 (the parallel resistance of resistors R2, R3, and R4). Resistor R1234 (not shown) is the wiring resistance between the VCSEL elements 20 in wiring 80 / 76 / 52 / 46 (the parallel resistance of resistors R1, R2, R3, and R4). Resistor R120 is the wiring resistance equivalent to half of resistor R12, resistor R230 is the wiring resistance equivalent to half of resistor R23, and resistor R340 is the wiring resistance equivalent to half of resistor R34. The resistor R1230 is a wiring resistance equivalent to half of the resistor R123, and the resistor R2340 is a wiring resistance equivalent to half of the resistor R234. The resistor R12340 is a wiring resistance equivalent to half of the resistor R1234.

[0148] By configuring the anode electrode pad 90 and the anode wiring 70 in this manner, the current supplied from the anode electrode pad 90 to the anode wiring 70 first flows in the −Y direction through regions 130, 131, 132, and 133 via the wiring 80, and reaches the boundary 140. The current that reaches the boundary 140 then splits into a current that flows in the Y direction through regions 133 and 132, turning back via the wiring 76, and a current that flows in the −Y direction through regions 134 and 135 via the wiring 80 / 76. The current flowing in the Y direction through the wiring 76 splits at the boundary 141 into a current that flows in the Y direction through region 131 via the wiring 76 / 52, and a current that flows in the −Y direction through region 132, turning back via the wiring 52. The current flowing in the −Y direction through wiring 80 / 76 is divided at boundary 142 into a current flowing in the Y direction through region 135 via wiring 52 and a current flowing in the −Y direction through region 136 via wiring 80 / 76 / 52. The current flowing in the Y direction through wiring 76 / 52 is divided at boundary 143 into a current flowing in the Y direction through region 130 via wiring 76 / 52 / 46 and a current flowing in the −Y direction through region 131 via wiring 46. The current flowing in the −Y direction through wiring 52 is divided at boundary 144 into a current flowing in the Y direction through region 132 via wiring 46 and a current flowing in the −Y direction through region 133 via wiring 52 / 46. The current flowing in the Y direction through wiring 52 is divided at boundary 145 into a current flowing in the Y direction through region 134 via wiring 52 / 46 and a current flowing in the −Y direction through region 135 via wiring 46. The current flowing in the −Y direction through the wiring 80 / 76 / 52 is divided at the boundary 146 into a current flowing in the Y direction through the region 136 via the wiring 46 and a current flowing in the −Y direction through the region 137 via the wiring 80 / 76 / 52 / 46. This makes it possible to supply current to all of the VCSEL elements 20A, 20B, 20C, 20D, 20E, 20F, 20G, and 20H connected to the anode wiring 70.

[0149] 23 , boundary 144 is located closer to the anode electrode pad 90 than boundary 140, and boundary 145 is located farther from the anode electrode pad 90 than boundary 140. However, the positional relationship between boundaries 140, 144, and 145 is not limited to this. That is, boundary 144 may be located in the same region between VCSEL elements 20 as boundary 140, or may be located farther from the anode electrode pad 90 than boundary 140. Similarly, boundary 145 may be located in the same region between VCSEL elements 20 as boundary 140, or may be located closer to the anode electrode pad 90 than boundary 140. In these cases, the division of the regions will differ from that shown in FIG. 23 . It is desirable to set the position of the boundary appropriately so as to obtain a desired current distribution.

[0150] 24 is a graph showing the results of calculations of the current values ​​flowing through each of the multiple VCSEL elements 20 connected to a common anode electrode pad 90. The horizontal axis indicates the number of the VCSEL element 20 counted from the anode electrode pad 90 side, and the vertical axis indicates the current value flowing through each VCSEL element 20.

[0151] In this example, the number of VCSEL elements 20 connected to one anode electrode pad 90 was 40. Boundary 140 was set between the eleventh and twelfth VCSEL elements 20 from the anode electrode pad 90 side. Boundary 141 was set between the ninth and tenth VCSEL elements 20 from the anode electrode pad 90 side. Boundary 142 was set between the twenty-first and twenty-second VCSEL elements 20 from the anode electrode pad 90 side. Boundary 143 was set between the sixth and seventh VCSEL elements 20 from the anode electrode pad 90 side. Boundary 144 was set between the eleventh and twelfth VCSEL elements 20 from the anode electrode pad 90 side. Boundary 145 was set between the twentieth and twenty-first VCSEL elements 20 from the anode electrode pad 90 side. Boundary 146 was set between the twenty-sixth and twenty-seventh VCSEL elements 20 from the anode electrode pad 90 side. In the calculation, the spacing between the light-emitting points of the VCSEL elements 20 was set to 30 μm, the width of the non-oxidized portion of the current confinement layer 32 of the VCSEL element 20 was set to 17.3 μm, the thickness of the wiring 46, 52, and 76 was set to 1 μm, the thickness of the wiring 80 was set to 7 μm, and the width of the wiring 46, 52, 76, and 80 was set to 6 μm. The amount of current injected into the anode electrode pad 90 was set to 2.4 A.

[0152] In the light-emitting device of this embodiment (Example 9), the current values ​​at the boundaries 143, 144, 145, and 146 are high, resulting in a distribution with four peaks as shown by the solid lines in Fig. 24. The ratio of the minimum to the maximum current values ​​at the 40 light-emitting points was 0.975, which means that the variation in current values ​​was reduced more than in the fifth embodiment.

[0153] In the fifth embodiment, an example in which the anode wiring 70 is configured with three layers of wiring is shown, and in the present embodiment, an example in which the anode wiring 70 is configured with four layers of wiring is shown, but the same idea can also be applied to the case in which the anode wiring 70 is configured with five or more layers of wiring.

[0154] Specifically, when the anode wiring 70 is configured with three or more layers of wiring, the variation in current value can be reduced by configuring it to satisfy the following relationship, where n is an integer greater than or equal to 2. That is, the insulating layer disposed between the nth wiring layer and the (n-1)th wiring layer is configured to be disposed in a surrounding area including the power supply position from the (n+1)th wiring layer to the nth wiring layer.

[0155] As described above, according to this embodiment, in a light emitting device having a plurality of light emitting elements, it is possible to improve the uniformity of the light emission intensity while suppressing a decrease in the reliability of wiring and the like.

[0156] [Seventh Embodiment] A light-emitting device according to a seventh embodiment of the present invention will be described with reference to FIGS. 25 to 32. Components similar to those in the light-emitting devices according to the first to sixth embodiments are designated by the same reference numerals, and descriptions thereof will be omitted or simplified. FIG. 25 is a cross-sectional view showing the general configuration of a light-emitting element constituting the light-emitting device according to this embodiment. FIGS. 26 and 28 are diagrams showing the constituent materials of the semiconductor layer and their resistance values. FIG. 27 is a graph showing the relationship between the area of ​​the non-oxidized portion of the current confinement layer and the element resistance. FIG. 29 is a graph showing the relationship between the width of the opening connecting the transparent conductive film to the light-emitting element and the element resistance. FIGS. 30 and 31 are graphs showing current distribution in the light-emitting device according to this embodiment. FIG. 32 is a diagram showing the element resistance of the light-emitting element in the light-emitting device of Example 11.

[0157] In the light-emitting device 100 according to this embodiment, the VCSEL element array is made up of a plurality of VCSEL elements 20 of different types with different resistance values. More specifically, when a VCSEL element array is made up of a plurality of VCSEL elements 20 with the same element resistance, the VCSEL elements 20 in a portion where the current value is relatively large are made up of VCSEL elements 20 with higher element resistance than the other VCSEL elements 20. The element resistance of the VCSEL element 20 is the resistance value between the cathode electrode 60 and the anode wiring 70.

[0158] There are no particular limitations on the method for changing the element resistance of a portion of the VCSEL elements 20. For example, the element resistance of the VCSEL elements 20 can be changed by adding a semiconductor layer between the cathode electrode 60 and the anode wiring 70, changing the area (width) of the non-oxidized portion of the current confinement layer 32, or changing the contact area between the anode wiring 70 and the contact layer 34. Alternatively, the element resistance of the VCSEL elements 20 may be changed by changing the effective carrier concentration of at least some of the semiconductor layers that make up the VCSEL elements 20.

[0159] 25 is a schematic cross-sectional view showing an example of a VCSEL device 20H in which the device resistance is increased by inserting a semiconductor layer 68. In the VCSEL device 20H shown in FIG. 25, a semiconductor layer 68 is inserted between the upper DBR layer 30 and the contact layer 34.

[0160] The material of the semiconductor layer 68 is not particularly limited. In the case of the VCSEL device 20 described in the first embodiment, the semiconductor layer 68 may be composed of, for example, a p-type GaAs layer, a p-type AlGaAs layer, a p-type AlInP layer, or the like. １７ cm －３ 1 and 2 show the physical properties of these materials when the film thickness is set to 1 μm, and the percentage increase in device resistance compared to the VCSEL device 20 without the semiconductor layer 68. For example, when the semiconductor layer 68 is inserted between the upper DBR layer 30 and the contact layer 34 with a doping concentration of 1×10 １７ cm －３ When the AlInP layer having a thickness of 250 nm is inserted, the device resistance of the VCSEL device 20H becomes 1.20 times that when the semiconductor layer 68 is not inserted.

[0161] FIG. 27 shows the area of ​​the non-oxidized portion of the current confinement layer 32 and the area of ​​the non-oxidized portion of the current confinement layer 32 when the area is 300 μm ２ 27 is a graph showing the results of calculations of the relationship between the ratio of the element resistance to the element resistance when . As shown in Fig. 27, the element resistance of the VCSEL element 20H increases as the area of ​​the non-oxidized portion of the current confinement layer 32 decreases. For example, when the width of the non-oxidized portion of the current confinement layer 32 is 17.3 µm, the area is 300 µm. ２By narrowing the diameter of the non-oxidized portion of the current confinement layer 32 to 16.5 μm, the area becomes 272 μm ２ The element resistance of the VCSEL element 20H is ２ The area of ​​the non-oxidized portion of the current confinement layer 32 can be changed by changing the width of the mesa structure 36, for example.

[0162] 28 is a cross-sectional view showing an example of a VCSEL device 20H in which a transparent conductive film 82 is provided between the anode wiring 70 and the contact layer 34. In the VCSEL device 20H shown in FIG. 28, the transparent conductive film 82 is provided between the insulating layer 50 and the anode wiring 70 so as to cover the mesa structure 36, and current supplied from the anode wiring 70 is injected into the VCSEL device 20H via the transparent conductive film 82. In this case, the device resistance of the VCSEL device 20 can be changed by changing the area (width d2) of the opening in the insulating layer 50. The transparent conductive film 82 can be made of, for example, indium tin oxide (ITO).

[0163] FIG. 29 is a graph showing the calculated relationship between the width d2 of the opening in the insulating layer 50 and the ratio of the element resistance to the element resistance when the width d2 is 10.6 μm. In FIG. 29, the plots marked with a black circle indicate actual measurements. As shown in FIG. 29, the element resistance of the VCSEL element 20H decreases as the width d2 increases. For example, when the width d2 is narrowed from 10.6 μm to 7.5 μm, the element resistance of the VCSEL element 20H becomes 1.15 times the element resistance when the width d2 is 10.6 μm. Conversely, when the width d2 is widened from 10.6 μm to 20 μm, the element resistance of the VCSEL element 20H becomes 0.93 times the element resistance when the width d2 is 10.6 μm. It can also be seen that the actual measurements are consistent with the calculated results.

[0164] One method for changing the effective carrier concentration of the semiconductor layer is to inject protons into the p-type semiconductor layer, which compensates for some of the p-type carriers, thereby increasing the resistance of the p-type semiconductor layer and, ultimately, the element resistance of the VCSEL element 20.

[0165] These methods for changing the resistance of the VCSEL element 20 may be used alone or in any combination.

[0166] 30 is a graph showing the results of calculation of the current value flowing through each of multiple VCSEL elements 20 connected to a common anode electrode pad 90. The horizontal axis indicates the number of the VCSEL element 20 counted from the anode electrode pad 90 side, and the vertical axis indicates the current value flowing through each VCSEL element 20. The solid line indicates the calculation result for the light-emitting device of this embodiment (Example 10), and the dashed line indicates the calculation result for the light-emitting device of the first embodiment (Example 1).

[0167] Here, the number of VCSEL elements 20 connected to one anode electrode pad 90 is set to 40. In the calculation, the interval between the light-emitting points of the VCSEL elements 20 is set to 30 μm, the width of the non-oxidized portion of the current confinement layer 32 of the VCSEL element 20 is set to 17.3 μm, the thickness and width of the wiring 46 and wiring 52 are set to 1 μm and 6 μm, respectively, and the amount of current injected into the anode electrode pad 90 is set to 2.4 A.

[0168] The calculation results for the first embodiment assume that the power supply position to the wiring 46 is between the 16th and 17th VCSEL elements 20 from the anode electrode pad 90 side, and the current values ​​are largest in the 16th and 17th VCSEL elements 20. Therefore, assuming this configuration of the first embodiment, in this embodiment, the element resistances of the VCSEL elements 20 near the 16th and 17th VCSEL elements 20 are set higher than the element resistances of the other VCSEL elements 20.

[0169] 30 shows the calculation results (Example 10) when the element resistance of the 12th to 24th VCSEL elements 20 on the anode electrode pad 90 side is set higher than the element resistance of the other VCSEL elements 20. Here, these VCSEL elements 20 are shaped like a VCSEL element with a doping concentration of 1×10 １７ cm －３ It is assumed that the VCSEL device 20H (device resistance is 1.81 times) is inserted with a semiconductor layer 68 made of an AlInP layer with a film thickness of 250 nm.

[0170] 30 , it is possible to reduce the variation in the current value in each VCSEL element 20 by increasing the element resistance of the VCSEL elements 20 near the power supply position to the wiring 46. The ratio of the minimum value to the maximum value of the current values ​​at the 40 light-emitting points (minimum value / maximum value) was 0.71 in Example 1, but was improved to 0.85 in Example 10.

[0171] 31 shows the calculation results (Example 11) for a case where the element resistance of the 8th to 11th, 15th to 20th, and 25th to 29th VCSEL elements 20 on the anode electrode pad 90 side, which have relatively large current values, is further increased compared to Example 10. Here, these VCSEL elements 20 are assumed to be VCSEL elements 20H (element resistance 1.08 times) in which the width of the non-oxidized portion of the current confinement layer 32 is 16.5 μm. The presence or absence of an additional semiconductor layer, the width of the non-oxidized portion of the current confinement layer 32, and the rate of increase in element resistance are summarized for each element number in FIG. 32.

[0172] 31 , by increasing the element resistance of the VCSEL elements 20 with relatively large current values ​​in Example 10, it is possible to further reduce the variation in current values ​​among the VCSEL elements 20. The ratio of the minimum value to the maximum value of the current values ​​at the 40 light-emitting points (minimum value / maximum value) was 0.85 in Example 10, but this was improved to 0.92 in Example 11.

[0173] In Example 11, if the minimum current value required for the light emission operation of one VCSEL element 20 is 0.06 A, the minimum current value required to be injected from one anode electrode pad 90 to which 40 VCSEL elements 20 are connected is 2.49 A. Furthermore, the power consumption in this case is 21.0 W. Therefore, according to this example, not only the variation in the current value but also the power consumption can be reduced.

[0174] Note that combining the increase in element resistance due to the semiconductor layer 68 with the increase in element resistance due to size change of the non-oxidized portion of the current confinement layer 32 has advantages over simply increasing the element resistance due to size change of the non-oxidized portion of the current confinement layer 32. That is, changing the size of the non-oxidized portion of the current confinement layer 32 affects not only the element resistance but also other characteristics of the VCSEL element 20, such as the FFP (Far Field Pattern) and lifespan. Therefore, by combining the increase in element resistance due to the semiconductor layer 68 with the increase in element resistance due to narrowing of the non-oxidized portion of the current confinement layer 32, it is possible to improve the current distribution while minimizing the effects on other characteristics of the VCSEL element.

[0175] In this way, by appropriately changing the element resistance of the VCSEL elements 20 that make up the VCSEL element array, it is possible to reduce variations in current value between the VCSEL elements 20 .

[0176] Furthermore, by appropriately increasing the types of element resistance of the VCSEL elements 20 according to the current distribution, it is possible to further reduce the variation in current value between the VCSEL elements 20. Furthermore, to change the element resistance of the VCSEL elements 20, any method may be used alone, or multiple methods may be used in any combination.

[0177] Although the present embodiment has been described on the basis of the configuration of the first embodiment in which the anode wiring 70 is configured with two layers of wiring, the present embodiment can also be applied to the configurations of the fifth and sixth embodiments in which the anode wiring 70 is configured with three or more layers of wiring, and can also be applied to the configurations of the second to fourth embodiments.

[0178] As described above, according to this embodiment, in a light emitting device having a plurality of light emitting elements, it is possible to improve the uniformity of the light emission intensity while suppressing a decrease in the reliability of wiring and the like.

[0179] [Eighth Embodiment] A light-emitting device according to an eighth embodiment of the present invention will be described with reference to Figs. 33 and 34. Components similar to those in the light-emitting devices according to the first to seventh embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 33 is a graph showing current distribution in the light-emitting device according to this embodiment. Fig. 34 is a diagram showing various electrical characteristics in the light-emitting devices of Examples 12 and 13 and Comparative Example 9.

[0180] In the seventh embodiment, the current variation is improved by increasing the element resistance of some of the VCSEL elements 20 that make up the VCSEL element array. In the present embodiment, an example is shown in which the current variation is further improved by uniformly increasing the element resistance of all of the VCSEL elements 20 that make up the VCSEL element array.

[0181] The various methods exemplified in the seventh embodiment can be used to increase the element resistance of the VCSEL element 20. That is, methods that can be used include lowering the doping concentration of the upper DBR layer 30, adding a semiconductor layer to the upper DBR layer 30, reducing the contact area between the transparent conductive film 82 and the contact layer 34, and narrowing the width of the mesa structure 36.

[0182] In this embodiment, instead of increasing the resistance of some of the VCSEL elements 20 constituting the VCSEL element array as in the seventh embodiment, all of the VCSEL elements 20 constituting the VCSEL element array are made uniformly high-resistance. Therefore, in this embodiment, it is not necessary to change the manufacturing process for each VCSEL element 20, and the manufacturing process can be simplified. This can also be expected to improve yield.

[0183] 33 is a graph showing the results of calculations of the current values ​​flowing through each of the multiple VCSEL elements 20 connected to a common anode electrode pad 90. In FIG. 33 , the solid line represents the calculation results (Example 12) when the doping concentration of the upper DBR layer 30 in the light-emitting device of the fourth embodiment is uniformly reduced to increase the element resistance of the VCSEL elements 20. The dashed line represents the calculation results (Example 13) when the doping concentration of the upper DBR layer 30 in the light-emitting device of the fifth embodiment is uniformly reduced to increase the element resistance of the VCSEL elements 20. The dashed-dotted line represents the calculation results (Reference Example 9) when the doping concentration of the upper DBR layer 30 in the first reference embodiment is uniformly reduced to increase the element resistance of the VCSEL elements 20. In Reference Example 9, the film thickness of the wiring constituting the anode wiring was set to 10 μm.

[0184] The calculation results in Fig. 33 are obtained when the element resistance of the VCSEL element is increased so that the ratio of the minimum value to the maximum value of the current (minimum value / maximum value) is 0.95 or more, and the minimum amount of current injected into the VCSEL element 20 is 0.06 A or more. Fig. 34 summarizes the various calculation values ​​in Examples 12, 13, and Reference Example 9.

[0185] 34 , in all of Examples 12 and 13 and Reference Example 9, the ratio of the maximum to minimum current can be set to 0.95. However, in Reference Example 9, the element resistance must be increased by 4.27 times, and it can be seen that the voltage and input power values ​​are also higher than in Examples 12 and 13. On the other hand, in Reference Example 9, the maximum current density of the wiring is lower than in Examples 12 and 13.

[0186] Comparing Example 12 with Example 13, Example 13 has a lower rate of increase in element resistance and a lower voltage, allowing for lower input power. On the other hand, Example 12 allows for a lower maximum current density in the wiring compared to Example 13. Therefore, it is desirable to appropriately select the configuration of the anode wiring 70 depending on the characteristics that are considered important in the anode wiring 70.

[0187] As described above, according to this embodiment, in a light emitting device having a plurality of light emitting elements, it is possible to improve the uniformity of the light emission intensity while suppressing a decrease in the reliability of wiring and the like.

[0188] [Ninth Embodiment] A light emitting device according to a ninth embodiment of the present invention will be described with reference to Fig. 35. Components similar to those in the light emitting devices according to the first to eighth embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 35 is a cross-sectional schematic diagram showing the general configuration of the light emitting device according to this embodiment.

[0189] In this embodiment, an example will be described in which the light emitting device according to the first to eighth embodiments is applied to a light emitting device that emits light in the SWIR (Short Wavelength Infrared Region) band.

[0190] The light emitting device 100 according to this embodiment further includes a VCSEL chip 160 in addition to the components of the light emitting device according to any one of the first to eighth embodiments. The VCSEL chip 160 is bonded onto the light emitting surfaces of the multiple VCSEL elements 20 that make up the VCSEL element array. The VCSEL chip 160 is a light emitting element that oscillates using light emitted from the VCSEL elements 20 as excitation light and emits light in the SWIR band.

[0191] The VCSEL chip 160 may include an InP substrate 162, an upper reflector 164, a resonator 166, a lower reflector 172, and an AR (Anti-Reflection) coating 174. The upper reflector 164, the resonator 166, and the lower reflector 172 are stacked in this order on one surface of the InP substrate 162. The AR coating 174 is provided on the other surface of the InP substrate 162. The VCSEL chip 160 is bonded onto the light-emitting surface of the VCSEL element 20 so that the lower reflector 172 faces the VCSEL element 20.

[0192] The upper reflecting mirror 164 is, for example, a SiO ２ layer and TiO ２The resonator 166 may be constructed by stacking seven pairs of layers, each pair consisting of an InP layer and an InGaAsP layer. Here, λc is the center wavelength of the high reflection band of the upper reflector 164, which is 1550 nm in this embodiment. The resonator 166 may be constructed by a pin junction consisting of an n-type layer, an undoped spacer portion, and a p-type layer. The undoped spacer portion may have, for example, five quantum well layers (only one layer is shown), each of which has an InGaAs well layer 168 with a thickness of 8 nm sandwiched between InGaAsP light absorption layers 170. The lower reflector 172 may be constructed by stacking multiple pairs of layers, each consisting of an InP layer and an InGaAsP layer with an optical film thickness of ¼ λc. By configuring the reflectance of the upper reflecting mirror 164 to be lower than the reflectance of the lower reflecting mirror 172, light oscillated between the upper reflecting mirror 164 and the lower reflecting mirror 172 is extracted to the InP substrate 162 side and emitted to the outside via the AR coating 174. The AR coating 174 serves to prevent reflection at the interface with the InP substrate 162.

[0193] The VCSEL element 20 emits light with a wavelength of, for example, 940 nm. The light emitted from the VCSEL element 20 enters the resonator 166 through the lower reflecting mirror 172 and is absorbed by the InGaAsP light absorption layer 170. Electrons and holes are generated by the light absorbed by the InGaAsP light absorption layer 170, and these electrons and holes enter the InGaAs well layer 168, where their density exceeds the transparent carrier density, resulting in gain. Laser oscillation occurs in the VCSEL chip 160 in this manner, enabling the light-emitting device 100 to emit laser light with a wavelength in the 1550 nm band.

[0194] In the light-emitting device 100 of this embodiment, the portion that emits light at a wavelength of 1550 nm can be selected by selecting the anode wiring 70 to supply power to from among the multiple anode wirings 70 connected to the VCSEL element array. Furthermore, a configuration that suppresses the spread of the current distribution in the VCSEL element array can minimize the space required for wiring the VCSEL elements 20 while suppressing the spread of the light-emission intensity distribution of the VCSEL elements 20 that make up the VCSEL element array.

[0195] This allows the chip size of the VCSEL element array to be reduced, which not only reduces the chip cost but also reduces the size and cost of the optical system, including the lenses.

[0196] In this embodiment, the VCSEL chip 160 excited by the 940 nm light is a 1550 nm band VCSEL, but this is not limiting. For example, the VCSEL chip 160 may be a VCSEL that emits light in a wavelength band other than the 1550 nm band, such as the 1900 nm band. Furthermore, the VCSEL chip 160 may be a VCSEL array in which multiple VCSEL elements are arranged, or an LED chip may be provided instead of the VCSEL chip 160.

[0197] As described above, according to this embodiment, in a light emitting device having a plurality of light emitting elements, it is possible to improve the uniformity of the light emission intensity while suppressing a decrease in the reliability of wiring and the like.

[0198] [Tenth Embodiment] A light-emitting device according to a tenth embodiment of the present invention will be described with reference to Figures 36A and 36B. Components similar to those in the light-emitting devices according to the first to ninth embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Figures 36A and 36B are plan schematic diagrams showing the general configuration of the light-emitting device according to this embodiment.

[0199] Although the first to ninth embodiments are based on a sequential drive light-emitting device in which the anode wiring 70 is divided into individual columns of the VCSEL element array, the present invention is also applicable to a flash drive light-emitting device in which the entire VCSEL element array emits light simultaneously. For example, the configurations of the above embodiments are also applicable to a light-emitting device in which a single anode wiring 70 is connected to all of the VCSEL elements 20 that make up the VCSEL element array. In a flash drive light-emitting device, the current supplied to the VCSEL elements 20 located in the center of the VCSEL element array is often less than the current supplied to the VCSEL elements 20 located on the periphery of the VCSEL element array. This is because the anode wiring generally has a single layer of electrodes, and current is supplied from the anode-side electrode pads 90 located on the periphery of the VCSEL element array.

[0200] 36A and 36B show a configuration in which the light emitting device according to any one of the first to ninth embodiments is applied to a two-dimensional flash array.

[0201] In FIG. 36A , an anode electrode pad 90 is disposed around the periphery of a VCSEL element array, which is a light-emitting device 100. Furthermore, VCSEL elements 20B are disposed in region 112 located in the center of the VCSEL element array, and VCSEL elements 20A are disposed in region 110 located on the periphery of the VCSEL element array. As in the previously described embodiment, VCSEL elements 20A have a two-layer structure with an insulating film between the wiring electrodes on the top of the VCSEL element, whereas VCSEL elements 20B do not have an insulating film between the wiring electrodes on the top of the VCSEL element. Therefore, the current supplied from electrode pad 90 is not supplied to the VCSEL elements up to boundary 400 between regions 110 and 112, but is divided from boundary 400 to regions 110 and 112 and supplied to the VCSEL elements. This configuration can suppress variations in the current supplied to the center and periphery of the VCSEL element array.

[0202] 36B shows an example in which electrode pads 90 are arranged on two of the four sides of the periphery of a VCSEL element array, which is a light-emitting device 100. In a plan view, VCSEL elements 20A are arranged in regions 110 located above and below the VCSEL element array, and VCSEL elements 20B are arranged in region 112 located between them. As in the previously described embodiment, VCSEL elements 20A have a two-layer structure with wiring electrodes on the top of the VCSEL element having an insulating film between them, whereas VCSEL elements 20B do not have an insulating film between the wiring electrodes on the top of the VCSEL element. Therefore, current supplied from electrode pad 90 is not supplied to the VCSEL elements up to boundary 400 between regions 110 and 112, but is divided from boundary 400 to region 110 and region 112 and supplied to the VCSEL elements. In this example, the VCSEL element 20A is arranged in a region close to the anode-side electrode pad 90, and the VCSEL element 20B is arranged in a region farther away. By arranging the VCSEL elements in this manner, the uniformity of the current injected into each VCSEL element can be improved.

[0203] In this embodiment, the VCSEL elements in region 112 are arranged in four rows or two columns, but the present invention is not limited to these, and the same effect can be achieved by appropriately changing the number of VCSEL elements 20B in the central portion of the VCSEL element array, or the number and ratio of elements in the central and peripheral portions. Also, in this embodiment, the VCSEL element array is divided into two regions, the central portion and the peripheral portion, or two regions, the upper and lower portions and the central portion, but similar to the previous embodiment, a configuration with three or more regions can also achieve the same effect.

[0204] Furthermore, the element resistance of the VCSEL element 20 closest to the anode-side electrode pad 90 in the current path is defined as resistance R2, and the element resistance of the VCSEL element 20 farthest from the anode-side electrode pad 90 is defined as resistance R1. The resistances R1 and R2 are set so as to satisfy the relationship R2 > R1. This allows for further reduction in current variation. Note that, from the perspective of uniformity of the current injected into each VCSEL element, it is preferable, but not essential, for resistances R1 and R2 to be different. Even if resistances R1 and R2 are the same, the two-layer electrode configuration of this embodiment allows for improved uniformity of the current injected into each VCSEL element compared to a typical VCSEL element array configured with a single electrode layer.

[0205] When the high peak power VCSELs of the second embodiment are used as the VCSEL elements in the two-dimensional flash array, the variation in current density affects the variation in the timing of pulsed light generation, as described above. Therefore, by improving the uniformity of the current injected into each VCSEL element as described above, it is possible to reduce the variation in the timing of pulsed light generation.

[0206] [Eleventh Embodiment] A distance measuring device according to an eleventh embodiment of the present invention will be described with reference to Fig. 37. Fig. 37 is a block diagram showing a schematic configuration of the distance measuring device according to this embodiment.

[0207] The distance measuring device 200 according to this embodiment is a distance measuring device (LiDAR device) in which the light emitting device 100 according to any one of the first to tenth embodiments is applied to a light source unit. The distance measuring device 200 can be configured with a control unit 210, a surface emitting laser array driver 212, a surface emitting laser array 214, an emission side optical system 218, a light receiving side optical system 220, an image sensor 222, and a distance data processing unit 224.

[0208] The surface-emitting laser array 214 is a light-emitting device 100 according to any one of the first to tenth embodiments mounted in a package. The surface-emitting laser array driver 212 is a drive unit that receives a drive signal from the control unit 210, generates a drive current for oscillating the surface-emitting laser array 214, and outputs the drive current to the surface-emitting laser array 214. Note that the surface-emitting laser array 214 and the surface-emitting laser array driver 212 do not necessarily need to be separate components, and the surface-emitting laser array 214 may have the function of the surface-emitting laser array driver 212.

[0209] The light-emitting side optical system 218 is an optical system that emits laser light generated by the surface-emitting laser array 214 toward the range to be measured. The light-receiving side optical system 220 is an optical system that guides laser light reflected by the measurement object 1000 to the image sensor 222. Note that although the light-emitting side optical system 218 and the light-receiving side optical system 220 are represented by a single convex lens-shaped member in Fig. 37, they are not composed of only a single convex lens-shaped member, but are composed of a lens group combining multiple lenses.

[0210] The image sensor 222 is a photoelectric conversion device in which a plurality of pixels, each including a photoelectric conversion unit, are arranged in a two-dimensional array, and is a light-receiving device that outputs an electrical signal in response to incident light. The image sensor 222 may be an imaging device such as a CMOS image sensor or a SPAD image sensor. The distance data processing unit 224 functions as a distance information acquisition unit that generates and outputs information regarding the distance to the measurement target object 1000 present in the distance measurement range based on the signal from the image sensor 222. Note that the distance data processing unit 224 only needs to be electrically connected to the image sensor 222, and may be disposed in the same package as the image sensor 222 or in a package separate from the image sensor 222.

[0211] The control unit 210 is configured by an information processing device including a microcomputer and logic circuits, and functions as a central processing device that controls the operation of each unit and performs various calculation processes in the distance measuring device 200.

[0212] Next, the operation of the distance measuring device according to this embodiment will be described with reference to Fig. 37. First, the control unit 210 outputs a drive signal to the surface-emitting laser array driver 212. The surface-emitting laser array driver 212 receives the drive signal from the control unit 210 and injects a current of a predetermined current value into the surface-emitting laser array 214. This causes the surface-emitting laser array 214 to oscillate, and laser light is output from the surface-emitting laser array 214.

[0213] The laser light generated by the surface-emitting laser array 214 is emitted toward the distance measurement range by the light-emitting side optical system 218. Of the laser light irradiated onto the measurement object 1000 in the distance measurement range, the laser light reflected by the measurement object 1000 and incident on the light-receiving side optical system 220 is guided to the image sensor 222 by the light-receiving side optical system 220.

[0214] Each pixel of the image sensor 222 generates an electric signal pulse in accordance with the timing of incidence of the laser light. The electric signal pulse generated by the image sensor 222 is input to the distance data processing unit 224.

[0215] The distance data processing unit 224 generates information about the distance to the measurement object 1000 along the light propagation direction based on the reception timing of the electrical signal pulse output from the image sensor 222. For example, the information about the distance to the measurement object 1000 is generated based on the time difference between the timing at which light is emitted from the surface-emitting laser array 214 and the timing at which the image sensor 222 receives the light. By calculating distance information based on the electrical signal pulse output from each pixel of the image sensor 222, three-dimensional information about the measurement object 1000 can be acquired.

[0216] The ranging device 200 of this embodiment can be applied to, for example, a control device in the automotive field that controls a vehicle to avoid collision with another vehicle, or a control device that controls automatic driving by following another vehicle. The ranging device 200 of this embodiment can also be applied to other moving objects (moving devices) such as ships, aircraft, and industrial robots, as well as moving object detection systems. The ranging device 200 of this embodiment can be widely applied to devices that use information about objects recognized three-dimensionally, including distance information. These moving objects can be configured to include the ranging device of this embodiment and control means that controls the moving object based on the distance information acquired by the ranging device.

[0217] Furthermore, the three-dimensional information including depth that can be acquired by the distance measuring device 200 of this embodiment can also be used in image capturing devices, image processing devices, display devices, etc. For example, using the three-dimensional information acquired by the distance measuring device 200 of this embodiment, it is possible to display a virtual object on an image of the real world without creating a sense of incongruity. Furthermore, by storing the three-dimensional information together with the image information, it is also possible to correct the blurring of the captured image after shooting.

[0218] [Twelfth Embodiment] A moving body according to a twelfth embodiment of the present invention will be described with reference to Figures 38A and 38B. Figures 38A and 38B are block diagrams showing an example of the configuration of a moving body according to this embodiment.

[0219] 38A shows an example of the configuration of a device mounted on a vehicle as an in-vehicle camera. The device 300 has a distance measurement unit 303 that measures the distance to an object to be measured, and a collision determination unit 304 that determines whether or not there is a possibility of a collision based on the distance measured by the distance measurement unit 303. The distance measurement unit 303 may be configured, for example, by the distance measuring device 200 described in the eleventh embodiment. Here, the distance measurement unit 303 is an example of a distance information acquisition means that acquires distance information to the object to be measured. In other words, the distance information is information related to the distance to the object to be measured, etc.

[0220] The device 300 is connected to a vehicle information acquisition device 310 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The device 300 is also connected to a control ECU 320, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 304. The device 300 is also connected to an alarm device 330 that issues an alarm to the driver based on the determination result of the collision determination unit 304. For example, if the determination result of the collision determination unit 304 indicates a high collision possibility, the control ECU 320 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 330 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel. These devices of the device 300 function as a mobile object control unit that controls the operation of controlling the vehicle as described above.

[0221] In this embodiment, the device 300 measures the distance around the vehicle, for example, the front or rear. Fig. 38B shows the device when measuring the distance in front of the vehicle (distance measurement range 350). The vehicle information acquisition device 310, which serves as a distance measurement control means, sends an instruction to the device 300 or the distance measurement unit 303 to perform a distance measurement operation. This configuration can further improve the accuracy of distance measurement.

[0222] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from a lane, etc. Furthermore, the present invention is not limited to vehicles such as automobiles, but can be applied to moving objects (moving devices) such as ships, aircraft, artificial satellites, industrial robots, and consumer robots. In addition, the present invention can be applied to a wide range of devices that use object recognition or biometric recognition, such as intelligent transport systems (ITS) and surveillance systems, without being limited to moving objects.

[0223] [First Reference Embodiment] A light emitting device according to a first reference embodiment will be described with reference to Figures 39 to 42. Components similar to those in the light emitting devices according to the first to tenth embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Figure 39 is a schematic plan view showing the general configuration of the light emitting device according to this reference example.

[0224] Figures 40 and 41 are cross-sectional schematic diagrams showing the general configuration of the light emitting device according to this reference example, and Figure 42 is a graph showing the current distribution in the light emitting device according to this reference example.

[0225] The light emitting device according to this reference example is a surface-emitting semiconductor light emitting device in which a plurality of VCSEL elements 20 are two-dimensionally arranged, similar to the light emitting devices according to the first to tenth embodiments. Fig. 39 is a schematic plan view of the light emitting device 100 as viewed from the light emission surface side.

[0226] 39, the light emitting device 100 according to this reference example includes a substrate 10, a plurality of VCSEL elements 20, a plurality of anode wirings 70, and a plurality of anode electrode pads 90. The VCSEL elements 20 are arranged in a matrix along the X and Y directions.

[0227] As an example, it is assumed here that 40 VCSEL elements 20 are arranged in the X direction and 40 in the Y direction, totaling 1600 VCSEL elements 20, are arranged on the substrate 10.

[0228] An anode wiring 70 is arranged in each column of the VCSEL element array. That is, a plurality of anode wirings 70 extending in the Y direction are arranged along the X direction on the substrate 10. In this example, it is assumed that 40 anode wirings 70, corresponding to the number of VCSEL elements arranged in the X direction, are arranged on the substrate 10. The anode wirings 70 are provided with an emission port 72 for light generated by the VCSEL elements 20.

[0229] The anode electrode pad 90 is electrically connected to one end (the upper side in FIG. 39 ) of each of the multiple anode wirings 70. In this example, it is assumed that 40 anode electrode pads 90, corresponding to the number of anode wirings 70 aligned in the X direction, are arranged on the substrate 10.

[0230] 40 is a cross-sectional view taken along lines A1-A1' and A2-A2' in FIG. 39, and FIG. 41 is a cross-sectional view taken along lines B1-B1' and B2-B2' in FIG. 39. The cross-sectional view taken along line A1-A1' in FIG. 40 and the cross-sectional view taken along line B1-B1' in FIG. 41 are cross-sectional views taken along a plane parallel to the Y-Z plane passing through the anode electrode pad 90. The cross-sectional view taken along line A2-A2' in FIG. 40 is a cross-sectional view taken along a plane parallel to the Y-Z plane passing through the emission port 72. The cross-sectional view taken along line B2-B2' in FIG. 41 is a cross-sectional view taken along a plane parallel to the Y-Z plane passing through a portion extending in the Y direction of the opening 44, which serves as an electrical connection between the anode wiring 70 and the VCSEL element 20. The opening 44 may be provided in a frame-shaped region surrounding the emission port 72.

[0231] In this reference example, the layer structure of the VCSEL element 20 may be similar to that of the first to tenth embodiments. Meanwhile, unlike the first to tenth embodiments, which are configured with two or more wiring layers, the anode wiring 70 and the anode electrode pad 90 are configured with a single wiring layer. The length of the electrical path connecting the anode electrode pad 90 and the VCSEL element 20 via the anode wiring 70 increases as the VCSEL element 20 is located farther from the anode electrode pad 90. In this specification, even when the wiring is configured with a laminate of multiple layers, if these layers are directly laminated without an insulating layer between them, it is referred to as a single layer. On the other hand, if the wiring is configured with a laminate of multiple layers and an insulating layer is provided between the multiple layers in at least some regions to separate the electrical paths, it is referred to as a two-layer (or three or more layers).

[0232] 42 is a graph showing the results of calculations of the current values ​​flowing through each of multiple VCSEL elements 20 connected to a common anode electrode pad 90. The horizontal axis represents the number of the VCSEL elements 20 counted from the anode electrode pad 90 side, and the vertical axis represents the current value flowing through each VCSEL element 20. In FIG. 42, the solid line represents the case where the anode wiring 70 in the light-emitting device of this reference example is set to a thickness of 1 μm (Reference Example 1), and the dashed line represents the case where the anode wiring 70 in the light-emitting device of this reference example is set to a thickness of 2 μm (Reference Example 2). The calculations were based on the following assumptions: the spacing between the light-emitting points of the VCSEL elements 20 is 30 μm; the width of the non-oxidized portion of the current confinement layer 32 of each VCSEL element 20 is 17.3 μm; the thicknesses and widths of the wiring 46 and wiring 52 are 1 μm and 6 μm, respectively; and the amount of current injected into the anode electrode pad 90 is 2.4 A.

[0233] As described above, in the light-emitting device of this reference example, the length of the electrical path connecting the anode electrode pad 90 and the VCSEL elements 20 via the anode wiring 70 is longer for VCSEL elements 20 located farther from the anode electrode pad 90. Therefore, the wiring resistance between the anode electrode pad 90 and the VCSEL elements 20 is higher for VCSEL elements 20 located farther from the anode electrode pad 90. As a result, the value of the current flowing through the VCSEL elements 20 does not decrease from the first VCSEL element 20 to the fortieth VCSEL element 20.

[0234] In the case of Reference Example 1, the ratio of the minimum value to the maximum value (minimum value / maximum value) of the current values ​​in the 40 VCSEL elements 20 was 0.24. If the minimum current value required for the light-emitting operation of one VCSEL element 20 is 0.06 A, then the minimum current value required to be injected from one anode electrode pad 90 to which 40 VCSEL elements 20 are connected is 4.7 A, and the power consumption in this case was 45.1 W.

[0235] In the case of Reference Example 2, the ratio of the minimum value to the maximum value (minimum value / maximum value) of the current values ​​of the 40 VCSEL elements 20 was 0.43. When the minimum current value required for the light-emitting operation of one VCSEL element 20 was 0.06 A, the power consumption was 22.3 W.

[0236] [Second Reference Embodiment] A light emitting device according to a second reference embodiment will be described with reference to Figures 43 to 48. Components similar to those in the light emitting devices according to the first to tenth embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Figure 43 is a schematic plan view showing the general configuration of the light emitting device according to this reference example.

[0237] Figures 44 and 45 are cross-sectional schematic diagrams showing the general configuration of the light-emitting device according to this reference example. Figure 46 is a graph showing current distribution in the light-emitting device according to this reference example. Figures 47A to 47C are diagrams explaining the relationship between the width and spacing of the emission ports and the anode wiring width. Figure 48 is a table showing the results of calculations of wiring width ratios and current density ratios when the anode wiring configuration is changed.

[0238] The light emitting device according to this reference example is a surface-emitting semiconductor light emitting device in which a plurality of VCSEL elements 20 are two-dimensionally arranged, similar to the light emitting devices according to the first to tenth embodiments. Fig. 43 is a schematic plan view of the light emitting device 100 as viewed from the light emission surface side.

[0239] 43 , the light emitting device 100 according to this reference example includes a substrate 10, a plurality of VCSEL elements 20, anode wiring 70, and an anode electrode pad 90. The VCSEL elements 20 are arranged in a matrix along the X and Y directions. As an example, it is assumed here that 40 VCSEL elements 20 are arranged in the X direction and 40 in the Y direction, for a total of 1,600 VCSEL elements 20, are arranged on the substrate 10.

[0240] The anode wiring 70 is a wiring common to the multiple VCSEL elements 20, and is provided across the entire area in which the VCSEL elements 20 are arranged. The anode electrode pad 90 is provided on the outer edge of the anode wiring 70. Current supplied from the anode electrode pad 90 is supplied to each VCSEL element 20 via the anode wiring 70. If the distance between the emission ports 72 of adjacent VCSEL elements 20 in the X direction is defined as width W, then the wiring width per column of the VCSEL element array can be said to correspond to width W.

[0241] Here, the region that is less than a predetermined distance from the anode electrode pad 90 is referred to as region 110, and the VCSEL element 20 disposed in region 110 is referred to as VCSEL element 20A. The region that is more than the predetermined distance from the anode electrode pad 90 is referred to as region 112, and the VCSEL element 20 disposed in region 112 is referred to as VCSEL element 20B. The boundary between region 110 and region 112, i.e., the VCSEL element 20 that is the predetermined distance from the anode electrode pad 90, is referred to as VCSEL element 20C. For example, line B-B' shown by the two-dot chain line in FIG. 43 is the boundary line between region 110 and region 112. Boundary line B-B' intersects with VCSEL element 20C in a plan view.

[0242] Fig. 44 is a cross-sectional view taken along lines A1-A1' and A2-A2' in Fig. 39, and Fig. 45 is a cross-sectional view taken along lines A1-A1' and B2-B2' in Fig. 39. The cross-sectional views taken along lines A1-A1' in Fig. 44 and Fig. 45 are cross-sectional views taken along lines A1-A1' and B2-B2' in Fig. 39. The cross-sectional views taken along line A1-A1' in Fig. 44 and Fig. 45 are cross-sectional views taken on a plane parallel to the Y-Z plane passing through the anode electrode pad 90. The cross-sectional view taken along line A2-A2' in Fig. 44 is a cross-sectional view taken on a plane parallel to the Y-Z plane passing through the injection port 72. The cross-sectional view taken along line B2-B2' in Fig. 45 is a cross-sectional view taken on a plane parallel to the Y-Z plane passing through a portion of the opening 44 extending in the Y direction.

[0243] In this reference example, the layer structure of the VCSEL element 20 may be the same as in the first to tenth embodiments. In this reference example, the anode wiring 70 is composed of a wiring 46 and a wiring 52 that is composed of a wiring layer located above the wiring layer that constitutes the wiring 46. The anode electrode pad 90 is composed of the wiring 52.

[0244] An insulating layer 50 is provided in a portion of the region between the wiring 46 and the wiring 52. More specifically, the insulating layer 50, which is disposed between the wiring layer constituting the wiring 46 and the wiring layer constituting the wiring 52, is provided in the region 110 but not in the region 112. That is, there is no electrical path connecting the wiring 46 and the wiring 52 in the region extending from the anode electrode pad 90 to the region 110. On the other hand, in the region 112, the wiring 46 and the wiring 52 are directly stacked without an insulating layer therebetween, and are electrically connected throughout the entire region 112. As shown in FIGS. 43 to 45, the end of the insulating layer 50 on the region 112 side (boundary line B-B') overlaps with the emission port 72 of the VCSEL device 20C in plan view. A boundary 140 between the regions 110 and 112 appears in the cross section taken along line A2-A2' but does not appear in the cross section taken along line B2-B2'.

[0245] By configuring the anode electrode pad 90 and the anode wiring 70 in this manner, the current supplied from the anode electrode pad 90 to the anode wiring 70 first flows in the −Y direction through the region 110 via the wiring 52 and reaches the boundary 140 between the regions 110 and 112. The current that reaches the boundary 140 is then divided into three currents: a current that flows in the Y direction through the region 110, turning back via the wiring 46; a current that flows in the −Y direction through the region 112 via the laminated film of the wiring 46 and the wiring 52; and a current that flows to the VCSEL element 20C. The current flowing in the Y direction through the wiring 46 is supplied to the VCSEL element 20A disposed in the region 110. The current flowing in the −Y direction through the laminated film of the wiring 46 and the wiring 52 is supplied to the VCSEL element 20B disposed in the region 112. This makes it possible to supply current to all of the VCSEL elements 20A, 20B, and 20C connected to the anode wiring 70.

[0246] 46 is a graph showing the results of calculations of the current values ​​flowing through each of multiple VCSEL elements 20 connected to a common anode electrode pad 90. The horizontal axis indicates the number of the VCSEL elements 20 counted from the anode electrode pad 90 side, and the vertical axis indicates the current value flowing through each VCSEL element 20. The solid line indicates the calculation results for the light-emitting device of this reference example (Reference Example 3). For comparison, the calculation results for the aforementioned Reference Example 1 are shown with a dashed line.

[0247] In this calculation, a sequential driving type light emitting device was assumed in which 40 VCSEL elements 20 arranged in a row along the Y direction as shown in FIG. 39 were connected to one anode wiring 70.

[0248] The VCSEL element 20C located at the boundary 140 was determined to be the 17th VCSEL element 20 from the anode electrode pad 90 side. In the calculation, the interval between the light-emitting points of the VCSEL elements 20 was set to 30 μm, the width of the non-oxidized portion of the current confinement layer 32 of the VCSEL element 20 was set to 17.3 μm, the thickness and width of the wiring 46 and wiring 52 were set to 1 μm and 6 μm, respectively, and the amount of current injected into the anode electrode pad 90 was set to 2.4 A.

[0249] In the light-emitting device of this reference example, as described above, current is supplied to each VCSEL element 20 from the boundary 140 between regions 110 and 112 through the wiring 46. Therefore, the current value is highest in the 17th VCSEL element 20C located at the boundary 140. The current values ​​flowing through the VCSEL elements 20 become smaller from the 17th VCSEL element 20C toward the first VCSEL element 20A, and from the 17th VCSEL element 20C toward the 40th VCSEL element 20B. As a result, a mountain-shaped distribution is obtained, as shown by the solid line in FIG. 46 . In Reference Example 3, the ratio of the minimum to the maximum current values ​​in the 40 VCSEL elements 20 (minimum / maximum) is 0.71, which allows for a reduction in current variation compared to Reference Examples 1 and 2. 46, in the light-emitting device according to this reference example, the current value is greatest at the boundary between the region 110 and the region 112, i.e., at the boundary 140. In other words, the boundary 140 is the portion of the anode wiring 70 where the current density is highest.

[0250] In a two-dimensional VCSEL element array, it is desirable to narrow the spacing between light-emitting points to achieve a high-density two-dimensional arrangement from the viewpoint of reducing chip costs, etc. On the other hand, when considering application to LiDAR systems, etc., higher light energy is preferable, and it is desirable to array the light-emitting points to increase the number of light-emitting points and the amount of light per light-emitting point. Therefore, even when reducing the chip size, it is not desirable to reduce the area of ​​the light-emitting portion and the size of the outlet. As a result, in order to reduce the chip size, it is necessary to reduce the spacing between the outlets, and the width of the wiring arranged between the outlets becomes narrower.

[0251] When all VCSEL elements constituting an array are driven simultaneously, i.e., in a light-emitting device using a flash drive method, the anode electrodes of all VCSEL elements constituting the array can be electrically connected. However, when the VCSEL elements constituting the array are driven in groups, i.e., in a light-emitting device using a sequential drive method, it is necessary to separate the anode wiring for each group to prevent the drive current from flowing into the VCSEL elements of other groups. Therefore, it is necessary to provide a space between the anode wirings of different groups to separate them, and it is also necessary to provide a space between the above-mentioned emission ports to separate the anode wirings. As a result, the wiring width becomes increasingly narrow.

[0252] Fig. 47A is a schematic plan view of two columns of the VCSEL element array of Fig. 43. Fig. 47B is a schematic plan view of Fig. 47A in which the pitch of the VCSEL elements 20 in the X direction is the same, but the width of the emission opening 72 is increased to increase the density of the optical power. Fig. 47C is a schematic plan view of Fig. 47A in which the width and spacing of the emission opening 72 in the X direction are the same, but the anode wiring 70 and anode electrode pad 90 are divided into columns.

[0253] 47A without changing the pitch of the VCSEL elements 20 in the X direction, the wiring width per row of the anode wiring 70 between the emission ports 72 narrows from width W to width W2, as shown in Fig. 47B. Furthermore, if the anode wiring 70 and anode electrode pads 90 are divided into rows, as shown in Fig. 47C, even if the width of the anode wiring 70 between the emission ports 72 is width W, the wiring width per row of the anode wiring 70 between the emission ports 72 narrows compared to the case of Fig. 47A.

[0254] Figure 48 summarizes the results of calculations of the wiring width ratio and current density ratio when the configuration of the anode wiring 70 is changed. In Figure 48, Reference Example 4 shows the results when the pitch between the VCSEL elements 20 is 30 μm and the opening diameter of the emission outlet 72 is 10 μm in the configuration of Figure 47A. Reference Example 5 shows the results when the pitch between the VCSEL elements 20 is 30 μm and the opening diameter of the emission outlet 72 is 17 μm in the configuration of Figure 47B (high optical power density). Reference Example 6 shows the results when the pitch between the VCSEL elements 20 is 30 μm, the opening diameter of the emission outlet 72 is 10 μm, and the separation width between the anode wirings 70 is 3 μm in the configuration of Figure 47C (sequential drive mode). Reference Example 7 shows the results when the pitch between the VCSEL elements 20 is 30 μm, the opening diameter of the emission port 72 is 17 μm, and the separation width between the anode wirings 70 is 3 μm in the configuration of FIG. 47C (high optical power density + sequential driving mode).

[0255] 48 , the area ratio of the injection port is the area ratio of the injection port 72 with respect to Reference Example 4 as the reference, and is 2.89 in Reference Examples 5 and 7, and 1 in Reference Example 6. The wiring width ratio is the ratio of the wiring width of the anode wiring 70 at the boundary portion 140 with respect to Reference Example 4 as the reference, and is 0.65 in Reference Example 5, 0.85 in Reference Example 6, and 0.50 in Reference Example 7. The current density ratio is the ratio of the current density when the current density is constant to the area of ​​the injection port 72, and is 4.45 in Reference Example 5, 1.18 in Reference Example 6, and 5.78 in Reference Example 7.

[0256] 48, the current density of the anode wiring 70 in Reference Examples 5, 6, and 7 is higher than the current density of the anode wiring 70 in Reference Example 4. If the current density of the anode wiring 70 in Reference Example 4 is 1, it is 7.22 times higher in the case of Reference Example 7.

[0257] Here, as shown in Figures 47A to 47C, the boundary 140 between the region 110 and the region 120 overlaps with the portion where the electrode width in the X direction narrows. Furthermore, focusing on the boundary 140, the boundary 140 is the electrical connection between the wiring 52 and the wiring 46, and the current flowing from the wiring 52 concentrates at this connection portion with a narrow wiring width. Therefore, if the current density in this vicinity increases, the durability of the anode wiring 70 will decrease due to electromigration, and in the worst case, the anode wiring 70 may break. In particular, when the chip size is reduced or the anode wiring 70 is separated for sequential driving, the width of the anode wiring 70 becomes narrower, and the impact of electromigration will also increase.

[0258] [Modified Embodiments] The present invention is not limited to the above-described embodiments and can be modified in various ways.

[0259] For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is substituted therefor, is also an embodiment of the present invention.

[0260] Furthermore, although the above embodiment has described that the problem of reduced wiring reliability is unlikely to occur in semiconductor light-emitting elements other than VCSEL elements, such as LEDs and edge-emitting lasers, the present disclosure does not exclude the application of the configuration of the present invention to semiconductor light-emitting elements other than VCSEL elements. Even when the configuration of the present invention is applied to semiconductor light-emitting elements other than VCSEL elements, it is possible to achieve the same effects as those described in the above embodiment, although the level of effect may be reduced. A semiconductor light-emitting element applicable to the present disclosure includes a pair of electrode layers and a light-emitting layer disposed between them, and emits light from the side of one of the electrode layers.

[0261] In the above embodiment, the mesa structure 36 and the emission port 72 have a rectangular shape in plan view, but they do not necessarily have to be rectangular and may be other polygonal or circular shapes. Furthermore, the VCSEL element does not necessarily have to have a mesa structure and may have a planar structure or a structure that combines a mesa structure and a planar structure.

[0262] In the above embodiment, the VCSEL element 20 is described assuming that it is a VCSEL element that emits light in the 940 nm band. However, the structure of the VCSEL element 20 and the constituent materials of each layer are not limited to the combinations described in the embodiment.

[0263] In the present disclosure, current variations are reduced by increasing the element resistance of VCSEL elements 20 with short electrical paths from the anode electrode pad 90, rather than increasing the element resistance of VCSEL elements 20 that are closer to the anode electrode pad 90. Generally, in light-emitting devices that include LEDs or VCSEL elements, increasing the element resistance increases the input power. Therefore, as in the present disclosure, the element resistance is not increased but rather reduced. In contrast, in the present disclosure, when variations occur in the current of each VCSEL element 20 constituting a VCSEL element array, VCSEL elements 20 with high element resistance are arranged in locations where the current is large. By configuring a light-emitting device in this manner, when injecting the required amount of current into all VCSEL elements 20 in the VCSEL element array, the overall amount of current injected into the VCSEL element array can be reduced, thereby reducing the input power.

[0264] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features.

[0265] The present invention is not limited to the above-described embodiments, and various modifications and variations can be made without departing from the spirit and scope of the present invention. Therefore, the following claims are appended to apprise the public of the scope of the present invention.

[0266] This application claims priority based on Japanese Patent Application No. 2024-062516, filed April 9, 2024, the entire contents of which are incorporated herein by reference.

[0267] 20...VCSEL element 46, 52, 76, 80...wiring 42, 50, 74, 78...insulating layer 60...cathode electrode 70...anode wiring 72...emission port 90...anode electrode pad 100...light emitting device 140...boundary portion

Claims

1. A light emitting device comprising: a plurality of semiconductor light emitting elements, each having a first electrode layer, a second electrode layer, and a light emitting layer disposed between the first and second electrode layers, and emitting light from the second electrode layer side; electrode pads for supplying power to the plurality of semiconductor light emitting elements; and wiring electrically connecting the second electrode layer of each of the plurality of semiconductor light emitting elements to the electrode pad, wherein the plurality of semiconductor light emitting elements include semiconductor light emitting elements disposed in a first region that is less than a first distance from the electrode pad and semiconductor light emitting elements disposed in a second region that is the first distance or more from the electrode pad, the wiring having first wiring and second wiring, the first wiring being in contact with the second electrode layer of each of the plurality of semiconductor light emitting elements, the first wiring and the second wiring not being in contact in the first region but being in contact in the second region, and the end of the contact portion between the first wiring and the second wiring on the first region side being located between adjacent semiconductor light emitting elements across the boundary between the first region and the second region.

2. The light emitting device according to claim 1, characterized in that the wiring has a plurality of emission ports for emitting light generated by the plurality of semiconductor light emitting elements, and the end portion is located between the emission ports of the semiconductor light emitting elements adjacent to each other across the boundary.

3. A light-emitting device according to claim 1 or 2, characterized in that the first wiring is formed by a first wiring layer, and the second wiring is formed by a second wiring layer that is a layer different from the first wiring layer.

4. The light emitting device according to claim 3, further comprising an insulating layer disposed between the first wiring layer and the second wiring layer, wherein the first wiring and the second wiring are separated by the insulating layer in the first region and are in contact with each other without the insulating layer in the second region.

5. The light emitting device according to claim 4, characterized in that the insulating layer has a plurality of openings in the second region for connecting the first wiring and the second wiring, and each of the plurality of openings is located between adjacent semiconductor light emitting elements.

6. The light emitting device according to claim 5, characterized in that the pitch of the emission ports for emitting light generated by the semiconductor light emitting element is P, the width of the emission ports is Ls, the width of the opening is Lx, and the separation width between adjacent wirings is Lh, satisfies the following relationship: Lx > P - Lh - Ls.

7. A light emitting device as described in any one of claims 1 to 6, characterized in that the semiconductor light emitting element arranged in the first region is electrically connected to the electrode pad via the first wiring and the second wiring in this order, and the semiconductor light emitting element arranged in the second region is electrically connected to the electrode pad via a stacked wiring of the first wiring and the second wiring and the second wiring in this order.

8. A light emitting device according to any one of claims 1 to 7, further comprising a resistor connected between the electrode pad and the first wiring, and the semiconductor light emitting element closest to the electrode pad is electrically connected to the electrode pad via the first wiring and the resistor in this order.

9. The light emitting device according to claim 8, wherein the resistance value of said resistor section is greater than the value of the wiring resistance between said adjacent semiconductor light emitting elements.

10. A light emitting device according to claim 8 or 9, characterized in that the electrode pad and the resistor portion are configured to include a first wiring layer that constitutes the first wiring.

11. The light emitting device described in any one of claims 1 to 8, characterized in that the plurality of semiconductor light emitting elements include semiconductor light emitting elements arranged in the first region at a second distance or more that is shorter than the first distance but less than the first distance, semiconductor light emitting elements arranged in a third region at a third distance or more that is shorter than the second distance but less than the second distance, and semiconductor light emitting elements arranged in a fourth region less than the third distance, the wiring further having a third wiring, the second wiring and the third wiring do not contact each other in the third region but contact each other in the first region and the second region, and an end of the contact portion between the second wiring and the third wiring on the third region side is located between adjacent semiconductor light emitting elements across the boundary between the third region and the first region.

12. The light emitting device described in claim 11, characterized in that the plurality of semiconductor light emitting elements include semiconductor light emitting elements arranged in the fourth region at a fourth distance equal to or greater than the third distance but less than the third distance, and semiconductor light emitting elements arranged in a fifth region less than the fourth distance, the wiring further having a fourth wiring, the third wiring and the fourth wiring do not contact each other in the fourth region but contact each other in the first region, the second region and the third region, and the end of the contact portion between the third wiring and the fourth wiring on the fourth region side is located between adjacent semiconductor light emitting elements across the boundary between the fourth region and the third region.

13. The light-emitting device according to claim 11 or 12, characterized in that the wiring comprises an (n-1)th wiring formed from an (n-1)th wiring layer, an nth wiring formed from an nth wiring layer, and an (n+1)th wiring formed from an (n+1)th wiring layer, and the (n-1)th wiring and the nth wiring are electrically insulated by an insulating layer between the (n-1)th wiring layer and the nth wiring layer in a surrounding area including a power supply position from the (n+1)th wiring to the nth wiring.

14. A light-emitting device according to any one of claims 1 to 13, characterized in that the element resistance of a first semiconductor light-emitting element, the length of which of the electrical paths from the contacting portion is a first length, is higher than the element resistance of a second semiconductor light-emitting element, the length of which of the electrical paths from the contacting portion is a second length that is longer than the first length.

15. A light-emitting device according to any one of claims 1 to 14, characterized in that the plurality of semiconductor light-emitting elements are arranged in a plurality of rows and a plurality of columns, and the wiring is provided for each of the plurality of rows or each of the plurality of columns.

16. The light-emitting device according to any one of claims 1 to 15, wherein the second electrode layer includes a transparent conductive film.

17. A light-emitting device according to any one of claims 1 to 16, characterized in that the light-emitting layer has a first reflecting mirror, a second reflecting mirror, and a resonator portion disposed between the first reflecting mirror and the second reflecting mirror and including an active layer.

18. The light emitting device according to claim 17, wherein each of the plurality of semiconductor light emitting elements includes a saturable absorbing layer disposed between the first reflecting mirror and the second reflecting mirror.

19. A light emitting device according to claim 17 or 18, further comprising a second semiconductor light emitting element having a third reflecting mirror, a fourth reflecting mirror, and a second resonator portion disposed between the third reflecting mirror and the fourth reflecting mirror and including a second active layer, wherein the second semiconductor light emitting element is excited by light of a first wavelength emitted from the plurality of semiconductor light emitting elements and emits light of a second wavelength different from the first wavelength.

20. A distance measuring device comprising: a light emitting device according to any one of claims 1 to 19; a light receiving device that receives light emitted from the light emitting device and reflected by an object to be measured; and a distance information acquisition unit that acquires information regarding the distance to the object to be measured based on the time difference between the timing at which light is emitted from the light emitting device and the timing at which light is received by the light receiving device.

21. A mobile body comprising: a distance measuring device according to claim 20; and control means for controlling the mobile body based on information relating to the distance acquired by the distance measuring device.

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