Semiconductor substrate and method for manufacturing the same

Abstract

This semiconductor substrate comprises a base substrate; a nitride semiconductor part located above the base substrate; and a root part that contains a nitride semiconductor and connects the base substrate and the nitride semiconductor part. The nitride semiconductor part has: a base section located above the root part; and a floating section that extends from the base section and is not in contact with the base substrate. The root part has a first tapered surface that faces a void.

Description

Semiconductor substrate and manufacturing method thereof

[0001] The present disclosure relates to semiconductor substrates and the like.

[0002] Patent Document 1 discloses a method of forming a mask pattern on a base substrate including a heterosubstrate and a seed layer, and laterally growing a nitride semiconductor layer on the mask portion using the seed layer exposed in the opening of the mask pattern as the growth starting point.

[0003] Japanese Patent Application Publication No. 2013-251304

[0004] The semiconductor substrate according to the present disclosure comprises a base substrate, a nitride semiconductor portion located above the base substrate, and a root portion including a nitride semiconductor and connecting the base substrate and the nitride semiconductor portion, the nitride semiconductor portion having a base portion located above the root portion and a floating portion extending from the base portion and not in contact with the base substrate, and the root portion having a first tapered surface facing a void.

[0005] FIG. 1 is a cross-sectional view showing the configuration of a semiconductor substrate according to the present embodiment. FIG. 2 is a plan view showing the configuration of a semiconductor substrate according to the present embodiment. FIG. 3 is an image of a semiconductor substrate according to the present embodiment. FIG. 4 is a flowchart showing a method for manufacturing a semiconductor substrate according to the present embodiment. FIG. 5 is a cross-sectional view showing the manufacturing method of a semiconductor substrate according to the present embodiment. FIG. 6 is a cross-sectional view showing the manufacturing method of a semiconductor substrate according to the present embodiment. FIG. 7 is a cross-sectional view showing the configuration of a semiconductor substrate according to the present embodiment. FIG. 8 is a plan view showing the configuration of a semiconductor substrate according to the present embodiment. FIG. 9 is a cross-sectional view showing the configuration of a semiconductor substrate according to the present embodiment. FIG. 10 is a cross-sectional view showing the configuration of a semiconductor substrate according to the present embodiment. FIG. 11 is an image of a semiconductor substrate according to the present embodiment. FIG. 12 is a flowchart showing a method for manufacturing a semiconductor substrate according to the present embodiment. FIG. 13 is a cross-sectional view showing the manufacturing method of a semiconductor substrate according to the present embodiment. FIG. 14 is a cross-sectional view showing the configuration of a semiconductor substrate according to the present embodiment. FIG. 15 is a cross-sectional view showing the configuration of a semiconductor substrate according to the present embodiment.

[0006] FIG. 1 is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. FIG. 2 is a plan view showing the configuration of the semiconductor substrate according to this embodiment. FIG. 3 is an image diagram of the semiconductor substrate according to this embodiment. As shown in FIGS. 1 to 3, the semiconductor substrate 10 includes a base substrate BS, a nitride semiconductor portion 8A located above the base substrate BS, and a root portion R1 including a nitride semiconductor and connecting the base substrate BS and the nitride semiconductor portion 8A. The nitride semiconductor portion 8A has a base portion B1 located above the root portion R1 and a floating portion F extending from the base portion B1 and not in contact with the base substrate BS. The root portion R1 has a first tapered surface T1 facing a gap JD. The gap JD may be a space surrounded by the base substrate BS, the root portion R1, and the floating portion F.

[0007] In the semiconductor substrate 10, when an external force is applied to the nitride semiconductor portion 8A, the root portion R1 has the first tapered surface T1 facing the gap JD, so that stress tends to concentrate near the end of the first tapered surface T1, facilitating peeling of the nitride semiconductor portion 8A. Because the floating portion F (wing portion) is not in contact with the base substrate BS, a wide floating portion with low defect density and high flatness can be formed. The thickness of the floating portion F may be, for example, 1.0 μm or more and 15 μm or less.

[0008] In this embodiment, the direction from the main substrate 1 to the nitride semiconductor portion 8A is referred to as "upward." Viewing an object from a line of sight parallel to the normal direction of the semiconductor substrate 10 (including perspective views) is sometimes referred to as "planar view."

[0009] The first tapered surface T1 may intersect with the base substrate BS. The first tapered surface T1 may have an inverse tapered shape (overhanging shape) that protrudes above the base substrate BS. The height of the first tapered surface T1 (the amount of rise of the slope in the third direction) when the semiconductor substrate 10 is viewed in cross section may be smaller than the thickness of the floating portion F. The height of the first tapered surface T1 when the semiconductor substrate 10 is viewed in cross section may be, for example, 400 nm or less. The height of the first tapered surface T1 when the semiconductor substrate 10 is viewed in cross section may be, for example, 200 nm or less. The height of the first tapered surface T1 when the semiconductor substrate 10 is viewed in cross section may be, for example, 5 nm or more and 200 nm or less. The length of the first tapered surface T1 (slope width) when the semiconductor substrate 10 is viewed in cross section may be, for example, 600 nm or less. The length (slope width) of the first tapered surface T1 when viewed in cross section of the semiconductor substrate 10 may be, for example, 400 nm or less. The length (slope width) of the first tapered surface T1 when viewed in cross section of the semiconductor substrate 10 may be, for example, 7 nm or more and 400 nm or less. The height and length of the first tapered surface T1 can be determined by cutting out a cross section using a focused ion beam (FIB) device and using a scanning electron microscope (SEM) or the like.

[0010] The base substrate BS includes a main substrate 1 and an underlayer 4 on the main substrate 1. The surface of the underlayer 4 may be exposed. The surface of the underlayer 4 may face the void JD. Threading dislocations in the underlayer 4 may extend to the surface of the underlayer 4. The main substrate 1 may not have the underlayer 4.

[0011] The nitride semiconductor portion 8A contains a nitride semiconductor as a main component. The nitride semiconductor is, for example, Al ｘ Ga ｙ In ｚ N (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1). Specific examples of nitride semiconductors include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). A GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N). Typical examples of GaN-based semiconductors include GaN, AlGaN, AlGaInN, and InGaN. The main component of the nitride semiconductor portion 8A may be the same as the main component of the root portion R1. The main component of the nitride semiconductor portion 8A may be different from the main component of the root portion R1. The nitride semiconductor portion 8A may be doped or non-doped. For example, the doped type is an n-type containing donors.

[0012] The main substrate 1 may be a free-standing heterogeneous substrate having a different lattice constant from that of the nitride semiconductor portion 8A. For example, the main substrate 1 may be a silicon substrate, a sapphire substrate, a silicon carbide substrate, a nitride substrate, or a ScMgAlO substrate. For example, the silicon carbide substrate may be a 4H—SiC substrate or a 6H—SiC substrate. For example, the nitride substrate may be a GaN substrate or an AlN substrate. The main substrate 1 may or may not contain a semiconductor. For example, the semiconductor may be silicon or silicon carbide. An example of a main substrate 1 that does not contain a semiconductor is a sapphire substrate.

[0013] The underlayer 4 may be, for example, a seed layer. The seed layer is a layer that serves as a starting point for growing a semiconductor crystal. The seed layer is a layer that is connected to the root portion R1. The seed layer includes a nitride semiconductor. The seed layer may be a GaN layer, an AlN layer, an AlGaN layer, an AlInN layer, an AlGaInN layer, an Al layer, or the like. The seed layer may be a layer formed at a low temperature. The seed layer may be a layer formed at 500° C. or lower. The thickness of the seed layer is, for example, 10 nm to 500 nm.

[0014] The underlayer 4 may have a buffer layer located on the main substrate. The underlayer 4 may include a buffer layer located on the main substrate and a seed layer located on the buffer layer. The buffer layer may be multiple layers. The buffer layer may be composed of a material different from that of the seed layer. The seed layer may be partially located on the buffer layer. The seed layer may be a seed pattern. The buffer layer may be a GaN layer, an AlN layer, an AlGaN layer, an AlInN layer, an AlGaInN layer, an Al layer, or the like. The buffer layer may be composed of multiple layers. The buffer layer may be a layer formed at a low temperature. The buffer layer may be a layer formed at 500° C. or lower. The thickness of the buffer layer is, for example, about 10 nm to 500 nm.

[0015] The underlayer 4 may be formed by sputtering. The threading dislocation density of the underlayer 4 is, for example, 1×10 ８ [cm －２ ]~1×10 １０ [cm －２ ]. Threading dislocations in the underlayer 4 may be inherited by the root portion R1. The threading dislocation density of the underlayer 4 may be lower than the threading dislocation density of the nitride semiconductor portion 8A. The C-plane of GaN may be exposed on the surface of the underlayer 4. The underlayer 4 may include seed portions S1 and S2 (e.g., nitride semiconductors) adjacent to each other in the first direction X1.

[0016] The first direction X1 may be the a-axis direction (<11-20> direction) of the nitride semiconductor portion 8A. The second direction X2 may be the m-axis direction (<1-100> direction) of the nitride semiconductor portion 8A. The third direction X3 (thickness direction of the nitride semiconductor portion 8A) orthogonal to the first and second directions may be the c-axis direction (<0001> direction) of the nitride semiconductor portion 8A.

[0017] The root portion R1 is located on the seed portion S1. The root portion R1 extends upward from above the seed portion S1. In the semiconductor substrate 10, the root portion R1 may have a first tapered surface T1. The root portion R1 may have two (pairs of) first tapered surfaces T1. The root portion R1 may have two (pairs of) first tapered surfaces T1 with the a-plane as a plane of symmetry. The void JD is located between the nitride semiconductor portion 8A and the base substrate BS. The ratio of the width in the first direction X1 to the thickness of the void JD (aspect ratio of the void) may be 3.0 or more, 5.0 or more, 10 or more, or 20 or more.

[0018] The nitride semiconductor portion 8A can be formed by an epitaxial lateral overgrowth (ELO) method, starting from a root portion R1 grown from a seed portion S1. The base portion B1 is located above the root portion R1. The base portion B1 is located on the root portion R1. The base portion B1 extends upward from the root portion R1. When the semiconductor substrate 10 is viewed in cross section, the thickness of the base portion B1 may be greater than the thickness of the root portion R1.

[0019] The floating portion F extends from the base portion B1 in the first direction X1. The floating portion F extends from the base portion B1 along the upper surface of the base substrate BS. When the semiconductor substrate 10 is viewed in cross section, the thickness of the floating portion F may be greater than the thickness of the root portion R1. The floating portion F may include an edge E located above the base substrate BS. The floating portion F may include an edge E located above the exposed surface of the underlayer 4. The edge E may include, for example, the a-plane or (11-22) plane of the nitride semiconductor. The edge E may be composed of, for example, the a-plane and (11-22) plane of the nitride semiconductor. The nitride semiconductor portion 8A extending from the root portion R1 connected to the seed portion S1 and the nitride semiconductor portion 8C extending from the root portion R2 connected to the seed portion S2 may be adjacent to each other in the first direction X1 with a gap GP interposed therebetween. The nitride semiconductor portion 8A extending from the root portion R1 connected to the seed portion S1 and the nitride semiconductor portion 8C extending from the root portion R2 connected to the seed portion S2 may be connected to each other.

[0020] In the nitride semiconductor portion 8A, the base portion B1 located above the root portion R1 is a dislocation inheritance portion with many threading dislocations. In the nitride semiconductor portion 8A, the floating portion F extending from the base portion B1 in the first direction X1 is a low-defect portion with a lower threading dislocation density than the dislocation inheritance portion (base portion B1). The threading dislocation density of the root portion R1 is, for example, 1×10 ８ [cm －２ ]~1×10 １０ [cm －２ The threading dislocation density of the floating portion F may be 1 / 5 or less of the threading dislocation density of the base portion B1. The threading dislocation density of the floating portion F may be 5×10 ６ [cm －２ ] or less. The threading dislocation densities of the root portion R1 and the floating portion F can be identified by, for example, performing CL (Cathode Luminescence) measurement on a plane parallel to the c-plane. Threading dislocations in the base substrate BS may be inherited by the root portion R1. Due to the voids JD, threading dislocations in the base substrate BS are not inherited by the floating portion F. The seed portions S1 and S2 are doped with impurities at a density of 2×10 １８ / cm ３The seed portions S1 and S2 may be made of a nitride semiconductor containing the above. The seed portions S1 and S2 may contain, for example, argon or oxygen as an impurity.

[0021] As shown in FIGS. 1 to 3 , the first tapered surface T1 may have a shape whose longitudinal direction is the m-axis direction (second direction X2) of the nitride semiconductor portion 8A. The first tapered surface T1 may have a shape extending to both ends of the nitride semiconductor portion 8A in the m-axis direction. The root portion R1 may have a second tapered surface T2 facing the gap JD. The second tapered surface T2 may be forward tapered. The root portion R1 may have two (pairs of) second tapered surfaces T2 with the a-plane of the nitride semiconductor as a symmetrical plane. The second tapered surface T2 is located above the first tapered surface T1. The second tapered surface T2 may have a shape whose longitudinal direction is the m-axis direction of the nitride semiconductor portion 8A. The second tapered surface T2 may have a shape extending to both ends of the nitride semiconductor portion 8A in the m-axis direction. The height of the second tapered surface T2 (the amount of rise of the slope in the third direction) when the semiconductor substrate 10 is viewed in cross section may be smaller than the thickness of the floating portion F. When the semiconductor substrate 10 is viewed in cross section, the height of the second tapered surface T2 may be greater than the height of the first tapered surface. When the semiconductor substrate 10 is viewed in cross section, the height of the second tapered surface T2 may be, for example, 1.2 μm or less. When the semiconductor substrate 10 is viewed in cross section, the height of the second tapered surface T2 may be, for example, 1.0 μm or less. When the semiconductor substrate 10 is viewed in cross section, the height of the second tapered surface T2 may be 200 nm or more and 1.0 μm or less. The height of the second tapered surface T2 can be measured by cutting a cross section using a focused ion beam (FIB) device and using a scanning electron microscope (SEM) or the like.

[0022] The thickness of the root portion R1 may be smaller than the thickness of the floating portion F. The semiconductor substrate 10 may include an amorphous film 7 located between the root portion R1 and the base portion B1. The amorphous film 7 may be an insulating film made of, for example, silicon nitride, silicon oxide, or the like. The amorphous film 7 may be contained within the root portion R1. A part of the amorphous film 7 may be exposed from the root portion R1. The nitride semiconductor portion 8A may be grown starting from a portion of the root portion R1 located outside the amorphous film 7.

[0023] The root portion R1 has an intermediate plane MT located between the first tapered surface T1 and the second tapered surface T2. The intermediate plane MT intersects with the first tapered surface T1 and the second tapered surface T2. The intermediate plane MT may intersect only with the first tapered surface T1. A side where the first tapered surface T1 and the intermediate plane MT intersect may be parallel to the m-axis of the nitride semiconductor portion 8A. A side where the intermediate plane MT and the second tapered surface T2 intersect may be parallel to the m-axis of the nitride semiconductor portion 8A. The intermediate plane MT may have a shape that follows the surface of the base substrate BS. The first tapered surface T1 and the second tapered surface T2 may extend from the intermediate plane MT. The intermediate plane MT does not have to overlap with the first tapered surface T1 in a plan view. The intermediate plane MT may overlap with the second tapered surface T2 in a plan view. The nitrogen polarity plane (-C plane) of the nitride semiconductor may be exposed at the intermediate plane MT.

[0024] FIG. 4 is a flowchart illustrating a method for manufacturing a semiconductor substrate according to this embodiment. FIG. 5 is a cross-sectional view illustrating a method for manufacturing a semiconductor substrate according to this embodiment. The method for manufacturing a semiconductor substrate illustrated in FIGS. 4 and 5 includes a step S10 of preparing an initial substrate SK, which includes a base substrate BS, a mask portion 5 and a nitride semiconductor portion 8A located above the base substrate BS, and a root portion R1 including a nitride semiconductor and connecting the base substrate BS and the nitride semiconductor portion 8A. The nitride semiconductor portion 8A has a base portion B1 located above the root portion R1 and a floating portion F connected to the base portion B1 and not in contact with the base substrate BS. The root portion R1 has a first tapered surface (initial tapered surface) T1 that contacts the mask portion 5, and a step S20 of removing the mask portion 5 from the initial substrate SK. Step S20 results in a structure in which the first tapered surface T1 faces the void JD. Wet etching using, for example, an HF solution can be used to remove the mask portion 5. In this embodiment, the structure of the first tapered surface T1 remains unchanged before and after step S20. The structure of the first tapered surface T1 may be changed before and after step S20.

[0025] The mask portion 5 may include a forward tapered edge surface EF in contact with the root portion R1. The base substrate BS includes a seed portion S1 adjacent to the mask portion 5 in a planar view. In the initial substrate SK, a part of the root portion R1 extending from the seed portion S1 may run onto the mask portion 5. In the initial substrate SK, an amorphous film 7 may be formed on the side surface of the root portion R1. The amorphous film 7 may be formed on the mask portion 5. The side surface of the root portion R1 may be covered with the amorphous film 7.

[0026] The initial substrate SK and the semiconductor substrate 10 may have a forward tapered second tapered surface T2. The second tapered surface T2 faces the gap JD in the initial substrate SK and the semiconductor substrate 10. The initial substrate SK and the semiconductor substrate 10 may have an intermediate surface MT. In the initial substrate SK, the intermediate surface MT is in contact with the mask portion 5. By step S20, the semiconductor substrate 10 has a structure in which the intermediate surface MT faces the gap JD.

[0027] Fig. 6 is a flowchart showing the method for manufacturing a semiconductor substrate according to this embodiment. Fig. 7 is a cross-sectional view showing the method for manufacturing a semiconductor substrate according to this embodiment. In step S10 of Fig. 4, as shown in Figs. 6 and 7, an initial substrate SK may be obtained by performing step S12 of preparing a template substrate TS including a mask pattern 6, step S14 of growing a root portion R1 from a seed portion S1 exposed in an opening of the mask pattern 6, step S16 of forming an amorphous film 7 (growth suppression film) in contact with the root portion R1 and the mask pattern 6, and step S18 of ELO (lateral overgrowth) of the nitride semiconductor portion 8A (base portion B1 and floating portion F) starting from at least a portion of the upper surface of the root portion R1.

[0028] In step S14, the root portion R1 is grown so that a portion of the root portion R1 contacts the side surface of the mask pattern 6. In step S14, the root portion R1 is grown so that a portion of the root portion R1 follows the side surface of the mask pattern 6. By growing the root portion R1 so that a portion of the root portion R1 follows the side surface of the mask pattern 6, a first tapered surface T1 is formed. In step S14, the root portion R1 is grown so that a portion of the root portion R1 contacts the upper surface of the mask pattern 6. In step S14, the root portion R1 is grown so that a portion of the root portion R1 is located on the upper surface of the mask pattern 6. In step S14, the root portion R1 is grown so that a portion of the root portion R1 covers a portion of the upper surface of the mask pattern 6. In step S14, the root portion R1 is grown so that the width of the portion of the root portion R1 located above the mask pattern 6 gradually decreases.

[0029] In step S18, the nitride semiconductor portion 8A (base portion B1 and wing portion F) may be grown by ELO, using the corner where the top surface and side surface of the root portion R1 intersect as the growth starting point. For example, in step S16, at least one defect portion DF may be formed in the amorphous film 7, and the crystal (nitride semiconductor crystal) exposed in the defect portion DF may be used as the growth starting point for ELO. For example, the defect portion DF may be an opening, a step, a break, a thin film portion, or the like. For example, multiple defect portions DF may be formed in the amorphous film 7 in step S16.

[0030] The root portion R1, the amorphous film 7, and the nitride semiconductor portion 8A may be formed successively using an MOCVD apparatus. When the root portion R1 includes a GaN-based semiconductor and the amorphous film 7 is silicon nitride, for example, the root portion R1 can be formed by supplying a raw material that serves as a gallium source and a raw material that serves as a nitrogen source, and then the supply of the raw material that serves as the nitrogen source is maintained while the supply of the raw material that serves as the gallium source is stopped and a silicon-based material is supplied, thereby forming the amorphous film 7. When the nitride semiconductor portion 8A is formed, the base portion B1 and the floating portion F1 may be formed simultaneously.

[0031] An example of FIG. 7 is shown below. As shown in FIG. 7 , an AlN layer serving as an underlayer 4 is formed on a main substrate 1 (silicon substrate) by sputtering. For example, the underlayer 4 may be formed to a thickness of 100 nm. Next, a silicon compound film (silicon nitride, silicon oxide, etc.) formed on the underlayer 4 by sputtering to a thickness of approximately 10 nm is patterned by photolithography to form a mask pattern 6 including a mask portion 5. For example, the mask pattern 6 may be formed in a stripe shape. For example, the mask pattern 6 may be formed by forming multiple masks with their longitudinal direction in the second direction X2 aligned in the first direction X1. This results in a template substrate TS.

[0032] Next, the template substrate TS is transferred to an MOCVD apparatus, where the root portion R1 is formed. The film formation conditions were a film formation temperature of 1100°C, an ammonia flow rate of 7.5 slm, and a TMG (trimethylgallium) flow rate of 5 sccm. In FIG. 7 , the root portion R1 climbed onto the edge of the mask portion 5, and the growth of the root portion R1 was stopped when the film thickness reached 1.5 μm.

[0033] Next, the film formation temperature was lowered by about 150° C. from the initial growth temperature, the supply of TMG was stopped, and SiH ４ (Silane): Flow rate 400 sccm, and ammonia (NH ３ ): A flow rate of 7.5 slm is supplied to deposit a thin SiN layer (about 1 nm). As a result, an amorphous film 7 (growth suppression film) is formed on the side and top surfaces of the base portion R1.

[0034] Next, the film formation temperature is raised to 250°C, and TMG and ammonia are supplied again to form the nitride semiconductor portion 8A. At this time, the amorphous film (growth suppression film) 7 has a significant effect on the crystal growth, and for example, nitride semiconductor crystals extending laterally from the corners of the base portion R1 grow in a state floating above the mask portion 5, forming the floating portion F. That is, in the nitride semiconductor portion 8A, the back surface (lower surface, -C plane) of the floating portion F is separated from the mask portion 5.

[0035] The thickness of the mask portion 5 may be, for example, 50 nm or less. The thickness of the amorphous film 7 may be smaller than the thickness of the mask portion 5. This makes it easier for the floating portion F to grow from the root portion R1 while suppressing growth on the mask portion 5. The thickness of the amorphous film 7 may be, for example, ⅓ or less of the thickness of the mask portion 5.

[0036] In this embodiment, the floating portion F floats in the air and does not come into contact with the mask portion 5, so even if the mask portion 5 is made very thin, the growth of the floating portion F is not hindered. By making the mask portion 5 thin, the flatness of the back surface of the floating portion F is improved. The flatness is improved when the thickness of the mask portion 5 is set to 50 nm or less. For example, the thickness of the mask portion 5 can be set to 30 nm or less.

[0037] Fig. 8 is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. Fig. 9 is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. In the semiconductor substrate 10 of Fig. 1, the floating portion F has an edge E located above the base substrate BS, but this is not limited to this. As shown in Figs. 8 and 9, a nitride semiconductor crystal extending from a root portion R1 on the seed portion S1 and a nitride semiconductor crystal extending from a root portion R2 on the seed portion S2 may be joined above the mask portion 5 to form a floating portion F connected to adjacent root portions R1 and R2.

[0038] 10 is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. As shown in FIG. 10, the semiconductor substrate 10 may include an upper layer portion UL located above the nitride semiconductor portion 8A. The upper layer portion UL may include, for example, a functional layer made of a GaN-based semiconductor. This functional layer may include an active layer (e.g., a light-emitting layer having a quantum well structure). The upper layer portion UL may include electrodes (e.g., an anode, a cathode, a gate, etc.). The anode and the active layer may overlap the floating portion F in a plan view.

[0039] FIG. 11 is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. FIG. 12 is an image of the semiconductor substrate according to this embodiment. As shown in FIGS. 11 and 12 , the semiconductor substrate 10 includes a base substrate BS, a nitride semiconductor portion 8A located above the base substrate BS, and a root portion R1 including a nitride semiconductor and connecting the base substrate BS and the nitride semiconductor portion 8A. The nitride semiconductor portion 8A includes a base portion B1 located above the root portion R1 and a floating portion F extending from the base portion B1 and not in contact with the base substrate BS. The root portion R1 has a first tapered surface T1 facing the gap JD. The nitride semiconductor portion 8A does not necessarily have to have a second tapered surface T2.

[0040] The gap JD may be a space surrounded by the base substrate BS, the root portion R1, and the floating portion F. The first tapered surface T1 may have a shape that follows a specific crystal plane of the nitride semiconductor. For example, the first tapered surface T1 may have a shape that follows the (10-1-1) plane, which is a specific crystal plane of the nitride semiconductor. The angle formed between the first tapered surface T1 and the surface of the base substrate BS may be 45 degrees or greater.

[0041] 11, the base portion R1 has the first tapered surface T1 facing the gap JD, which makes the stress in the vicinity of the interface between the base substrate BS and the base portion R1 uniform, facilitating peeling of the nitride semiconductor portion 8A (fracture of the base portion R1). By exposing a chemically strong crystal plane such as the (10-1-1) plane on the surface, chemical resistance in subsequent processes (such as the development process) is improved.

[0042] 11 and 12 , the floating portion F may include a plurality of protrusions Q that protrude toward the base substrate BS. Each of the plurality of protrusions Q may have a slope that follows the (10-1-1) plane of the nitride semiconductor. A protrusion group QA including the plurality of protrusions Q may be located across the entire lower surface of the floating portion F (the surface facing the base substrate BS).

[0043] The first tapered surface T1 may intersect with the base substrate BS. The first tapered surface T1 may have an inverse tapered shape (overhanging shape) that protrudes above the base substrate BS. The base substrate BS may include a main substrate 1 and an underlayer 4 on the main substrate 1, and the surface of the underlayer 4 may be exposed (facing the void JD). Threading dislocations in the underlayer 4 may extend to the surface of the underlayer 4. The lattice constant of the main substrate 1 may be different from the lattice constant of the nitride semiconductor portion 8A.

[0044] The second tapered surface T2 may be connected to the first tapered surface T1. The second tapered surface T2 may extend from the first tapered surface T1. The second tapered surface T2 may intersect with the first tapered surface T1. The second tapered surface T2 may extend from the upper end of the first tapered surface T1. When the semiconductor substrate 10 is viewed in cross section, the height of the first tapered surface T1 (the amount of rise of the slope in the third direction) may be greater than the height of the second tapered surface T2 (the amount of rise of the slope in the third direction).

[0045] FIG. 13 is a flowchart illustrating a method for manufacturing a semiconductor substrate according to this embodiment. FIG. 14 is a cross-sectional view illustrating a method for manufacturing a semiconductor substrate according to this embodiment. The method for manufacturing a semiconductor substrate illustrated in FIGS. 13 and 14 includes the steps of: preparing an initial substrate SK including a base substrate BS, a nitride semiconductor portion 8A located above the base substrate BS, and a root portion R1 including a nitride semiconductor and connecting the base substrate BS and the nitride semiconductor portion 8A; the nitride semiconductor portion 8A having a base portion B1 located above the root portion R1 and a floating portion F extending from the base portion B1 and not in contact with the base substrate BS; and wet-etching the root portion R1 of the initial substrate SK using an etching solution EL to form a first tapered surface T1 at the root portion R1. The etching solution EL may be introduced through a gap GP between two adjacent floating portions F. The etching solution EL (etchant) may be, for example, a KOH solution.

[0046] In step S40, the bottom surfaces of the root portion R1 and the floating portion F of the initial substrate SK may be wet-etched simultaneously. By simultaneously wet-etching the bottom surfaces of the root portion R1 and the floating portion F of the initial substrate SK, a first tapered surface T1 can be formed in the root portion R1, and at the same time, multiple protrusions Q can be formed on the bottom surface of the floating portion F. The first tapered surface T1 is parallel to the (10-1-1) plane of the nitride semiconductor, and by wet-etching the bottom surface of the floating portion F of the initial substrate SK, multiple protrusions Q including a surface parallel to the (10-1-1) plane are formed. For example, the bottom surface of the floating portion F is the (000-1) plane of the nitride semiconductor.

[0047] 15 is a cross-sectional view showing the configuration of the semiconductor substrate according to this embodiment. As shown in Fig. 15, the nitride semiconductor crystal growing from the root portion R1 on the seed portion S1 and the nitride semiconductor crystal growing from the root portion R2 on the seed portion S2 are joined above the mask portion 5, and then the back surface (-C surface) of the crystal is wet-etched with KOH or the like, thereby forming a floating portion F that is connected to the adjacent root portions R1 and R2 and has a plurality of protrusions Q that protrude toward the base substrate BS.

[0048] 16 is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. As shown in FIG. 16, the semiconductor substrate 10 may include an upper layer portion UL located above the nitride semiconductor portion 8A. The upper layer portion UL may include, for example, a functional layer made of a GaN-based semiconductor, and this functional layer may include an active layer (e.g., a light-emitting layer having a quantum well structure). The upper layer portion UL may include electrodes (e.g., an anode, a cathode, a gate, etc.). The anode and the active layer may overlap the floating portion F in a plan view.

[0049] FIG. 17 is a flowchart showing a method for manufacturing a semiconductor device according to this embodiment. FIGS. 18 and 19 are cross-sectional views showing a method for manufacturing a semiconductor device according to this embodiment. As shown in FIGS. 17 to 19 , the method for manufacturing a semiconductor device according to this embodiment includes a step S60 of preparing a semiconductor substrate 10, a step S70 of forming an upper layer portion UL including a functional layer above the nitride semiconductor portion 8A, and a step S80 of peeling an element portion 15 including a floating portion F from the base substrate BS to obtain a semiconductor device 20. As shown in FIG. 18 , the element portion 15 obtained by forming the upper layer portion UL on the nitride semiconductor portion 8A of the semiconductor substrate 10 of FIG. 1 may be transferred to a transfer substrate PS (e.g., a submount substrate) to obtain a semiconductor device 20. As shown in FIG. 19 , the element portion 15 obtained by forming the upper layer portion UL on the nitride semiconductor portion 8A of the semiconductor substrate 10 of FIG. 11 may be transferred to a transfer substrate PS (e.g., a submount substrate) to obtain a semiconductor device 20.

[0050] Figures 20 and 21 are block diagrams showing a semiconductor substrate manufacturing apparatus according to this embodiment. The semiconductor substrate manufacturing apparatus 50 of Figure 20 includes an apparatus M10 that performs step S10 of Figure 4, an apparatus M20 that performs step S20 of Figure 4, and a control device M1 that controls the apparatus M10 and the apparatus M20. The semiconductor substrate manufacturing apparatus 50 of Figure 21 includes an apparatus M30 that performs step S30 of Figure 13, an apparatus M40 that performs step S40 of Figure 13, and a control device M3 that controls the apparatus M30 and the apparatus M40.

[0051] Fig. 22 is a block diagram showing a semiconductor device manufacturing apparatus according to this embodiment. The semiconductor device manufacturing apparatus 90 in Fig. 22 includes an apparatus M60 that performs step S60 in Fig. 17, an apparatus M70 that performs step S70 in Fig. 17, an apparatus M80 that performs step S80 in Fig. 17, and a control device M6 that controls the apparatus M60, the apparatus M70, and the apparatus M80.

[0052] 23 is a schematic diagram showing the configuration of an electronic device according to this embodiment. The electronic device 25 includes a semiconductor device 20, a drive substrate 23 on which the semiconductor device 20 is mounted, and a control circuit 27 that controls the drive substrate 23. The semiconductor device 20 may include a base portion R1. The semiconductor device 20 may include an upper layer portion UL (a functional layer 9 including an active layer and an electrode D). The control circuit 27 may include a processor. Examples of the electronic device 25 include a display device, a laser emission device (including a Fabry-Perot type and a surface-emitting type), a lighting device, a communication device, an information processing device, a sensing device, a power control device, and the like.

[0053] [Summary] Disclosure 1: A semiconductor substrate comprising: a base substrate; a nitride semiconductor portion located above the base substrate; and a root portion including a nitride semiconductor and connecting the base substrate and the nitride semiconductor portion, wherein the nitride semiconductor portion has a base portion located above the root portion and a floating portion extending from the base portion and not in contact with the base substrate, and the root portion has a first tapered surface facing a void.

[0054] Disclosure 2: The semiconductor substrate of Disclosure 1, wherein the first tapered surface intersects with the base substrate.

[0055] Disclosure 3: A semiconductor substrate according to Disclosure 1 or 2, wherein the first tapered surface is an inverted tapered surface that protrudes above the base substrate.

[0056] Disclosure 4: The semiconductor substrate according to any one of Disclosures 1 to 3, wherein the first tapered surface has a shape that follows a specific crystal plane of the nitride semiconductor.

[0057] Disclosure 5: The semiconductor substrate according to Disclosure 4, wherein the specific crystal plane is the (10-1-1) plane.

[0058] Disclosure 6: A semiconductor substrate according to any one of Disclosures 1 to 5, wherein the first tapered surface has a shape whose longitudinal direction is the m-axis direction of the nitride semiconductor.

[0059] Disclosure 7: A semiconductor substrate according to any one of Disclosures 1 to 6, wherein the base portion has a second tapered surface facing the void.

[0060] Disclosure 8: The semiconductor substrate according to Disclosure 7, wherein the second tapered surface is a forward tapered surface.

[0061] Disclosure 9: A semiconductor substrate according to any one of Disclosures 1 to 8, wherein the thickness of the root portion is smaller than the thickness of the floating portion.

[0062] Disclosure 10: A semiconductor substrate according to any one of Disclosures 1 to 9, wherein the floating portion includes a plurality of protrusions that protrude toward the base substrate.

[0063] Disclosure 11: The semiconductor substrate according to Disclosure 10, wherein each of the plurality of protrusions has a slope along the (10-1-1) plane of the nitride semiconductor.

[0064] Disclosure 12: A semiconductor substrate according to Disclosure 10 or 11, wherein the group of protrusions including the plurality of protrusions is located across the entire lower surface of the floating portion.

[0065] Disclosure 13: A semiconductor substrate according to any one of Disclosures 1 to 12, wherein the floating portion includes an edge located above the base substrate.

[0066] Disclosure 14: A semiconductor substrate according to Disclosure 13, wherein threading dislocations in the root portion are inherited by the base portion, and the threading dislocation density in the floating portion is 1 / 5 or less of the threading dislocation density in the base portion.

[0067] Disclosure 15: The threading dislocation density of the floating portion is 5×10 ６ [cm －２ 15. The semiconductor substrate of Disclosure 14, wherein:

[0068] Disclosure 16: A semiconductor substrate according to any one of Disclosures 1 to 15, wherein the base substrate has a main substrate and an underlayer including a nitride semiconductor.

[0069] Disclosure 17: The semiconductor substrate of any one of Disclosures 1 to 16, comprising an amorphous film located between the root portion and the base portion.

[0070] Disclosure 18: The semiconductor substrate according to Disclosure 16, wherein the surface of the underlayer is exposed.

[0071] Disclosure 19: The semiconductor substrate according to Disclosure 16, wherein threading dislocations in the underlayer extend to the surface.

[0072] Disclosure 20: A semiconductor substrate according to any one of Disclosures 1 to 19, comprising a functional layer located above the nitride semiconductor portion.

[0073] Disclosure 21: The semiconductor substrate according to Disclosure 16, wherein the lattice constant of the main substrate is different from the lattice constant of the nitride semiconductor portion.

[0074] Disclosure 22: A method for manufacturing a semiconductor substrate, comprising: a step of preparing an initial substrate comprising: a base substrate; a mask portion and a nitride semiconductor portion located above the base substrate; and a root portion including a nitride semiconductor and connecting the base substrate and the nitride semiconductor portion, the nitride semiconductor portion having a base portion located above the root portion and a floating portion connected to the base portion and not in contact with the base substrate, the root portion having a first tapered surface in contact with the mask portion; and a step of removing the mask portion from the initial substrate.

[0075] Disclosure 23: The method for manufacturing a semiconductor substrate according to Disclosure 22, wherein the mask portion includes a forward tapered edge surface that contacts the base portion.

[0076] Disclosure 24: A method for manufacturing a semiconductor substrate described in Disclosure 22 or 23, wherein the base substrate includes a seed portion adjacent to the mask portion in a planar view, and in the initial substrate, a root portion extending from the seed portion rides on top of the mask portion.

[0077] Disclosure 25: A method for manufacturing a semiconductor substrate according to any one of Disclosures 22 to 24, wherein an amorphous film is formed on the side surface of the base portion of the initial substrate.

[0078] Disclosure 26: The method for manufacturing a semiconductor substrate according to any one of Disclosures 22 to 25, wherein an amorphous film is formed on the mask portion of the initial substrate.

[0079] Disclosure 27: A method for manufacturing a semiconductor substrate, comprising: a step of preparing an initial substrate comprising a base substrate, a nitride semiconductor portion located above the base substrate, and a root portion including a nitride semiconductor and connecting the base substrate and the nitride semiconductor portion, the nitride semiconductor portion having a base portion located above the root portion and a floating portion connected to the base portion and not in contact with the base substrate; and a step of wet-etching the root portion of the initial substrate to form a first tapered surface in the root portion.

[0080] Disclosure 28: The method for manufacturing a semiconductor substrate according to Disclosure 27, wherein the bottom surfaces of the root portion and the floating portion of the initial substrate are simultaneously wet etched.

[0081] Disclosure 29: The method for manufacturing a semiconductor substrate according to Disclosure 27 or 28, wherein the first tapered surface is parallel to the (10-1-1) plane of the nitride semiconductor, and a plurality of protrusions including a surface parallel to the (10-1-1) plane are formed by wet etching the lower surface of the floating portion of the initial substrate.

[0082] Disclosure 30: A semiconductor substrate manufacturing apparatus that performs each of the steps described in Disclosure 22 or 27.

[0083] Disclosure 31: A method for manufacturing a semiconductor device, comprising the steps of preparing a semiconductor substrate according to any one of Disclosures 1 to 21, and forming an upper layer portion including a functional layer above the nitride semiconductor portion.

[0084] (Notes) The above disclosure is intended to be illustrative and explanatory, and is not intended to be limiting. Based on these examples and explanations, many variations will be obvious to those skilled in the art, and these variations are also included in the embodiments.

[0085] REFERENCE SIGNS LIST 1 Main substrate 4 Underlayer 5 Mask portion 6 Mask pattern 7 Amorphous film 8A Nitride semiconductor portion 10 Semiconductor substrate 20 Semiconductor device E Edge (of nitride semiconductor portion) F Floating portion R1, R2 Root portion JD Air gap B1, B2 Base portion S1, S2 Seed portion TS Template substrate BS Base substrate

Claims

1. A semiconductor substrate comprising: a base substrate; a nitride semiconductor portion located above the base substrate; and a root portion including a nitride semiconductor and connecting the base substrate and the nitride semiconductor portion, wherein the nitride semiconductor portion has a base portion located above the root portion and a floating portion extending from the base portion and not in contact with the base substrate, and the root portion has a first tapered surface facing a void.

2. The semiconductor substrate of claim 1, wherein said first tapered surface intersects with said base substrate.

3. The semiconductor substrate according to claim 1 or 2, wherein the first tapered surface is an inverse tapered surface that protrudes above the base substrate.

4. The semiconductor substrate according to any one of claims 1 to 3, wherein the first tapered surface has a shape that follows a specific crystal plane of the nitride semiconductor.

5. The semiconductor substrate according to claim 4, wherein the specific crystal plane is the (10-1-1) plane.

6. The semiconductor substrate according to any one of claims 1 to 5, wherein the first tapered surface has a shape whose longitudinal direction is the m-axis direction of the nitride semiconductor.

7. The semiconductor substrate according to any one of claims 1 to 6, wherein the base portion has a second tapered surface facing the gap.

8. The semiconductor substrate according to claim 7, wherein the second tapered surface is a forward tapered surface.

9. The semiconductor substrate according to any one of claims 1 to 8, wherein the thickness of the root portion is smaller than the thickness of the floating portion.

10. The semiconductor substrate according to any one of claims 1 to 9, wherein the floating portion includes a plurality of protrusions that protrude toward the base substrate.

11. The semiconductor substrate according to claim 10, wherein each of the plurality of protrusions has a slope that is aligned with the (10-1-1) plane of the nitride semiconductor.

12. The semiconductor substrate according to claim 10 or 11, wherein the group of protrusions including the plurality of protrusions is located across the entire lower surface of the floating portion.

13. The semiconductor substrate according to any one of claims 1 to 12, wherein the floating portion includes an edge located above the base substrate.

14. The semiconductor substrate according to claim 13, wherein threading dislocations in the root portion are inherited by the base portion, and the threading dislocation density in the floating portion is 1 / 5 or less of the threading dislocation density in the base portion.

15. The threading dislocation density of the floating portion is 5×10 ６ [cm －２ 15. The semiconductor substrate according to claim 14, wherein:

16. The semiconductor substrate according to any one of claims 1 to 15, wherein the base substrate comprises a main substrate and an underlayer containing a nitride semiconductor.

17. The semiconductor substrate of any one of claims 1 to 16, further comprising an amorphous film located between the root portion and the base portion.

18. The semiconductor substrate according to claim 16, wherein the surface of the underlayer is exposed.

19. A method for manufacturing a semiconductor substrate, comprising: preparing an initial substrate comprising a base substrate, a mask portion and a nitride semiconductor portion located above the base substrate, and a root portion including a nitride semiconductor and connecting the base substrate and the nitride semiconductor portion, the nitride semiconductor portion having a base portion located above the root portion and a floating portion connected to the base portion and not in contact with the base substrate, the root portion having a first tapered surface in contact with the mask portion; and removing the mask portion from the initial substrate.

20. The method for manufacturing a semiconductor substrate according to claim 19, wherein the mask portion includes a forward tapered edge surface that contacts the base portion.

21. A method for manufacturing a semiconductor substrate according to claim 19 or 20, wherein the base substrate includes a seed portion adjacent to the mask portion in a plan view, and in the initial substrate, a root portion extending from the seed portion rides on top of the mask portion.

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