Advanced radiative cooling system for semiconductor chips using integrated metal-optic layers

Abstract

Radiative cooling as a passive and energy-efficient method that can reduce temperature-induced performance degradation and mitigate localized hotspots in semiconductor chips and other high-density integrated circuits, particularly critical with the advent of 3D-integrated CMOS technologies. A semiconductor chip has a front-end-of-the-line (FOEL) layer comprising a plurality of electronic components. The chip may further comprise a back-end-of-the-line (BOEL) layer comprising one or more thermally-emitting elements configured to emit infrared radiation such that heat on the semiconductor chip is dispersed.

Description

ADVANCED RADIATIVE COOLING SYSTEM FOR SEMICONDUCTOR CHIPS USING INTEGRATED METAL-OPTIC LAYERSCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims benefit of U.S. Provisional Application No. 63 / 635,807 filed April 18, 2024, the specification(s) of which is / are incorporated herein in their entirety by reference.FIELD OF THE INVENTION

[0002] The present invention is directed to a radiative cooling mechanism implementing the back-end-of-the-line (BEOL) layers of semiconductor chips.BACKGROUND OF THE INVENTION

[0003] Localized hot spots in semiconductor chips refer to areas within the integrated circuit that generate and accumulate excessive heat compared to surrounding regions. These hot spots arise due to uneven power dissipation across the chip, often caused by high transistor density, intense computational activity, or leakage currents in certain areas. The presence of hot spots can lead to various problems, including thermal-induced performance degradation, reduced reliability and lifespan of the device, and potential failure of the semiconductor material. One of the current challenges in addressing hot spots is the need for effective thermal management solutions that can be integrated into the chip design without compromising its performance or increasing its size. Additionally, as chip architectures become more complex and power densities increase, developing scalable and efficient cooling techniques that can target specific localized areas remains a significant hurdle.

[0004] To address the issue of localized hot spots in semiconductor chips, several techniques are commonly employed, each with its own drawbacks. Dynamic Voltage and Frequency Scaling (DVFS) adjusts the voltage and frequency of the processor based on workload and temperature to reduce heat generation. However, lowering the frequency and voltage can slow down the processing speed, impacting overall performance. Dynamic Thermal Management (DTM) involves real-time monitoring of the chip's temperature and taking corrective actions, such as throttling the clock speed, to prevent overheating. While effective in preventing thermal damage, DTM can lead to inconsistent performance, which is problematic for applications requiring stableoperation.

[0005] Moreover, DVFS and DTM require sensors to monitor the temperature and workload across the chip. Integrating these sensors into the chip design can be challenging and may increase the complexity and cost of the semiconductor device. Additionally, the sensors themselves can consume power and occupy valuable space on the chip, potentially impacting overall efficiency and performance. Liquid cooling and microfluidic cooling are effective techniques for cooling chips but can be expensive and complex to implement, adding additional components that increase the size and weight of the system. Moreover, Liquid cooling can be effective for single-layer chips, but its efficiency can be significantly reduced for stacked integrated circuits (3D ICs). This is because the cooling fluid has limited access to the inner layers of the stack, making it challenging to remove heat from the hot spots effectively. Thus, there exists a present need for an efficient implementation of radiative cooling in semiconductor chips.BRIEF SUMMARY OF THE INVENTION

[0006] It is an objective of the present invention to provide devices and systems that allow for a radiative cooling mechanism implementing the back-end-of-the-line (BEOL) layers of semiconductor chips, as specified in the independent claims. Embodiments of the invention are given in the dependent claims. Embodiments of the present invention can be freely combined with each other if they are not mutually exclusive.

[0007] Radiative cooling is the process by which heat is dissipated by emitting thermal radiation into the cold outer space through Earth's transparent atmospheric window (8-13 pm wavelength). In some aspects, the present invention focused on improving radiative cooling efficiency by developing angular-selective emitters that minimize absorption of environmental radiation, thus maintaining effective cooling under humid and other challenging conditions.

[0008] According to some embodiments, the present invention features an interconnecting wire layer configured to be integrated into a semiconductor chip. In some embodiments, the semiconductor chip may comprise a complementary metal-oxide-semiconductor (CMOS) chip. The interconnecting wire layer may comprise one or more thermally-emitting wires connecting a plurality of electronic components integrated into the semiconductor chip and configured to emit infrared radiation suchthat heat on the semiconductor chip is dispersed.

[0009] In other embodiments, the present invention features a semiconductor chip. The chip may comprise a front-end-of-the-line (FOEL) layer comprising a plurality of electronic components. The chip may further comprise a back-end-of-the-line (BOEL) layer comprising one or more thermally-emitting wires connecting the plurality of electronic components (250) and configured to emit infrared radiation such that heat on the semiconductor chip is dispersed.

[0010] In some other embodiments, the present invention features a three-dimensional integrated circuit (IC). The IC may comprise a plurality of semiconductor chips. Each semiconductor chip may comprise a front-end-of-the-line (FOEL) layer comprising a plurality of electronic components. Each chip may further comprise a back-end-of-the-line (BOEL) layer comprising one or more thermally-emitting wires connecting the plurality of electronic components (250) and configured to emit infrared radiation such that heat on the semiconductor chip is dispersed.

[0011] According to some embodiments, the present invention features an interconnect wire patterned to have a plurality of projections extending from a central wire body. The interconnect wire is configured to radiate infrared wavelengths and have near-unity emissivity. In some embodiments, the interconnect wire (150) may be constructed from a thermally conductive material.

[0012] In non-limiting embodiments, the present invention provides a semiconductor chip comprising a front-end-of-the-line (FOEL) layer comprising a plurality of electronic components, and a back-end-of-the-line (BOEL) layer comprising thermally-emitting wires for passive radiative cooling.

[0013] In other embodiments, the present invention provides an integrated circuit (IC) comprising a plurality of electronic components, and thermally-emitting interconnects operatively connecting the electronic component. The thermally-emitting interconnects are configured to dissipate excess heat as infrared radiation into a heat sink.

[0014] One of the unique and inventive technical features of the present invention is the implementation of the back-end-of-the-line (BOEL) layer of a semiconductor formetal-optic devices directly implemented onto the semiconductor chip. Without wishing to limit the invention to any theory or mechanism, it is believed that the technical feature of the present invention advantageously provides for enhanced radiative cooling in semiconductor chips without altering existing foundry process rules, increasing the ease and cost-efficiency of manufacturing semiconductor chips with radiative cooling. None of the presently known prior references or work has the unique inventive technical feature of the present invention.

[0015] Any feature or combination of features described herein are included within the scope of the present invention provided that the features included in any such combination are not mutually inconsistent as will be apparent from the context, this specification, and the knowledge of one of ordinary skill in the art. Additional advantages and aspects of the present invention are apparent in the following detailed description and claims.BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

[0016] The features and advantages of the present invention will become apparent from a consideration of the following detailed description presented in connection with the accompanying drawings in which:

[0017] FIG. 1 shows nanoengineered thermally-emitting wires. Wires are integrated within the BEOL of CMOS chips for passive radiative cooling. Engineered metal interconnects serve as directional thermal emitters, dissipating excess heat as infrared radiation into a heat sink while adhering to standard foundry design rules.

[0018] FIG. 2 shows schematics of enhanced thermoelectric generation through radiative cooling (a). The cold side of the thermal generator has near unity thermal emissivity (b).

[0019] FIG. 3A is a diagram of a thermally-emitting element of the present invention.

[0020] FIG. 3B shows the thermally-emitting elements of the present invention coupled to a heat sink such that the elements thermally emit into the heat sink.

[0021] FIG. 4 shows a diagram of an interconnecting wire layer implementing the thermally-emitting elements of the present invention.

[0022] FIG. 5A shows a diagram of a semiconductor chip implementing the thermally-emitting elements of the present invention.

[0023] FIG. 5B shows a diagram of a three-dimensional integrated circuit implementing the thermally-emitting elements of the present invention.DETAILED DESCRIPTION OF THE INVENTION

[0024] Following is a list of elements corresponding to a particular element referred to herein:

[0025] 100 interconnecting wire layer

[0026] 150 thermally-emitting element

[0027] 200 front-end-of-the-line layer

[0028] 250 electronic components

[0029] 300 heat sink

[0030] 1000 semiconductor chip

[0031] 2000 three-dimensional integrated circuit

[0032] The term “hot spot” is defined herein as a location on a semiconductor chip where uneven power dissipation caused by high transistor density, intense computational activity, or leakage currents cause a localized increase in heat.

[0033] Referring to the figures, the present invention provides a thermally-emitting element (150) configured to emit infrared radiation, thereby dispersing heat. In some embodiments, the thermally-emitting element (150) may be configured to emit the infrared radiation toward a heat sink (300). One or more of the thermally-emitting element (150) can be used with electronic devices for cooling purposes.

[0034] In some embodiments, a material of the thermally-emitting elements (150) may comprise copper, aluminum, tungsten, titanium nitride, or a combination thereof. In some embodiments, the thermally-emitting elements (150) may comprise a thermally conductive material.

[0035] In some embodiments, the thermally-emitting elements (150) may comprise one or more pairs of symmetrical flat protrusions disposed along a length of the element. In some embodiments, each flat protrusion of the one or more pairs of symmetrical flat protrusions may comprise a rectangular shape, a triangular shape, a rounded shape, or a combination thereof. Due to the symmetrical nature, each flat protrusion in a pair may have the same shape. In some embodiments, the shape of the flat protrusions maydiffer across different pairs. In some embodiments, the shape of the flat protrusions may be the same across different pairs. It is understood that the thermally-emitting elements (150) are not limited to these configurations.

[0036] In other embodiments, the one or more thermally-emitting elements (150) may comprise wires connecting the plurality of electronic components (250), capacitors, insulators, or any other electronic components.

[0037] Referring now to FIG. 3A, the present invention features an interconnecting wire layer (100) configured to be integrated into a semiconductor chip (1000). The interconnecting wire layer (100) may comprise one or more thermally-emitting elements (150) configured to emit infrared radiation such that heat on the semiconductor chip (1000) is dispersed. In some embodiments, the semiconductor chip (1000) may comprise a plurality of electronic components (250).

[0038] Referring now to FIG. 5A, the present invention features a semiconductor chip (1000). The chip (1000) may comprise a front-end-of-the-line (FOEL) layer (200) comprising a plurality of electronic components (250). The chip (1000) may further comprise a back-end-of-the-line (BOEL) layer (100) comprising one or more thermally-emitting elements (150) configured to emit infrared radiation such that heat on the semiconductor chip (1000) is dispersed.

[0039] Referring now to FIG. 5B, the present invention features a three-dimensional integrated circuit (IC) (2000). The IC (2000) may comprise a plurality of semiconductor chips. Each semiconductor chip (1000) may comprise a front-end-of-the-line (FOEL) layer (200) comprising a plurality of electronic components (250). Each chip (1000) may further comprise a back-end-of-the-line (BOEL) layer (100) comprising one or more thermally-emitting elements (150) configured to emit infrared radiation such that heat on the semiconductor chip (1000) is dispersed.

[0040] In some embodiments, the one or more thermally-emitting elements (150) may be localized at one or more hot spots on the semiconductor chip (1000). In some embodiments, the semiconductor chip may comprise a complementary metal-oxide-semiconductor (CMOS) chip, a silicon-on-insulator (SOI) chip, a silicon photonic chip, any other semiconductor type, or a combination thereof.

[0041] In some embodiments, the plurality of electronic components (250) may comprise transistors, p-n junctions, inductors, gates, or a combination thereof.

[0042] Without wishing to be limited to a particular theory or mechanism, the present invention addresses the issue of localized hot spots in semiconductor chips by exploiting the nanoscale patterning capabilities in the back end of the line (BEOL), which refers to the final stages of chip fabrication where metal interconnects are formed. This capability opens the door for integrating metal-optic techniques, enabling the homogeneous integration of nanophotonics and electronics. The interconnect wires are repurposed to create nano-antennas that efficiently radiate infrared wavelengths, transforming the metal from having near-zero emissivity to near-unity emissivity (FIG. 3A).

[0043] According to some embodiments, the present invention features an interconnect wire (150) patterned to have a plurality of projections extending from a central wire body. The interconnect wire (150) is configured to radiate infrared wavelengths and have near-unity emissivity. In some embodiments, the interconnect wire (150) may be constructed from a thermally conductive material.

[0044] In some aspects, the plurality of projections may have the same shape or varying shapes. In other aspects, the plurality of projections may have the same length or varying lengths. In some embodiments, the central wire body has a flat elongated shape. In other embodiments, the plurality of projections have a flat shape. In some embodiments, the central wire body and the plurality of projections are co-planar.

[0045] In some other embodiments, the plurality of projections extend perpendicularly from the central wire body. Alternatively, the plurality of projections extend at non-right angles from the central wire body.

[0046] In some other embodiments, the plurality of projections extend from both sides of the central wire body. In one embodiment, the plurality of projections on one side align with the plurality of projections on the other side of the central wire body. In another embodiment, the plurality of projections on one side is offset from the plurality of projections on the other side of the central wire body. Alternatively, the plurality of projections extends from only one side of the central wire body.

[0047] In non-limiting embodiments, the present invention provides a semiconductor chip (1000) comprising a front-end-of-the-line (FOEL) layer (200) comprising a plurality of electronic components (250), and a back-end-of-the-line (BOEL) layer (100) comprising thermally-emitting wires (150) for passive radiative cooling.

[0048] In other non-limiting embodiments, the present invention provides an integrated circuit (IC) (2000) comprising a plurality of electronic components (250), and thermally-emitting interconnects operatively connecting the electronic components (250). The thermally-emitting interconnects are configured to dissipate excess heat as infrared radiation into a heat sink.

[0049] Without wishing to limit the present invention, the wire geometry is co-designed to achieve high emissivity without compromising the circuit's performance, considering key merit figures such as low resistance and capacitance. These co-designed wires can be used in regions prone to heat localization, as well as in 3D integrated circuits (ICs). 3D ICs are increasingly vital for the development of high-performance computing, telecommunications, and defense technologies, but present significant challenges when it comes to thermal management. The advantage of this approach is that the elements where the most heat is generated now become the thermal emitters. Even in 3D ICs without direct contact, heat is efficiently radiated, and this solution can be designed at the nanoscale wherever needed.

[0050] In some embodiments, the elements thermally radiate into a heat sink that is not in direct contact with the element (FIG. 3B). In some embodiments, the heat sink (300) may be constructed from a metallic material. Non-limiting examples include copper and aluminum. In other embodiments, the heat sink (300) may comprise a thermally conductive material.

[0051] While radiative cooling has been used to enhance the cooling power of heat sinks or through coatings used on chips surrounding, the present invention creates a thermal dissipation channel without direct contact (conduction) or an intermediate medium (convection), which makes it ideal for cooling local hot spots inside the chip or in 3D ICs.

[0052] Expanding the application of radiative cooling, the present invention can be used to significantly enhance the efficiency of thermoelectric generators (TEGs). In anon-limiting embodiment, the cold side of TEGs was transformed into optimized thermal emitters via femtosecond laser processing and anodization of aluminum surfaces to form structured aluminum oxide matrices with superior radiative cooling characteristics. This approach markedly increased the temperature gradient across TEGs, improving their overall energy conversion efficiency.

[0053] In other embodiments, a CMOS metal optics platform was created that enabled the integration of optical functionalities directly into standard CMOS manufacturing processes. By repurposing existing back-end-of-the-line (BEOL) metal interconnect layers in CMOS chips, nanoscale metallic structures were designed that can control light at optical frequencies using standard CMOS foundry processes. This platform allowed conventional metal wiring structures within CMOS chips to function not just as electrical interconnects but also as efficient optical components.

[0054] In some embodiments, the metal interconnects in the CMOS BEOL can serve as directional thermal emitters, as shown in FIG. 2. These designs adhere to existing foundry design rules to ensure direct implementation into established semiconductor fabrication processes without requiring additional manufacturing steps.

[0055] In some embodiments, the present invention offers hotspot mitigation for next-generation microelectronics. 3D stacking of integrated circuits (ICs) concentrates power in small regions and introduces thermal barriers, leading to thermal power concentration and steep temperature gradients that are difficult to cool. The present invention provides nanowires to act as resonant infrared (thermal) antennas due to the large effective area of these antennas compared to their physical dimensions. Without wishing to be limited to a particular theory or mechanism, the radiative cooling approach that embeds these wires in the BEOL to dissipate heat can allowe for an increase in the total power removed from the chip by up to 20%. This extra cooling channel is especially useful in areas where thermal isolation limits the overall conduction efficiency.

[0056] Although there has been shown and described the preferred embodiment of the present invention, it will be readily apparent to those skilled in the art that modifications may be made thereto which do not exceed the scope of the appended claims. Therefore, the scope of the invention is only to be limited by the following claims. In some embodiments, the figures presented in this patent application are drawn to scale,including the angles, ratios of dimensions, etc. In some embodiments, the figures are representative only and the claims are not limited by the dimensions of the figures. In some embodiments, descriptions of the inventions described herein using the phrase “comprising” includes embodiments that could be described as “consisting essentially of” or “consisting of”, and as such the written description requirement for claiming one or more embodiments of the present invention using the phrase “consisting essentially of” or “consisting of” is met.

[0057] The reference numbers recited in the below claims are solely for ease of examination of this patent application, and are exemplary, and are not intended in any way to limit the scope of the claims to the particular features having the corresponding reference numbers in the drawings.

Claims

WHAT IS CLAIMED IS:

1. An interconnecting wire layer (100) configured to be integrated into a semiconductor chip (1000), the interconnecting wire layer (100) comprising one or more thermally-emitting elements (150) configured to emit infrared radiation such that heat on the semiconductor chip (1000) is dispersed.

2. The interconnecting wire layer (100) of claim 1 , wherein the one or more thermally-emitting elements (150) are configured to emit the infrared radiation towards a heat sink (300).

3. The interconnecting wire layer (100) of claim 1 , wherein each element of the one or more thermally-emitting elements (150) comprises one or more pairs of symmetrical flat protrusions disposed along a length of the element.

4. The interconnecting wire layer (100) of claim 1 , wherein the one or more thermally-emitting elements (150) comprise one or more wires connecting a plurality of electronic components (250) integrated into the semiconductor chip (1000).

5. The interconnecting wire layer (100) of claim 4, wherein the plurality of electronic components (250) comprise transistors, p-n junctions, inductors, gates, or a combination thereof.

6. The interconnecting wire layer (100) of claim 1 , wherein a material of the one or more thermally-emitting elements (150) comprises copper, aluminum, tungsten, titanium nitride, or a combination thereof.

7. An interconnect wire (150) patterned to have a plurality of projections extending from a central wire body, wherein the interconnect wire (150) is configured to radiate infrared wavelengths, wherein the interconnect wire (150) has near-unity emissivity.

8. The interconnect wire (150) of claim 7, wherein the plurality of projections have the same shape or varying shapes.

9. The interconnect wire (150) of claim 7, wherein the plurality of projections havethe same length or varying lengths.

10. The interconnect wire (150) of claim 7, wherein the central wire body has a flat elongated shape.11 . The interconnect wire (150) of claim 7, wherein the plurality of projections have a flat shape.

12. The interconnect wire (150) of claim 7, wherein the central wire body and the plurality of projections are co-planar.

13. The interconnect wire (150) of claim 7, wherein the interconnect wire (150) is constructed from a thermally conductive material.

14. A semiconductor chip (1000) comprising: a. a front-end-of-the-line (FOEL) layer (200) comprising a plurality of electronic components (250); and b. a back-end-of-the-line (BOEL) layer (100) comprising one or more thermally-emitting elements (150) configured to emit infrared radiation such that heat on the semiconductor chip (1000) is dispersed.

15. The semiconductor chip (1000) of claim 14, wherein the one or more thermally-emitting elements (150) are configured to emit the infrared radiation towards a heat sink (300).

16. The semiconductor chip (1000) of claim 14, wherein the plurality of electronic components (250) comprise transistors, p-n junctions, inductors, gates, or a combination thereof.

17. The semiconductor chip (1000) of claim 14, wherein each element of the one or more thermally-emitting elements (150) comprises one or more pairs of symmetrical flat protrusions disposed along a length of the element.

18. The semiconductor chip (1000) of claim 17, wherein each flat protrusion of the one or more pairs of symmetrical flat protrusions comprises a rectangular shape, a triangular shape, a rounded shape, or a combination thereof.

19. The semiconductor chip (1000) of claim 14, wherein the one or more thermally-emitting elements (150) comprise one or more wires connecting the plurality of electronic components (250).

20. The semiconductor chip (1000) of claim 14, wherein a material of the one or more thermally-emitting elements (150) comprises copper, aluminum, tungsten, titanium nitride, or a combination thereof.

21. A three-dimensional integrated circuit (IC) (2000) comprising a plurality of semiconductor chips, each semiconductor chip (1000) comprising: a. a front-end-of-the-line (FOEL) layer (200) comprising a plurality of electronic components (250); and b. a back-end-of-the-line (BOEL) layer (100) comprising one or more thermally-emitting elements (150) configured to emit infrared radiation such that heat on the semiconductor chip (1000) is dispersed.

22. The three-dimensional IC (2000) of claim 21 , wherein the one or more thermally-emitting elements (150) are configured to emit the infrared radiation towards a heat sink (300).

23. The three-dimensional IC (2000) of claim 21 , wherein the plurality of electronic components (250) comprise transistors, p-n junctions, inductors, gates, or a combination thereof.

24. The three-dimensional IC (2000) of claim 21 , wherein each element of the one or more thermally-emitting elements (150) comprises one or more pairs of symmetrical flat protrusions disposed along a length of the element.

25. The three-dimensional IC (2000) of claim 21 , wherein each flat protrusion of the one or more pairs of symmetrical flat protrusions comprises a rectangular shape, a triangular shape, a rounded shape, or a combination thereof.

26. The three-dimensional IC (2000) of claim 21 , wherein the one or more thermally-emitting elements (150) comprise one or more wires connecting the plurality of electronic components (250).

27. A semiconductor chip (1000) comprising: a. a front-end-of-the-line (FOEL) layer (200) comprising a plurality of electronic components (250); and b. a back-end-of-the-line (BOEL) layer (100) comprising thermally-emitting wires (150) for passive radiative cooling.

28. An integrated circuit (IC) (2000) comprising: a. a plurality of electronic components (250); and b. thermally-emitting interconnects operatively connecting the electronic components (250), wherein the thermally-emitting interconnects are configured to dissipate excess heat as infrared radiation into a heat sink.

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