New multi-chip on-chip ultrasonic interconnection packaging method

Abstract

The present invention relates to the technical field of chip packaging. Disclosed is a new multi-chip on-chip ultrasonic interconnection packaging method, which solves the technical problems of low yield and high cost in multi-chip packaging. The key points of the technical solution thereof are as follows: by means of chip thinning, and the compatibility between wire bonding and flip chip packing processes and traditional processes, the use of a DRIE process is avoided, and the effective utilization rate of wafers is improved; and chip manufacturing is decoupled from multi-chip interconnection while multi-chip interconnection packaging is realized, thereby eliminating the necessity of wafer-level packaging, increasing the flexibility of chip manufacturing and testing, and thus greatly reducing packaging costs.

Description

A novel multi-chip on-chip ultrasonic interconnection packaging method TECHNICAL FIELD

[0001] The present application relates to the technical field of chip packaging, in particular to a novel multi-chip on-chip ultrasonic interconnection packaging method. BACKGROUND

[0002] The multi-chip on-chip ultrasonic interconnection technology can flexibly connect multiple ultrasonic chips, increase the angle range of ultrasonic beam coverage, and is widely applicable to wearable ultrasonic, interventional ultrasonic and other applications.

[0003] For example, in the interventional ultrasonic application, the length of the rigid portion at the end of the ultrasonic catheter affects the passability of the catheter. For example, the Eagle Eye product of Philips Company is a side-view IVUS phased array imaging catheter, the transducer and the chip are placed forward and backward along the catheter axis and connected by a metal wire, so that the length of the rigid portion at the end of the catheter cannot be further reduced, the passability of the catheter is poor, and the clinical use value is reduced. This problem can be solved by using the Transducer-on-CMOS structure, that is, the ultrasonic transducer is directly integrated onto the surface of the ASIC (Application Specific Integrated Circuit), forming a vertical stack structure of the transducer and the ASIC, thereby reducing the length of the rigid portion at the end of the catheter and increasing the passability of the interventional ultrasonic probe in the blood vessel.

[0004] For the multi-chip packaging of the above transducer, the Flex-to-Rigid (F2R, high-precision micro-assembly) process published by Philips Company uses wafer-level packaging, polyimide (PI) is spin-coated onto the entire wafer, and an electrical interconnection layer (RDL, Redistribution Layer) is made between the PI layers. This process arranges all the chips that need to be interconnected on the same wafer according to a certain pitch, and simultaneously realizes the thinning of the chips and the separation between the multi-chips by a Deep Reactive Ion Etching (DRIE) process on the back of the chips. However, arranging multiple chips that need to be interconnected on the same wafer according to the pitch required for bending is equivalent to regarding the multi-chip system as a large chip, which affects the final yield; at the same time, using the DRIE process to realize the thinning and separation of the chips will cause a large proportion of waste of the effective area of the wafer, leading to an increase in the cost of the probe.

[0005] SUMMARY

[0006] The present application provides a novel multi-chip on-chip ultrasonic interconnection packaging method, which aims to improve the yield of multi-chip packaging and reduce the cost.

[0007] The above technical purposes of the application are achieved by the following technical solutions.

[0008] A novel multi-chip on-chip ultrasonic interconnection packaging method, comprising:

[0009] Cutting and thinning a plurality of chips that need to be interconnected; wherein the chips comprise a vertical stacked structure formed by directly integrating an ultrasonic transducer to the surface of an ASIC;

[0010] Welding the thinned chips to a flexible substrate to obtain a multi-chip interconnection system; wherein the flexible substrate is provided with an insulating layer and an electrical interconnection layer;

[0011] Bending the multi-chip interconnection system with the flexible substrate to obtain an on-chip ultrasonic integrated module, completing packaging.

[0012] Further, the welding of the thinned chips to the flexible substrate comprises:

[0013] Welding the thinned chips to the flexible substrate through a wire bonding process; or

[0014] Welding the thinned chips to the flexible substrate through a flip chip process.

[0015] Further, when the thinned chips are welded to the flexible substrate through the flip chip process, it comprises:

[0016] Removing the insulating layer below each chip and mechanically interconnecting between the chips to form a first window, obtaining a multi-chip interconnection system; or

[0017] Only removing the insulating layer below each chip to form a plurality of second windows, obtaining a multi-chip interconnection system.

[0018] Further, when removing the insulating layer, the removal is performed by exposure and development.

[0019] Further, pads can be provided at any position of the chips and the flexible substrate.

[0020] Further, bending the multi-chip interconnection system with the flexible substrate comprises bending the multi-chip interconnection system with the flexible substrate in the direction of the radial inside of the chips to obtain an on-chip ultrasonic integrated module of a ring-shaped phased array.

[0021] An interventional device comprising an on-chip ultrasonic integrated module packaged by the novel multi-chip on-chip ultrasonic interconnection packaging method described in the application.

[0022] A wearable device comprising an on-chip ultrasonic integrated module packaged by the novel multi-chip on-chip ultrasonic interconnection packaging method described in the present application.

[0023] The present application has the beneficial effect that the novel multi-chip on-chip ultrasonic interconnection packaging method described in the present application decouples the manufacturing of chips and the interconnection of multi-chips, eliminates the necessity of wafer-level packaging, and increases the flexibility of chip manufacturing and testing; and since the thinning of chips, wire bonding and flip chip packaging processes are compatible with traditional processes, the use of DRIE process is avoided, the effective utilization of wafers is improved, the multi-chip interconnection packaging is realized, and the packaging cost is greatly reduced. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is a structural cross-sectional view of a ring-shaped phased array imaging system in an embodiment of the present application;

[0025] Figure 2 is a transducer interconnection schematic diagram when a wire bonding process is used in an embodiment of the present application;

[0026] Figure 3 is a transducer interconnection schematic diagram without an insulating layer between chips when a flip chip process is used in an embodiment of the present application;

[0027] Figure 4 is a transducer interconnection schematic diagram with an insulating layer between chips when a flip chip process is used in an embodiment of the present application;

[0028] Figure 5 is a schematic diagram of a multi-chip bent ring-shaped phased array imaging system in an embodiment of the present application.

[0029] In the figure: 1 - transducer; 2 - ASIC chip; 3 - flexible substrate; 31 - insulating layer; 32 - electrical interconnection layer; 33 - first window; 34 - second window; 4 - transducer-ASIC vertical stack structure; 5 - pad position. DETAILED DESCRIPTION

[0030] The technical solutions of the present application will be described in detail below with reference to the accompanying drawings.

[0031] The on-chip ultrasonic integrated module in an embodiment of the present application is shown in the ring-shaped phased array on-chip ultrasonic integrated module of Figures 1 and 5, which comprises a flexible substrate and a plurality of transducers and ASIC integrated vertical stack structures welded on the flexible substrate from the inside out. Each vertical stack structure is a separately cut and thinned chip, and the chips are connected through the RDL (electrical interconnection) layer on the flexible substrate.

[0032] The novel multi-chip on-chip ultrasonic interconnection packaging method described in the present application specifically comprises:

[0033] (1) Cutting and thinning a plurality of chips that need to be interconnected separately. The thickness of the chips is related to the diameter of the entire module after integration, and the diameter depends on the actual use scenario of the catheter (for example, the size of the blood vessel), which can have multiple options. In addition, the number of chips that can be interconnected is not limited to three as shown in Figures 2, 3, and 4, and the number of interconnected chips can be changed arbitrarily according to actual design needs.

[0034] (2) Welding the thinned chips to a flexible substrate to obtain a multi-chip interconnection system; wherein the flexible substrate is provided with an insulating layer and an electrical interconnection layer.

[0035] In the embodiments of the present application, the insulating layer on the flexible substrate can be, for example, a polyimide layer.

[0036] In the embodiments of the present application, the thinned chips are welded to the flexible substrate by a wire bonding packaging process or a flip chip packaging process, and the structure of the welding is shown in Figure 2.

[0037] Specifically, after welding the chips to the flexible substrate by the wire bonding packaging process, the flexible substrate is bent along the direction of the dashed line in Figure 2 to obtain an on-chip ultrasonic integrated module of a ring-shaped phased array as shown in Figure 5.

[0038] After welding by the flip chip packaging process, the insulating layer under the chips at the corresponding position of the flexible substrate needs to be removed, and the removal method is divided into two types. One is to remove the insulating layer under the chips and between the chips at the corresponding position of the flexible substrate to obtain a large first window as shown in Figure 3. The other is to remove only the insulating layer under the chips at the corresponding position of the flexible substrate while retaining the insulating layer between the chips at the corresponding position of the flexible substrate, thereby forming a second window between adjacent chips as shown in Figure 4.

[0039] The first window and the second window are both formed at the aperture position of the transducer, so that the ultrasonic transducer can effectively emit and receive ultrasonic waves in the radial direction of the catheter.

[0040] In the embodiments of the present application, for the wire bonding or flip chip interconnection scheme, the pad positions on the chips and the pad positions on the flexible substrate are not limited to the positions at both ends of the chips as shown in Figure 2, and the pad positions can be designed at any position according to actual needs.

[0041] (3) Bending the multi-chip interconnection system with the flexible substrate to obtain an on-chip ultrasonic integrated module, and completing packaging.

[0042] In the embodiments of the present application, the multi-chip interconnection system with a flexible substrate is bent in the direction of the inner side of the chip (the bending direction of the dashed line in FIGS. 2, 3 and 4), and a ring-shaped phased array on-chip ultrasonic integrated module can be obtained, as shown in FIG. 5.

[0043] The on-chip ultrasonic integrated module described above can be used in interventional devices, wearable devices and the like.

[0044] The above is an exemplary embodiment of the present application, and the protection scope of the present application is defined by the claims and their equivalents.

Claims

1. A novel multi-chip on-chip ultrasonic interconnect packaging method, characterized by, The application relates to a method for packaging a multi-chip on-chip ultrasound integrated module. The method comprises the following steps: cutting and thinning a plurality of chips which need to be interconnected, wherein the chips comprise a vertical stacked structure formed by directly integrating an ultrasonic transducer to an ASIC surface; welding the thinned chips to a flexible substrate to obtain a multi-chip interconnection system, wherein the flexible substrate is provided with an insulating layer and an electrical interconnection layer; 2. The packaging method of claim 1, wherein, bending the multi-chip interconnection system with the flexible substrate to obtain the on-chip ultrasound integrated module, and completing the packaging. The step of welding the thinned chips to the flexible substrate comprises: welding the thinned chips to the flexible substrate through a wire bonding process; or 3. The packaging method of claim 2, wherein, welding the thinned chips to the flexible substrate through a flip chip process. When the thinned chips are welded to the flexible substrate through the flip chip process, the method comprises the following steps: removing the insulating layer below each chip and mechanically interconnected between the chips to form a first window, and obtaining the multi-chip interconnection system; or 4. The packaging method of claim 3, wherein, only removing the insulating layer below each chip to form a plurality of second windows, and obtaining the multi-chip interconnection system.

5. The packaging method of claim 2, wherein, When the insulating layer is removed, the removal is performed in a manner of exposure and development.

6. The packaging method of claim 1, wherein, Pads can be arranged at any position of the chips and the flexible substrate.

7. An interventional device, characterized by The step of bending the multi-chip interconnection system with the flexible substrate comprises the following step:

8. A wearable device, comprising: bending the multi-chip interconnection system with the flexible substrate in a direction of a radial inner side of the chips to obtain the on-chip ultrasound integrated module of a ring-shaped phased array. The invasive device comprises the on-chip ultrasound integrated module packaged by the novel multi-chip on-chip ultrasound interconnection packaging method according to any one of claims 1 to 6. The wearable device comprises the on-chip ultrasound integrated module packaged by the novel multi-chip on-chip ultrasound interconnection packaging method according to any one of claims 1 to 6.

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