Surface-emitting semiconductor laser element and method for manufacturing same

Abstract

This method comprises: (a) forming a hole formation preparation layer on a substrate; (b) forming holes that are two-dimensionally arranged at respective lattice points in the hole formation preparation layer to form a hole formation layer; (c) performing first facet growth to close the opening surfaces of the holes; (d) performing second facet growth for a growth time of 40% or more of the growth time of the first facet growth to form a first embedding layer; (e) growing a second embedding layer for embedding and flattening the first embedding layer to form a guide layer including an air hole layer having air holes corresponding to the holes; and (f) performing crystal growth of a semiconductor layer including an active layer on the guide layer.

Description

Surface-emitting semiconductor laser element and its manufacturing method

[0001] The present invention relates to a surface-emitting semiconductor laser device having a photonic crystal and a method for manufacturing the same.

[0002] In recent years, development of a photonic-crystal surface-emitting laser (PCSEL) using a photonic crystal (PC) has been progressing.

[0003] For example, Patent Document 1 proposes a method of embedding holes with a hexagonal columnar structure with side surfaces consisting of {10-10} in a group III nitride semiconductor layer using facet selective growth in order to enhance the diffraction effect in the hole layer in a photonic crystal laser and obtain a high resonance effect. It describes how this method realizes a photonic crystal laser element equipped with a photonic crystal having a large filling factor and a large optical confinement coefficient.

[0004] Furthermore, Patent Document 2 proposes a method for forming a photonic crystal laser by growing a crystal to form a recess having a facet, closing the opening of the void, and then using mass transport to embed the void in a group III nitride semiconductor layer, thereby obtaining a photonic crystal laser with a large coupling coefficient for light waves propagating through the photonic crystal layer.

[0005] Japanese Patent No. 7101370 Japanese Patent Application Laid-Open No. 2020-38892

[0006] However, the inventors of the present application have found that when the voids are closed by facet growth and then filled by mass transport, minute voids remain in the buried layer, causing crystal dislocations, and that these crystal dislocations cause protrusions and the like in the active layer, resulting in degradation of device characteristics.

[0007] The present invention has been made based on this finding, and aims to provide a surface-emitting semiconductor laser element having a photonic crystal, which has a high-quality semiconductor layer in which abnormal growth of protrusions and the like is suppressed, and which has good element characteristics and an excellent element life, and a method for manufacturing the same.

[0008] A method for manufacturing a surface-emitting semiconductor laser device having a photonic crystal according to one embodiment of the present invention includes: (a) forming a hole formation preparation layer on a substrate; (b) forming holes in the hole formation preparation layer, arranged two-dimensionally at each of lattice points, to form a hole formation layer; (c) performing first facet growth to close the openings of the holes; (d) performing second facet growth for a growth time that is 40% or more of the growth time of the first facet growth to form a first burying layer; (e) growing a second burying layer that flatly buries the first burying layer, and forming a guide layer including a vacancy layer having vacancies corresponding to the holes; and (f) performing crystal growth of a semiconductor layer including an active layer on the guiding layer.

[0009] A surface-emitting semiconductor laser element having a photonic crystal according to another embodiment of the present invention is a surface-emitting laser element made of a nitride semiconductor, comprising: a substrate; a first semiconductor layer provided on the substrate; an active layer provided on the first semiconductor layer; and a second semiconductor layer provided on the active layer and having an opposite conductivity type to that of the first semiconductor layer, wherein the first semiconductor layer has a hole layer which is a photonic crystal layer having holes arranged with two-dimensional periodicity in a plane parallel to the active layer; and a burying layer, wherein the burying layer has a first burying layer which closes the holes and a second burying layer which flatly buries the first burying layer, and a rate of dislocations in the active layer is 100 ppm or less with respect to the number of holes.

[0010] It is a cross-sectional view schematically showing an example of the structure of the PCSEL element of the first embodiment. It is an enlarged cross-sectional view schematically showing the holes arranged in the hole layer shown in FIG. 1A. It is a plan view schematically showing the upper surface of the PCSEL element. It is a cross-sectional view schematically showing a cross-section in a plane parallel to the n-side guide layer. It is a plan view schematically showing the lower surface of the PCSEL element. It is a flowchart showing a method for manufacturing the PCSEL element of the first embodiment. It is a cross-sectional view schematically showing a cross-section of the n-side guide layer in the steps S0 to S3 of forming the embedded layer. It is a plan view schematically showing the main opening and the sub-opening of the resist, and the main hole and the sub-hole after etching. It is a view schematically showing a cross-section perpendicular to the central axis CX of the formed hole layer. It is a SEM image showing a cross-section perpendicular to the central axis CX of the formed hole layer. It is a SEM image of the cross-section of the growth layer after performing hole blocking growth (step S1). It is a schematic partial enlarged cross-sectional view showing an enlarged view of the region W shown in FIG. 8A. It is a SEM image of the cross-section of the n-side guide layer after performing planarization embedded growth (step S3). It is a schematic partial enlarged cross-sectional view showing an enlarged view of the same region W as the region shown in FIG. 8A. It is a fluorescence microscope image of the surface of an epiwafer in which a hole layer is formed in a partial region of the n-side guide layer without performing void filling growth and crystal growth is performed up to the p-contact layer. It is a fluorescence microscope image of the surface of an epiwafer in which a hole layer is formed in a partial region of the n-side guide layer without performing void filling growth and crystal growth is performed up to the active layer. It is an AFM image of the surface of the active layer shown in FIG. 10B. It is an enlarged AFM image of a partial region E of the image shown in FIG. 11A. It is a surface roughness profile along the line F-F in FIG. 11B. It is a view showing a cross-section of the semiconductor structure layer and schematically showing dislocation lines and protrusions. It is a graph plotting the generation rate RD of dislocations DL with respect to the growth time of hole blocking growth (step S1) and void filling growth (step S2). It is a fluorescence microscope image of the surface of an epiwafer when void filling growth (step S2) is performed with a growth time TP = 7 min. It is a fluorescence microscope image of the surface of an epiwafer when void filling growth (step S2) is performed with a growth time TP = 12 min. It is an AFM image of the surface of the active layer when void filling growth is performed with a growth time TP = 12 min. It is an enlarged AFM image of a partial region G of the image shown in FIG. 15A. It is a surface roughness profile along the line H-H in FIG. 11B.1 is a graph showing the optical output maintenance rate when a PCSEL element is continuously driven, and FIG. 2 is a graph plotting the element lifetime against the dislocation occurrence rate RD.

[0011] In the following, preferred embodiments of the present invention will be described, which may be modified or combined as appropriate. In the following description and accompanying drawings, substantially the same or equivalent parts are designated by the same reference numerals.

[0012] [First Embodiment] 1. Structure of Photonic Crystal Surface-Emitting Laser Element A photonic crystal surface-emitting laser element (PCSEL element) is a surface-emitting semiconductor laser element that has a resonator layer in a direction parallel to semiconductor light-emitting structure layers (n-side guide layer, light-emitting layer, p-side guide layer) that constitute a light-emitting element, and emits coherent light in a direction perpendicular to the resonator layer.

[0013] That is, in a PCSEL element, light waves propagating in a plane parallel to the air hole layer (photonic crystal layer) are diffracted by the diffraction effect of the photonic crystal to form a two-dimensional resonance mode, and are also diffracted in a direction perpendicular to the parallel plane. That is, in a PCSEL element, the light extraction direction is perpendicular to the resonance direction (in the plane parallel to the air hole layer).

[0014] Fig. 1A is a cross-sectional view schematically illustrating an example of the structure of a photonic crystal surface-emitting laser device (PCSEL device) 10 according to an embodiment of the present invention, and Fig. 1B is an enlarged cross-sectional view schematically illustrating an air hole layer 14P and air holes 14K arranged in the air hole layer 14P in Fig. 1A.

[0015] 2A is a plan view schematically showing the upper surface of the PCSEL device 10. Also, Fig. 2B is a cross-sectional view schematically showing a cross section of the hole layer 14P in a plane parallel to the n-side guide layer 14, and Fig. 2C is a plan view schematically showing the lower surface of the PCSEL device 10. As shown in Fig. 1A, a semiconductor structure layer 11 is formed on a light-transmitting device substrate 12. The semiconductor layers are stacked perpendicular to the central axis CX of the semiconductor structure layer 11.

[0016] The semiconductor structure layer 11 is made of a hexagonal nitride semiconductor, for example, a GaN-based semiconductor, in this embodiment.

[0017] More specifically, a semiconductor structure layer 11 consisting of a plurality of semiconductor layers is formed on an element substrate 12, in this order: an n-clad layer (first clad layer of a first conductivity type) 13; an n-side guide layer (first guide layer) 14 which is a guide layer provided on the n-side; a light distribution adjustment layer 23; an active layer (ACT) 15; a p-side guide layer (second guide layer) 16 which is a guide layer provided on the p-side; an electron barrier layer (EBL: Electron Blocking Layer) 17; a p-clad layer (second clad layer of a second conductivity type) 18; and a p-contact layer 19.

[0018] Although the case where the first conductivity type is n-type and the second conductivity type opposite to the first conductivity type is p-type will be described, the first conductivity type and the second conductivity type may be p-type and n-type, respectively.

[0019] The element substrate 12 is a hexagonal GaN single crystal substrate that has a high transmittance for light emitted from the active layer 15. More specifically, the element substrate 12 is a hexagonal GaN single crystal substrate whose main surface (crystal growth surface) is a +c plane, which is a {0001} plane in which Ga atoms are arranged on the outermost surface. The back surface (light emission surface) is a -c plane, which is a (000-1) plane in which N atoms are arranged on the outermost surface. The -c plane is suitable as a light emission surface because it is resistant to oxidation and the like.

[0020] Although the element substrate 12 is not limited to this, a so-called just substrate, or, for example, a substrate whose main surface is offset by approximately 1° in the m-axis direction is preferred. For example, a substrate offset by approximately 0.3 to 0.7° in the m-axis direction can achieve mirror-finish growth under a wide range of growth conditions. The back surface of the substrate opposite the main surface is the light-emitting surface, and is the "-c" plane, which is the (000-1) plane with N atoms arranged on the outermost surface. The -c plane is resistant to oxidation and is therefore suitable as a light-extraction surface.

[0021] The composition, thickness, and other configurations of each semiconductor layer will be explained below, but these are merely examples and can be modified as appropriate.

[0022] The n-clad layer 13 is, for example, n-Al having an aluminum (Al) composition of 4%. ０．０４ Ga ０．９６ The Al composition ratio is set so that the refractive index is smaller than that of the layer adjacent to the active layer 15 (i.e., the n-side guide layer 14).

[0023] The n-side guide layer 14 is composed of a lower guide layer 14A, an air-hole layer 14P (or PC layer) which is a photonic crystal layer, and a buried layer 14B. As shown in FIG. 1B, the air-hole layer 14P has a thickness d ＰＣ The buried layer 14B has a thickness D. For example, the hole layer 14P has a thickness d ＰＣ is 40 to 180 nm.

[0024] In this specification, the air hole layer 14P refers to the layer portion of the n-side guide layer 14 that extends from the upper end to the lower end of the air holes (see FIG. 1B). ＰＣ is equal to the height of the hole.

[0025] The lower guide layer 14A is made of n-GaN and has a thickness of 100 to 400 nm, for example. The air hole layer 14P is made of n-GaN and has a thickness (or the height of the air holes 14K) of 40 to 180 nm.

[0026] The buried layer 14B is made of n-GaN or n-InGaN, or undoped GaN or undoped InGaN. Alternatively, it may be a layer in which these semiconductor layers are stacked. The layer thickness D of the buried layer 14B is, for example, 30 to 150 nm. The buried layer 14B is made of a first buried layer 14B1 and a second buried layer 14B2. In other words, the buried layer 14B is a stacked buried layer in which the second buried layer 14B2 is stacked on the first buried layer 14B1.

[0027] A light-distribution-adjustment layer 23, which is a hetero semiconductor layer (a heterogeneous semiconductor layer) having a different crystal composition from that of the second buried layer 14B2 and forming a heterostructure with the second buried layer 14B2, is provided on the second buried layer 14B2, which is a surface layer of the buried layer 14B. The light-distribution-adjustment layer 23 may be a semiconductor layer of the same conductivity type as that of the second buried layer 14B2, or at least one of the layers may be an i-layer (intrinsic semiconductor layer).

[0028] The light distribution adjustment layer 23 is provided between the buried layer 14B and the active layer 15, and has the function of adjusting the coupling efficiency between the light propagating in the hole layer 14P and the hole layer 14P acting as a resonator.

[0029] In this embodiment, the light distribution adjustment layer 23 is made of undoped In. ０．０３ Ga ０．９７ The light distribution adjustment layer 23 is an N layer, and has a thickness of, for example, 50 nm. The thickness of the light distribution adjustment layer 23 is selected depending on the composition or refractive index of the light distribution adjustment layer 23 and the adjustment of the coupling efficiency.

[0030] The n-side semiconductor layer including the n-side guide layer 14 and the light distribution-adjusting layer 23 is also referred to as a first semiconductor layer, but the light distribution-adjusting layer 23 does not necessarily have to be provided.

[0031] The active layer 15, which is a light-emitting layer, is a multiple quantum well (MQW) layer having, for example, two quantum well layers. The barrier layer and quantum well layer of the MQW are made of GaN (layer thickness 6.0 nm) and InGaN (layer thickness 4.0 nm), respectively. The central emission wavelength of the active layer 15 is 440 nm.

[0032] The active layer 15 is preferably located within 180 nm of the air hole layer 14P (i.e., within the period PK of the air holes), in which case a high resonance effect can be obtained by the air hole layer 14P.

[0033] The p-side guide layer 16 is an undoped In ０．０２ Ga ０．９８ It consists of a p-side guide layer (1) 16A which is an N layer (layer thickness 70 nm) and a p-side guide layer (2) 16B which is an undoped GaN layer (layer thickness 180 nm).

[0034] The p-side guide layer 16 is an undoped layer in consideration of light absorption by a dopant (Mg: magnesium, etc.), but may be doped to obtain good electrical conductivity. In addition, the In composition and layer thickness of the p-side guide layer (1) 16A can be appropriately selected to adjust the electric field distribution in the oscillation operation mode.

[0035] The electron barrier layer (EBL) 17 is a p-type Al doped with magnesium (Mg). ０．２ Ga ０．８The N layer has a thickness of, for example, 15 nm.

[0036] The p-cladding layer 18 is made of Mg-doped p-Al ０．０６ Ga ０．９４ The Al composition of the p-cladding layer 18 is preferably selected so that the refractive index is smaller than that of the p-side guide layer 16.

[0037] The p-contact layer 19 is an Mg-doped p-GaN layer having a thickness of, for example, 20 nm. The carrier density of the p-contact layer 19 is set to a concentration that allows for ohmic contact with the transparent electrode 29, which is a transparent conductive layer provided on the surface of the p-contact layer 19. Instead of p-type GaN, p-type or undoped InGaN may be used. Alternatively, a layer in which a GaN layer and an InGaN layer are stacked may be used.

[0038] The layer consisting of the p-side guide layer 16, the electron barrier layer 17, the p-cladding layer 18 and the p-contact layer 19 is also referred to as a second semiconductor layer.

[0039] In this specification, "n-side" and "p-side" do not necessarily mean having n-type or p-type. For example, the n-side guide layer means a guide layer provided on the n-side of the active layer, and may be an undoped layer (or i-layer). Furthermore, the n-clad layer 13 may be composed of multiple layers rather than a single layer, and in that case, not all layers need to be n-layers (n-doped layers), and may include an undoped layer (i-layer). The same applies to the p-side guide layer 16 and the p-clad layer 18.

[0040] Furthermore, it is not necessary to provide all of the semiconductor layers described above, and it is sufficient to have a configuration having a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and an active layer (light-emitting layer) sandwiched between these layers.

[0041] Furthermore, in this embodiment, the case where the vacancy layer 14P is provided in the first semiconductor layer (n-type semiconductor layer) has been described, but the vacancy layer may be provided in the second semiconductor layer (p-type semiconductor layer).

[0042] On the p-contact layer 19, a p-electrode 20B (second electrode) is provided, which is composed of a conductive translucent electrode 29 in ohmic contact with the p-contact layer 19 and a metal layer 28 formed on the translucent electrode 29. The metal layer 28 is formed by laminating a silver (Ag) layer and a gold (Au) layer in this order. That is, the p-electrode 20B functions as a light-reflecting layer, and the interface between the translucent electrode 29 and the Ag layer of the metal layer 28 is a reflective surface SR. The reflective surface SR is provided parallel to the hole layer 14P.

[0043] The p-electrode 20B has a circular shape with a diameter RA centered on the central axis CX of the void formation region 14R. Specifically, the translucent electrode 29 has a diameter RA of, for example, 300 μm in top view (i.e., when viewed from a direction perpendicular to the semiconductor structure layer 11).

[0044] The p-electrode 20B may also be made of Pd, Al, an Al alloy, etc. A pad electrode or the like may be provided on the p-electrode 20B.

[0045] The transparent electrode 29 is formed of a transparent conductor, such as indium tin oxide (ITO). Note that the transparent electrode 29 is not limited to ITO, and other transparent conductors such as zinc tin oxide (ZTO), GZO (ZnO:Ga), and AZO (ZnO:Al) can be used.

[0046] The side and top surfaces of the semiconductor structure layer 11 and the side surfaces of the p-electrode 20B are made of SiO ２ The insulating film 21 is formed so as to overlap the p-electrode 20B and cover the edge of the upper surface of the p-electrode 20B.

[0047] The insulating film 21 also functions as a protective film, protecting the aluminum (Al)-containing crystal layer that constitutes the PCSEL element 10 from corrosive gases and the like. It also prevents short circuits caused by deposits or solder creeping up during mounting, contributing to improved reliability and yield. The insulating film 21 is made of SiO ２ Not limited to ZrO ２ , HfO ２ , TiO ２ , Al ２ O ３ , SiNx, etc. can be selected.

[0048] A circular n-electrode 20A (first electrode) (see FIG. 2C) is formed on the back surface of the element substrate 12. An anti-reflection (AR) coating layer 27 is formed on the inner surface of the n-electrode 20A.

[0049] The n-electrode 20A is made of Ti / Au and is in ohmic contact with the element substrate 12. In addition to Ti / Au, the electrode material can be selected from Ti / Al, Ti / Rh, Ti / Al / Pt / Au, Ti / Pt / Au, and the like.

[0050] The light emitted from the active layer 15 is diffracted by the air hole layer 14P (PC layer). The light is diffracted by the air hole layer 14P (diffraction surface WS), and the light is directly emitted from the air hole layer 14P (direct diffracted light Ld: first diffracted light). The light is also diffracted by the air hole layer 14P and reflected by the reflection surface SR (reflected diffracted light Lr: second diffracted light). These two light beams are then emitted to the outside from a light emission region 20L ( FIG. 2C ) on the rear surface (emission surface) 12R of the element substrate 12.

[0051] 2B, in the hole layer 14P, the holes 14K are periodically arranged within, for example, a rectangular hole-forming region 14R. As shown in FIG. 2C, the anode region RA is formed so as to be included within the hole-forming region 14R.

[0052] The n-electrode 20A is provided as a ring-shaped electrode outside the p-electrode 20B so as not to overlap the p-electrode 20B when viewed from a direction perpendicular to the hole layer 14P. The region inside the n-electrode 20A is the light emission region 20L. A bonding pad 20C is provided, which is electrically connected to the n-electrode 20A and for connecting a wire for power supply from an external source.

[0053] 2. Manufacturing Method of Air Hole Layer and Recrystallization Growth The following describes the manufacturing process and recrystallization growth of the air hole layer. Metalorganic Vapor Phase Epitaxy (MOVPE) was used as the crystal growth method. Note that the following describes the formation method for the air hole layer 14P, taking as an example a case where the air hole layer 14P is a double-lattice photonic crystal layer; however, single-lattice photonic crystal layers and multiple-lattice photonic crystal layers can also be formed in a similar manner. (a) Manufacturing Flow FIG. 3 is a flowchart showing the manufacturing method of the PCSEL device 10. The following describes in detail the process of manufacturing the PCSEL device 10, with reference to FIG. 3 , by forming air holes in the air hole layer by filling and growing multiple recesses (holes), followed by growing the active layer and p-side guide layer.

[0054] 4A and 4B are cross-sectional views schematically showing the cross section of the n-side guide layer 14 in steps S0 to S3 of forming the burying layer 14B. For ease of explanation and understanding, FIG. 4 illustrates a case where the air-hole layer 14P is a single-lattice photonic crystal layer, but a multi-lattice photonic crystal layer can also be formed in the same manner. The burying layer 14B (laminated burying layer) formed by recrystallization growth on the air-holes will be described in detail below with reference to FIGS. 3 and 4A and 4B.

[0055] (Step S0) Hole Formation Preparation Layer First, an n-type Al layer having an Al composition of 4% is formed on the element substrate 12 as the n-clad layer 13. ０．０４ Ga ０．９６ An N layer was grown on the n-cladding layer 13. Subsequently, a hole formation preparation layer 14E, which is an n-type GaN layer, was grown on the n-cladding layer 13. This hole formation preparation layer 14E is a preparation layer for forming the lower guide layer 14A and the hole layer 14P containing holes. The hole formation preparation layer 14E has a surface (upper surface) consisting of a flat (0001) plane.

[0056] After forming the hole formation preparation layer 14E, the substrate was removed from the chamber of the MOVPE apparatus, and fine recesses (holes) were formed on the surface of the growth layer. Subsequently, after obtaining a clean surface by cleaning, a silicon nitride film (SiN ｘA resist for electron beam lithography was applied thereon, and the substrate was placed in an electron beam lithography system to pattern a two-dimensional periodic structure.

[0057] 5 is a plan view schematically showing the main opening K1 and sub-opening K2 in the resist, and the main hole 14H1 and sub-hole 14H2 after etching. As shown in FIG. 5, a pattern was performed in which pairs of openings, each consisting of an oval-shaped main opening K1 and a sub-opening K2 smaller than the main opening K1, were two-dimensionally arranged in the plane of the resist in a square lattice pattern with a period PK. Note that for clarity of the drawing, the openings are shown hatched.

[0058] More specifically, the main apertures K1 are arranged two-dimensionally with their centers of gravity CD1 in two mutually orthogonal directions (x direction and y direction) on lattice points of a square lattice with a period P K. Similarly, the sub-apertures K2 are arranged two-dimensionally with their centers of gravity CD2 in the x direction and y direction on lattice points of a square lattice with a period P K.

[0059] The major axes of the main aperture K1 and the sub aperture K2 are parallel to the <11-20> direction of the crystal orientation, and the minor axes of the main aperture K1 and the sub aperture K2 are parallel to the <1-100> direction.

[0060] The center of gravity CD2 of the sub-opening K2 is spaced apart from the center of gravity CD1 of the main opening K1 by Δx and Δy. Here, Δx=Δy. That is, the center of gravity CD2 of the sub-opening K2 is spaced apart from the center of gravity CD1 of the main opening K1 in the <1-100> direction.

[0061] The distance Δx, Δy between the centers of gravity of the main opening K1 and the sub-opening K2 was set to Δx=Δy=0.46PK. After the patterned resist was developed, SiN ｘ The film was selectively dry-etched to form main openings K1 and sub-openings K2 arranged two-dimensionally on the lattice points of a square lattice with a period PK. ｘ formed to penetrate the membrane.

[0062] The period (hole spacing) PK was set to PK=177.5 nm in order to set the oscillation wavelength (λ) to 438 nm.

[0063] Subsequently, the resist is removed, and the patterned SiN ｘ Using the film as a hard mask, recesses (holes) were formed in the GaN surface. The GaN was dry-etched in the depth direction using a chlorine-based gas and argon gas in an ICP-RIE apparatus, thereby forming a main hole 14H1 and a sub-hole 14H2, which were oblong cylindrical recesses dug perpendicular to the GaN surface.

[0064] The recesses dug in the surface portion of the hole formation preparation layer 14E (GaN) by the above etching are simply referred to as holes to distinguish them from the air holes in the void layer 14P. Furthermore, when there is no particular distinction between the main holes 14H1 and the sub-holes 14H2, they may be referred to as holes 14H. The shape of the holes 14H is not limited to an elongated cylindrical shape, and may be cylindrical, polygonal, or the like.

[0065] As a result of the above, holes 14H were formed in the hole formation preparation layer 14E, and a hole formation layer 14J was formed (FIG. 4, step S0).

[0066] (Step S1) Vacancy Closure Growth (First Facet Growth) First, the substrate (FIG. 4, SO) with the hole 14H formed therein was cleaned and then re-inserted into the reactor of the MOVPE apparatus, where recrystallization growth was performed. Specifically, ammonia (NH), a group V source, and trimethylgallium (TMG), a group III source, were supplied, and buried growth (GaN growth) was performed by facet growth or growth dominated by facet growth (facet growth mode). That is, the opening, which is the top surface of the hole 14H, was closed, and the vacancies (air-holes) were closed (vacancy closure growth).

[0067] Specifically, the burying growth was performed at a first growth temperature (920° C.) at which the shape of the hole 14H was transformed into a shape composed of thermally stable surfaces by a thermal effect. The void filling growth was performed for 18 minutes (min).

[0068] More specifically, in this first growth temperature region, N atoms are attached to the outermost surface of the growth substrate, so that N-polar faces are selectively grown. Therefore, as shown in Figure 4, crystals whose surfaces have {1-101} facets are selectively grown. In Figure 4, the hole formation layer 14J (GaN layer) before the formation of the burying layer 14B is indicated by a dashed line.

[0069] More specifically, the lower ends (lower sides) of the opposing {1-101} facets butted against each other due to the void closing growth (first facet growth), thereby closing the opening of hole 14H. Hole 14H was closed by this void closing growth, and hollow hole 14K was formed.

[0070] (Step S2) Gap-filling growth (second facet growth) Following step S1, gap-filling growth was performed under the same growth conditions as step S1. That is, based on the finding that gaps MP are generated at the lower ends of opposing facets that butt against each other, gap-filling growth (facet growth) was performed in which the gaps MP were filled with a semiconductor (GaN) after the voids were closed. Two types of growth wafers were produced using gap-filling growth times of 7 minutes and 12 minutes.

[0071] The gap-filling growth progresses the growth of the {1-101} facet, and the gaps MP at the lower ends of the facets formed when the {1-101} facets collide are filled with GaN, forming gap-filling portions EB. At this time, the crystal growth in steps S1 and S2 is performed under conditions that selectively grow the {1-101} facet, so the gaps MP gradually shrink and disappear, forming gap-filling portions EB. The gap-filling portions EB extend in a direction perpendicular to the void layer 14P, and their diameter is on the order of several nanometers, approximately one-tenth or less of the voids 14K. The first burying growth is performed by the above-described void-closing growth (step S1) and gap-filling growth (step S2), forming a first burying layer 14B1.

[0072] (Step S3) Planarization Buried Growth (Second Buried Growth) After filling the gap MP in the hole 14H, a second buried layer 14B2 with a thickness D2 of 50 nm was grown. The second buried layer 14B2 was grown by raising the substrate temperature (growth temperature) to 1050°C (second growth temperature) and then supplying triethylgallium (TEG) and NH3. The second growth temperature was higher than the first growth temperature. However, the temperature relationship between the second growth temperature and the first growth temperature may be reversed as long as the growth surface of the second buried layer 14B2 is grown to a (0001) plane. As shown in FIG. 4, mass transport was generated by thermal effects, resulting in planarization buried growth (second buried growth), and the second buried layer 14B2 with a flat (0001) plane appeared on its surface. In this way, under growth conditions in which planarization and burying are achieved by mass transport (mass transport mode), a buried layer 14B in which the gaps MP are filled with a semiconductor (GaN) is formed. The formation of the buried layer 14B completes the formation of the n-side guide layer 14.

[0073] For ease of explanation, the layer extending from the upper surface of the hole layer 14P (the surface closer to the active layer 15) to the upper surface 14JS of the hole-forming layer 14J (including a portion of the hole-forming layer 14J) is referred to as the first buried layer 14B1, and the layer extending from the upper surface 14JS of the hole-forming layer 14J to the flat surface formed by the second buried growth is referred to as the second buried layer 14B2 (see FIG. 4, S3). The entire semiconductor layer extending from the upper surface of the hole layer 14P to the upper surface of the second buried layer 14B2 (including a portion of the hole-forming layer 14J) is referred to as the buried layer 14B. The thickness of the first buried layer 14B1 is defined as D1, and the thickness of the second buried layer 14B2 is defined as D2. Therefore, the thickness of the buried layer 14B is given by D = D1 + D2. The longer the gap-filling growth time, the thicker the buried layer 14B becomes, but the desired thickness can be achieved by etching with H annealing. This shortens the distance between the active layer and the voids, thereby increasing the optical coupling efficiency.

[0074] In this specification, the “top surface” of each semiconductor layer of the n-side guide layer (first guide layer) 14 refers to the surface on the side closer to the active layer 15 .

[0075] In this embodiment, GaN is used for the second burying growth. The second burying layer 14B2 also functions as a light distribution adjusting layer for adjusting the coupling efficiency (light field) between light and the hole layer 14P.

[0076] In this embodiment, undoped GaN is used for the first buried growth and the second buried growth. However, the first buried growth and the second buried growth are not limited to GaN, and n-GaN, n-InGaN, undoped GaN, undoped InGaN, or a combination of these semiconductors can also be used.

[0077] (Step S4) Growth of Active Layer and P-Type Semiconductor Layer Subsequently, in the reactor, semiconductor layers including the active layer 15 were further grown on the n-side guide layer 14. Specifically, crystal growth of the layers above the light distribution adjustment layer 23 was performed.

[0078] More specifically, the light distribution adjustment layer 23 is grown on the second buried layer 14B2. Specifically, the light distribution adjustment layer 23 is made of undoped In ０．０３ Ga ０．９７ It is an N layer, and is a semiconductor layer (heterogeneous semiconductor layer) having a different crystal composition from the buried layer 14B (GaN layer).

[0079] Next, the active layer 15, p-side guide layer 16, electron barrier layer 17, p-cladding layer 18, and p-contact layer 19 were sequentially grown on the light distribution adjustment layer 23. In this manner, an epitaxial wafer of the PCSEL device 10 was fabricated. A process for forming a p-electrode 20B, an n-electrode 20A, and an insulating film 21 was carried out on the epitaxial wafer, and a plurality of PCSEL devices 10 were manufactured by separating the epitaxial wafer into individual devices.

[0080] (b) Hole Layer The above-described filling process formed a hole layer 14P with a double lattice structure in which holes 14K, each consisting of a pair of a main hole 14K1 and a subhole 14K2, were two-dimensionally arranged at each square lattice point. Here, the subholes 14K2 have a smaller hole diameter and height than the main holes 14K1. In the present invention, the upper surfaces of the holes in the hole layer 14P with a multi-lattice structure refer to the upper surface of the main holes 14K1 or the subholes 14K2 that is closer to the upper layer (active layer) (i.e., the hole having a shallower upper surface).

[0081] The hole layer 14P may have a single lattice structure in which holes of the same size are two-dimensionally arranged at each square lattice point. In the following description, when there is no need to distinguish between the main holes 14K1 and the sub-holes 14K2, they will be referred to as holes 14K.

[0082] 6 is a diagram showing a cross section of the formed void layer 14P perpendicular to the central axis CX. When the holes 14H are filled with the group III nitride, the shape of the holes 14H is deformed by a thermal effect into a shape formed by thermally stable surfaces, and voids 14K are formed.

[0083] That is, in the +c-plane substrate, the inner side surface of the hole 14H changes shape to the (1-100) plane (i.e., m-plane), that is, changes shape from an oval cylindrical shape to an oval hexagonal prism-shaped hole 14K whose side surface is formed by the m-plane.

[0084] 7 is an SEM image showing a cross section perpendicular to the central axis CX of the formed pore layer 14P. The formed primary pores 14K1 had a long hexagonal prism shape with a major axis of 75.2 nm and a minor axis of 45.0 nm, and a major axis / minor axis ratio of 1.67. The secondary pores 14K2 had a long hexagonal prism shape with a major axis of 45.8 nm and a minor axis of 39.2 nm, and a major axis / minor axis ratio of 1.17, and were closer to a regular hexagonal prism than the primary pores 14K1.

[0085] Furthermore, it was confirmed that the distances Δx and Δy between the centers of gravity of the main void 14K1 and the subvoid 14K2 were 65.4 nm (Δx = Δy = 0.46PK), which was unchanged from before filling. It was also confirmed that the major axes of the main void 14K1 and the subvoid 14K2 were parallel to the <11-20> axis (i.e., the a-axis).

[0086] Furthermore, the void filling factors FF1 and FF2 of the main voids 14K1 and the sub-voids 14K2 were calculated to be 10.5% and 5.1%, respectively. Here, the void filling factor is the ratio of the area occupied by each void per unit area in a two-dimensional regular array. Specifically, when the areas of the main voids 14K1 and the sub-voids 14K2 in the void layer 14P are A1 and A2, respectively, the void filling factors FF1 and FF2 of the main voids 14K1 and the sub-voids 14K2 are given by the following equations:

[0087] FF1 = A1 / PK ２ , FF2=A2 / PK ２ As described above, in this embodiment, the upper surfaces of the holes 14H are closed by the void blocking growth (step S1) and the void filling growth (step S2), and then filled by the planarization growth (step S3), thereby completing the formation of the n-side guide layer 14 including the void layer 14P.

[0088] 3. Protrusions and Dislocations in Buried Growth (without Void-Filling Growth) (1) Protrusions on the Growth Surface Figure 8A is a cross-sectional SEM image of the growth layer after void-filling growth (step S1). The cross section is taken along line A-A in Figure 7. Figure 8B is a schematic partially enlarged cross-sectional view of a region W including void 14K and the {1-101} facet shown in Figure 8A.

[0089] In void-closing growth, the {1-101} facets are selectively grown until the opposing facets come into contact with each other, resulting in closed voids 14K. However, as shown in Figures 8A and 8B, it was discovered that even after the voids 14K are closed by the {1-101} facets, minute gaps MP remain in the region above the voids 14K where the facets come into contact.

[0090] 9A is a cross-sectional SEM image of the n-side guide layer 14 after planarization burying growth (step S3, second burying growth) is performed without gap-filling growth (step S2, second facet growth) following the steps shown in FIGS. 8A and 8B, and FIG. 9B is a schematic partially enlarged cross-sectional view showing an enlarged portion of the same region W as shown in FIG. 8A.

[0091] Even after planarization and burying growth by mass transport was performed, it was confirmed that minute voids MP remained above the voids 14K, although their size had decreased. In other words, it was found that the voids were not closed by mass transport due to the movement of surface atoms.

[0092] 10A is a fluorescence microscope image of the surface of an epitaxial wafer in which the gap filling growth (step S2) has not been performed, a vacancy layer 14P (main vacancies 14K1 and sub-vacancies 14K2) has been formed in a partial region of the n-side guide layer 14, and crystal growth has been performed up to the p-contact layer 19. Region A is a region in which the vacancy layer 14P has been formed, and region B is a region in which the vacancy layer 14P has not been formed.

[0093] In a fluorescent microscope image of the surface of the p-contact layer 19, a protruding pattern was observed in region A where the void layer 14P was formed, but no protruding pattern was observed in region B. In a metallurgical microscope image (not shown), no protruding patterns were observed in region A or region B.

[0094] 10B is a fluorescence microscope image of the surface of an epitaxial wafer in which the gap-filling growth (step S2) is not performed, and a vacancy layer 14P (main vacancies 14K1 and sub-vacancies 14K2) is formed in a partial region of the n-side guide layer 14, and crystal growth has been performed up to the active layer 15 (ACT). Region a is the region in which the vacancy layer 14P is formed, and region b is the region in which the vacancy layer 14P is not formed.

[0095] In a fluorescent microscope image of the surface of the active layer 15, a protruding pattern was observed in the region a where the void layer 14P was formed, but no protruding pattern was observed in the region b. This indicates that such protrusions were already formed at the stage when the active layer 15 was grown.

[0096] Fig. 11A is an atomic force microscope (AFM) image of the surface of the active layer 15 shown in Fig. 10B. Fig. 11B is an enlarged AFM image of a partial region E of the image shown in Fig. 11A, and Fig. 11C is a surface roughness (RAW) profile along line F-F in Fig. 11B.

[0097] As shown in the AFM image and the surface roughness profile, it was found that protrusions with a height of about 5 nm were formed on the active layer 15, and it was confirmed that spiral growth occurred when growing the active layer 15. Therefore, from the above-mentioned fluorescence microscope image, AFM image, and surface roughness profile, it was considered that such protrusions were caused by the filling of the voids 14K.

[0098] In GaN-based materials, when screw dislocations are present, spiral growth occurs around the screw dislocations. Spiral growth is particularly likely to occur under growth conditions that require low-temperature growth, such as for InGaN, i.e., growth conditions that result in weak migration.

[0099] (2) Dislocations From the above, it is believed that in the conventional technology, dislocations caused by voids MP generated during the void-filling growth process existed in the PCSEL element. Specifically, it is believed that the voids MP generated during the void-filling growth process remained above the voids 14K, and the voids MP became the starting points for dislocations, causing spiral growth. Figure 12 is a diagram showing a cross section of the semiconductor structure layer 11, and is a schematic diagram showing dislocation lines and protrusions PJ of dislocations DL caused by the void 14K filling growth.

[0100] 12, since the protrusions PJ in the active layer 15 resulting from the embedding growth of the vacancies 14K are considered to occur in correspondence with the dislocations DL, the number of the protrusions PJ is equal to the number of the dislocations DL. When the unit area of ​​the plane parallel to the vacancy layer 14P is used, NJ is the number of the protrusions PJ per unit area, and NH is the number of the vacancies per unit area, the ratio of the protrusions PJ to the number of the vacancies 14K (the occurrence rate of the dislocations DL) RD is given by the following equation:

[0101] RD = (number of protrusions per unit area) / (number of vacancies per unit area) = NJ / NH Formula (1) Furthermore, using the vacancy period PK, the dislocation occurrence rate RD is given by the following formula: RD = (number of protrusions per unit area) / (1 / PK ２) Equation (2) In the case of a double lattice structure in which multiple voids exist within one period of the photonic crystal, the distance between the voids is close, so the main void 14K1 and the sub-void 14K2 may be treated as a single void. That is, since the multiple voids are close to each other, even if dislocations occur, they will be grouped together, or multiple dislocations will form a single protrusion. In the case of a single lattice photonic crystal layer, there is no distinction between main voids and sub-voids, so the number is simply based on the number of voids.

[0102] 4. Reduction of Dislocations by Gap-Filling Growth (1) Reduction of Dislocations and Protrusions FIG. 13 is a graph plotting the occurrence rate RD (ppm) of dislocations DL against the growth time of void-clotting growth (step S1) and gap-filling growth (step S2).

[0103] More specifically, as described above, the occurrence rate RD is plotted when the void-filling growth was performed with a growth time TF of 18 min, and when the void-filling growth was performed following the void-filling growth with a growth time TP of 7 min (total time with TF: 25 min) and TP of 12 min (total time with TF: 30 min). The occurrence rate RD (ppm) of dislocation DL was calculated using formula (1) from the number of protrusions PJ observed by observing the surface of the epi-wafer having the semiconductor structure layer 11 thus formed with a fluorescence microscope.

[0104] It was confirmed that by performing the void closing growth for a growth time TF of 18 min, the lower ends (lower sides) of the opposing {1-101} facets met each other, and the upper surface of the hole 14H was closed.

[0105] The occurrence rate when only void-filling growth was performed, i.e., when the gap-filling growth time TP was 0 min, was RD = 318 ppm. When void-filling growth was performed after void-filling growth for a growth time TP = 7 min, the occurrence rate RD = 97 ppm, which was reduced to less than one-third. Furthermore, when void-filling growth was performed for a growth time TP = 12 min, the occurrence rate RD = 0, and the occurrence rate RD was reduced to the extent that no protrusions PJ were observed.

[0106] 14A and 14B are fluorescence microscope images of the surface of the epitaxial wafer (surface of the p-contact layer 19) when the void filling growth (step S2) was performed at growth times TP = 7 min and TP = 12 min, respectively, after the void blocking growth (step S1). In FIGS. 14A and 14B, region A is a region where the void layer 14P is formed, and region B is a region where the void layer 14P is not formed.

[0107] When the growth time TP of the gap-filling growth was 7 minutes, only a small amount of protrusions were observed in the region A where the porous layer 14P was formed, and when the growth time TP was 12 minutes, no protrusions PJ were observed.

[0108] Fig. 15A is an AFM image of the surface of active layer 15 when gap-filling growth was performed at a growth time TP of 12 min. Fig. 15B is an enlarged AFM image of a partial region G of the image shown in Fig. 15A, and Fig. 15C is a surface roughness (RAW) profile along line H-H in Fig. 15B.

[0109] As shown in these AFM images and surface roughness profiles, when gap-filling growth was performed with a growth time TP of 12 min, no protrusions PJ were observed, indicating that the active layer 15 could be grown without spiral growth. In other words, gap-filling growth was able to suppress the occurrence of dislocations originating from the voids MP. Conventionally, in order to increase the optical coupling coefficient and improve laser characteristics, it is preferable to shorten the distance between the active layer and the upper surface of the voids. Therefore, after or when voids are blocked, it has been thought preferable to block the voids by moving surface atoms via mass transport rather than crystal growth. However, it has been discovered that mass transport cannot eliminate the voids that occur during void blockage, which is a factor that reduces device life. As described above, while voids remain during mass transport, it has been found that by performing gap-filling growth with a growth time TP that is a certain degree longer than the growth time TF of void-blocking growth, the ratio of dislocations to the number of voids (occurrence rate RD) can be significantly reduced, thereby suppressing the occurrence of protrusions.

[0110] (2) Device Characteristics Figure 16 is a graph showing the optical output maintenance rate when the fabricated PCSEL device 10 is continuously driven. Figure 17 is a graph plotting the device lifetime against the ratio of dislocations to the number of vacancies (occurrence rate RD). The device lifetime was defined as the time until the optical output maintenance rate reached 70%.

[0111] More specifically, a current of 5 amperes (A) was applied to the PCSEL device 10 (current density: approximately 4 kA / cm ２ ) and the maintenance rate of light output versus drive time H (hours) was measured. In FIG. 16, the horizontal axis represents drive time H. １／２ The light output is shown as 100% when the drive time H is 0. The drive time H was also evaluated up to about 800 hours.

[0112] It can be seen from FIG. 16 that when gap filling growth (step S2) was performed (TP=7 min, 12 min), the light output maintenance rate was significantly improved compared to when it was not performed (TP=0 min).

[0113] Furthermore, as shown in FIG. 17, it was found that a long device life can be obtained by reducing the dislocation occurrence rate RD to approximately 100 ppm or less. In other words, it was found that by setting the growth time TP of the gap-filling growth to 7 minutes or more, the device life can be significantly improved by one order of magnitude or more. Furthermore, as shown in FIG. 17, it is more preferable in terms of device life that the dislocation occurrence rate RD be 90 ppm or less, which is the inflection point. Furthermore, in semiconductor layers where dislocations occur, current leakage due to dislocations may occur. The present invention can suppress the occurrence of current leakage and improve device characteristics.

[0114] 5. Gap-filling growth (1) Growth time of gap-filling growth As described above, the growth time TF of the void-filling growth (step S1) was 18 min, whereas the gap-filling growth (step S2) was performed under the same growth conditions as the void-filling growth, with the growth time TP set to 7 min and 12 min.

[0115] In order to reduce the dislocation occurrence rate RD to approximately 100 ppm or less and obtain a long device life, it is preferable to perform the void filling growth for a growth time TP of 40% or more of the growth time TF of the void blocking growth, taking into consideration the results for the growth time TP = 7 min.

[0116] In this example, the first growth rate RF, which is the growth rate of the void-filling growth (step S1), and the second growth rate RP, which is the growth rate of the void-filling growth (step S2), are set to be the same. When the first growth rate RF and the second growth rate RP are different, it is preferable to perform the void-filling growth under conditions where the product of the growth time TP and the second growth rate RP is 40% or more of the product of the growth time TF and the first growth rate RF.

[0117] Furthermore, as shown in FIG. 17, if the dislocation occurrence rate RD at which the device lifetime saturates is 50 ppm (the dashed line in the figure), it is preferable from FIG. 13 that the growth time TP is 9 minutes or more, that is, the gap-filling growth is performed for a growth time TP that is 50% or more of the growth time TF.

[0118] Note that, since a long period of time for the gap filling growth increases the thickness of the buried layer 14B and reduces the coupling efficiency between light and the void layer 14P, it is preferable that the growth time TP of the void filling growth be 100% or less of the growth time TF of the void filling growth, and considering the result for the growth time TP = 12 min, it is even more preferable that it be 70% or less.

[0119] (2) Growth Conditions for Gap-Filling Growth Changing the growth conditions in the gap-filling growth (step S2) allows the voids MP to be filled more quickly. It is believed that the voids MP are formed when the tips of the {1-101} facets change to {1-100} planes before the opposing {1-101} facets meet. In other words, it is believed that the inner wall surfaces of the voids MP are mainly {1-100} planes.

[0120] Therefore, to increase the rate at which the crystal fills the voids MP, it is effective to suppress the formation of the {1-100} plane and promote lateral growth by, for example, increasing the growth rate, lowering the growth temperature, or increasing the V / III ratio, compared to the void-closing growth (step S1). The rate at which the voids MP are filled can also be increased by increasing the growth rate of the {1-101} plane, for example, by increasing the amount of group III material. Furthermore, by changing the growth atmosphere from a nitrogen atmosphere to a hydrogen atmosphere, the growth of the (0001) plane can be accelerated relative to the {1-100} plane. In other words, the voids MP can be filled in a shorter time. Therefore, the hydrogen partial pressure of the carrier gas may be increased. In other words, growth may be performed by changing at least one of these growth conditions.

[0121] (3) Crystal composition of gap-filling growth In the gap-filling growth (step S2), the same GaN was grown as in the void-blocking growth (step S1), but GaN may be grown by adding a small amount of In. In functions as a surfactant, strengthening mass transport in the voids MP and promoting lateral growth, thereby increasing the rate at which the voids MP are filled. In this case, the crystal composition by growth is adjusted to In. ｘ Ga １－ｘ When N is used, it is preferable to add In so that the In composition x is less than 1.0% (0<x<0.01).

[0122] In this case, a gap filling portion EB doped with In is formed immediately above the voids 14K. That is, a gap filling portion EB doped with In (In ｘ Ga １－ｘ N) is formed, and the formation of dislocations DL and protrusions PJ is prevented.

[0123] As described above in detail, according to the present invention, it is possible to obtain an active layer in which the occurrence of protrusions (dislocations) is extremely suppressed. That is, it is possible to provide a surface-emitting semiconductor laser device having a photonic crystal, which has a high-quality active layer in which abnormal growth of protrusions and the like is suppressed, and which has good device characteristics and an excellent device life, and a method for manufacturing the same.

[0124] Note that, unless otherwise specified, the numerical values ​​and the like in the above-described embodiments are merely examples and can be modified as appropriate. Furthermore, while a PCSEL element with a double lattice structure has been exemplified, the present invention can also be applied to PCSEL elements with a single lattice structure and, in general, PCSEL elements with a multi-lattice structure. Furthermore, while the present invention has been exemplified with a photonic crystal layer (hole layer) in which the holes have a hexagonal columnar shape, the present invention can also be applied to cases in which the holes in the photonic crystal layer have an irregular columnar shape, such as a cylindrical, rectangular, polygonal, or teardrop shape.

[0125] 10: PCSEL element 12: Element substrate 13: n-cladding layer 14: n-side guide layer 14B: Buried layer 14B1, 14B2: First buried layer, second buried layer 14H: Hole 14H1, 14H2: Main hole, sub-hole 14K: Void 14K1, 14K2: Main hole, sub-hole 14P: Void layer 15: Active layer 16: p-side guide layer 18: p-cladding layer 20A: n-electrode 20B: p-electrode 23: Light distribution adjustment layer DL: Dislocation EB: Void filling part MP: Void PJ: Protrusion PK: Void period

Claims

1. A method for manufacturing a surface-emitting semiconductor laser device having a photonic crystal, comprising: (a) forming a hole formation preparation layer on a substrate; (b) forming holes in the hole formation preparation layer, arranged two-dimensionally at each of the lattice points, to form a hole formation layer; (c) performing first facet growth to close the openings of the holes; (d) performing second facet growth for a growth time that is 40% or more of the growth time of the first facet growth to form a first burying layer; (e) growing a second burying layer that evenly buries the first burying layer, and forming a guide layer including a vacancy layer having vacancies corresponding to the holes; and (f) performing crystal growth of a semiconductor layer including an active layer on the guiding layer.

2. The method for manufacturing a surface-emitting semiconductor laser element according to claim 1, wherein the surface-emitting semiconductor laser element is a GaN-based semiconductor laser element, and the crystal growth surface of the substrate and the surface of the second burying layer are {0001} planes.

3. The method for manufacturing a surface-emitting semiconductor laser device according to claim 1, wherein the growth time of the second facet growth is 50% or more and 100% or less of the growth time of the first facet growth.

4. The method for manufacturing a surface-emitting semiconductor laser device according to claim 1, wherein the rate of dislocations in the active layer relative to the number of vacancies is 100 ppm or less.

5. The method for manufacturing a surface-emitting semiconductor laser device according to claim 2, wherein the first facet growth is growth of GaN, and the second facet growth is performed by adding In to GaN at a composition of less than 1%.

6. A method for manufacturing a surface-emitting semiconductor laser device according to claim 1, wherein the second facet growth is performed under the same growth conditions as the first facet growth.

7. A method for manufacturing a surface-emitting semiconductor laser device according to any one of claims 1 to 5, wherein the second facet growth is performed by changing at least one growth condition from the first facet growth, among growth rate, growth temperature, V / III ratio, and hydrogen partial pressure.

8. A surface-emitting laser element made of a nitride semiconductor, comprising: a substrate; a first semiconductor layer provided on the substrate; an active layer provided on the first semiconductor layer; and a second semiconductor layer provided on the active layer and having an opposite conductivity type to that of the first semiconductor layer, wherein the first semiconductor layer has a void layer which is a photonic crystal layer having voids arranged with two-dimensional periodicity in a plane parallel to the active layer; and a burying layer, wherein the burying layer has a first burying layer which closes the voids and a second burying layer which flatly buries the first burying layer, and wherein the rate of dislocations in the active layer is 100 ppm or less relative to the number of voids.

9. The surface-emitting semiconductor laser element according to claim 8, wherein the surface-emitting semiconductor laser element is a GaN-based semiconductor laser element, and the crystal growth surface of the substrate and the surface of the second burying layer are {0001} planes.

10. The surface-emitting semiconductor laser device according to claim 8, wherein the rate of dislocations in said active layer relative to the number of said vacancies is 50 ppm or less.

11. The first buried layer and the second buried layer are GaN, and an In buried layer is formed between the first buried layer and the second buried layer directly above at least one of the voids. ｘ Ga １－ｘ 11. The surface-emitting semiconductor laser device according to claim 8, further comprising a gap filling portion made of N (0<x<0.01).

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