Display panel and display apparatus

Abstract

The present application relates to the technical field of display. Disclosed are a display panel and a display apparatus. The display panel comprises a base substrate, and a first pattern layer, a first insulating layer, a second pattern layer, a second insulating layer and a light-emitting unit film layer, which are located on the base substrate and are sequentially stacked. Since the absolute value of the difference between the distance from a first pattern in the first pattern layer to the central axis of a region and the distance from a second pattern in the second pattern layer to the central axis of the region is relatively small, an orthographic projection of the first pattern on the base substrate and an orthographic projection of the second pattern on the base substrate are approximately symmetrical with respect to the central axis of the region, and thus it is ensured that a protrusion of the first insulating layer at the position of the first pattern and a protrusion of the second insulating layer at the position of the second pattern match and complement each other, and the flatness of a surface on which the part of the light-emitting unit film layer that is located in a light-emitting region is arranged is further ensured, thereby avoiding the problem of the color separation of light rays, and improving the display effect of the display panel.

Description

Display panel and display device

[0001] The present disclosure claims priority to the Chinese patent application No. 202410832150.2, filed on June 25, 2024, and entitled "Display panel and display device", the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0003] The display panel comprises a substrate substrate and a pixel unit located in a display area of the substrate substrate. The pixel unit can emit light, thereby realizing display of the display panel. SUMMARY

[0004] The present application provides a display panel and a display device, and the technical solutions are as follows:

[0005] In one aspect, a display panel is provided, comprising:

[0006] a substrate substrate having a display area;

[0007] a first pattern layer located on one side of the substrate substrate, and the first pattern layer comprises a first pattern;

[0008] a first insulating layer located on a side of the first pattern layer away from the substrate substrate;

[0009] a second pattern layer located on a side of the first insulating layer away from the substrate substrate, and the second pattern layer comprises a second pattern;

[0010] a second insulating layer located on a side of the second pattern layer away from the substrate substrate;

[0011] and a light emitting unit film layer located on a side of the second insulating layer away from the substrate substrate, the light emitting unit film layer comprising a plurality of light emitting units, the plurality of light emitting units being located in the display area, each of the light emitting units having a light emitting area for emitting light;

[0012] The orthographic projection of the first pattern on the substrate and the orthographic projection of the second pattern on the substrate are respectively located on two sides of a region central axis of the light-emitting region, and the absolute value of the difference between the distance between the first pattern and the region central axis and the distance between the second pattern and the region central axis is less than or equal to 10 microns, the region central axis being a line segment perpendicular to the bearing surface of the substrate and passing through the center of the light-emitting region.

[0013] Optionally, the light-emitting unit film layer comprises, in sequence from the direction away from the substrate, an anode layer, a pixel defining layer, a light-emitting layer, and a cathode layer.

[0014] The anode layer comprises a plurality of anode patterns, the pixel defining layer comprises a plurality of hollow regions, each of the hollow regions being used to expose at least part of a corresponding one of the anode patterns; the light-emitting layer comprises a plurality of light-emitting patterns, each of the light-emitting patterns being in contact with the anode pattern exposed by a corresponding one of the hollow regions, and the cathode layer being in contact with the plurality of light-emitting patterns.

[0015] Each of the light-emitting regions of the light-emitting units is a region in which at least part of the anode pattern exposed by a corresponding one of the hollow regions is located.

[0016] Optionally, the center of the light-emitting region is the center of the smallest circle circumscribing the light-emitting region, or the center of the light-emitting region is the center of the smallest rectangle circumscribing the light-emitting region.

[0017] Optionally, the orthographic projection of the first pattern on the substrate and the orthographic projection of the second pattern on the substrate do not overlap with the orthographic projection of the hollow region of the pixel defining layer on the substrate.

[0018] Optionally, the anode pattern comprises a target region pattern not exposed by the hollow region.

[0019] The orthographic projection of the first pattern on the substrate and the orthographic projection of the target region pattern on the substrate at least partially overlap, and the orthographic projection of the second pattern on the substrate and the orthographic projection of the target region pattern on the substrate at least partially overlap.

[0020] Optionally, at least one of the first pattern layer and the second pattern layer further comprises at least one third pattern.

[0021] The orthographic projection of the at least one third pattern on the substrate is symmetrical with respect to the region central axis.

[0022] Optionally, for any one of the first pattern layer and the second pattern layer, if the pattern layer includes one third pattern, a projection of the third pattern on the substrate covers a projection of the area axis on the substrate, and an absolute value of a difference between a distance between a third pattern axis of the third pattern and the area axis is less than or equal to 10 microns;

[0023] If the number of the third patterns included in the pattern layer is an odd number greater than 1, the third patterns included in the pattern layer include a target third pattern and at least one third pattern group, the third pattern group includes a first third pattern and a second third pattern, a projection of the target third pattern on the substrate covers a projection of the area axis on the substrate, and an absolute value of a difference between a distance between a third pattern axis of the target third pattern and the area axis is less than or equal to 10 microns; a projection of the first third pattern on the substrate and a projection of the second third pattern on the substrate are respectively located on two sides of the area axis, and an absolute value of a difference between a distance between the first third pattern and the area axis and a distance between the second third pattern and the area axis is less than or equal to 10 microns.

[0024] Optionally, for any one of the first pattern layer and the second pattern layer, if the number of the third patterns included in the pattern layer is an even number greater than 1, the third patterns included in the pattern layer include at least one third pattern group, the third pattern group includes a first third pattern and a second third pattern;

[0025] a projection of the first third pattern on the substrate and a projection of the second third pattern on the substrate are respectively located on two sides of the area axis, and an absolute value of a difference between a distance between the first third pattern and the area axis and a distance between the second third pattern and the area axis is less than or equal to 10 microns.

[0026] Optionally, the first pattern layer includes one third pattern group, the third pattern group includes a first third pattern and a second third pattern;

[0027] a projection of the first third pattern on the substrate and a projection of the second third pattern on the substrate are respectively located on two sides of the area axis, and an absolute value of a difference between a distance between the first third pattern and the area axis and a distance between the second third pattern and the area axis is less than or equal to 10 microns.

[0028] The second pattern layer comprises a third pattern, and a normal projection of the third pattern on the substrate substrate covers a normal projection of the axis in the region on the substrate substrate, and an absolute value of a difference between a distance between a third pattern axis of the third pattern and the axis in the region is less than or equal to 10 microns.

[0029] Optionally, one of the first pattern layer and the second pattern layer comprises a fourth pattern.

[0030] A normal projection of the fourth pattern on the substrate substrate is located between the light emitting regions of adjacent light emitting units; a distance between the fourth pattern and a target pattern in a target pattern layer of the first pattern layer and the second pattern layer is greater than or equal to 1 micron.

[0031] The target pattern layer is another pattern layer of the first pattern layer and the second pattern layer except the pattern layer where the fourth pattern is located, the target pattern layer is the first pattern layer, and the target pattern is the first pattern, and the target pattern layer is the second pattern layer, and the target pattern is the second pattern.

[0032] Optionally, the display panel further comprises a third pattern layer and a third insulating layer.

[0033] The third pattern layer is located on one side of the substrate substrate, and the third pattern layer comprises at least one fifth pattern.

[0034] The third insulating layer is located on a side of the third pattern layer away from the substrate substrate.

[0035] The normal projection of the at least one fifth pattern on the substrate substrate is symmetrical with respect to the axis in the region of the light emitting region.

[0036] Optionally, the third pattern layer comprises one fifth pattern, and a normal projection of the fifth pattern on the substrate substrate covers the light emitting region of the light emitting unit.

[0037] Optionally, the third pattern layer is located on a side of the second insulating layer away from the substrate substrate, and the third insulating layer is located between the third pattern layer and the light emitting unit film layer; or,

[0038] The third pattern layer is located between the substrate substrate and the first pattern layer, and the third insulating layer is located between the third pattern layer and the first pattern layer.

[0039] Optionally, the thickness of the first insulating layer and the second insulating layer ranges from 0.5 microns to 3 microns.

[0040] In another aspect, a display device is provided, the display device comprising: a power supply assembly; and a display panel as described in the above aspect.

[0041] The power supply assembly is connected to the display panel and is configured to supply power to the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0043] FIG. 1 is a color separation schematic diagram of a display panel according to an embodiment of the present application;

[0044] FIG. 2 is a structural schematic diagram of a display panel according to an embodiment of the present application;

[0045] FIG. 3 is a top view of a substrate according to an embodiment of the present application;

[0046] FIG. 4 is a schematic diagram of a setting principle of a first pattern and a second pattern according to an embodiment of the present application;

[0047] FIG. 5 is a structural schematic diagram of another display panel according to an embodiment of the present application;

[0048] FIG. 6 is a structural schematic diagram of still another display panel according to an embodiment of the present application;

[0049] FIG. 7 is a structural schematic diagram of still another display panel according to an embodiment of the present application;

[0050] FIG. 8 is a structural schematic diagram of still another display panel according to an embodiment of the present application;

[0051] FIG. 9 is a structural schematic diagram of still another display panel according to an embodiment of the present application;

[0052] FIG. 10 is a structural schematic diagram of still another display panel according to an embodiment of the present application;

[0053] FIG. 11 is a partial cross-sectional view of a display panel according to an embodiment of the present application;

[0054] FIG. 12 is a structural schematic diagram of still another display panel according to an embodiment of the present application;

[0055] FIG. 13 is a structural schematic diagram of still another display panel according to an embodiment of the present application;

[0056] FIG. 14 is a structural schematic diagram of a display panel according to an embodiment of the present application;

[0057] FIG. 15 is a partial cross-sectional view of a display panel according to an embodiment of the present application;

[0058] FIG. 16 is a partial top view of a fifth pattern and an anode pattern according to an embodiment of the present application;

[0059] FIG. 17 is a partial top view of a first source-drain layer according to an embodiment of the present application;

[0060] FIG. 18 is a partial top view of a first source-drain layer and a second source-drain layer according to an embodiment of the present application;

[0061] FIG. 19 is a partial top view of a first source-drain layer, a second source-drain layer and an anode layer according to an embodiment of the present application;

[0062] FIG. 20 is a partial top view of a first source-drain layer, a second source-drain layer, an anode layer and a pixel definition layer according to an embodiment of the present application;

[0063] FIG. 21 is a structural schematic diagram of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical scheme and advantages of the present application more clear, the embodiments of the present application will be described in further detail below with reference to the drawings.

[0065] With the increasing functions of existing mobile electronic products, such as the number of driving chips (IC) cores, central processing unit (CPU), graphics processing unit (GPU) functions, the number of cameras, the increase of auxiliary functions (satellite phones and navigation modules, etc.) and the consumption of electric energy, the proportion of the consumption of electric energy also increases greatly. In order to improve the endurance time of the battery, the energy consumption of the display can be reduced.

[0066] In some embodiments, in order to improve the transmittance of the display panel, so that the display panel has better power consumption benefits and is more slim, the scheme of using no polarizer (POL) (the transmittance of the polarizer is basically impossible to exceed 50% in principle) is adopted. For example, the polarizer arranged on the upper side of the pixel unit in the display panel is replaced by the technology of color filter on encapsulation (COE).

[0067] The color filter layer is different from the polarizer. After the light from the outside enters the display panel, the anode layer in the display panel can reflect the light from the outside, and the reflected light can be emitted again through the color filter layer. Thus, under the dark state display of the display panel, the flatness of the anode layer can be reflected by the reflected light of the anode pattern in the sub-pixels of different colors. The display panel includes a red (R) sub-pixel, a green (G) sub-pixel and a blue (B) sub-pixel.

[0068] Referring to FIG. 1, the color filter layer includes a red filter part, a green filter part and a blue filter part. After the light from the outside enters the display panel, because the flatness of the anode layer is poor, the mixed reflected light is not white light. For example, the red light and the blue light in FIG. 1 are mixed together to present purple light. That is, the poor flatness of the anode layer can cause the color separation phenomenon of the COE display panel, and the display effect of the display panel is poor. In order to solve the color separation phenomenon of the display panel, it is necessary to improve the flatness of the setting plane of the anode layer.

[0069] The existing solutions are all to use the same layer symmetric design scheme to realize the flatness of the setting plane of the anode layer. However, the existing solutions can usually be applied only in the existing eight transistor (8T), low pixel density (such as 400PPI) and opening rate of 16% to 19% scenarios. For the fanout in panel (FIP) setting in the display area, high pixel density (such as greater than 500PPI), high opening rate (greater than 20%), Tendam device, and large size organic light emitting diode display panel scenarios, the layout compression of each signal line is inevitable, and therefore it is more and more difficult to use the same layer symmetric design scheme to realize the flatness of the setting plane of the anode layer.

[0070] FIG. 2 is a structural schematic diagram of a display panel provided by an embodiment of the present application. Referring to FIG. 2, the display panel 100 includes a substrate 101, a first pattern layer 102, a first insulating layer 103, a second pattern layer 104, a second insulating layer 105 and a light emitting unit film layer 106.

[0071] As shown in FIG. 3, the substrate 101 has a display area 101a. The first pattern layer 102 is located on one side of the substrate 101. The first insulating layer 103 is located on the side of the first pattern layer 102 away from the substrate 101. The second pattern layer 104 is located on the side of the first insulating layer 103 away from the substrate 101. The second insulating layer 105 is located on the side of the second pattern layer 104 away from the substrate 101. The light emitting unit film layer 106 is located on the side of the second insulating layer 105 away from the substrate 101. That is, the first pattern layer 102, the first insulating layer 103, the second pattern layer 104, the second insulating layer 105, and the light emitting unit film layer 106 are sequentially stacked in the direction away from the substrate 101.

[0072] The first insulating layer 103 is located between the first pattern layer 102 and the second pattern layer 104, and is used to insulate the first pattern layer 102 and the second pattern layer 104 from each other. The second insulating layer 105 is located on the side of the second pattern layer 104 away from the substrate 101, and is used to insulate the second pattern layer 104 and other film layers from each other. For example, in FIG. 2, the second insulating layer 105 is located between the second pattern layer 104 and the light emitting unit film layer 106, and is used to insulate the second pattern layer 104 and the light emitting unit film layer 106 from each other.

[0073] The first pattern layer 102 includes a first pattern 1021, and the second pattern layer 104 includes a second pattern 1041. The light emitting unit film layer 106 includes a plurality of light emitting units 106a (one light emitting unit 106a is shown in FIG. 2), and the plurality of light emitting units 106a are located in the display area 101a. Each light emitting unit 106a has a light emitting area 106a1 for emitting light.

[0074] In the embodiment of the present application, as shown in FIG. 4a, when the first pattern layer 102 includes the first pattern 1021, the surface of the first insulating layer 103 away from the substrate 101 is convex (i.e., the surface is uneven and has an inclination) at the position of the first pattern 1021. As shown in FIG. 4a, the thickness h1 of the portion of the first insulating layer 103 close to the first pattern 1021 is greater than the thickness h2 of the portion of the first insulating layer 103 away from the first pattern 1021, i.e., h1>h2.

[0075] Referring to FIG. 4b, in the case where the second pattern layer 104 includes the second pattern 1041, the second insulating layer 105 is convex (i.e., the surface is uneven and has a slope) away from the surface of the substrate 101 at the position where the second pattern 1041 is located. Referring to FIG. 4b, the thickness h3 of the portion of the second insulating layer 105 close to the second pattern 1041 is greater than the thickness h4 of the portion of the second insulating layer 105 away from the second pattern 1041, i.e., h3>h4.

[0076] Combining a and b to obtain c, so that the convexity of the first insulating layer 103 at the position of the first pattern 1021 and the convexity of the second insulating layer 105 at the position of the second pattern 1041 can complement each other and improve the flatness of the setting surface of the light emitting unit film layer 106 as much as possible. Referring to FIG. 4c, the sum h1+h4 of the thicknesses of the portions of the first insulating layer 103 and the second insulating layer 105 close to the first pattern 1021 is approximately equal to the sum h2+h3 of the thicknesses of the portions of the first insulating layer 103 and the second insulating layer 105 close to the second pattern 1041, i.e., h1+h4≈h2+h3. Among them, the absolute value of the difference between h1+h4 and h2+h3 can be less than 0.1 μm.

[0077] Referring to FIG. 2, in order to make the convexity of the first insulating layer 103 at the position of the first pattern 1021 and the convexity of the second insulating layer 105 at the position of the second pattern 1041 complement each other, the orthographic projection of the first pattern 1021 on the substrate 101 and the orthographic projection of the second pattern 1041 on the substrate 101 can be located on the two sides of the area central axis Z1 in the light emitting area 106a1, respectively. And the absolute value of the difference between the distance b1 between the first pattern 1021 and the area central axis Z1 and the distance b2 between the second pattern 1041 and the area central axis Z1 is less than or equal to 10 μm (microns), i.e., |b1-b2|≤10 μm. The area central axis Z1 is a line segment perpendicular to the bearing surface of the substrate 101 and passing through the center of the light emitting area 106a1.

[0078] Since the absolute value of the difference between the distance between the first pattern 1021 and the area central axis Z1 and the distance between the second pattern 1041 and the area central axis Z1 is small, the distance between the first pattern 1021 and the area central axis Z1 can be made substantially equal to the distance between the second pattern 1041 and the area central axis Z1. In this way, the orthographic projection of the first pattern 1021 on the substrate 101 and the orthographic projection of the second pattern 1041 on the substrate 101 can be substantially symmetrical with respect to the area central axis Z1, and the convexity of the first insulating layer 103 at the position of the first pattern 1021 and the convexity of the second insulating layer 105 at the position of the second pattern 1041 can be complementary to each other, thereby ensuring the flatness of the setting surface of the light emitting unit film layer 106 at the part of the light emitting area 106a1, and further avoiding the problem of color separation of light, and improving the display effect of the display panel 100.

[0079] In summary, the display panel provided by the embodiments of the present application includes a substrate, and a first pattern layer, a first insulating layer, a second pattern layer, a second insulating layer and a light emitting unit film layer which are sequentially stacked on the substrate in a direction away from the substrate. Since the absolute value of the difference between the distance between the first pattern in the first pattern layer and the area central axis and the distance between the second pattern in the second pattern layer and the area central axis is small, the orthographic projection of the first pattern on the substrate and the orthographic projection of the second pattern on the substrate can be substantially symmetrical with respect to the area central axis, and the convexity of the first insulating layer at the position of the first pattern and the convexity of the second insulating layer at the position of the second pattern can be complementary to each other, thereby ensuring the flatness of the setting surface of the light emitting unit film layer at the part of the light emitting area, further avoiding the problem of color separation of light, and improving the display effect of the display panel.

[0080] The embodiments of the present application can realize the flatness of the setting surface of the light emitting unit film layer by two pattern layers, which can facilitate the display panel to realize more complex design (more complex design refers to higher requirements for the wiring density and the line width), such as high PPI, sensor (Sensor) integration, FIP and the like. Moreover, the design space can be saved, and more space can be provided for layout arrangement.

[0081] Optionally, since the design of the first pattern 1021 and the second pattern 1041 can ensure the flatness of the setting surface of the light emitting unit film layer 106, the thickness of the first insulating layer 103 and the second insulating layer 105 does not need to be set to be relatively thick to realize the flatness. Optionally, the thickness of the first insulating layer 103 and the second insulating layer 105 can range from 0.5 μm to 3 μm.

[0082] Referring to FIG. 2, the light emitting unit film layer 106 includes, in sequence from the direction away from the substrate base plate 101, an anode layer 1061, a pixel defining layer 1062, a light emitting layer 1063, and a cathode layer 1064. The anode layer 1061 includes a plurality of anode patterns 10611, each of which can serve as an anode of one light emitting unit 106a. The pixel defining layer 1062 includes a plurality of hollowed-out regions, each of which is used to expose at least part of a corresponding one of the anode patterns 10611. The light emitting layer 1063 includes a plurality of light emitting patterns 10631, each of which serves as a light emitting functional layer (EL layer) of one light emitting unit 106a. Each of the light emitting patterns 10631 and the anode pattern 10611 exposed by the corresponding one of the hollowed-out regions are in contact. The cathode layer 1064 is in contact with the plurality of light emitting patterns 10631. The cathode layer 1064 can serve as the cathode of the plurality of light emitting units 106a, i.e., the cathode layer 1064 of the plurality of light emitting units 106a is a common film layer.

[0083] wherein the light emitting region 106a1 of each of the light emitting units 106a is a region in which at least part of the anode pattern 10611 exposed by the corresponding one of the hollowed-out regions is located. That is, the hollowed-out region can be used to define the light emitting region 106a1 of the light emitting unit 106a.

[0084] Optionally, the shape of the light emitting region 106a1 of the light emitting unit 106a can be a regular pattern such as a circle, a square, an ellipse, a regular hexagon, a regular octagon, etc. Of course, the shape of the light emitting region 106a1 of the light emitting unit 106a can also be an irregular pattern. The embodiments of the present application do not limit the shape of the light emitting region 106a1 of the light emitting unit 106a.

[0085] If the shape of the light emitting region 106a1 of the light emitting unit 106a is a regular pattern, the region central axis Z1 of the light emitting region 106a1 can be easily defined because the center of the regular pattern can be easily found. If the shape of the light emitting region 106a1 of the light emitting unit 106a is an irregular pattern, the center of the light emitting region 106a1 is difficult to determine, which in turn causes the region central axis Z1 of the light emitting region 106a1 to be difficult to define.

[0086] Therefore, in order to define the region central axis Z1 of the light emitting region 106a1 of various different shapes, whether the shape of the light emitting region 106a1 is a regular pattern or not, the center of the light emitting region 106a1 can be determined as the center of the minimum circumscribed circle of the light emitting region 106a1, or as the center of the minimum circumscribed rectangle of the light emitting region 106a1.

[0087] It should be noted that, in the case where the shape of the light emitting region 106a1 is circular, the minimum circumscribed circle of the light emitting region 106a1 is the light emitting region 106a1 itself. In the case where the shape of the light emitting region 106a1 is rectangular, the minimum circumscribed rectangle of the light emitting region 106a1 is the light emitting region 106a1 itself. Since the minimum circumscribed circle or the minimum circumscribed rectangle can be determined for any shape, the region central axis Z1 of the light emitting region 106a1 can be determined based on the center of the minimum circumscribed circle or the center of the minimum circumscribed rectangle.

[0088] In the embodiment of the present application, referring to FIG. 2, the orthographic projection of the first pattern 1021 on the substrate 101 and the orthographic projection of the second pattern 1041 on the substrate 101 are both not overlapped with the orthographic projection of the hollow region of the pixel defining layer 1062 on the substrate 101. That is, the orthographic projection of the first pattern 1021 on the substrate 101 and the orthographic projection of the second pattern 1041 on the substrate 101 are both covered by the orthographic projection of the solid region of the pixel defining layer 1062 on the substrate 101. The orthographic projection of the first pattern 1021 on the substrate 101 and the orthographic projection of the second pattern 1041 on the substrate 101 are both located outside the light emitting region 106a1. Thus, the existence of the first pattern 1021 and the second pattern 1041 can be avoided from affecting the normal display and light emitting of the light emitting region 106a1, and the display effect of the display panel can be ensured.

[0089] Referring to FIG. 5, the distance between the edge of the first pattern 1021 close to the light emitting region 106a1 and the edge of the hollow region of the pixel defining layer 1062 close to the first pattern 1021 is defined as the first distance d1. Assuming that the edge of the hollow region of the pixel defining layer 1062 close to the first pattern 1021 is the zero position of the first distance (represented by “0”), the zero position deviates close to the hollow region as the positive value of the first distance (represented by “+”), and the zero position deviates away from the hollow region as the negative value of the first distance (represented by “-”). Then, in order to make the orthographic projection of the first pattern 1021 on the substrate 101 and the orthographic projection of the hollow region of the pixel defining layer 1062 on the substrate 101 not overlapped, the first distance d1 can be made as the negative value of the first distance, i.e., d1<0.

[0090] The distance between the edge of the second pattern 1041 close to the side of the light-emitting region 106a1 and the edge of the hollow region of the pixel defining layer 1062 close to the side of the second pattern 1041 is denoted as a second distance d2. Assuming that the edge of the hollow region of the pixel defining layer 1062 close to the side of the second pattern 1041 is the zero position of the second distance (denoted as “0”), the zero position deviates close to the hollow region as a positive value of the second distance (denoted as “+”), and the zero position deviates away from the hollow region as a negative value of the second distance (denoted as “-”). Then, in order to make the orthographic projection of the second pattern 1041 on the substrate 101 and the orthographic projection of the hollow region of the pixel defining layer 1062 on the substrate 101 not overlap, the second distance d2 can be a negative value of the second distance, that is, d2 < 0.

[0091] That is, in the case where the first distance d1 and the second distance d2 are both less than 0, not only can the orthographic projection of the first pattern 1021 on the substrate 101 and the orthographic projection of the second pattern 1041 on the substrate 101 be substantially symmetrical with respect to the region central axis Z1, but also the orthographic projection of the first pattern 1021 on the substrate 101 and the orthographic projection of the second pattern 1041 on the substrate 101 can both be located outside the light-emitting region 106a1 (that is, do not exceed the edge of the pixel defining layer 1062). Thus, the first pattern 1021 and the second pattern 1041 can be avoided from affecting the normal display and light emission of the light-emitting region 106a1, and the display effect of the display panel 100 is better while the flatness of the setting surface of the light-emitting unit film layer 106 is ensured.

[0092] In the embodiment of the present application, referring to FIG. 6, the orthographic projection of the solid region of the pixel defining layer 1062 on the substrate 101 can cover the orthographic projection of the edge of the anode pattern 10611 on the substrate 101. That is, a part of the anode pattern 10611 is not exposed by the hollow region. For ease of description, the part of the anode pattern 10611 not exposed by the hollow region is referred to as a target region pattern M in the embodiment of the present application.

[0093] Optionally, the orthographic projection of the first pattern 1021 on the substrate 101 and the orthographic projection of the target region pattern M on the substrate 101 at least partially overlap. The at least partial overlap can include two meanings: 1. a part of the orthographic projection of the first pattern 1021 on the substrate 101 overlaps with the orthographic projection of the target region pattern M on the substrate 101, and another part of the orthographic projection of the first pattern 1021 on the substrate 101 does not overlap with the orthographic projection of the target region pattern M on the substrate 101; 2. the orthographic projection of the first pattern 1021 on the substrate 101 is covered by the orthographic projection of the target region pattern M on the substrate 101.

[0094] In the first case, as shown in FIG. 7, the orthographic projection of the edge of the first pattern 1021 on the substrate 101 near the side of the light-emitting region 106a1 is within the orthographic projection of the target region pattern M on the substrate 101, and the orthographic projection of the edge of the first pattern 1021 on the substrate 101 away from the side of the light-emitting region 106a1 is outside the orthographic projection of the target region pattern M on the substrate 101. In the second case, as shown in FIG. 6, the orthographic projection of the edge of the first pattern 1021 on the substrate 101 near the side of the light-emitting region 106a1 and the orthographic projection of the edge of the first pattern 1021 on the substrate 101 away from the side of the light-emitting region 106a1 are both within the orthographic projection of the target region pattern M on the substrate 101.

[0095] In addition, the orthographic projection of the second pattern 1041 on the substrate 101 and the orthographic projection of the target region pattern M on the substrate 101 are partially overlapped. The partial overlap can include two meanings: 1. a part of the orthographic projection of the second pattern 1041 on the substrate 101 is overlapped with the orthographic projection of the target region pattern M on the substrate 101, and another part of the orthographic projection of the second pattern 1041 on the substrate 101 is not overlapped with the orthographic projection of the target region pattern M on the substrate 101; 2. the orthographic projection of the second pattern 1041 on the substrate 101 is covered by the orthographic projection of the target region pattern M on the substrate 101.

[0096] In the first case, as shown in FIG. 7, the orthographic projection of the edge of the second pattern 1041 on the substrate 101 near the side of the light-emitting region 106a1 is within the orthographic projection of the target region pattern M on the substrate 101, and the orthographic projection of the edge of the second pattern 1041 on the substrate 101 away from the side of the light-emitting region 106a1 is outside the orthographic projection of the target region pattern M on the substrate 101. In the second case, as shown in FIG. 6, the orthographic projection of the edge of the second pattern 1041 on the substrate 101 near the side of the light-emitting region 106a1 and the orthographic projection of the edge of the second pattern 1041 on the substrate 101 away from the side of the light-emitting region 106a1 are both within the orthographic projection of the target region pattern M on the substrate 101.

[0097] Because the orthographic projection of the first pattern 1021 on the substrate 101 and the orthographic projection of the target region pattern M on the substrate 101 are at least partially overlapped, and the orthographic projection of the second pattern 1041 on the substrate 101 and the orthographic projection of the target region pattern M on the substrate 101 are at least partially overlapped, not only the normal display of the light-emitting region 106a1 is not affected, but also the distance between the first pattern 1021 and the second pattern 1041 can be reduced, which is convenient for the layout design of other patterns.

[0098] Of course, referring to FIG. 8, the orthographic projection of the first pattern 1021 on the substrate 101 and the orthographic projection of the second pattern 1041 on the substrate 101 are both non-overlapping with the orthographic projection of the anode pattern 10611 on the substrate 101. That is, the orthographic projection of the first pattern 1021 on the substrate 101 and the orthographic projection of the second pattern 1041 on the substrate 101 are both located outside the orthographic projection of the anode pattern 10611 on the substrate 101. The present embodiment does not limit the overlapping relationship between the first pattern 1021 and the second pattern 1041 and the anode pattern 10611.

[0099] Referring to FIGS. 6-8, the distance between the edge of the first pattern 1021 on the side close to the light-emitting region 106a1 and the edge of the anode pattern 10611 on the side close to the first pattern 1021 is denoted as a third distance d3. Assuming that the edge of the anode pattern 10611 on the side close to the first pattern 1021 is the zero position of the third distance d3 (denoted by “0”), the zero position deviates towards the side close to the hollow region, which is a positive value of the third distance (denoted by “+”), and the zero position deviates away from the side close to the hollow region, which is a negative value of the third distance (denoted by “-”). Then, the orthographic projection of the first pattern 1021 on the substrate 101 and the orthographic projection of the anode pattern 10611 on the substrate 101 are non-overlapping, which can mean that the third distance d3 is less than 0 (i.e., d3<0), and the orthographic projection of the first pattern 1021 on the substrate 101 and the orthographic projection of the target pattern region of the anode pattern 10611 on the substrate 101 are at least partially overlapping, which can mean that the third distance d3 is greater than or equal to 0 (i.e., d3≥0).

[0100] The distance between the edge of the second pattern 1041 on the side close to the light-emitting region 106a1 and the edge of the anode pattern 10611 on the side close to the second pattern 1041 is denoted as a fourth distance d4. Assuming that the edge of the anode pattern 10611 on the side close to the second pattern 1041 is the zero position of the fourth distance d4 (denoted by “0”), the zero position deviates towards the side close to the hollow region, which is a positive value of the fourth distance (denoted by “+”), and the zero position deviates away from the side close to the hollow region, which is a negative value of the fourth distance (denoted by “-”). Then, the orthographic projection of the second pattern 1041 on the substrate 101 and the orthographic projection of the anode pattern 10611 on the substrate 101 are non-overlapping, which can mean that the fourth distance d4 is less than 0 (i.e., d4<0), and the orthographic projection of the second pattern 1041 on the substrate 101 and the orthographic projection of the target pattern region of the anode pattern 10611 on the substrate 101 are at least partially overlapping, which can mean that the fourth distance d4 is greater than or equal to 0 (i.e., d4≥0).

[0101] In the present embodiment, the third distance d3 and the fourth distance d4 can be greater than 0, equal to 0, or less than 0. The present embodiment does not limit this.

[0102] In the embodiments of the present application, referring to FIG. 9, at least one of the first pattern layer 102 and the second pattern layer 104 further comprises at least one third pattern T1. The orthographic projection of the at least one third pattern T1 on the substrate 101 is symmetrical with respect to the area central axis Z1. Wherein the at least one of the first pattern layer 102 and the second pattern layer 104 is respectively: the first pattern layer 102, the second pattern layer 104, and the first pattern layer 102 and the second pattern layer 104. The at least one third pattern T1 can refer to one or more third patterns T1. The symmetry with respect to the area central axis Z1 can refer to approximate symmetry.

[0103] Referring to FIG. 9, for any pattern layer of the first pattern layer 102 and the second pattern layer 104, if the pattern layer (for example, the second pattern layer 104) comprises one third pattern T1, the orthographic projection of the third pattern T1 on the substrate 101 covers the orthographic projection of the area central axis Z1 on the substrate 101, and the absolute value of the distance d5 between the third pattern central axis Z2 of the third pattern T1 and the area central axis Z1 is less than or equal to 10 μm. Wherein, the absolute value of the distance d5 between the third pattern central axis Z2 of the third pattern T1 and the area central axis Z1 is less than or equal to 10 μm can be used to indicate that the third pattern T1 is approximately symmetrical with respect to the area central axis Z1.

[0104] For any pattern layer of the first pattern layer 102 and the second pattern 1041, if the number of third patterns T1 included in the pattern layer is an odd number greater than 1, the plurality of third patterns T1 included in the pattern layer comprises a target third pattern and at least one third pattern group. The orthographic projection of the target third pattern on the substrate 101 covers the orthographic projection of the area central axis Z1 on the substrate 101, and the absolute value of the distance between the third pattern central axis of the target third pattern and the area central axis Z1 is less than or equal to 10 μm. Wherein, the absolute value of the distance between the third pattern central axis of the target third pattern and the area central axis Z1 is less than or equal to 10 μm can be used to indicate that the target third pattern is approximately symmetrical with respect to the area central axis Z1. In addition, the third pattern group comprises a first third pattern and a second third pattern. The orthographic projection of the first third pattern on the substrate 101 and the orthographic projection of the second third pattern on the substrate 101 are respectively located on both sides of the area central axis Z1, and the absolute value of the difference between the distance between the first third pattern and the area central axis Z1 and the distance between the second third pattern and the area central axis Z1 is less than or equal to 10 μm. That is, the first third pattern and the second third pattern are approximately symmetrical with respect to the area central axis Z1.

[0105] Referring to FIG. 9, for any of the first pattern layer 102 and the second pattern layer 104, if the pattern layer (taking the first pattern layer 102 as an example) includes a number of third patterns T1 which is an even number greater than 1, the pattern layer includes a plurality of third patterns T1 including at least one third pattern group T1a. The third pattern group T1a includes a first third pattern T1a1 and a second third pattern T1a2. The orthographic projection of the first third pattern T1a1 on the substrate 101 and the orthographic projection of the second third pattern T1a2 on the substrate 101 are respectively located on both sides of the region central axis Z1, and the absolute value of the difference between the distance d6 between the first third pattern T1a1 and the region central axis Z1 and the distance d7 between the second third pattern T1a2 and the region central axis Z1 is less than or equal to 10 μm. That is, the first third pattern T1a1 and the second third pattern T1a2 are substantially symmetrical with respect to the region central axis Z1.

[0106] For example, referring to FIG. 9, the first pattern layer 102 includes one third pattern group T1a, and the third pattern group T1a includes a first third pattern T1a1 and a second third pattern T1a2. The orthographic projection of the first third pattern T1a1 on the substrate 101 and the orthographic projection of the second third pattern T1a2 on the substrate 101 are respectively located on both sides of the region central axis Z1, and the absolute value of the difference between the distance d6 between the first third pattern T1a1 and the region central axis Z1 and the distance d7 between the second third pattern T1a2 and the region central axis Z1 is less than or equal to 10 μm, i.e., |d6-d7|≤10 μm. The second pattern layer 104 includes one third pattern T1, and the orthographic projection of the third pattern T1 on the substrate 101 covers the orthographic projection of the region central axis Z1 on the substrate 101. The absolute value of the distance d5 between the third pattern central axis Z2 of the third pattern T1 and the region central axis Z1 is less than or equal to 10 μm, i.e., d5≤10 μm.

[0107] Optionally, the third pattern central axis Z2 of the third pattern T1 is a line segment perpendicular to the surface of the third pattern T1 and passing through the center of the third pattern T1. In order to define the third pattern central axis of the third pattern T1 of various different shapes, whether the shape of the third pattern T1 is a regular figure or not, the center of the third pattern T1 can be determined as the center of the minimum circumscribed circle of the third pattern T1, or the center of the minimum circumscribed rectangle of the third pattern T1.

[0108] It should be noted that in the case of the shape of the third pattern T1 being a circle, the minimum circumscribed circle of the third pattern T1 is the third pattern T1 itself. In the case of the shape of the third pattern T1 being a rectangle, the minimum circumscribed distance of the third pattern T1 is the third pattern T1 itself.

[0109] In the embodiment of the present application, referring to FIG. 10, one of the first pattern layer 102 and the second pattern layer 104 (for example, the second pattern layer 104) includes the fourth pattern T2. The orthographic projection of the fourth pattern T2 on the substrate 101 is located between the light-emitting areas 106a1 of the adjacent light-emitting units 106a. The distance d8 between the fourth pattern T2 and the target pattern in the target pattern layer (for example, the first pattern layer 102) is greater than or equal to 1 μm, that is, d8≤1 μm.

[0110] wherein the target pattern layer is another pattern layer in the first pattern layer 102 and the second pattern layer 104 except the pattern layer in which the fourth pattern T2 is located. Referring to FIG. 10, the target pattern layer is the first pattern layer 102, and the target pattern is the first pattern 1021. Alternatively, the target pattern layer is the second pattern layer 104, and the target pattern is the second pattern 1041.

[0111] Since the distance d8 between the fourth pattern T2 and the target pattern is greater than or equal to 1 μm, the thickness of the fourth pattern T2 and the target pattern is prevented from being superimposed to cause the second insulating layer 105 to locally protrude away from the surface of the substrate 101, thereby ensuring the flatness of the setting surface of the light-emitting unit film layer 106 and avoiding the problem of color separation of the display panel 100.

[0112] Referring to FIG. 10, for example, the second pattern layer 104 includes the fourth pattern T2, the target pattern layer is the first pattern layer 102, and the target pattern is the first pattern 1021. Alternatively, the first pattern layer 102 includes the fourth pattern T2, the target pattern layer is the second pattern layer 104, and the target pattern is the second pattern 1041.

[0113] In the embodiment of the present application, referring to FIG. 11, the display panel 100 can include, in sequence from the substrate 101 in the direction away from the substrate 101, a buffer layer (buffer) n1, an active layer (poly) n2, a gate insulating layer (GI) n3, a gate layer (gate) n4, an inter level dielectric (ILD) n5, a first source-drain layer (SD1) n6, a first planarization layer (PLN1) n7, a second source-drain layer (SD2) n8, a second planarization layer (PLN2) n9, an anode layer 1061, a pixel definition layer (PDL) 1062, a light-emitting layer 1063 and a cathode layer 1064 included in the light-emitting unit film layer 106, and an encapsulation film layer n10.

[0114] The display panel 100 includes a plurality of pixel units, each of which includes a pixel circuit and a light emitting unit 106a. The pixel circuit and the light emitting unit 106a are connected to provide a driving signal for the light emitting unit 106a, and the light emitting unit 106a is used to emit light under the driving of the driving signal, thereby realizing display.

[0115] Optionally, the active layer n2, the gate insulating layer n3, the gate layer n4, the interlayer dielectric layer n5, the first source-drain layer n6, the first planarization layer n7, the second source-drain layer n8 and the second planarization layer n8 can be collectively referred to as a pixel circuit film layer, and the pixel circuit film layer includes the pixel circuits of a plurality of pixel units. The anode layer 1061, the pixel defining layer 1062, the light emitting layer 1063 and the cathode layer 1064 can be collectively referred to as a light emitting unit film layer 106, and the light emitting unit film layer 106 includes the light emitting units 106a of a plurality of pixel units.

[0116] Optionally, the pixel circuit can include a plurality of thin film transistors (TFT) and at least one storage capacitor. Optionally, the pixel circuit can include seven thin film transistors and one storage capacitor, that is, the pixel circuit is a 7T1C driving circuit. Alternatively, the pixel circuit can include other numbers of thin film transistors and other numbers of storage capacitors. The number of thin film transistors included in the pixel circuit and the number of storage capacitors included in the pixel circuit are not limited in the embodiments of the present application.

[0117] Each thin film transistor includes a gate, a source and a drain. The plurality of thin film transistors included in the pixel circuit in each pixel unit are connected to each other to realize the function of driving the light emitting unit 106a in the pixel unit to emit light.

[0118] The active layer n2 includes a plurality of active patterns corresponding to the plurality of thin film transistors, and each active pattern includes a source region, a drain region and a channel region. The source and the drain of each thin film transistor are located in the first source-drain layer, and the source of the thin film transistor is connected to the source region, and the drain is connected to the drain region.

[0119] The gate layer n4 includes a plurality of gate patterns corresponding to the plurality of thin film transistors. The channel region is the overlapping area of the orthogonal projection of the gate pattern on the substrate 101 and the orthogonal projection of the active pattern on the substrate 101.

[0120] The first source-drain layer n6 includes the sources and the drains of the plurality of thin film transistors. The source of each thin film transistor is connected to the source region of the active pattern in the active layer in the thin film transistor through the via in the interlayer dielectric layer n5 and the gate insulating layer n3. The drain of each thin film transistor is connected to the drain region of the active pattern in the active layer in the thin film transistor through the via in the interlayer dielectric layer n5 and the gate insulating layer n3.

[0121] The second source-drain layer n8 includes a plurality of first connection patterns n81, which can be used to connect with electrodes of the thin film transistors in the first source-drain layer n6 and anode patterns 10611 in the anode layer 1061. The first connection patterns n81 can be used to transmit signals.

[0122] In the embodiments of the present application, the first pattern layer 102 can be the first source-drain layer n6 in the display panel 100, and the second pattern layer 104 can be the second source-drain layer n8 in the display panel 100. Referring to FIG. 11, the first pattern 1021 is located in the first source-drain layer n6, and the second pattern 1041 is located in the second source-drain layer n8. Moreover, the first pattern 1021 and the second pattern 1041 are substantially symmetrical with respect to the area central axis Z1 of the area of the light-emitting region 106a1. In addition, the first insulating layer 103 can be the first planar layer n7, and the second insulating layer 105 can be the second planar layer n9.

[0123] Optionally, each pattern included in the first pattern layer 102 and the second pattern layer 104 can be various different signal lines or patterns in the display panel 100. The first pattern layer 102 and the second pattern layer 104 can include a first pattern, a second pattern, a third pattern, and a fourth pattern.

[0124] For example, in the scheme shown in FIG. 2, the first pattern layer 102 includes the first pattern 1021. The first pattern 1021 can be one of a reset signal line (Vinit) and a reference signal line (Vref). The second pattern layer 104 includes the second pattern 1041. The second pattern 1041 can be one of the reference signal line (Vref), a data signal line (Data), a driving signal line (VDD), and the reset signal line (Vinit). Of course, the patterns in the first pattern layer 102 and the second pattern layer 104 are not limited to the above-mentioned various cases, and the embodiments of the present application do not limit the specific signals of each pattern in the first pattern layer 102 and the second pattern layer 104.

[0125] In the scheme shown in FIG. 9, the first pattern layer 102 includes the first pattern 1021 and two third patterns (T1a1 and T1a2). Any of the three patterns included in the first pattern layer 102 can be one of the first reset signal line (Vinit1), the second reset signal line (Vinit2) and the reference signal line (Vref). The second pattern layer 104 includes the second pattern 1041 and one third pattern T1. Any of the two patterns included in the second pattern layer 104 can be one of the reference signal line (Vref), the data signal line (Data) and the driving signal line (VDD). Of course, the patterns in the first pattern layer 102 and the second pattern layer 104 are not limited to the above-mentioned various cases, and the embodiments of the present application do not limit the specific signals of the various patterns in the first pattern layer 102 and the second pattern layer 104.

[0126] In the scheme shown in FIG. 10, the first pattern layer 102 includes the first pattern 1021. The first pattern 1021 can be one of the reset signal line (Vinit) and the second reset signal line (Vinit2). The second pattern layer 104 includes the second pattern 1041 and a fourth pattern T2. Any of the two patterns included in the second pattern layer 104 can be one of the reference signal line (Vref), the data signal line (Data) and the driving signal line (VDD). Of course, the patterns in the first pattern layer 102 and the second pattern layer 104 are not limited to the above-mentioned various cases, and the embodiments of the present application do not limit the specific signals of the various patterns in the first pattern layer 102 and the second pattern layer 104.

[0127] In the embodiments of the present application, the display panel 100 further includes a third pattern layer 107 and a third insulating layer 108. The third pattern layer 107 is located on one side of the substrate 101, and the third pattern layer 107 includes at least one fifth pattern 1071. The third insulating layer 108 is located on the side of the third pattern layer 107 away from the substrate 101.

[0128] The orthographic projection of the at least one fifth pattern 1071 on the substrate 101 is symmetrical with respect to the area central axis Z1 of the light-emitting area 106a1. The orthographic projection of the at least one fifth pattern 1071 on the substrate 101 being symmetrical with respect to the area central axis Z1 of the light-emitting area 106a1 can mean that the orthographic projection of the at least one fifth pattern 1071 on the substrate 101 is substantially symmetrical with respect to the area central axis Z1 of the light-emitting area 106a1.

[0129] Optionally, in the case where the third pattern layer 107 includes a plurality of fifth patterns 1071, the arrangement mode of the plurality of fifth patterns 1071 can be similar to the arrangement mode of the plurality of third patterns T1.

[0130] For example, if the number of the fifth patterns 1071 included in each third pattern layer 107 is an odd number greater than 1, the plurality of fifth patterns 1071 included in the third pattern layer 107 include a target fifth pattern and at least one fifth pattern group. The target fifth pattern has a normal projection on the substrate 101 of an axis Z1 in a normal projection covering area on the substrate 101, and an absolute value of a difference between a fifth pattern axis of the target fifth pattern and the area axis Z1 is less than or equal to 10 μm. The absolute value of the difference between the fifth pattern axis of the target fifth pattern and the area axis Z1 being less than or equal to 10 μm can be used to indicate that the target fifth pattern is substantially symmetrical with respect to the area axis Z1. In addition, the fifth pattern group includes a first fifth pattern and a second fifth pattern. The normal projection on the substrate 101 of the first fifth pattern and the normal projection on the substrate 101 of the second fifth pattern are located on opposite sides of the area axis Z1, and an absolute value of a difference between a distance between the first fifth pattern and the area axis Z1 and a distance between the second fifth pattern and the area axis Z1 is less than or equal to 10 μm. That is, the first fifth pattern and the second fifth pattern are substantially symmetrical with respect to the area axis Z1.

[0131] Referring to FIG. 12, if the number of the fifth patterns 1071 included in the third pattern layer 107 is an even number greater than 1, the plurality of fifth patterns 1071 included in the third pattern layer 107 include at least one fifth pattern group 1071a. The fifth pattern group includes a first fifth pattern 1071a1 and a second fifth pattern 1071a2. The normal projection on the substrate 101 of the first fifth pattern 1071a1 and the normal projection on the substrate 101 of the second fifth pattern 1071a2 are located on opposite sides of the area axis Z1, and an absolute value of a difference between a distance d9 between the first fifth pattern 1071a1 and the area axis Z1 and a distance d10 between the second fifth pattern 1071a2 and the area axis Z1 is less than or equal to 10 μm, i.e., |d9-d10|≤10 μm. That is, the first fifth pattern 1071a1 and the second fifth pattern 1071a2 are substantially symmetrical with respect to the area axis Z1.

[0132] If the third pattern layer 107 includes one fifth pattern 1071, the normal projection on the substrate 101 of the fifth pattern 1071 covers the normal projection on the substrate 101 of the axis Z1, and an absolute value of a distance between a fifth pattern axis of the fifth pattern 1071 and the area axis Z1 is less than or equal to 10 μm. The absolute value of the distance between the fifth pattern axis of the fifth pattern 1071 and the area axis Z1 being less than or equal to 10 μm can be used to indicate that the fifth pattern 1071 is substantially symmetrical with respect to the area axis Z1.

[0133] Alternatively, referring to FIG. 13, if the third pattern layer 107 includes a fifth pattern 1071, the fifth pattern 1071 covers the light emitting region 106a1 of the light emitting unit 106a in the orthographic projection on the substrate 101. That is, the fifth pattern 1071 is a block pattern covering the light emitting region 106a1.

[0134] In the embodiment of the present application, referring to FIG. 13, the third pattern layer 107 can be located on the side of the second insulating layer 105 away from the substrate 101, and the third insulating layer 108 is located between the third pattern layer 107 and the light emitting unit film layer 106. That is, the first pattern layer 102, the first insulating layer 103, the second pattern layer 104, the second insulating layer 105, the third pattern layer 107, the third insulating layer 108 and the light emitting unit film layer 106 are sequentially stacked in the direction away from the substrate 101.

[0135] In this case, the second insulating layer 105 is located between the second pattern layer 104 and the third pattern layer 107, and the second insulating layer 105 is used to insulate the second pattern layer 104 and the third pattern layer 107 from each other. The third insulating layer 108 is located between the third pattern layer 107 and the light emitting unit film layer 106, and the third insulating layer 108 is used to insulate the third pattern layer 107 and the light emitting unit film layer 106 from each other.

[0136] Alternatively, referring to FIG. 14, the third pattern layer 107 is located between the substrate 101 and the first pattern layer 102, and the third insulating layer 108 is located between the third pattern layer 107 and the first pattern layer 102. That is, the third pattern layer 107, the third insulating layer 108, the first pattern layer 102, the first insulating layer 103, the second pattern layer 104, the second insulating layer 105 and the light emitting unit film layer 106 are sequentially stacked in the direction away from the substrate 101.

[0137] In this case, the second insulating layer 105 is located between the second pattern layer 104 and the light emitting unit film layer 106, and the second insulating layer 105 is used to insulate the second pattern layer 104 and the light emitting unit film layer 106 from each other. The third insulating layer 108 is located between the third pattern layer 107 and the first pattern layer 102, and the third insulating layer 108 is used to insulate the third pattern layer 107 and the first pattern layer 102 from each other.

[0138] In the embodiments of the present application, referring to FIG. 15, the display panel 100 can include, in sequence from the substrate 101 and away from the substrate 101, a buffer layer (buffer) n1, an active layer (poly) n2, a gate insulator layer (GI) n3, a gate layer n4, an inter level dielectric layer (ILD) n5, a first source-drain layer (SD1) n6, a first planarization layer (PLN1) n7, a second source-drain layer (SD2) n8, a second planarization layer (PLN2) n9, a third source-drain layer (SD3) n11, a third planarization layer (PLN3) n12, an anode layer 1061 included in a light-emitting unit film layer 106, a pixel definition layer (PDL) 1062, a light-emitting layer 1063, a cathode layer 1064, and an encapsulation film layer n10.

[0139] The display panel 100 includes a plurality of pixel units, each of which includes a pixel circuit and a light-emitting unit 106a. The pixel circuit and the light-emitting unit 106a are connected to provide a driving signal for the light-emitting unit 106a, and the light-emitting unit 106a is configured to emit light under the driving of the driving signal, thereby realizing display.

[0140] Optionally, the active layer n2, the gate insulator layer n3, the gate layer n4, the inter level dielectric layer n5, the first source-drain layer n6, the first planarization layer n7, the second source-drain layer n8, the second planarization layer n9, the third source-drain layer n11, and the third planarization layer n12 can be collectively referred to as a pixel circuit film layer, which includes the pixel circuits of the plurality of pixel units. The anode layer 1061, the pixel definition layer 1062, the light-emitting layer 1063, the cathode layer 1064 can be collectively referred to as a light-emitting unit film layer 106, which includes the light-emitting units 106a of the plurality of pixel units.

[0141] The active layer b2 includes a plurality of active patterns corresponding to a plurality of thin film transistors, each of which includes a source region, a drain region, and a channel region. The source and the drain of the thin film transistor are located in the first source-drain layer, and the source and the source region are connected, and the drain and the drain region are connected.

[0142] The gate layer n4 includes a plurality of gate patterns corresponding to a plurality of thin film transistors. The channel region is an overlapping area of the orthographic projection of the gate pattern on the substrate 101 and the orthographic projection of the active pattern on the substrate 101.

[0143] The first source-drain layer n6 includes a plurality of source electrodes and drain electrodes of thin film transistors. The source electrode of each thin film transistor is connected to the source region of the active pattern of the active layer in the thin film transistor through the via hole in the interlayer dielectric layer n5 and the gate insulating layer n3.

[0144] The second source-drain layer n8 includes a plurality of first connection patterns n81, and the third source-drain layer n11 includes a plurality of second connection patterns n111. The first connection patterns n81 can be used to connect to the electrodes of the thin film transistors in the first source-drain layer n6 and the second connection patterns n111, and the second connection patterns n111 are also used to connect to the anode patterns 10611 in the anode layer 1061. The first connection patterns n81 and the second connection patterns n111 can be used to transmit signals.

[0145] In the scheme described in FIG. 15, in the embodiments of the present application, the first pattern layer 102 can be the first source-drain layer n6 in the display panel 100, the second pattern layer 104 can be the second source-drain layer n8 in the display panel 100, and the third pattern layer 107 can be the third source-drain layer n11 in the display panel 100. The first pattern 1021 is located in the first source-drain layer n6, and the second pattern 1041 is located in the second source-drain layer n8. Moreover, the first pattern 1021 and the second pattern 1041 are substantially symmetrical with respect to the area central axis Z1 of the light-emitting area 106a1. In addition, the third pattern layer 107 includes a fifth pattern group, and the first fifth pattern and the second fifth pattern are substantially symmetrical with respect to the area central axis Z1 of the light-emitting area 106a1. Meanwhile, the first insulating layer 103 can be the first planar layer n7, the second insulating layer 105 can be the second planar layer n9, and the third insulating layer 108 can be the third planar layer n12.

[0146] Alternatively, the first pattern layer 102 can be the second source-drain layer n8 in the display panel 100, the second pattern layer 104 can be the third source-drain layer n11 in the display panel 100, and the third pattern layer 107 can be the first source-drain layer n6 in the display panel 100. The first pattern 1021 is located in the second source-drain layer n8, and the second pattern 1041 is located in the third source-drain layer n11. Moreover, the first pattern 1021 and the second pattern 1041 are substantially symmetrical with respect to the area central axis Z1 of the light-emitting area 106a1. In addition, the third pattern layer 107 includes a fifth pattern group, and the first fifth pattern and the second fifth pattern are substantially symmetrical with respect to the area central axis Z1 of the light-emitting area 106a1. Meanwhile, the first insulating layer 103 can be the second planar layer n9, the second insulating layer 105 can be the third planar layer n12, and the third insulating layer 108 can be the first planar layer n7.

[0147] Optionally, the patterns included in the first pattern layer 102, the second pattern layer 104 and the third pattern layer 107 can all be different signal lines or patterns in the display panel 100. The patterns included in the first pattern layer 102, the second pattern layer 104 and the third pattern layer 107 can include a first pattern, a second pattern, a third pattern, a fourth pattern and a fifth pattern.

[0148] For example, in the scheme shown in FIG. 12, the first pattern layer 102 includes a first pattern 1021. The first pattern 1021 can be one of a reset signal line (Vinit) and a reference signal line (Vref). The second pattern layer 104 includes a second pattern 1041. The second pattern 1041 can be one of the reference signal line (Vref), a data signal line (Data) and a driving signal line (VDD). The third pattern layer 107 includes four fifth patterns 1071. Referring to FIG. 16, the left two fifth patterns 1071 of the four fifth patterns 1071 can be a first integrated structure, and the right two fifth patterns 1071 can be a second integrated structure. Either of the first integrated structure and the second integrated structure can be one of the data signal line (Data) and the driving signal line (VDD). FIG. 12 can be a cross-sectional view of FIG. 16 along the direction of AA'. Of course, the patterns in the first pattern layer 102, the second pattern layer 104 and the third pattern layer 107 are not limited to the above-mentioned various cases, and the embodiments of the present application do not limit the specific signals of the patterns in the first pattern layer 102, the second pattern layer 104 and the third pattern layer 107.

[0149] In the scheme shown in FIG. 13, the first pattern layer 102 includes a first pattern 1021. The first pattern 1021 can be one of a reset signal line (Vinit) and a reference signal line (Vref). The second pattern layer 104 includes a second pattern 1041. The second pattern 1041 can be one of the reference signal line (Vref), a data signal line (Data) and a driving signal line (VDD). The third pattern layer 107 includes a block-shaped fifth pattern 1071. The fifth pattern 1071 can be one of the data signal line (Data) and the driving signal line (VDD). Of course, the patterns in the first pattern layer 102, the second pattern layer 104 and the third pattern layer 107 are not limited to the above-mentioned various cases, and the embodiments of the present application do not limit the specific signals of the patterns in the first pattern layer 102, the second pattern layer 104 and the third pattern layer 107.

[0150] In the scheme shown in FIG. 14, the first pattern layer 102 includes a first pattern 1021. The first pattern 1021 can be one of a reset signal line (Vinit), a reference signal line (Vref), and a driving signal line (VDD). The second pattern layer 104 includes a second pattern 1041. The second pattern 1041 can be one of a data signal line (Data) and a driving signal line (VDD). The third pattern layer 107 includes a block-shaped fifth pattern 1071. The fifth pattern 1071 can be one of the reset signal line (Vinit), the reference signal line (Vref), and a dummy signal line. The dummy signal line refers to a signal line that is not connected to a signal. Of course, the patterns in the first pattern layer 102, the second pattern layer 104, and the third pattern layer 107 are not limited to the above-described various cases, and embodiments of the present application do not limit the specific signals of the various patterns in the first pattern layer 102, the second pattern layer 104, and the third pattern layer 107.

[0151] In embodiments of the present application, taking the example that the display panel 100 includes two source-drain layers, as shown in FIGS. 17-20, the first pattern 1021 can be one signal line in the first source-drain layer n6, and the second pattern 1041 can be one signal line in the second source-drain layer n8. Moreover, the orthographic projection of the first pattern 1021 on the substrate 101 and the orthographic projection of the second pattern 1041 on the substrate 101 are substantially symmetrical with respect to the area central axis Z1 of the light-emitting area 106a1.

[0152] In embodiments of the present application, referring to FIG. 3, the substrate 101 also has a peripheral area 101b surrounding the display area 101a. The display panel 100 includes a driving circuit (such as a row driving circuit and a data driving circuit, etc.) that can be located in the peripheral area 101. The driving circuit can be connected to the pixel unit and used to provide a driving signal for the pixel unit.

[0153] Referring to FIGS. 11 and 15, the encapsulation film layer n10 can include a first film layer n101, a second film layer n102, and a third film layer n103 that are stacked in a direction away from the substrate 101.

[0154] Optionally, the first film layer n101 and the third film layer n103 can be made of inorganic materials, and the second film layer n102 can be made of an organic material. For example, the first film layer n101 and the third film layer n103 can be made of one or more inorganic oxides such as SiNx (silicon nitride), SiOx (silicon oxide), and SiOxNy (silicon oxynitride). The second film layer n102 can be made of a resin material. The resin can be a thermoplastic resin or a thermosetting resin, and the thermoplastic resin can include an acrylic (PMMA) resin, and the thermosetting resin can include an epoxy resin.

[0155] Optionally, the second film layer n102 can be made by inkjet printing (IJP) method. The first film layer n101 and the third film layer n103 can be made by chemical vapor deposition (CVD) method.

[0156] In summary, the display panel provided by the embodiments of the present application includes a substrate, and a first pattern layer, a first insulating layer, a second pattern layer, a second insulating layer and a light emitting unit film layer which are sequentially stacked in a direction away from the substrate. Since the absolute value of the difference between the distance between the first pattern in the first pattern layer and the area central axis and the distance between the second pattern in the second pattern layer and the area central axis is small, the first pattern and the second pattern on the substrate are approximately symmetrical with respect to the area central axis, the protrusion of the first insulating layer at the position of the first pattern and the protrusion of the second insulating layer at the position of the second pattern are complementary to each other, the flatness of the setting surface of the part of the light emitting unit film layer in the light emitting area is ensured, the problem of color separation of light is avoided, and the display effect of the display panel is improved.

[0157] FIG. 21 is a structural schematic diagram of a display device provided by an embodiment of the present application. Referring to FIG. 21, the display device includes a power supply component 200 and a display panel 100 provided by the above-described embodiments. The power supply component 200 and the display panel 100 are connected, and the power supply component 200 is configured to supply power to the display panel 100.

[0158] Optionally, the display panel can be an organic light-emitting diode (OLED) display panel, and the display device can be an OLED display device. For example, the display panel can be an active-matrix organic light-emitting diode (AMOLED) display panel, and the display device can be an AMOLED display device.

[0159] Optionally, the display device can be any appropriate display device, including but not limited to a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and an e-book, or any product or component having a display function.

[0160] Since the display device can have substantially the same technical effects as the display panel described in the above embodiments, for the purpose of brevity, the technical effects of the display device are not described again here.

[0161] The terminology used in the description of the embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless otherwise defined, all terms of art used herein have the same meaning as commonly understood by one of ordinary skill in the art in the field of the application. In addition, unless otherwise defined, scientific and technical terms can have the meanings that are commonly understood by one of ordinary skill in the art in the field of the application.

[0162] The terminology used in the description of the embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless otherwise defined, all terms of art used herein have the same meaning as commonly understood by one of ordinary skill in the art in the field of the application. In addition, unless otherwise defined, scientific and technical terms can have the meanings that are commonly understood by one of ordinary skill in the art in the field of the application. The words "first," "second," "third," and the like, used in the description of the embodiments herein do not necessarily have an ordinal meaning according to their classification in the application. Rather, these terms can be used solely to distinguish or identify different components or features of the present application. Similarly, terms such as "a" or "an," as used herein, are intended to mean "one or more" or "at least one," unless otherwise indicated. The use of the term "at least" with respect to a property, such as at least one, indicates that the property can have additional instances. The use of the term "including" or "containing" with respect to a list of elements or items is intended to mean that the list is inclusive of other elements or items not listed, as well as of those listed. The use of the term "connected" or "coupled" with respect to two elements or items is intended to mean that the two elements or items are in either physical or electrical communication, whether directly or indirectly. The use of the terms "upper," "lower," "left," "right," and the like with respect to an object described herein is merely intended to reflect relative positions on the object as it is described, and can change when the object is turned over or otherwise repositioned.

[0163] The above description is merely illustrative of the application, and is not intended to limit the application. Any modification, equivalent replacement, improvement, and the like made within the spirit and principle of the application shall fall within the scope of the application.

Claims

1. A display panel, characterized by, The display panel comprises: a substrate substrate having a display area; a first pattern layer located on one side of the substrate substrate, and the first pattern layer comprising a first pattern; a first insulating layer located on one side of the first pattern layer away from the substrate substrate; a second pattern layer located on one side of the first insulating layer away from the substrate substrate, and the second pattern layer comprising a second pattern; a second insulating layer located on one side of the second pattern layer away from the substrate substrate; and a light emitting unit film layer located on one side of the second insulating layer away from the substrate substrate, the light emitting unit film layer comprising a plurality of light emitting units located in the display area, each of the light emitting units having a light emitting area for emitting light; wherein the orthographic projection of the first pattern on the substrate substrate and the orthographic projection of the second pattern on the substrate substrate are respectively located on both sides of a region central axis of the light emitting area, and the absolute value of the difference between the distance between the first pattern and the region central axis and the distance between the second pattern and the region central axis is less than or equal to 10 microns, and the region central axis is a line segment perpendicular to the bearing surface of the substrate substrate and passing through the center of the light emitting area.

2. The display panel of claim 1, wherein, The light emitting unit film layer comprises: an anode layer, a pixel defining layer, a light emitting layer and a cathode layer stacked in turn in the direction away from the substrate substrate; The anode layer comprises a plurality of anode patterns, the pixel defining layer comprises a plurality of hollow areas, each of the hollow areas is used to expose at least part of a corresponding one of the anode patterns; the light emitting layer comprises a plurality of light emitting patterns, each of the light emitting patterns is in contact with the anode pattern exposed by a corresponding one of the hollow areas, and the cathode layer is in contact with the plurality of light emitting patterns; wherein the light emitting area of each of the light emitting units is a region where at least part of the anode pattern exposed by one of the hollow areas is located.

3. The display panel of claim 2, wherein, The center of the light emitting area is the center of the smallest circumscribed circle of the light emitting area, or the center of the light emitting area is the center of the smallest circumscribed rectangle of the light emitting area.

4. The display panel of claim 2, wherein, The orthographic projection of the first pattern on the substrate substrate and the orthographic projection of the second pattern on the substrate substrate do not overlap with the orthographic projection of the hollow area of the pixel defining layer on the substrate substrate.

5. The display panel of claim 4, wherein, The anode pattern comprises a target area pattern not exposed by the hollow area; The orthographic projection of the first pattern on the substrate substrate and the orthographic projection of the target area pattern on the substrate substrate at least partially overlap, and the orthographic projection of the second pattern on the substrate substrate and the orthographic projection of the target area pattern on the substrate substrate at least partially overlap.

6. The display panel of any one of claims 1 to 5, wherein, At least one of the first pattern layer and the second pattern layer further comprises at least one third pattern; The orthographic projection of the at least one third pattern on the substrate substrate is symmetrical with respect to the region central axis.

7. The display panel of claim 6, wherein, For any one of the first pattern layer and the second pattern layer, if the pattern layer includes one third pattern, a projection of the third pattern on the substrate covers a projection of the area axis on the substrate, and an absolute value of a difference between a distance between a third pattern axis of the third pattern and the area axis is less than or equal to 10 microns; If the number of the third patterns included in the pattern layer is an odd number greater than 1, the third patterns included in the pattern layer include a target third pattern and at least one third pattern group, the third pattern group includes a first third pattern and a second third pattern, a projection of the target third pattern on the substrate covers a projection of the area axis on the substrate, and an absolute value of a difference between a distance between a third pattern axis of the target third pattern and the area axis is less than or equal to 10 microns; a projection of the first third pattern on the substrate and a projection of the second third pattern on the substrate are respectively located on two sides of the area axis, and an absolute value of a difference between a distance between the first third pattern and the area axis and a distance between the second third pattern and the area axis is less than or equal to 10 microns.

8. The display panel of claim 6, wherein, For any one of the first pattern layer and the second pattern layer, if the number of the third patterns included in the pattern layer is an even number greater than 1, the third patterns included in the pattern layer include at least one third pattern group, the third pattern group includes a first third pattern and a second third pattern; a projection of the first third pattern on the substrate and a projection of the second third pattern on the substrate are respectively located on two sides of the area axis, and an absolute value of a difference between a distance between the first third pattern and the area axis and a distance between the second third pattern and the area axis is less than or equal to 10 microns.

9. The display panel of claim 6, wherein, The first pattern layer includes one third pattern group, the third pattern group includes a first third pattern and a second third pattern; a projection of the first third pattern on the substrate and a projection of the second third pattern on the substrate are respectively located on two sides of the area axis, and an absolute value of a difference between a distance between the first third pattern and the area axis and a distance between the second third pattern and the area axis is less than or equal to 10 microns; The second pattern layer includes one third pattern, and a projection of the third pattern on the substrate covers a projection of the area axis on the substrate, an absolute value of a difference between a distance between a third pattern axis of the third pattern and the area axis is less than or equal to 10 microns.

10. The display panel of any one of claims 1 to 5, wherein, One of the first pattern layer and the second pattern layer includes a fourth pattern; A normal projection of the fourth pattern on the substrate substrate is located between the light emitting regions of adjacent light emitting units; a distance between the fourth pattern and a target pattern in a target pattern layer in the first pattern layer and the second pattern layer is greater than or equal to 1 microns; Wherein, the target pattern layer is another pattern layer in the first pattern layer and the second pattern layer except the pattern layer where the fourth pattern is located, the target pattern layer is the first pattern layer, then the target pattern is the first pattern, the target pattern layer is the second pattern layer, then the target pattern is the second pattern.

11. The display panel according to any one of claims 1 to 5, characterized in that, The display panel further comprises: a third pattern layer and a third insulating layer; The third pattern layer is located on one side of the substrate substrate, and the third pattern layer comprises at least one fifth pattern; The third insulating layer is located on the side of the third pattern layer away from the substrate substrate; Wherein, the normal projection of the at least one fifth pattern on the substrate substrate is axisymmetric with respect to the region axis of the light emitting region.

12. The display panel of claim 11, wherein, The third pattern layer comprises one fifth pattern, and the normal projection of the fifth pattern on the substrate substrate covers the light emitting region of the light emitting unit.

13. The display panel of claim 11, wherein, The third pattern layer is located on the side of the second insulating layer away from the substrate substrate, and the third insulating layer is located between the third pattern layer and the light emitting unit film layer; or, The third pattern layer is located between the substrate substrate and the first pattern layer, and the third insulating layer is located between the third pattern layer and the first pattern layer.

14. The display panel according to any one of claims 1 to 5, characterized in that, The thickness of the first insulating layer and the second insulating layer ranges from 0.5 microns to 3 microns.

15. A display device comprising: The display device comprises: a power supply component and a display panel as claimed in any one of claims 1 to 14; Wherein, the power supply component and the display panel are connected, and the power supply component is used to power the display panel.

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