Chip and manufacturing method therefor, and electronic device

Abstract

The present application relates to the field of chips, and provides a chip and a manufacturing method therefor, and an electronic device. In the chip, by using a metal contact hole having "a larger upper portion and a smaller lower portion", an alignment process window between a backside through-silicon via and the bottom of the metal contact hole can be increased. The chip comprises a substrate, a first metal wiring layer, a second metal wiring layer, a metal contact hole, and a backside through-silicon via; the substrate is provided with a dielectric layer; the first metal wiring layer is located on the side of the dielectric layer away from the substrate; the second metal wiring layer is located on the side of the substrate away from the first metal wiring layer; the metal contact hole is located on the side of the first metal wiring layer close to the substrate; the backside through-silicon via is connected between the metal contact hole and the second metal wiring layer; the metal contact hole comprises a first hole section and a second hole section, the first hole section is arranged in the dielectric layer, the second hole section is located in the substrate, and the pore size of the second hole section is greater than the pore size of the first hole section; the backside through-silicon via is connected to the second hole section, and the first metal wiring layer is connected to the first hole section.

Description

Chips and their manufacturing methods, electronic devices Technical Field

[0001] This application relates to the field of chip technology, and in particular to a chip and its manufacturing method, and an electronic device. Background Technology

[0002] Referring to Figure 1, in traditional chip manufacturing processes, both signal and power paths are led out through multi-layer metal wiring on the front side. However, with the evolution of process nodes, the number of devices within a chip has increased significantly. To maintain a constant chip area, the number of wiring layers on the front side has increased accordingly, leading to an increase in the length of power lines (power supply paths). This makes the problems of resistance-induced voltage drop (IR Drop) and signal interference increasingly difficult to solve.

[0003] Schematic, referring to Figure 2, the prior art provides a backside power delivery network (BSPDN) technology, which leads the chip's power lines through the back of the wafer (i.e., the substrate), decoupling the signal path and the power supply path, and resolving the contradiction between IR drop and area reduction. In this case, the power supply path includes a power contact (PCT) on the front side and a backside through-silicon via (BSTSV). Due to the etching process characteristics, the power contact (PCT) has a "larger at the top and smaller at the bottom" structure, that is, the critical dimension (CD) at the bottom of the power contact (PCT) is smaller. This results in a smaller alignment process window between the backside through-silicon via (BSTSV) and the power contact (PCT), leading to a large contact resistance between the backside through-silicon via (BSTSV) and the power contact (PCT), or even no contact at all (see Figure 3). Summary of the Invention

[0004] This application provides a chip and its fabrication method, as well as an electronic device. By employing a metal contact hole with a smaller top and a larger bottom, the alignment process window between the back silicon via (BSTSV) and the bottom of the metal contact hole can be increased.

[0005] This application provides a chip including a substrate, a first metal wiring layer, a second metal wiring layer, a metal contact hole, and a back through-silicon via (TSV). A dielectric layer is disposed on the substrate. The first metal wiring layer is located on the side of the dielectric layer away from the substrate. The second metal wiring layer is located on the side of the substrate away from the first metal wiring layer. The metal contact hole is located on the side of the first metal wiring layer closer to the substrate. The back TSV penetrates the substrate and connects the metal contact hole and the second metal wiring layer. The metal contact hole includes a first segment and a second segment. The first segment is disposed in the dielectric layer, and the second segment is located in the substrate, with the diameter of the second segment being larger than the diameter of the first segment. The back TSV is connected to the second segment, and the first metal wiring layer is connected to the first segment.

[0006] The chip provided in this application connects a first metal trace layer located on the front side of the substrate to a second metal trace layer on the back side of the substrate via metal contact holes and back through-silicon vias (TSVs). The chip employs a novel type of metal contact hole, comprising a first segment and a second segment, with the diameter of the second segment being larger than that of the first segment. This results in a "smaller at the top, larger at the bottom" structure, approximating a "barrel shape." In this configuration, the back TSV connects to the second segment. Due to the larger diameter of the second segment, the bottom of the metal contact hole has a larger critical dimension (CD). This increases the process window for alignment between the bottom of the back TSV and the metal contact hole during fabrication, enabling better contact between them, reducing contact resistance, and ultimately improving chip performance.

[0007] In some possible implementations, the ratio of the diameter d2 of the second hole segment to the diameter d1 of the first hole segment is greater than 1 and less than or equal to 8; that is, 1 < d2 / d2 ≤ 8. By setting the ratio of the diameter of the second hole segment to the diameter of the first hole segment to be less than or equal to 8, the fabrication of the first hole segment a1 and the second hole segment a2 can be guaranteed without increasing the difficulty of the process.

[0008] In some possible implementations, the diameter of the second aperture segment is larger than the diameter of the back through-silicon via.

[0009] In some possible implementations, the ratio of the depth h2 of the second via to the depth h1 of the first via is between 1 / 6 and 2, i.e., 1 / 6 ≤ h2 / h1 ≤ 2. If the depth h2 of the second via is too small, the depth of the back-side through-silicon via (TSV) increases, thereby increasing the fabrication difficulty of the TSV. Therefore, to reduce the fabrication difficulty of the back-side TSV, the depth h2 of the second via should not be too small. If the depth h2 of the second via is too large, it increases the difficulty of the filling process for the second via. Therefore, to reduce the fabrication difficulty of the second via, the depth h2 of the second via should not be too large.

[0010] In some possible implementations, the metal contact hole is symmetrical or approximately symmetrical along the hole's axis, which ensures that there is no misalignment between the first and second hole segments in the metal contact hole, thus improving the reliability of the metal contact hole.

[0011] In some possible implementations, the first and second hole segments are integrated into a single structure, meaning they are manufactured in a single process, which simplifies the manufacturing process and reduces manufacturing costs.

[0012] In some possible implementations, the first and second hole segments are made of the same material. In this case, the first and second hole segments can be manufactured using the same filling process in a single operation.

[0013] In some possible implementations, the first metal trace layer and the metal contact hole are integrated into one structure, which can simplify the manufacturing process and reduce manufacturing costs.

[0014] In some possible implementations, the chip has multiple metal trace layers on the side of the dielectric layer away from the substrate, with the first metal trace layer being the one closest to the substrate among the multiple metal trace layers; the chip also includes field-effect transistors disposed on the substrate, with the source and drain structures of the field-effect transistors connected to the first metal trace layer.

[0015] In some possible implementations, the second metal trace layer is a backside power delivery network (BSPDN), and the metal vias are power contacts (PCTs). In this case, the second metal trace layer can achieve backside power delivery through backside through-silicon vias (TSVs) and metal vias.

[0016] In some possible implementations, the dielectric layer includes silicon dioxide (SiO2).

[0017] This application also provides a method for fabricating a chip, comprising: forming a dielectric layer on the front side of a substrate; etching the dielectric layer to form an opening and a first via located at the bottom of the opening, exposing the substrate at the bottom of the first via; etching the substrate along the bottom of the first via to form a hole in the substrate; wherein the diameter of the hole is larger than the diameter of the first via; filling the hole and the first via to form a metal contact hole, and filling the opening to form a first metal wiring layer; forming a back silicon via connected to the metal contact hole in the substrate from the back side of the substrate; and forming a second metal wiring layer connected to the back silicon via on the back side of the substrate.

[0018] The chip fabrication method provided in this application involves forming a large-diameter hole at the bottom of a first via, and filling the first via and the hole to form a metal contact hole. This metal contact hole includes a first segment formed at the first via and a second segment formed at the hole, with the diameter of the second segment being larger than that of the first segment. In this case, when forming a back-side through-silicon via (TSV) on the back side of the substrate corresponding to the second segment, the process window for alignment between the bottom of the TSV and the metal contact hole is increased. This allows for better contact between the TSV and the metal contact hole, reducing contact resistance and improving chip performance.

[0019] In some possible implementations, the holes and first vias are filled to form metal contact holes, and the openings are filled to form a first metal trace layer. This includes using a one-time filling process to form metal contact holes in the holes and first vias and to form a first metal trace layer in the openings. This simplifies the manufacturing process and reduces manufacturing costs.

[0020] In some possible implementations, the holes and the first via are filled to form metal contact holes, and the openings are filled to form a first metal trace layer, including: using a single selective tungsten deposition process or a cobalt electroplating process to fill the holes and the first via to form metal contact holes, and to fill the openings to form a first metal trace layer.

[0021] In some possible implementations, etching is performed along the bottom of the first via to form a hole in the substrate, including selective etching of the substrate along the bottom of the first via using halogen-containing gases NH3 and Cl2 to form a hole in the substrate.

[0022] In some possible implementations, a dielectric layer is formed on the front side of the substrate, and the dielectric layer is etched to form an opening and a first via at the bottom of the opening to expose the substrate. This includes: forming a dielectric layer on the front side of the substrate, etching the dielectric layer on the front side of the substrate to form an opening, and etching at the bottom of the opening to form a first via to expose the substrate. That is, the opening is formed first, and then the first via is formed at the bottom of the opening.

[0023] In some possible implementations, a dielectric layer is formed on the front side of the substrate, and the dielectric layer is etched to form an opening and a first via located at the bottom of the opening, exposing the substrate. This includes: forming a dielectric layer on the front side of the substrate, etching the dielectric layer on the front side of the substrate to form a first via and expose the substrate; then etching the surface of the dielectric layer to form an opening, with the first via located at the bottom of the opening. That is, the first via is formed first, and then an opening is formed at the top of the first via.

[0024] This application also provides an electronic device, which includes a circuit board and a chip as provided in any of the aforementioned possible implementations, wherein the circuit board and the chip are electrically connected. Attached Figure Description

[0025] Figure 1 is a schematic diagram of the structure of a chip provided in the prior art;

[0026] Figure 2 is a schematic diagram of the structure of a chip provided in the prior art;

[0027] Figure 3 is a schematic diagram of the structure of a chip provided in the prior art;

[0028] Figure 4 is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0029] Figure 5 is a schematic diagram of the structure of a chip provided in the prior art;

[0030] Figure 6 is a schematic diagram of the structure of two metal contact holes provided in the embodiments of this application;

[0031] Figure 7 is a flowchart of a chip manufacturing method provided in an embodiment of this application;

[0032] Figure 8 is a schematic diagram of the structure of a chip during the manufacturing process according to an embodiment of this application;

[0033] Figure 9 is a schematic diagram of the structure of a chip during the manufacturing process according to an embodiment of this application;

[0034] Figure 10 is a schematic diagram of the structure of a chip during the manufacturing process according to an embodiment of this application;

[0035] Figure 11 is a schematic diagram of the structure of a chip during the manufacturing process according to an embodiment of this application;

[0036] Figure 12 is a schematic diagram of the structure of a chip during the manufacturing process according to an embodiment of this application;

[0037] Figure 13 is a schematic diagram of the structure of a chip during the manufacturing process according to an embodiment of this application. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0039] The terms "first," "second," etc., used in the specification, embodiments, claims, and drawings of this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or order. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can indicate three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item)" refers to one or more, and "more" refers to two or more. "Installation," "connection," "linking," etc., should be interpreted broadly, for example, it can be an electrical connection or a mechanical connection; it can be a fixed connection or a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium, or a connection within two elements. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, for example, including a series of steps or units. Methods, systems, products, or equipment are not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or equipment. Terms such as “up,” “down,” “left,” and “right” are used only with respect to the orientation of components in the accompanying drawings. These directional terms are relative concepts used for relative description and clarification and may vary accordingly depending on the orientation of the components in the drawings.

[0040] This application provides an electronic device that uses a novel chip. The chip employs a metal contact hole with a smaller top and a larger bottom to bring out signals from the back side. Because the bottom of the metal contact hole has a larger size, the process window for aligning the back through-silicon via (BSTSV) with the bottom of the metal contact hole can be increased when fabricating the BTSV, thus reducing the difficulty of the process.

[0041] This application does not limit the form of the aforementioned electronic device. The electronic device can be any electronic product with a chip, such as consumer electronics, home electronics, automotive electronics, financial terminal products, communication electronics, etc.

[0042] As illustrated, the aforementioned consumer electronics products can include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics products can include smart door locks, televisions, smart speakers, refrigerators, robot vacuum cleaners, etc. In-vehicle electronics products can include in-vehicle navigation systems, in-vehicle displays, etc. Financial terminal products can include automated teller machines (ATMs), self-service electronic devices, etc. Communication electronic products can include servers, storage devices, radar, base stations, and other communication equipment.

[0043] Depending on actual needs, the above-mentioned electronic devices may also include other devices electrically connected to the chip, such as printed circuit boards (PCBs), input / output devices, etc. This application does not impose any restrictions on this.

[0044] The chip structure provided in the embodiments of this application will be described in detail below.

[0045] Schematic, referring to Figure 4, an embodiment of this application provides a chip, which includes a substrate Sub, a first metal wiring layer 10, and a second metal wiring layer 20. The first metal wiring layer 10 is disposed on the front side of the substrate Sub, and the second metal wiring layer 20 is disposed on the back side of the substrate Sub.

[0046] Referring to Figure 4, the front side of the substrate Sub can refer to the side on which the active device is disposed, and the back side of the substrate Sub refers to the opposite side.

[0047] As illustrated, in some possible implementations, a field-effect transistor T fabricated using a front end of line (FEOL) process can be disposed on the front side of the substrate Sub. This field-effect transistor T can be a fin field-effect transistor (finfet), a gate all around field-effect transistor (GAA), or a planar field-effect transistor; this application does not impose any limitations on this.

[0048] Referring again to Figure 4, in some possible implementations, the first metal trace layer 10 can be the metal trace layer closest to the substrate Sub among a plurality of metal trace layers located on the front side of the substrate Sub. For example, the first metal trace layer 10 can be a metal trace layer M0 formed using a middle end of line (MEOL) process, and the first metal trace layer 10 (M0) can be connected to the source / drain structure S / D (i.e., source or drain) of the field-effect transistor T to supply power to the field-effect transistor T through the first metal trace layer 10. The following embodiments are all described using this as an example.

[0049] Referring to Figure 4, a metal contact hole 1 is provided on the side of the first metal wiring layer 10 near the substrate. A back silicon via (BSTSV) is provided below the metal contact hole 1. The first metal wiring layer 10 is connected to the back silicon via (BSTSV) through the metal contact hole 1. The back silicon via (BSTSV) is connected to the second metal wiring layer 20 on the back side of the substrate Sub. That is, the first metal wiring layer 10 on the front side of the substrate is led out to the back side of the substrate and connected to the second metal wiring layer 20 through the metal contact hole 1 and the back silicon via (BSTSV), so that signal transmission can be performed between the front and back sides of the substrate.

[0050] For example, in some possible implementations, referring to Figure 4, the second metal trace layer 20 can be a back power supply network (BSPDN), and the metal contact hole 1 can be a power contact (PCT). In this way, the back power supply network (BSPDN) (20) can be connected to the field-effect transistor T through the back silicon via (BSTSV), the metal contact hole 1, and the first metal trace layer 10, thereby enabling power supply to the field-effect transistor T.

[0051] As illustrated, in some possible implementations, the aforementioned power contact hole can be an all-in-on power contact (AIO PCT), which can simplify the manufacturing process and reduce manufacturing costs.

[0052] Referring to Figures 2 and 3, in the prior art, the power contact hole (PCT) has a "larger at the top and smaller at the bottom" structure, which makes the alignment process window between the back silicon via (BSTSV) and the power contact hole (PCT) smaller, resulting in a large contact resistance between the back silicon via (BSTSV) and the power contact hole (PCT), or even no contact at all.

[0053] To address the aforementioned technical problems, the chip provided in this application embodiment employs a novel metal contact hole 1 (PCT). Referring to Figure 4, the metal contact hole 1 includes a first hole segment a1 (also referred to as the upper hole segment) and a second hole segment a2 (also referred to as the lower hole segment). The first hole segment a1 is disposed in the dielectric layer 100 on the front side of the substrate Sub, and the second hole segment a2 is located in the substrate Sub. The diameter of the second hole segment a2 is larger than the diameter of the first hole segment a1, and the first hole segment a1 and the second hole segment a2 are connected. In other words, the metal contact hole 1 (PCT) has a "smaller at the top and larger at the bottom" structure, approximately resembling a "barrel shape".

[0054] In some possible implementations, the diameter of the back through-silicon via (BSTSV) is smaller than the diameter of the second segment a2.

[0055] In this configuration, the bottom of the back through-silicon via (BSTSV) (i.e., the end closest to the first metal layer 10) is connected to the second via segment a2, and the top (i.e., the end furthest from the first metal layer 10) is connected to the second metal layer 20 (BSPDN). The first metal layer 10 is connected to the top of the first via segment a1. In this way, the first metal layer 10, located on the front side of the substrate Sub, can be led out to the back side of the substrate Sub through the metal contact hole 1 and the back through-silicon via (BSTSV), and connected to the second metal layer 20.

[0056] Because the second hole segment 20 has a larger aperture, the bottom of the metal contact hole 1 has a larger critical dimension (CD). This increases the process window for aligning the bottom of the back through silicon via (BSTSV) and the metal contact hole 1 during the fabrication of the BTSV, thereby enabling good contact between the BTSV and the metal contact hole 1, reducing contact resistance, and further improving chip performance.

[0057] It should be noted that the metal contact hole 1 provided in this application embodiment is not limited to the back power supply scenario of a chip. This novel metal contact hole 1 can be applied to any scenario where signals from the front of the substrate need to be led out to the back of the substrate. This application embodiment is only used as an example of back power supply of a chip for illustration.

[0058] The following description, in conjunction with the configuration of the first hole segment a1 and the second hole segment a2, further explains the metal contact hole 1.

[0059] Indicatively, in some possible implementations, the first segment a1 and the second segment a2 of the metal contact hole 1 can be manufactured in a single process, meaning the metal contact hole 1 can be an integrated structure, such as an integrated power contact hole (AIO PCT), thereby simplifying the process and reducing manufacturing costs. When the metal contact hole 1 adopts an integrated structure, the first segment a1 and the second segment a2 have the same material, such as tungsten (Wu). Furthermore, compared to the buried power rail (BPR) structure and the via buried power rail contact hole (vBPR) structure used in the chip shown in Figure 5, the integrated structure of the metal contact hole 1 also avoids alignment problems and the risk of metal contamination.

[0060] As illustrated in Figure 5, in the chip, a buried power rail (BPR) structure is formed on the substrate surface during the front-end process (FEOL). Then, a buried power rail contact via (vBPR) structure connected to the BPR structure is formed during the mid-end process (MEOL). In the back-end process (BEOL), the back side of the substrate is thinned to form a back through-silicon via (BSTSV) connected to the vBPR structure. Finally, a metal wiring layer is formed on the back side of the substrate to achieve the back-end lead-out of the power lines. In this approach, although the BPR structure has a large critical dimension (CD), an additional process is required to fabricate the BPR structure separately, increasing process complexity. Furthermore, the introduction of metal filler in the front-end process (FEOL) to fabricate the BPR structure poses a risk of metal contamination. Additionally, since the vBPR structure and the BPR structure are formed in the front-end and mid-end processes respectively, additional alignment issues arise for the vBPR structure and the BPR structure.

[0061] In contrast, the metal contact hole 1 in this application can be formed into an integral structure through a single filling process in the intermediate process, which has self-alignment and thus eliminates alignment problems, while also avoiding the risk of introducing metal contamination in the preceding process.

[0062] Of course, in some possible implementations, the metal contact hole 1 can be manufactured in a single process with the first metal trace layer 10, that is, the metal contact hole 1 and the first metal trace layer 10 can be an integrated structure, thereby further simplifying the process and reducing manufacturing costs. When the metal contact hole 1 and the first metal trace layer 10 adopt an integrated structure, the metal contact hole 1 and the first metal trace layer 10 can have the same material, such as tungsten (Wu).

[0063] Furthermore, this application does not impose any restrictions on the material or structure of the dielectric layer 100 for which the first hole segment a1 is set. The dielectric layer 100 can be a single film layer or multiple film layers. In practice, it can be set according to the chip manufacturing requirements, and this application does not impose any restrictions on this.

[0064] Indicatively, in some possible implementations, the dielectric layer 100 in which the first aperture segment a1 is disposed may include a dielectric material such as silicon dioxide (SiO2). For example, the dielectric layer 100 may be a SiO2 layer, but is not limited thereto.

[0065] This application does not impose any restrictions on the ratio (d2 / d1) between the aperture d2 of the second hole segment a2 and the aperture d1 of the first hole segment a1, as long as d2 / d1 > 1. Of course, considering actual manufacturing processes, in some possible implementations, d2 / d1 can be set to ≤ 8. This ensures the fabrication of the first hole segment a1 and the second hole segment a2 without increasing the complexity of the manufacturing process. However, if d2 / d1 > 8, the aperture d2 of the second hole segment a2 will be too large, occupying too much chip area, which is detrimental to chip development.

[0066] As an illustration, in some possible implementations, d2 / d1 can be 1.2, 1.5, 3, 4, 5, 6, 7, 8, etc.

[0067] This application does not impose any restrictions on the ratio (h2 / h1) between the depth h2 of the second hole segment a2 and the depth h1 of the first hole segment a1. In practice, it can be set according to the requirements.

[0068] If the depth h2 of the second hole segment a2 is too small, the depth of the back through silicon via (BSTSV) will increase, which will increase the difficulty of fabricating the BTSV. Therefore, in order to reduce the difficulty of fabricating the BTSV, the depth h2 of the second hole segment a2 should not be too small.

[0069] If the depth h2 of the second hole segment a2 is too large, it will increase the difficulty of the filling process of the second hole segment a2. Therefore, in order to reduce the difficulty of the manufacturing process of the second hole segment a2, the depth h2 of the second hole segment a2 should not be too large.

[0070] Based on this, in some possible implementations, 1 / 6 ≤ h2 / h1 ≤ 2 can be set, such as h2 / h1 being 1 / 6, 1 / 2, 1, 1.5, 2, etc.

[0071] This application does not impose any restrictions on the shape of the second hole segment a2; in practice, it can be manufactured according to requirements.

[0072] For example, referring to Figure 6(a), in some possible implementations, the cross-section of the second hole segment a2 can be approximately rectangular.

[0073] For example, referring to Figure 6(b), in some possible implementations, the cross-section of the second hole segment a2 can be approximately trapezoidal.

[0074] The cross-section of the second aperture segment a2 shown in Figure 6(a) and (b) is a cross-section along the width direction of the fin structure in the field-effect transistor.

[0075] In addition, in some possible implementations, the metal contact hole 1 is symmetrical or approximately symmetrical along the axis of the hole, that is, the first hole segment a1 and the second hole segment a2 are both symmetrical or approximately symmetrical along the axis of the hole, ensuring that there is no misalignment between the first hole segment a1 and the second hole segment a2, thus improving the reliability of the metal contact hole 1. For details, please refer to the relevant manufacturing method section below.

[0076] The following description, in conjunction with the chip manufacturing method, further illustrates the chip provided in the embodiments of this application.

[0077] As illustrated in FIG7, this application provides a method for manufacturing a chip, which may include:

[0078] Step 01: Referring to Figure 8, a dielectric layer 100 is formed on the front side of the substrate Sub. The dielectric layer 100 is etched to form an opening 101, and the bottom of the opening 101 is further etched to form a first via V1 to expose the substrate Sub.

[0079] Schematic, in some possible implementations, step 01 above may include: referring to FIG8(a), fabricating a field-effect transistor T (e.g., a finfet) on the front side of the substrate Sub using a front-end process (FEOL), followed by forming a dielectric layer 100 (e.g., a SiO2 layer) on the field-effect transistor T using a mid-end process (MEOL). Then, referring to FIG8(b), etching the dielectric layer 100 to form an opening 101, which exposes the source / drain structure S / D of the field-effect transistor T. Then, referring to FIG8(c), using an anisotropic etching process, etching the dielectric layer 100 downwards along the bottom of the opening 101 to form a first via V1 with a high aspect ratio to expose the substrate Sub.

[0080] Of course, as another possible implementation, the dielectric layer 100 can be etched in step 01 to form a first via V1 to expose the substrate Sub, and then an opening 101 can be formed on the surface of the dielectric layer 100 by etching, with the first via V1 located at the bottom of the opening 101.

[0081] Step 02: Referring to Figure 9, the substrate Sub is etched along the bottom of the first via V1 to form a hole b in the substrate Sub; wherein the diameter of the hole b is larger than the diameter of the first via V1.

[0082] Indicatively, in some possible implementations, step 02 may include: referring to FIG9, an etching gas with high selectivity for etching the substrate and dielectric layer (such as silicon / silicon dioxide), such as halogen-containing gases NH3 and Cl2, may be used to isotropically etch the substrate Sub along the bottom of the first via V1, forming a hole b in the substrate Sub at the bottom of the first via V1. The diameter of the hole b is larger than the diameter of the first via V1, and the shape of the hole b can be controlled by adjusting the etching cavity gas pressure, RF power, bias voltage, and plasma concentration.

[0083] As illustrated, in some possible implementation methods, the ratio of the aperture of hole b to the aperture of the first via V1 can be controlled to be greater than 1 and less than or equal to 8 by adjusting the cavity gas pressure, radio frequency power, bias voltage, and plasma concentration; the ratio of the depth of hole b to the depth of the first via V1 can be greater than or equal to 1 / 6 and less than or equal to 2. For details, please refer to the relevant content above.

[0084] It should be understood that the first via V1 and hole b formed by segmented etching in step 02 can make the first via V1 and hole b as a whole symmetrical or approximately symmetrical along the axis of the hole, and there will be no misalignment between the two.

[0085] Step 03: Referring to Figure 10, fill the hole b and the first via V1 to form a metal contact hole 1, and fill the opening 101 to form a first metal trace layer 10.

[0086] Schematic, referring to Figure 10, in some possible implementations, step 03 may include: forming a metal contact hole 1 in the hole b and the first via V1 using a one-time filling process, such as selective tungsten deposition (SW) or electrochemical plating (ECP) cobalt (Co), and forming a first metal trace layer 10 in the opening 101. The metal contact hole 1 may be an integrated power contact hole (AIO PCT), and the first metal trace layer 10 may be the metal trace layer M0 closest to the substrate Sub among multiple metal trace layers on the front side of the chip, and is connected to the source / drain structure S / D of the field-effect transistor T, as detailed in the foregoing description.

[0087] The first through hole V1 after filling forms the first hole segment a1 of the metal contact hole 1, and the hole b after filling forms the second hole segment a2 of the metal contact hole 1, and the diameter of the second hole segment a2 is larger than the diameter of the first hole segment a1.

[0088] It is understandable that by filling the hole b, the first via V1 and the opening 101 in one process, the metal contact hole 1 and the first metal trace layer 10 can be integrated into a single structure.

[0089] Of course, depending on the actual needs, the hole b, the first through hole V1 and the opening 101 can also be filled in multiple filling processes. For example, the hole b, the first through hole V1 and the opening 101 can be filled in three separate filling processes, or the hole b and the first through hole V1 can be filled in the same filling process, while the opening 101 is filled separately.

[0090] Since the first through hole V1 and the hole b formed in step 02 are symmetrical or approximately symmetrical along the axis of the hole, the first hole segment a1 and the second hole segment a2 formed after filling the first through hole V1 and the hole b in step 03 are also symmetrical or approximately symmetrical along the axis of the hole. This ensures that there will be no misalignment between the first hole segment and the second hole segment, thus improving the reliability of the metal contact hole.

[0091] Subsequently, as shown in Figure 11, multiple metal trace layers, metal connection pads, etc., can be formed on the first metal trace layer 10 through back-end processing (BEOL) to bring out some signal paths from the front.

[0092] Step 04: Referring to Figure 12, a back silicon via (BSTSV) connected to the metal contact hole 1 is formed in the substrate Sub from the back side.

[0093] Schematic, referring to Figure 12, in some possible implementations, step 04 may include: temporarily bonding the front side of the chip (or wafer) to the carrier 200, thinning the back side of the substrate Sub, and then fabricating a back silicon via (BSTSV) on the back side of the substrate Sub, the BTSV being aligned with the bottom of the metal contact hole 1, i.e., located in the area of ​​the second hole segment a2.

[0094] Because the second hole segment 20 has a larger aperture, the bottom of the metal contact hole 1 (i.e., the bottom of the second hole segment a2) has a larger critical dimension (CD). This increases the process window for alignment between the bottom of the back through silicon via (BSTSV) and the metal contact hole 1 during the fabrication of the BTSV, thereby enabling good contact between the BTSV and the metal contact hole 1, reducing contact resistance, and further improving chip performance.

[0095] Step 05: Form a second metal trace layer 20 on the back side of the substrate Sub that is connected to the back through silicon via (BSTSV).

[0096] Indicatively, in some possible implementations, step 04 may include: referring to FIG13, forming a second metal trace layer 20 connected to a back through-silicon via (BSTSV) on the back side of the substrate Sub. This second metal trace layer 20 may be a single metal trace layer or multiple metal trace layers. This second metal trace layer 20 may serve as a backside power supply network (BSPDN), supplying power to devices on the front side of the substrate through the BTSV.

[0097] Of course, other manufacturing processes can be performed after the second metal trace layer 20, such as forming a metal connector on the top of the second metal trace layer 20 to bring out the power path.

[0098] After the fabrication process on the back side of the substrate is completed, the carrier 200 located on the front side of the substrate can be debonded.

[0099] It should be understood that the sequence number of each of the above-mentioned production processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0100] In addition, for other related content in the above chip manufacturing method, you can refer to the corresponding parts in the aforementioned chip structure, which will not be repeated here; for other configuration structures in the aforementioned chip, you can refer to the above manufacturing method and related processes for adjustment, which will not be repeated here.

[0101] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip, characterized in that, include: A substrate, on which a dielectric layer is disposed; The first metal wiring layer is located on the side of the dielectric layer away from the substrate; The second metal trace layer is located on the side of the substrate away from the first metal trace layer; The metal contact hole is located on the side of the first metal trace layer closest to the substrate; A back-side through-silicon via penetrates the substrate and connects the metal contact hole to the second metal trace layer; The metal contact hole includes a first segment and a second segment. The first segment is disposed in the dielectric layer, and the second segment is located in the substrate. The diameter of the second segment is larger than that of the first segment. The back silicon via is connected to the second segment, and the first metal trace layer is connected to the first segment.

2. The chip according to claim 1, characterized in that, The ratio of the diameter of the second hole segment to the diameter of the first hole segment is greater than 1 and less than or equal to 8.

3. The chip according to claim 1 or 2, characterized in that, The first hole segment and the second hole segment are made of the same material.

4. The chip according to any one of claims 1-3, characterized in that, The diameter of the second aperture segment is larger than the diameter of the back through-silicon via.

5. The chip according to any one of claims 1-4, characterized in that, The ratio of the depth of the second hole segment to the depth of the first hole segment is between 1 / 6 and 2.

6. The chip according to any one of claims 1-5, characterized in that, The metal contact hole is symmetrical or approximately symmetrical along the axis of the hole.

7. The chip according to any one of claims 1-6, characterized in that, The first hole segment and the second hole segment are an integrated structure.

8. The chip according to any one of claims 1-7, characterized in that, The first metal trace layer and the metal contact hole are an integrated structure.

9. The chip according to any one of claims 1-8, characterized in that, The chip has multiple metal trace layers on the side of the dielectric layer away from the substrate, and the first metal trace layer is the one closest to the substrate among the multiple metal trace layers; The chip also includes field-effect transistors disposed on the substrate, and the source-drain structure of the field-effect transistors is connected to the first metal wiring layer.

10. The chip according to any one of claims 1-9, characterized in that, The second metal trace layer is the back power supply network (BSPDN), and the metal contact hole is the power contact hole (PCT).

11. The chip according to any one of claims 1-10, characterized in that, The dielectric layer includes silicon dioxide (SiO2).

12. A method for manufacturing a chip, characterized in that, include: A dielectric layer is formed on the front side of the substrate, the dielectric layer is etched to form an opening and a first via located at the bottom of the opening, and the substrate is exposed at the bottom of the first via. The substrate is etched along the bottom of the first via to form a hole in the substrate; wherein the diameter of the hole is larger than the diameter of the first via; The hole and the first via are filled to form a metal contact hole, and the opening is filled to form a first metal trace layer; From the back side of the substrate, a back through-silicon via is formed in the substrate to connect with the metal contact hole; A second metal trace layer is formed on the back side of the substrate and connected to the back through-silicon via.

13. The method for manufacturing a chip according to claim 12, characterized in that, The process of filling the hole and the first via to form a metal contact hole, and filling the opening to form a first metal trace layer, includes: A one-time filling process is used to form metal contact holes in the holes and the first via, and to form a first metal trace layer in the opening.

14. The method for manufacturing a chip according to claim 12 or 13, characterized in that, The process of filling the hole and the first via to form a metal contact hole, and filling the opening to form a first metal trace layer, includes: A selective tungsten deposition process or a cobalt electroplating process is used to fill the holes and the first via to form metal contact holes, and the openings are filled to form a first metal trace layer.

15. The method for manufacturing a chip according to any one of claims 12-14, characterized in that, The etching of the substrate along the bottom of the first via to form a hole in the substrate includes: The substrate is etched along the bottom of the first via using halogen-containing gases NH3 and Cl2 to form a hole in the substrate.

16. The method for manufacturing a chip according to any one of claims 12-15, characterized in that, The step of forming a dielectric layer on the front side of a substrate, etching the dielectric layer to form an opening and a first via at the bottom of the opening to expose the substrate includes: A dielectric layer is formed on the front side of the substrate. An opening is formed by etching the dielectric layer on the front side of the substrate. A first via is formed by etching at the bottom of the opening to expose the substrate.

17. The method for manufacturing a chip according to any one of claims 12-16, characterized in that, The step of forming a dielectric layer on the front side of a substrate, etching the dielectric layer to form an opening and a first via at the bottom of the opening to expose the substrate includes: A dielectric layer is formed on the front side of the substrate. The dielectric layer on the front side of the substrate is etched to form a first via and expose the substrate. Then, the surface of the dielectric layer is etched to form an opening, and the first via is located at the bottom of the opening.

18. An electronic device, characterized in that, It includes a circuit board and a chip as described in any one of claims 1-11, wherein the circuit board is electrically connected to the chip.

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